Maxim MAX9967AGCCQ Dual, low-power, 500mbps ate driver/comparator with 35ma load Datasheet

19-3195; Rev 1; 2/05
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
The MAX9967 dual, low-power, high-speed, pin electronics driver/comparator/load (DCL) IC includes, for each
channel, a three-level pin driver, a dual comparator, variable clamps, and an active load. The driver features a
wide voltage range and high-speed operation, includes
high-impedance and active-termination (3rd-level drive)
modes, and is highly linear even at low-voltage swings.
The dual comparator provides low dispersion (timing
variation) over a wide variety of input conditions. The
clamps provide damping of high-speed device-undertest (DUT) waveforms when the device is configured as a
high-impedance receiver. The programmable load supplies up to 35mA of source and sink current. The load
facilitates contact/continuity testing, at-speed parametric
testing of IOH and IOL, and pullup of high-output-impedance devices.
The MAX9967A provides tight matching of gain and offset for the drivers, and offset for the comparators and
active load, allowing reference levels to be shared
across multiple channels in cost-sensitive systems. Use
the MAX9967B for system designs that incorporate
independent reference levels for each channel.
The MAX9967 provides high-speed, differential control
inputs with optional internal termination resistors that
are compatible with ECL, LVPECL, LVDS, and GTL.
ECL/LVPECL or flexible open-collector outputs with
optional internal pullup resistors are available for the
comparators. These features significantly reduce the
discrete component count on the circuit board.
A 3-wire, low-voltage, CMOS-compatible serial interface
programs the low-leakage, slew-rate limit, and tristate/terminate operational configurations of the
MAX9967.
The MAX9967’s operating range is -1.5V to +6.5V with
power dissipation of only 1.15W per channel. The
device is available in a 100-pin, 14mm x 14mm body,
and 0.5mm pitch TQFP. An exposed 8mm x 8mm die
pad on the top of the package facilitates efficient heat
removal. The device is specified to operate with an
internal die temperature of +70°C to +100°C, and
features a die temperature monitor output.
Applications
Features
♦ Low Power Dissipation: 1.15W/Channel (typ)
♦ High Speed: 500Mbps at 3VP-P
♦ Programmable 35mA Active-Load Current
♦ Low Timing Dispersion
♦ Wide -1.5V to +6.5V Operating Range
♦ Active Termination (3rd-Level Drive)
♦ Low Leakage Mode: 60nA
♦ Integrated Clamps
♦ Interfaces Easily with Most Logic Families
♦ Integrated PMU Connection
♦ Digitally Programmable Slew Rate
♦ Internal Termination Resistors
♦ Low Gain and Offset Error
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX9967ADCCQ*
0°C to +70°C
100 TQFP-EPR**
MAX9967AGCCQ*
0°C to +70°C
100 TQFP-EPR**
MAX9967ALCCQ
0°C to +70°C
100 TQFP-EPR**
MAX9967AMCCQ*
0°C to +70°C
100 TQFP-EPR**
MAX9967AQCCQ*
0°C to +70°C
100 TQFP-EPR**
MAX9967ARCCQ*
0°C to +70°C
100 TQFP-EPR**
MAX9967BDCCQ
0°C to +70°C
100 TQFP-EPR**
MAX9967BGCCQ
0°C to +70°C
100 TQFP-EPR**
MAX9967BLCCQ
0°C to +70°C
100 TQFP-EPR**
MAX9967BMCCQ
0°C to +70°C
100 TQFP-EPR**
MAX9967BQCCQ*
0°C to +70°C
100 TQFP-EPR**
MAX9967BRCCQ
0°C to +70°C
100 TQFP-EPR**
*Future product—contact factory for availability.
**EPR = Exposed pad reversed (TOP).
Pin Configuration and Typical Application Circuits appear at
end of data sheet.
Selector Guide appears at end of data sheet.
Low-Cost Mixed-Signal/System-on-Chip ATE
Commodity Memory ATE
PCI or VXI Programmable Digital Instruments
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX9967
General Description
MAX9967
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
ABSOLUTE MAXIMUM RATINGS
VCC to GND .........................................................-0.3V to +11.5V
DHV_ to DTV_........................................................…………±10V
VEE to GND............................................................-7.0V to +0.3V
DLV_ to DTV_ ........................................................…………±10V
VCC - VEE ................................................................-0.3V to +18V
CHV_ or CLV_ to DUT_..........................................…………±10V
GS to GND ...........................................................……………±1V
CH_, NCH_, CL_, NCL_ to GND (open collector) ....-2.5V to +5V
DUT_, LDH_, LDL_ to GND ...................................-2.5V to +7.5V
CH_, NCH_, CL_, NCL_ to GND (open emitter) ..(VCCO_ + 1.0V)
All Other Pins to GND ......................(VEE - 0.3V) to (VCC + 0.3V)
DATA_, NDATA_, RCV_, NRCV_,
Current Out of CH_, NCH_, CL_, NCL_ (open emitter) ....+50mA
LDEN_, NLDEN_ to GND ...............................…-2.5V to +5.0V
DHV_, DLV_, DTV_, CHV_, CLV_,
DATA_ to NDATA_, RCV_ to NRCV_,
CPHV_, CPLV_ Current.....................................……….±10mA
LDEN_ to NLDEN_............................................…………±1.5V
TEMP Current...................................................-0.5mA to +20mA
VCCO_ to GND ..........................................................-0.3V to +5V
SCLK, DIN, CS, RST, TDATA_,
DUT_ Short Circuit to -1.5V to +6.5V..........................Continuous
TRCV_, TLDEN_ to GND ..................................…-1.0V to +5V
Power Dissipation (TA = +70°C)
MAX9967_ _CCQ (derate 167mW/°C above +70°C) ....13.3W*
DHV_, DLV_, DTV_, CHV_, CLV_, COM_,
Storage Temperature Range .............................-65°C to +150°C
FORCE_, SENSE_ to GND.................................-2.5V to +7.5V
Junction Temperature ......................................................+125°C
CPHV_ to GND ......................................................-2.5V to +8.5V
Lead Temperature (soldering, 10s) ....................………..+300°C
CPLV_ to GND.......................................................-3.5V to +7.5V
DHV_ to DLV_........................................................…………±10V
*Dissipation wattage values are based on still air with no heat sink. Actual maximum allowable power dissipation is a function of heat
extraction technique and may be substantially higher.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0,
TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Positive Supply
VCC
9.5
9.75
10.5
V
Negative Supply
VEE
-6.5
-5.25
-4.5
V
VLDH_ = VLDL _ = 0
120
155
VLDH_ = VLDL _ = 3.5V, load enabled,
driver = high impedance
220
255
VLDH_ = VLDL _ = 0
-220
-265
-320
-365
2.3
2.9
W
+6.5
V
Positive Supply Current
(Note 2)
ICC
Negative Supply Current
(Note 2)
IEE
VLDH_ = VLDL _ = 3.5V, load enabled,
driver = high impedance
Power Dissipation
PD
(Notes 2, 3)
DUT_ CHARACTERISTICS
Operating Voltage Range
Leakage Current in HighImpedance Mode
Leakage Current in Low-Leakage
Mode
2
VDUT
IDUT
(Note 4)
-1.5
LLEAK = 0; 0 ≤ VDUT_ ≤ 3V
±1.5
LLEAK = 0; VDUT_ = -1.5V, +6.5V
±3
LLEAK = 1; 0 ≤ VDUT_ ≤ 3V, TJ < +90°C
±60
LLEAK = 1; VDUT_ = -1.5V, +6.5V;
TJ < +90°C
±110
LLEAK = 1; 0 < VDUT_ < 3V, VLDL _=
VLDH_ = 3.5V; TJ < +90°C
±80
LLEAK = 1; VDUT_ = -1.5V, +6.5V;
VLDL _ = VLDH_ = 3.5V; TJ < +90°C
±160
_______________________________________________________________________________________
mA
mA
µA
nA
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0,
TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Driver in term mode (DUT_ = DTV_)
4.0
Driver in high-impedance mode
8.0
(Notes 5, 6)
20
µs
Low-Leakage Disable Time
(Notes 6, 7)
20
µs
Low-Leakage Recovery
Time to return to the specified maximum
leakage after a 3V, 4V/ns step at DUT_
4
µs
Combined Capacitance
CDUT
Low-Leakage Enable Time
pF
LEVEL PROGRAMMING INPUTS (DHV_, DLV_, DTV_, CHV_, CLV_, CPHV_, CPLV_, COM_, LDH_, LDL_)
Input Bias Current
±25
IBIAS
Settling time
To 0.1% of full-scale change (Note 7)
1
µA
µs
DIFFERENTIAL CONTROL INPUTS (DATA_, NDATA_, RCV_, NRCV_, LDEN_, NLDEN_)
Input High Voltage
VIH
-1.6
+3.5
V
Input Low Voltage
VIL
-2.0
+3.1
V
±0.15
±1.0
V
±25
µA
Differential Input Voltage
VDIFF
Input Bias Current
MAX9967_DCCQ, MAX9967_MCCQ
Input Termination Voltage
VTDATA_,
VTRCV_,
VTLDEN_
Input Termination Resistor
MAX9967_GCCQ, MAX9967_LCCQ, and
MAX9967_QCCQ
-2.1
+3.5
V
MAX9967_GCCQ, MAX9967_LCCQ, and
MAX9967_QCCQ, between signal and
corresponding termination voltage input
48
52
Ω
1.45
V
SINGLE-ENDED CONTROL INPUTS (CS, SCLK, DIN, RST)
Internal Threshold Reference
Internal Reference Output
Resistance
External Threshold Reference
VTHRINT
1.05
RO
1.25
20
kΩ
VTHR
0.43
1.73
V
Input High Voltage
VIH
VTHR +
0.2
3.5
V
Input Low Voltage
VIL
-0.1
VTHR 0.2
V
Input Bias Current
IB
±25
µA
50
MHz
SERIAL INTERFACE TIMING (Figure 6)
SCLK Frequency
fSCLK
SCLK Pulse-Width High
tCH
8
ns
SCLK Pulse-Width Low
tCL
8
ns
CS Low to SCLK High Setup
tCSS0
3.5
ns
CS High to SCLK High Setup
tCSS1
3.5
ns
_______________________________________________________________________________________
3
MAX9967
ELECTRICAL CHARACTERISTICS (continued)
MAX9967
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0,
TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SCLK High to CS High Hold
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
tCSH1
3.5
ns
DIN to SCLK High Setup
tDS
3.5
ns
DIN to SCLK High Hold
tDH
3.5
ns
tCSWH
20
ns
CS Pulse Width High
TEMPERATURE MONITOR (TEMP)
TJ = +70°C, RL ≥ 10MΩ
Nominal Voltage
Temperature Coefficient
Output Resistance
3.43
V
+10
mV/°C
15
kΩ
DRIVERS (Note 8)
DC OUTPUT CHARACTERISTICS (RL ≥ 10MΩ)
DHV_, DLV_, DTV_, Output Offset
Voltage
VOS
At DUT_ with VDHV_, VDTV_,
VDLV_ independently tested
at +1.5V
MAX9967A
±15
MAX9967B
±100
DHV_, DLV_, DTV_, Output Offset
Temperature Coefficient
DHV_, DLV_, DTV_, Gain
±65
AV
Measured with VDHV_, VDLV_,
and VDTV_ at 0 and 4.5V
MAX9967A
(Note 9)
0.999
MAX9967B
0.96
DHV_, DLV_, DTV_, Gain
Temperature Coefficient
1.00
mV
µV/°C
1.001
V/V
1.001
ppm/°C
-35
VDUT = 1.5V, 3V (Note 10)
±5
Full range (Notes 10, 11)
±15
DHV_ to DLV_ Crosstalk
VDLV_ = 0;
VDHV_ = 200mV, 6.5V
±2
mV
DLV_ to DHV_ Crosstalk
VDHV_ = 5V;
VDLV_ = -1.5V, +4.8V
±2
mV
DTV_ to DLV_ and DHV_
Crosstalk
VDHV_ = 3V; VDLV_ = 0;
VDTV_ = -1.5V, +6.5V
±2
mV
DHV_ to DTV_ Crosstalk
VDTV_ = 1.5V; VDLV_ = 0;
VDHV_ = 1.6V, 3V
±3
mV
DLV_ to DTV_ Crosstalk
VDTV_ = 1.5V; VDHV_ = 3V; VDLV_ = 0, 1.4V
±3
mV
Linearity Error
DHV_, DTV_, DLV_ DC PowerSupply Rejection Ratio
PSRR
Maximum DC Drive Current
IDUT_
DC Output Resistance
RDUT_
DC Output Resistance Variation
4
∆RDUT_
(Note 12)
40
dB
±60
IDUT_ = ±30mA (Note 13)
49
mV
50
IDUT_ = ±1mA to ±8mA
0.5
IDUT_ = ±1mA to ±40mA
1
_______________________________________________________________________________________
±120
mA
51
Ω
2.5
Ω
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0,
TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
kΩ
Sense Resistance
RSENSE
7.50
10
13.75
Force Resistance
RFORCE
320
400
500
Force Capacitance
CFORCE
2
Ω
pF
DYNAMIC OUTPUT CHARACTERISTICS (ZL = 50Ω)
Drive-Mode Overshoot
VDLV_ = 0, VDHV_ = 0.1V
30
VDLV_ = 0, VDHV_ = 1V
40
mV
VDLV_ = 0, VDHV_ = 3V
50
Term-Mode Overshoot
(Note 14)
0
mV
Settling Time to Within 25mV
3V step (Note 15)
10
ns
Settling Time to Within 5mV
3V step (Note 15)
20
ns
TIMING CHARACTERISTICS (ZL = 50Ω) (Note 16)
Prop Delay, Data to Output
2.2
ns
Prop Delay Match, tLH vs. tHL
tPDD
3VP-P
±50
ps
Prop Delay Match, Drivers Within
Package
(Note 17)
40
ps
+3
ps/°C
Prop Delay Temperature
Coefficient
Prop Delay Change vs. Pulse
Width
3VP-P, 40MHz, 2.5ns to 22.5ns pulse width,
relative to 12.5ns pulse width
±60
ps
Prop Delay Change vs. CommonMode Voltage
VDHV_ - VDLV_ = 1V, VDHV_ = 0 to 6V
85
ps
Prop Delay, Drive to High
Impedance
tPDDZ
VDHV_ = 1.0V, VDLV_ = -1.0V, VDTV_ = 0
3.2
ns
Prop Delay, High Impedance to
Drive
tPDZD
VDHV_ = 1.0V, VDLV_ = -1.0V, VDTV_ = 0
3.3
ns
Prop Delay, Drive to Term
tPDDT
VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V
2.5
ns
Prop Delay, Term to Drive
tPDTD
VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V
2.2
ns
0.2VP-P, 20% to 80%
370
1VP-P, 10% to 90%
630
DYNAMIC PERFORMANCE (ZL = 50Ω)
Rise and Fall Time
tR , t F
Rise and Fall Time Match
tR vs. tF
3VP-P, 10% to 90%
1.0
1.3
ps
1.5
ns
5VP-P, 10% to 90%
2.0
3VP-P, 10% to 90%
±0.03
ns
SC1 = 0, SC0 = 1 Slew Rate
Percent of full speed (SC0 = SC1 = 0),
3VP-P, 20% to 80%
75
%
SC1 = 1, SC0 = 0 Slew Rate
Percent of full speed (SC0 = SC1 = 0),
3VP-P, 20% to 80%
50
%
SC1 = 1, SC0 = 1 Slew Rate
Percent of full speed (SC0 = SC1 = 0),
3VP-P, 20% to 80%
25
%
_______________________________________________________________________________________
5
MAX9967
ELECTRICAL CHARACTERISTICS (continued)
MAX9967
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0,
TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Minimum Pulse Width
(Note 18)
CONDITIONS
MIN
TYP
0.2VP-P
650
1VP-P
1.0
3VP-P
2.0
5VP-P
2.9
MAX
UNITS
ps
ns
0.2VP-P
1700
1VP-P
1000
3VP-P
500
5VP-P
350
Dynamic Crosstalk
(Note 20)
10
mVP-P
Rise and Fall Time, Drive to Term
tDTR, tDTF
VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V,
10% to 90%, Figure 1a (Note 21)
1.6
ns
Rise and Fall Time, Term to Drive
tTDR, tTDF
VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V,
10% to 90%, Figure 1b (Note 21)
0.7
ns
Data Rate (Note 19)
Mbps
COMPARATORS (Note 8)
DC CHARACTERISTICS
Input Voltage Range
VIN
Differential Input Voltage
VDIFF
Hysteresis
VHYST
Input Offset Voltage
VOS
(Note 4)
-1.5
0
VDUT_ = 1.5V
mV
±20
MAX9967B
±100
±50
CMRR
VDUT_ = 0, 3V
47
78
VDUT_ = 0, 6.5V
54
78
VDUT_ = -1.5V, +6.5V
44
61
VCC Power-Supply Rejection
Ratio (Note 12)
PSRR
VEE Power-Supply Rejection
Ratio (Note 12)
PSRR
mV
µV/°C
dB
±3
VDUT_ = 1.5V, 3V
Linearity Error (Note 10)
V
V
MAX9967A
Input Offset Voltage Temperature
Coefficient
Common-Mode Rejection Ratio
(Note 22)
+6.5
±8
VDUT_ = 6.5V
±5
VDUT_ = -1.5V
±25
VDUT_ = -1.5V, +6.5V
57
80
VDUT_ = 0, 6.5V
44
64
VDUT_ = -1.5V
33
60
mV
dB
dB
AC CHARACTERISTICS (Note 23)
Minimum Pulse Width (Note 24)
Prop Delay
Prop Delay Temperature
Coefficient
6
tPW(MIN)
tPDL
MAX9967_DCCQ, MAX9967_GCCQ,
MAX9967_LCCQ, MAX9967_RCCQ
MAX9967_MCCQ, MAX9967_QCCQ
0.7
ns
0.85
2.2
ns
+6
ps/°C
_______________________________________________________________________________________
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0,
TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
Prop Delay Match, High/Low vs.
Low/High
Prop Delay Match, Comparators
Within Package
(Note 17)
TYP
MAX
UNITS
±25
ps
35
ps
Prop Delay Dispersion vs.
Common-Mode Input (Note 25)
VCHV_ = VCLV_= 0, 6.4V
±75
VCHV_ = VCLV_ = -1.4V
±175
Prop Delay Dispersion vs. Overdrive
100mV to 1V
220
ps
Prop Delay Dispersion vs. Pulse
Width
2.5ns to 22.5ns pulse width, relative to
12.5ns pulse width
±40
ps
Prop Delay Dispersion vs. Slew Rate
0.5V/ns to 2V/ns slew rate
100
ps
Waveform Tracking 10% to 90%
VDUT_ = 1.0VP-P, tR = tF =
1.0ns, 10% to 90% relative
to timing at 50% point
Term mode
250
High-Z mode
500
ps
ps
OPEN-COLLECTOR LOGIC OUTPUTS (CH_, NCH_, CL_, NCL_: MAX9967_DCCQ, MAX9967_GCCQ, MAX9967_LCCQ,
and MAX9967_RCCQ)
VCCO_ Voltage Range
VVCCO_
Output Low-Voltage Compliance
Output High Current
Output Low Current
IOH
IOL
Output High Voltage
Output Low Voltage
Differential Rise Time
Differential Fall Time
3.5
V
+0.10
8.4
V
mA
mA
-0.05
7.6
-0.5
0
8
VOH
ICH_ = INCH_ = ICL _ = INCL _ = 0,
MAX9967_LCCQ, MAX9967_RCCQ
VCCO_
- 0.05
VCCO_
- 0.005
V
VOL
ICH_ = INCH_ = ICL _ = INCL _ = 0,
MAX9967_LCCQ, MAX9967_RCCQ
VCCO_
- 0.4
V
Output Voltage Swing
Output Termination Resistor
0
Set by IOL, RTERM, and VCCO_
MAX9967_DCCQ, MAX9967_GCCQ
MAX9967_DCCQ, MAX9967_GCCQ
RTERM
ICH_ = INCH_ = ICL _ = INCL _ = 0,
MAX9967_LCCQ, MAX9967_RCCQ
360
Single-ended measurement from VCCO_ to
CH_, NCH_, CL_, NCL_, MAX9967_LCCQ,
MAX9967_RCCQ
48
tR
20%
to
80%
tF
20%
to
80%
MAX9967_DCCQ,
MAX9967_GCCQ, RTERM = 50Ω at
end of line
MAX9967_LCCQ, MAX9967_RCCQ
MAX9967_DCCQ,
MAX9967_GCCQ, RTERM = 50Ω at
end of line
390
440
mV
52
Ω
280
ps
280
ps
MAX9967_LCCQ, MAX9967_RCCQ
OPEN-EMITTER LOGIC OUTPUTS (CH_, NCH_, CL_, NCL_: MAX9967_MCCQ and MAX9967_QCCQ)
VCCO_ Voltage Range
VVCCO_
VCCO_ Supply Current
IVCCO_
-0.1
All outputs 50Ω to (VVCCO_ - 2V)
+3.5
165
V
mA
_______________________________________________________________________________________
7
MAX9967
ELECTRICAL CHARACTERISTICS (continued)
MAX9967
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0,
TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
Output High Voltage
VOH
50Ω to (VVCCO_ - 2V)
Output Low Voltage
VOL
50Ω to (VVCCO_ - 2V)
Output Voltage Swing
50Ω_to (V VCCO_ - 2V)
MIN
TYP
VCCO_
- 1.0
VCCO_
- 0.85
800
MAX
UNITS
V
VCCO_
- 1.7
VCCO_
- 1.6
V
850
900
mV
Differential Rise Time
tR
20% to 80%
370
ps
Differential Fall Time
tF
20% to 80%
370
ps
CLAMPS
High Clamp Input Voltage Range
VCPH_
Low Clamp Input Voltage Range
VCPL_
Clamp Offset Voltage
VOS
-0.3
-2.5
Voltage Gain
V
At DUT_ with IDUT_ = -1mA, VCPLV_ = 0
±100
±0.5
PSRR
IDUT_ = 1mA, VCPHV_ = 0
54
IDUT_ = -1mA, VCPLV_ = 0
54
AV
0.96
dB
1.00
ISCDUT_
ROUT
IDUT_ = 1mA, VCPLV_ = -1.5V,
VCPHV_ = -0.3V to +6.5V
±10
IDUT _= -1mA, VCPHV_ = 6.5V,
VCPLV_ = -1.5V to +5.3V
±10
mV
mV/°C
-100
Clamp Linearity
Clamp DC Impedance
+5.3
±100
Voltage Gain Temperature
Coefficient
Short-Circuit Output Current
V
At DUT_ with IDUT_ = 1mA, VCPHV_ = 0
Offset Voltage Temperature
Coefficient
Clamp Power-Supply Rejection
Ratio (Note 12)
+7.5
V/V
ppm/°C
mV
VCPHV_ = 0, VCPLV_ = -1.5V, VDUT_ = 6.5V
50
95
mA
VCPHV_ = 6.5V, VCPLV_ = 5V, VDUT_ = -1.5V
-95
-50
mA
VCPHV_ = 3V, VCPLV_ = 0,
IDUT_ = ±5mA and ±15mA
50
55
Ω
-1.5
+5.7
V
-7.2
+8.0
V
ACTIVE LOAD (VCOM_ = +1.5V, RL > 1MΩ, driver in high-impedance mode, unless otherwise noted)
COM_ Voltage Range
VCOM_
Differential Voltage Range
COM_ Offset Voltage
VDUT_ - VCOM_
Vos
ISOURCE = ISINK = 20mA
MAX9967A
±15
MAX9967B
±100
Offset Voltage Temperature
Coefficient
COM_ Voltage Gain
Voltage Gain Temperature
Coefficient
8
µV/°C
50
AV
VCOM_ = 0, 4.5V,
ISOURCE = ISINK = 20mA
0.98
1.00
±25
_______________________________________________________________________________________
mV
V/V
ppm/°C
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0,
TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Output Resistance, Sink or
Source
Output Resistance, Linear Region
MIN
VCOM_ = -1.5V, +5.7V;
ISOURCE = ISINK = 20mA (Note 10)
COM_ Linearity Error
COM_ Output-Voltage PowerSupply Rejection Ratio
CONDITIONS
PSRR
Ro
Ro
Deadband
TYP
MAX
UNITS
±3
±15
mV
VCOM_ = 2.5V,
ISOURCE = ISINK = 20mA
40
dB
ISOURCE = ISINK = 35mA; VDUT_ = 3V, 6.5V
with VCOM_ = -1.5V and VDUT_ =
-1.5V, +2V with VCOM_ = 5.7V
25
kΩ
ISOURCE = ISINK = 1mA; VDUT_ = 3V, 6.5V
with VCOM_ = -1.5V and VDUT_ = -1.5V,
+2V with VCOM_ = 5.7V
500
kΩ
IDUT_ = ±10mA, ISOURCE = ISINK = 35mA,
VCOM_ = 2.5V
6
VCOM_ = 2.5V, 95% ISOURCE to 95% ISINK
400
Ω
700
mV
40
mA
10.1
mA/V
SOURCE CURRENT (VDUT_ = 4.5V)
Maximum Source Current
VLDL _ = 3.8V
36
9.9
Source Programming Gain
ATC
VLDL _ = 0.3V, 3V;
VLDH = 0.1V
Source Current Offset (Combined
Offset of LDL_ and GS)
IOS
VLDL_ = 20mV
Source Current Temperature
Coefficient
Source Current Power-Supply
Rejection Ratio
MAX9967A (Note 9)
10
50
MAX9967B
0
200
ISOURCE = 35mA
PSRR
Source Current Linearity
(Note 26)
10
µA
µA/oC
-6
ISOURCE = 25mA
±70
ISOURCE = 35mA
±84
VLDL _ = 100mV, 1V, 2.5V
VLDL _ = 3.5V
±60
±130
µA/V
µA
SINK CURRENT (VDUT_ = -1.5V)
Maximum Sink Current
VLDH_ = 3.8V
-40
Sink Programming Gain
ATC
VLDH_ = 0.3V, 3V; VLDL_ = 0.1V
Sink Current Offset (Combined
Offset of LDH_ and GS)
IOS
VLDH_ = 20mV
Sink Current Temperature
Coefficient
Sink Current Power-Supply
Rejection Ratio
ISINK = 35mA
PSRR
-10.1
-10
-36
mA
-9.9
mA/V
MAX9967A (Note 9)
-50
-10
MAX9967B
-200
0
+6
µA
µA/°C
ISINK = 25mA
±70
ISINK = 35mA
±84
µA /V
_______________________________________________________________________________________
9
MAX9967
ELECTRICAL CHARACTERISTICS (continued)
MAX9967
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0,
TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Sink Current Linearity
(Note 26)
CONDITIONS
MIN
TYP
MAX
VLDH_ = 100mV, 1V, 2.5V
±60
VLDH_ = 3.5V
±130
UNITS
µA
GROUND SENSE
GS Voltage Range
VGS
GS Common-Mode Error
GS Input Bias Current
Verified by GS common-mode error test
VDUT_ = -1.5V, VGS = ±250mV, VLDH_- VGS
= 0.1V
±250
mV
±25
µA
VDUT_ = +4.5V, VGS = ±250mV, VLDL_ VGS = 0.1V
±25
VGS = 0
±25
µA
AC CHARACTERISTICS (ZL = 50Ω to GND)
Enable Time (Note 27)
tEN
Disable Time (Note 27)
tDIS
ISOURCE = 20mA, VCOM_ = -1.5V
ISINK = 20mA, VCOM_ = +1.5V
ISOURCE = 20mA, VCOM_ = -1.5V
ISINK = 20mA, VCOM_ = +1.5V
2.2
ns
1.9
ns
To 10%
10
To 1.5%
50
Current Settling Time on
Commutation
ISOURCE = ISINK = 1mA and
35mA (Notes 7, 28)
Spike During Enable/Disable
Transition
ISOURCE = ISINK = 35mA, VCOM_ = 0
100
ns
mV
Note 1: All minimum and maximum limits are 100% production tested. Tests are performed at nominal supply voltages unless otherwise noted.
Note 2: Total for dual device at worst-case setting. RL > 10MΩ. The supply currents are measured with typical supply voltages.
Note 3: Does not include internal dissipation of the comparator outputs. With output loads of 50Ω to (VVCCO - 2V), this adds 120mW
(typ) to the total device power (MAX9967_MCCQ and MAX9967_QCCQ). For MAX9967_LCCQ, additional power dissipation is typically (32mA x VVCCO).
Note 4: Externally forced voltages may exceed this range provided that the Absolute Maximum Ratings are not exceeded.
Note 5: Transition time from LLEAK being asserted to leakage current dropping below specified limits.
Note 6: Based on simulation results only.
Note 7: Transition time from LLEAK being deasserted to output returning to normal operating mode.
Note 8: With the exception of Offset and Gain/CMRR tests, reference input values are calibrated for offset and gain.
Note 9: Measured at VCC = +9.75, VEE = -5.25V, and TJ = +85°C.
Note 10: Relative to straight line between 0 and 4.5V.
Note 11: Specifications measured at the end points of the full range. Full ranges are -1.3V ≤ VDHV_ ≤ 6.5V, -1.5V ≤ VDLV_ ≤ 6.3V,
-1.5V ≤ VDTV_ ≤ 6.5V.
Note 12: Change in offset voltage with power supplies independently set to their minimum and maximum values.
Note 13: Nominal target value is 50Ω. Contact factory for alternate trim selections within the 45Ω to 51Ω range.
Note 14: VDTV_ = +1.5V, RS = 50Ω. External signal driven into T-line is a 0 to +3V edge with 1.2ns rise time (10% to 90%).
Measurement is made using the comparator.
Note 15: Measured from the crossing point of DATA_ inputs to the settling of the driver output.
Note 16: Prop delays are measured from the crossing point of the differential input signals to the 50% point of the expected output
swing. Rise time of differential inputs DATA_ and RCV_ is 250ps (10% to 90%).
Note 17: Rising edge to rising edge or falling edge to falling edge.
Note 18: Specified amplitude is programmed. At this pulse width, the output reaches at least 95% of its nominal (DC) amplitude. The
pulse width is measured at DATA_.
10
______________________________________________________________________________________
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0,
TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1)
Note 19: Specified amplitude is programmed. Maximum data rate is specified in transitions per second. A square wave that reaches
at least 95% of its programmed amplitude may be generated at one-half this frequency.
Note 20: Crosstalk from either driver to the other. Aggressor channel is driving 3VP-P into a 50Ω load. Victim channel is in term mode
with VDTV_ = +1.5V.
Note 21: Indicative of switching speed from DHV_ or DLV_ to DTV_ and DTV_ to DHV_ or DLV_ when VDLV_ < VDTV_ < VDHV_. If
VDTV_ < VDLV_ or VDTV_ > VDHV_, switching speed is degraded by approximately a factor of 3.
Note 22: Change in offset voltage over the input range.
Note 23: Unless otherwise noted, all propagation delays are measured at 40MHz, VDUT_ = 0 to +2V, VCHV_ = VCLV_ = +1V, slew rate
= 2V/ns, ZS = 50Ω, driver in term mode with VDTV_ = 0. Comparator outputs are terminated with 50Ω to GND at scope input
with VCCO_ = 2V. Open-collector outputs are also terminated (internally or externally) with RTERM = 50Ω to VCCO_.
Measured from VDUT_ crossing calibrated CHV_/CLV_ threshold to crossing point of differential outputs.
Note 24: VDUT_ = 0 to +1V, VCHV_ = VCLV _ = +0.5V. At this pulse width, the output reaches at least 90% of its DC voltage swing.
The pulse width is measured at the crossing points of the differential outputs.
Note 25: Relative to propagation delay at VCHV_ = VCLV_ = +1.5V. VDUT_ = 200mVP-P. Overdrive = 100mV.
Note 26: Relative to segmented interpolations between 20mV, 200mV, 2V, and 3V.
Note 27: Measured from the crossing point of LDEN_ inputs to the 10% point of the output voltage change.
Note 28: VCOM_ = 1.5V, Rs = 50Ω, driving voltage = +4V to -1V transition and -1V to +4V transition. Settling time is measured from
VDUT_ = 1.5V to ISINK/ISOURCE settling within specified tolerance.
tDTF
tTDR
DHV_
DHV_
90%
90%
10%
DTV_
90%
10%
DTV_
90%
10%
10%
DLV_
DLV_
tDTR
tTDF
Figure 1a. Drive to Term Rise and Fall Time
Figure 1b. Term to Drive Rise and Fall Time
Typical Operating Characteristics
DLV_ = 0
RL = 50Ω
DHV_ = 5V
40
MAX9967 toc02
DHV_ = 500mV
MAX9967 toc01
DLV_ = 0
RL = 50Ω
DRIVER TRAILING EDGE TIMING ERROR
vs. PULSE WIDTH
DRIVER LARGE-SIGNAL RESPONSE
MAX9967 toc03
DRIVER SMALL-SIGNAL RESPONSE
20
DHV_ = 3V
DHV_ = 1V
TIMING ERROR (ps)
DHV_ = 200mV
VDUT_ (500mV/div)
VDUT_ (50mV/div)
LOW PULSE
0
-20
-40
HIGH PULSE
-60
DHV_ = 100mV
0
-80
0
NORMALIZED TO PW = 12.5ns
PERIOD = 25ns DHV_ = +3V DLV_ = 0
-100
t (2.50ns/div)
t (2.50ns/div)
0
5
10
15
20
25
PULSE WIDTH (ns)
______________________________________________________________________________________
11
MAX9967
ELECTRICAL CHARACTERISTICS (continued)
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
35
RISING EDGE
25
15
FALLING EDGE
5
-5
HIGH IMPEDANCE TO DHV_
DHV_ TO DTV_
VDUT_ (250mV/div)
TIME DELAY (ps)
45
MAX9967 toc05
NORMALIZED TO VCM = 1.5V
55
HIGH IMPEDANCE TO DRIVE TRANSITION
DRIVE-TO-TERM TRANSITION
MAX9967 toc04
65
MAX9967 toc06
DRIVER TIME DELAY
vs. COMMON-MODE VOLTAGE
VDUT_ (250mV/div)
MAX9967
Typical Operating Characteristics (continued)
0
DLV_ TO DTV_
-15
HIGH IMPEDANCE TO DLV_
RL = 50Ω
0
-25
RL = 50Ω
-35
0
1
2
3
4
t (2.5ns/div)
t (2.5ns/div)
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
6
5
2
1
0
-1
-2
-3
-4
-5
-6
1.5
2.5
3.5
4.5
5.5
0
-1
-2
6.5
-1.5 -0.5 0.5
1.5
2.5
3.5
4.5
5.5
2
1
0
-1
-2
-3
-4
-5
-6
-1.5 -0.5 0.5
6.5
3.5
4.5
5.5
CROSSTALK TO DUT_ FROM DTV_
WITH DUT_ = DHV_
1.6
0
-0.4
DLV_ = 0
DTV_ = 1.5V
1.2
0.8
0.4
0.4
0
-0.4
0.2
0.1
0
-0.1
-0.8
-0.8
-0.2
-1.2
-1.2
-0.3
-1.6
-1.6
NORMALIZED AT DLV_ = 0
0
1.5
NORMALIZED AT DHV_ = 5V
-2.0
3.0
DLV_ VOLTAGE (V)
4.5
6.0
-0.5
0.5
1.5
2.5
3.5
4.5
DHV_ VOLTAGE (V)
5.5
6.5
DHV_ = 3V
DLV_ = 0
0.3
DUT_ ERROR (mV)
0.4
0.5
MAX9967 toc11
2.0
6.5
MAX9967 toc12
CROSSTALK TO DUT_ FROM DHV_
WITH DUT_ = DLV_
DHV_ = 5V
DTV_ = 1.5V
-1.5
2.5
CROSSTALK TO DUT_ FROM DLV_
WITH DUT_ = DHV_
0.8
-2.0
1.5
VDUT_ (V)
DUT_ ERROR (mV)
DUT_ ERROR (mV)
2
1
VDUT_ (V)
1.2
12
4
3
DUT_ = DTV_
4
3
VDUT_ (V)
MAX9967 toc10
1.6
6
5
-3
-4
-5
-6
-1.5 -0.5 0.5
2.0
DUT_ = DLV_
LINEARITY ERROR (mV)
4
3
6
5
MAX9967 toc07
DUT_ = DHV_
LINEARITY ERROR (mV)
LINEARITY ERROR (mV)
6
5
MAX9967 toc08
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
MAX9967 toc09
COMMON-MODE VOLTAGE (V)
-0.4
NORMALIZED AT DTV_ = 1.5V
-0.5
-1.5 -0.5 0.5
1.5
2.5
3.5
DTV_ VOLTAGE (V)
______________________________________________________________________________________
4.5
5.5
6.5
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
0.3
0.2
0.1
0
-0.1
2.0
2.0
1.5
1.0
0.5
0
1.0
0
-0.5
-1.0
-1.5
-0.3
-1.0
-2.0
-0.4
-1.5
-1.5 -0.5 0.5
1.5
2.5
3.5
4.5
5.5
6.5
-2.5
NORMALIZED AT DLV_ = 0
-2.0
-1.5 -0.5 0.5
1.5
2.5
3.5
4.5
5.5
-1.5 -0.5 0.5
6.5
4.5
5.5
DRIVER OFFSET vs. TEMPERATURE
COMPARATOR OFFSET
vs. COMMON-MODE VOLTAGE
0.2
1.5
VEE = -6.5V
1.0
OFFSET (mV)
1.0000
-0.2
-0.4
-0.6
0.5
VEE = -4.5V
0
-0.5
VEE = -5.5V
-0.8
0.9998
-1.0
-1.0
0.9996
65
70
75
80
-1.5
-1.2
NORMALIZED AT TJ = +85°C
90
95
-2.0
60
100
NORMALIZED AT VCM = 1.5V
AND VEE = -5.5V
NORMALIZED AT TJ = +85°C
-1.4
85
MAX9967 toc18
0.4
65
70
75
80
85
90
95
100
-1.5 -0.5 0.5
1.5
2.5
3.5
4.5
5.5
TEMPERATURE (°C)
TEMPERATURE (°C)
COMMON-MODE VOLTAGE (V)
COMPARATOR RISING-EDGE TIMING
VARIATION vs. COMMON-MODE VOLTAGE
COMPARATOR FALLING-EDGE TIMING
VARIATION vs. COMMON-MODE VOLTAGE
COMPARATOR TIMING VARIATION
vs. OVERDRIVE
VEE = -4.5V
VEE = -5.5V
VEE = -6.5V
-100
NORMALIZED AT
VCM = 1.5V AND VEE = -5.25V
-150
VEE = -5.5V
0
1.5
2.5
3.5
4.5
COMMON-MODE VOLTAGE (V)
5.5
6.5
MAX9967 toc21
150
FALLING EDGE
100
50
VEE = -6.5V
-100
-1.5 -0.5 0.5
RISING EDGE
0
NORMALIZED AT
VCM = 1.5V AND VEE = -5.25V
-150
-1.5 -0.5 0.5
6.5
200
VEE = -4.5V
50
-50
250
DELAY (ps)
50
100
TIMING VARIATION (ps)
100
300
MAX9967 toc20
150
MAX9967 toc19
150
6.5
2.0
MAX9967 toc17
MAX9967 toc16
0.6
OFFSET (mV)
1.0002
60
3.5
DRIVER GAIN vs. TEMPERATURE
0
0.9994
2.5
DHV_ VOLTAGE (V)
1.0004
-50
1.5
DLV_ VOLTAGE (V)
1.0006
0
NORMALIZED AT DHV_ = 3V
-3.0
DTV_ VOLTAGE (V)
1.0008
TIMING VARIATION (ps)
0.5
-0.5
NORMALIZED AT DTV_ = 1.5V
DTV_ = 1.5V
DLV_ = -1.5V
1.5
-0.2
-0.5
GAIN (V/V)
DTV_ = 1.5V
DHV_ = 6.5V
2.5
DUT_ ERROR (mV)
DUT_ ERROR (mV)
3.0
MAX9967 toc15
DLV_ = 0
DHV_ = 6.5V
CROSSTALK TO DUT_ FROM DHV_
WITH DUT_ = DTV_
DUT_ ERROR (mV)
0.4
MAX9967 toc13
0.5
CROSSTALK TO DUT_ FROM DLV_
WITH DUT_ = DTV_
MAX9967 toc14
CROSSTALK TO DUT_ FROM DTV_
WITH DUT_ = DLV_
1.5
2.5
3.5
4.5
COMMON-MODE VOLTAGE (V)
5.5
6.5
-50
NORMALIZED TO OVERDRIVE = 0.5V
-100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
OVERDRIVE (V)
______________________________________________________________________________________
13
MAX9967
Typical Operating Characteristics (continued)
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
-20
LOW PULSE
-40
-60
10
LOW PULSE
0
-10
-20
HIGH PULSE
-30
20
-40
-80
0
5
10
15
20
5
10
15
20
-20
-30
-40
0.5
1.0
1.5
2.0
0
COMPARATOR DIFFERENTIAL
OUTPUT RESPONSE (MAX9967_MCCQ)
0
-50
-60
NORMALIZED TO SR = 1.2V/ns
-70
0.5
1.0
1.5
SLEW RATE (V/ns)
14
2.0
2.5
t (2.50ns/div)
VDUT_ = 0 TO 3V PULSE, CHV_ =
CLV_ = +1.5V, EXTERNAL LOAD = 50Ω
2.5
SLEW RATE (V/ns)
VOUT_ (200mV/div)
MAX9967 toc25
0
-10
NORMALIZED TO SR = 1.2V/ns
MAX9967 toc26
COMPARATOR DIFFERENTIAL
OUTPUT RESPONSE (MAX9967_LCCQ)
10
-40
25
COMPARATOR TIMING VARIATION
vs. INPUT SLEW RATE, DUT_ FALLING
VOUT_ (50mV/div)
PROPAGATION DELAY (ps)
0
PULSE WIDTH (ns)
20
-30
-70
PULSE WIDTH (ns)
30
-20
-60
-60
25
0
-10
MAX9967 toc27
-100
10
-50
NORMALIZED TO
PW = 12.5ns, PERIOD = 25ns
-50
NORMALIZED TO PW = 12.5ns
PERIOD = 25ns
MAX9967 toc24
30
PROPAGATION DELAY (ps)
TIMING ERROR (ps)
20
TIMING ERROR (ps)
HIGH PULSE
0
30
MAX9967 toc22
20
COMPARATOR TIMING VARIATION
vs. INPUT SLEW RATE, DUT_ RISING
COMPARATOR TRAILING-EDGE TIMING
ERROR vs. PULSE WIDTH, MAX9967_MCCQ
COMPARATOR TRAILING TIMING
ERROR vs. PULSE WIDTH, MAX9967_LCCQ
MAX9967 toc23
MAX9967
Typical Operating Characteristics (continued)
t (2.50ns/div)
VDUT = 0 TO 3V PULSE, CHV_ =
CLV_ = 1.5V, EXTERNAL LOAD = 50Ω
______________________________________________________________________________________
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
COMPARATOR RESPONSE
HIGH SLEW-RATE OVERDRIVE
COMPARATOR OFFSET
vs. TEMPERATURE
MAX9967 toc30
MAX9967 toc29
MAX9967 toc28
HIGH-IMPEDANCE MODE
CLAMP RESPONSE
0.8
0.6
DIGITIZED
OUTPUT
INPUT
RISING EDGE
0.2
V (500mV/div)
OFFSET (mV)
V (500mV/div)
0.4
0
-0.2
FALLING EDGE
-0.4
0
0
-0.6
INPUT SLEW RATE = 6V/ns
NORMALIZED TO TJ = +85°C
-0.8
60
65
70
75
80
85
90
95
t (5.0ns/div)
DUT_ = 0 TO 3V SQUARE WAVE
RS = 25Ω
CPLV_ = -0.1V CPHV_ = +3.1V
100
TEMPERATURE (°C)
ACTIVE-LOAD LINEARITY ERROR IDUT_
vs. LDH_
LINEARITY ERROR (µA)
20
10
0
-10
COM_ = 1.5V
LDL_ = 0
DUT_ = -1.5V
50
0
-50
-20
COM_ = 2.5V
LDH_ = 3.5V
LDL_ = 3.5V
-30
1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50
VDUT_ (V)
COM_ = 1.5V
LDH_ = 0
DUT_ = 4.5V
80
60
40
20
0
-20
-40
-60
-80
-100
-40
100
LINEARITY ERROR (µA)
30
IDUT_ (mA)
100
MAX9967 toc31
40
ACTIVE-LOAD LINEARITY ERROR IDUT_
vs. LDL_
MAX9967 toc32
ACTIVE-LOAD VOLTAGE vs. CURRENT
MAX9967 toc33
t (2.50ns/div)
-100
0.01
0.1
1
LDH_ VOLTAGE (V)
CALIBRATION POINTS AT
LDH_ = 20mV, 200mV, 2V, 3V
10
0.01
0.1
1
10
LDL_ VOLTAGE (V)
CALIBRATION POINTS AT
LDL_ = 20mV, 200mV, 2V, 3V
______________________________________________________________________________________
15
MAX9967
Typical Operating Characteristics (continued)
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
60
LDH_ = LDL_ = 3.5V
40
0.2
20
IDUT_ (nA)
0.4
0
-0.2
700
LDH_ = LDL_ = 0
0
-20
-0.6
-60
-0.8
-80
-1.5 -0.5 0.5
1.5
2.5
3.5
4.5
5.5
100
0
-1.5 -0.5 0.5
1.5
2.5
3.5
4.5
5.5
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0
6.5
VDUT_ (V)
CPHV_ VOLTAGE (V)
CLAMP CURRENT
vs. DIFFERENCE VOLTAGE
HIGH-IMPEDANCE TO
LOW-LEAKAGE TRANSITION
DRIVER REFERENCE CURRENT
vs. DRIVER REFERENCE VOLTAGE
RL = 100kΩ
CL = 20pF
-400
-500
-600
LOW LEAKAGE TO HIGH IMPEDANCE
HIGH IMPEDANCE TO LOW LEAKAGE
-700
2.25
2.00
INPUT CURRENT (µA)
IDUT_ (250nA/div)
-200
-300
2.50
DLV_
1.75
DHV_
1.50
1.25
1.00
DTV_
0.75
0.50
-800
0
DUT_ = 0
CPHV_ = 3V
0.25
-1000
0
-0.75
-0.50
-0.25
0
0
CPLV_ VOLTAGE (V)
COMPARATOR REFERENCE INPUT CURRENT
vs. INPUT VOLTAGE
3.5
500
2.5
2.0
CHV_ / CLV_
1.5
300
250
0.5
150
0
CPLV_ = -2.2V
350
200
1.5
2.5
3.5
INPUT VOLTAGE (V)
4.5
5.5
6.5
3.5
5.5
6.5
4.5
5.5
4.5
-600
CPHV_ = 7.2V
-650
-700
-750
-800
-850
-900
100
-1.5 -0.5 0.5
2.5
INPUT CURRENT
vs. INPUT VOLTAGE, CPLV_
400
1.0
1.5
INPUT VOLTAGE (V)
450
CPHV_ CURRENT (nA)
3.0
-1.5 -0.5 0.5
INPUT CURRENT
vs. INPUT VOLTAGE, CPHV_
MAX9967 toc40
DUT_ = 6.5V
t (5µs/div)
t = 0 IS THE RISING EDGE OF CS
MAX9967 toc42
-1.00
CPLV_ CURRENT (nA)
-1.25
MAX9967 toc41
-1.50
INPUT CURRENT (nA)
MAX9967 toc39
MAX9967 toc37
-100
16
400
VDUT_ (V)
0
4.0
500
200
LDH_ = LDL_ = 3.5V
6.5
100
-900
600
300
-100
-1.0
IDUT_ (µA)
800
-40
LDH_ = LDL_ = 0
-0.4
DUT_ = 3V
CPLV_ = 0
900
MAX9967 toc36
80
IDUT_ (µA)
0.6
1000
MAX9967 toc35
0.8
IDUT_ (µA)
100
MAX9967 toc34
1.0
CLAMP CURRENT
vs. DIFFERENCE VOLTAGE
LOW-LEAKAGE CURRENT
vs. DUT_ VOLTAGE
HIGH-IMPEDANCE LEAKAGE CURRENT
vs. DUT_ VOLTAGE
MAX9967 toc38
MAX9967
Typical Operating Characteristics (continued)
-0.5 0.5
1.5
2.5
3.5
4.5
CPHV_ VOLTAGE (V)
5.5
6.5
7.5
-2.5 -1.5 -0.5 0.5
1.5
2.5
CPLV_ VOLTAGE (V)
______________________________________________________________________________________
3.5
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
INPUT CURRENTS
vs. INPUT VOLTAGE, COM_
-550
-600
LDL
SUPPLY CURRENT, ICC vs. VCC
MAX9967 toc44
250
225
175
0.925
0.900
0.875
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
100
B
0
-1.5
0
1.5
3.0
4.5
RL = 10kΩ, CL = 0.5pF, VEE = - 5.25V
9.5 9.6 9.7 9.8 9.9 10.0 10.1 10.2 10.3 10.4 10.5
6.0
VCC ( V)
A: DUT_ = DTV_ = 1.5V, DHV_ = 3V, DLV_ = 0,
CHV_ = CLV_ = 0, CPHV_ = 7.2V, CPLV_ = -2.2V,
LDH_ = LDL_ = 0
ISOURCE = ISINK = 0
COM_ VOLTAGE (V)
INPUT VOLTAGE (V)
A
25
0.800
0
125
50
0.825
-700
D
150
75
0.850
-650
C
200
0.950
ICC (mA)
LDH
-500
0.975
COM_ CURRENT (µA)
-450
INPUT CURRENT (nA)
1.000
MAX9967 toc43
-400
MAX9967 toc45
LOAD REFERENCES INPUT CURRENTS
vs. INPUT VOLTAGE
B: SAME AS A EXCEPT DRIVER DISABLED HIGH-Z AND
LOAD ENABLED
C: SAME AS B EXCEPT ISOURCE = ISINK = 35mA
D: SAME AS C EXCEPT LOW-LEAKAGE MODE ASSERTED
IEE (mA)
-210
-230
B
A
-250
-270
D
-290
C
122
IEE vs. TEMPERATURE
-210
121
120
119
118
-212
-214
-216
-218
-220
-222
-224
117
-226
-330
116
-228
-350
115
-310
-6.50 -6.25 -6.00 -5.75 -5.50 -5.25 -5.00 -4.75 -4.50
VEE ( V)
A: DUT_ = DTV_ = 1.5V, DHV_ = 3V, DLV_ = 0,
CHV_ = CLV_ = 0, CPHV_ = 7.2V, CPLV_ = -2.2V,
LDH_ = LDL_ = 0
ISOURCE = ISINK = 0
DUT_ = DTV_ = 1.5V, DHV_ = 3V, DLV_ = 0
CHV_ = CLV_ = 0, CPHV_ = 7.2V
CPLV_ = -2.2V, LDH_ = LDL_ = 0
VCC = 9.75V, VEE = -5.25V
MAX9967 toc48
123
DUT_ = DTV_ = 1.5V, DHV_ = 3V, DLV_ = 0
CHV_ = CLV_ = 0, CPHV_ = 7.2V
CPLV_ = -2.2V, LDH_ = LDL_ = 0
VCC = 9.75V, VEE = -5.25V
SUPPLY CURRENT (mA)
-190
124
SUPPLY CURRENT (mA)
RL = 10kΩ, CL = 0.5pF, VCC = 9.75V
MAX9967 toc46
-170
ICC vs. TEMPERATURE
125
MAX9967 toc47
SUPPLY CURRENT, IEE vs. VEE
-150
-230
60 65 70 75 80 85 90 95 100 105 110
60 65 70 75 80 85 90 95 100 105 110
TEMPERATURE (°C)
TEMPERATURE (°C)
B: SAME AS A EXCEPT DRIVER DISABLED HIGH-Z AND
LOAD ENABLED
C: SAME AS B EXCEPT ISOURCE = ISINK = 35mA
D: SAME AS C EXCEPT LOW-LEAKAGE MODE ASSERTED
______________________________________________________________________________________
17
MAX9967
Typical Operating Characteristics (continued)
MAX9967
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
Pin Description
PIN
NAME
FUNCTION
1
TEMP
Temperature Monitor Output
2, 9, 12, 14, 17,
24, 35, 45, 46, 60,
80, 81, 91
VEE
Negative Power-Supply Input
3, 5, 10, 16, 21,
23, 25, 34, 43, 44,
82, 83, 92
GND
Ground Connection
4, 11, 15, 22, 33,
41, 42, 66, 84, 85,
93
VCC
Positive Power-Supply Input
6
DUT1
8
SENSE1
13
GS
18
SENSE2
19
DUT2
20
Channel 1 Device-Under-Test Input/Output. Combined I/O for driver, comparator, clamp, and load.
Channel 1 Sense Output to External PMU
Ground Sense. GS is the ground reference for LDH_ and LDL_.
Channel 2 Sense Output to External PMU
Channel 2 Device-Under-Test Input/Output. Combined I/O for driver, comparator, clamp, and load.
FORCE2 Channel 2 Force Input from External PMU
26
CLV2
Channel 2 Low Comparator Reference Input
27
CHV2
Channel 2 High Comparator Reference Input
28
DLV2
Channel 2 Driver Low Reference Input
29
DTV2
Channel 2 Driver Termination Reference Input
30
DHV2
Channel 2 Driver High Reference Input
31
CPLV2
Channel 2 Low-Clamp Reference Input
32
CPHV2
Channel 2 High-Clamp Reference Input
36
NCH2
37
CH2
Channel 2 Comparator High Output. Differential output of channel 2 high comparator.
Channel 2 Collector Voltage Input. Voltage for channel 2 comparator output pullup resistors. For
open-collector outputs, this is the pullup voltage for the internal termination resistors. For openemitter outputs, this is the collector voltage of the output transistors. Not internally connected on
open-collector versions without internal termination resistors.
38
VCCO2
39
NCL2
40
CL2
47
COM2
Channel 2 Active-Load Commutation Voltage Reference Input
48
LDL2
Channel 2 Active-Load Source Current Reference Input
49
LDH2
Channel 2 Active-Load Sink Current Reference Input
50, 76
N.C.
No Connect. Make no connection.
51
TDATA2
52
NDATA2 Channel 2 Multiplexer Control Inputs. Differential controls DATA2 and NDATA2 select driver 2’s
input from DHV2 or DLV2. Drive DATA2 above NDATA2 to select DHV2. Drive NDATA2 above
DATA2 DATA2 to select DLV2.
53
18
FORCE1 Channel 1 Force Input from External PMU
7
Channel 2 Comparator Low Output. Differential output of channel 2 low comparator.
Channel 2 Data Termination Voltage Input. Termination voltage input for the DATA2 and NDATA2
differential inputs. Not internally connected on versions without internal termination resistors.
______________________________________________________________________________________
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
PIN
NAME
54
TRCV2
55
NRCV2
56
RCV2
57
58
59
FUNCTION
Channel 2 RCV Termination Voltage Input. Termination voltage input for the RCV2 and NRCV2
differential inputs. Not internally connected on versions without internal termination resistors.
Channel 2 Multiplexer Control Inputs. Differential controls RCV2 and NRCV2 place channel 2 into
receive mode. Drive RCV2 above NRCV2 to place channel 2 into receive mode. Drive NRCV2 above
RCV2 to place channel 2 into drive mode.
Channel 2 Load Enable Termination Voltage Input. Termination voltage input for the LDEN2 and
NLDEN2 differential inputs. Not internally connected on versions without internal termination
resistors.
NLDEN2 Channel 2 Multiplexer Control Inputs. Differential controls LDEN2 and NLDEN2 enable/disable the
active load. Drive LDEN2 above NLDEN2 to enable the channel 2 active load. Drive NLDEN2 above
LDEN2 LDEN2 to disable the channel 2 active load.
TLDEN2
61
RST
Reset Input. Asynchronous reset input for the serial register. RST is active low and asserts
low-leakage mode. At power-up, hold RST low until VCC and VEE have stabilized.
62
CS
Chip-Select Input. Serial port activation input. CS is active low.
63
THR
64
SCLK
65
DIN
Single-Ended Logic Threshold. Leave THR unconnected to set the threshold to +1.25V or force THR
to a desired threshold voltage.
Serial-Clock Input. Clock for serial port.
68
Data Input. Serial port data input.
Channel
1 Multiplexer Control Inputs. Differential controls LDEN1 and NLDEN1 enable/disable the
LDEN1
active load. Drive LDEN1 above NLDEN1 to enable the channel 1 active load. Drive NLDEN1 above
NLDEN1 LDEN1 to disable the channel 1 active load.
69
TLDEN1
70
RCV1
71
NRCV1
72
TRCV1
67
Channel 1 Load Enable Termination Voltage Input. Termination voltage input for the LDEN1 and
NLDEN1 differential inputs. Not internally connected on versions without internal termination
resistors.
Channel 1 Multiplexer Control Inputs. Differential controls RCV1 and NRCV1 place channel 1 into
receive mode. Drive RCV1 above NRCV1 to place channel 1 into receive mode. Drive NRCV1 above
RCV1 to place channel 1 into drive mode.
Channel 1 RCV Termination Voltage Input. Termination voltage input for the RCV1 and NRCV1
differential inputs. Not internally connected on versions without internal termination resistors.
74
Channel 1 Multiplexer Control Inputs. Differential controls DATA1 and NDATA1 select driver 1’s
input from DHV1 or DLV1. Drive DATA1 above NDATA1 to select DHV1. Drive NDATA1 above
NDATA1 DATA1 to select DLV1.
75
TDATA1
77
LDH1
Channel 1 Active-Load Sink Current Reference Input
78
LDL1
Channel 1 Active-Load Source Current Reference Input
79
COM1
Channel 1 Active Load Commutation Voltage Reference Input
86
CL1
87
NCL1
73
DATA1
Channel 1 Data Termination Voltage Input. Termination voltage input for the DATA1 and NDATA1
differential inputs. Not internally connected on versions without internal termination resistors.
Channel 1 Low Comparator Output. Differential output of channel 1 low comparator.
______________________________________________________________________________________
19
MAX9967
Pin Description (continued)
MAX9967
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
Pin Description (continued)
PIN
88
NAME
VCCO1
FUNCTION
Channel 1 Collector Voltage Input. Voltage for channel 1 comparator output pullup resistors. For
open-collector outputs, this is the pullup voltage for the internal termination resistors. For openemitter outputs, this is the collector voltage of the output transistors. Not internally connected on
open-collector versions without internal termination resistors.
89
CH1
90
NCH1
94
CPHV1
Channel 1 High-Clamp Reference Input
95
CPLV1
Channel 1 Low-Clamp Reference Input
96
DHV1
Channel 1 Driver High Reference Input
97
DTV1
Channel 1 Driver Termination Reference Input
98
DLV1
Channel 1 Driver Low Reference Input
99
CHV1
Channel 1 High-Comparator Reference Input
100
CLV1
Channel 1 Low-Comparator Reference Input
Channel 1 High Comparator High Output. Differential output of channel 1 high-side comparator.
Detailed Description
The MAX9967 dual, low-power, high-speed, pin electronics DCL IC includes, for each channel, a three-level
pin driver, a dual comparator, variable clamps, and an
active load. The driver features a -1.5V to +6.5V operating range and high-speed operation, includes highimpedance and active-termination (3rd-level drive)
modes, and is highly linear even at low voltage swings.
The dual comparator provides low dispersion (timing
variation) over a wide variety of input conditions. The
clamps provide damping of high-speed DUT_ waveforms when the device is configured as a high-impedance receiver. The programmable load supplies up to
35mA of source and sink current. The load facilitates
contact/continuity testing, at-speed parametric testing
of IOH and IOL, and pullup of high output-impedance
devices.
The MAX9967A provides tight matching of gain and offset for the drivers and offset for the comparators and
active load, allowing reference levels to be shared
across multiple channels in cost-sensitive systems. Use
the MAX9967B for system designs that incorporate
independent reference levels for each channel.
20
Optional internal resistors at the high-speed inputs provide compatibility with ECL, LVPECL, LVDS, and GTL
interfaces. Connect the termination voltage inputs
(TDATA_, TRCV_, TLDEN_) to the appropriate voltage
for terminating ECL, LVPECL, GTL, or other logic.
Leave the inputs unconnected for 100Ω differential
LVDS termination. In addition, ECL/LVPECL or flexible
open-collector outputs with optional internal pullup
resistors are available for the comparators. These features significantly reduce the discrete component count
on the circuit board.
A 3-wire, low-voltage, CMOS-compatible serial interface programs the low-leakage, load-disable, slew-rate,
and tri-state/terminate operational configurations of the
MAX9967.
Output Driver
The driver input is a high-speed multiplexer that selects
one of three voltage inputs: DHV_, DLV_, or DTV_. This
switching is controlled by high-speed inputs DATA_ and
RCV_ and mode control bit TMSEL (Table 1). A slew-rate
circuit controls the slew rate of the buffer input. Select one
of four possible slew rates according to Table 2. The
speed of the internal multiplexer sets the100% driver slew
rate (see the Driver Large-Signal Response graph in the
Typical Operating Characteristics).
______________________________________________________________________________________
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
TEMP
CS
SCLK
DIN
RST
THR
CH_ MODE BITS
LLEAK
SC0
SC1
TMSEL
LDDIS
LDCAL
SERIAL
INTERFACE
VCC
VEE
GND
SERIAL INTERFACE IS COMMON TO BOTH CHANNELS.
MODE BITS INDEPENDENTLY LATCHED FOR EACH CHANNEL.
400Ω
FORCE_
DLV_
DHV_
SLEWRATE
CONTROL
MULTIPLEXER
10kΩ
SENSE_
BUFFER
50Ω
DUT_
DTV_
OPTIONAL
RDATA_ = 5OΩ
SC0
LLEAK
SC1
TDATA_
DATA_
NDATA_
RCV_
NRCV_
HIGH-Z
TMSEL
TRCV_
CPHV_
OPTIONAL
RRCV_ = 5OΩ
OPTIONAL
CLAMPS
CPLV_
CHV_
CH_
NCH_
VCCO_
COMPARATORS
4 x 50Ω
OPTIONAL
CL_
GS
VCC
NCL_
CLV_
LDH_
LLEAK
LDCAL
LDDIS
LDEN_
NLDEN_
ACTIVELOAD
CONTROL
SINK
(HIGH)
CURRENT
ACTIVE
LOAD
RLDEN_
50Ω
OPTIONAL
SOURCE
(LOW)
CURRENT
TLDEN_
COM_
LDL_
GS
ONE OF TWO IDENTICAL CHANNELS SHOWN
VEE
______________________________________________________________________________________
21
MAX9967
Functional Diagram
DUT_ can be toggled at high speed between the buffer
output and high-impedance mode, or it can be placed
into low-leakage mode (Figure 2, Table 1). In highimpedance mode, the clamps are connected. Highspeed input RCV_ and mode control bits TMSEL and
LLEAK control the switching. In high-impedance mode,
the bias current at DUT_ is less than 1.5µA over the 0 to
3V range, while the node maintains its ability to track
high-speed signals. In low-leakage mode, the bias current at DUT_ is further reduced to less than 50nA, and
signal tracking slows. See the Low-Leakage Mode,
LLEAK section for more details.
The nominal driver output resistance is 50Ω. Contact
the factory for different resistance values within the 45Ω
to 51Ω range.
Clamps
Configure the voltage clamps (high and low) to limit the
voltage at DUT_ and to suppress reflections when the
channel is configured as a high-impedance receiver.
The clamps behave as diodes connected to the outputs of high-current buffers. Internal circuitry compensates for the diode drop at 1mA clamp current. Set the
clamp voltages using the external connections CPHV_
and CPLV_. The clamps are enabled only when the driver is in the high-impedance mode (Figure 2). For transient suppression, set the clamp voltages to
approximately the minimum and maximum expected
HIGHSPEED
INPUTS
DUT_ voltage range. The optimal clamp voltages are
application specific and must be empirically determined. If clamping is not desired, set the clamp voltages at least 0.7V outside the expected DUT_ voltage
range; overvoltage protection remains active without
loading DUT_.
Comparators
The MAX9967 provides two independent high-speed
comparators for each channel. Each comparator has
one input connected internally to DUT_ and the other
input connected to either CHV_ or CLV_ (see the
Functional Diagram). Comparator outputs are a logical
result of the input conditions, as indicated in Table 3.
Three configurations are available for the comparator
differential outputs to ease interfacing with a wide variety of logic families. An open-collector configuration
switches an 8mA current source between the two outputs. This configuration is available with and without
internal termination resistors connected to V CCO_
(Figure 3). For open-collector versions without internal
termination, leave V CCO_ unconnected and add the
required external resistors. These resistors are typically
50Ω to the pullup voltage at the receiving end of the
output trace. Alternate configurations may be used,
provided that the Absolute Maximum Ratings are not
exceeded. For open-collector versions with internal termination, connect VCCO_ to the desired VOH voltage.
REFERENCE
INPUTS
DLV_
0
0
DHV_
1
SLEW RATE
BUFFER
0
1
0
DTV_
50Ω
DUT_
1
DATA_
RCV_
HIGH-Z
CPHV_
CLAMPS
MODE
4
LLEAK
SC1
SC0
CPLV_
TMSEL
MAX9967
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
COMPARATORS
ACTIVE LOAD
Figure 2. Simplified Driver Channel
22
______________________________________________________________________________________
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
INTERNAL
CONTROL
REGISTER
EXTERNAL
CONNECTIONS
DRIVER OUTPUT
DATA_
RCV_
TMSEL
LLEAK
1
0
X
0
Drive to DHV_
0
0
X
0
Drive to DLV_
X
1
1
0
Drive to DTV_
(term mode)
X
1
0
0
High-impedance
(high-z) mode
X
X
X
1
Low-leakage mode
Table 2. Slew-Rate Logic
SC1
SC0
DRIVER SLEW RATE (%)
0
0
100
0
1
75
1
0
50
1
1
25
Each output provides a nominal 400mVP-P swing and
50Ω source termination.
An open-emitter configuration is also available (Figure 4).
Connect an external collector voltage to VCCO_ and add
external pulldown resistors. These resistors are typically
50Ω to VCCO_ - 2V at the receiving end of the output
trace. Alternate configurations may be used provided that
the Absolute Maximum Ratings are not exceeded.
Active Load
The active load consists of linearly programmable
source and sink current sources, a commutation buffer,
and a diode bridge (see Functional Diagram). Analog
reference inputs LDH_ and LDL_ program the sink and
source currents, respectively, within the 0 to 35mA
range. Analog reference input COM_ sets the commutation buffer output voltage. The source and sink naming
convention is referenced to the device under test.
Current out of the MAX9967 constitutes sink current and
current into the MAX9967 constitutes source current.
The programmed source (low) current loads the device
under test when VDUT_ > VCOM_. The programmed
sink (high) current loads the device under test when
VDUT_ < VCOM_.
The GS input allows a single level-setting DAC, such as
the MAX5631 or MAX5734, to program the MAX9967’s
active load, driver, comparator, and clamps. Although
all of the DAC levels are typically offset by V GS, the
operation of the MAX9967’s ground-sense input nullifies this offset with respect to the active-load currents.
Connect GS to the ground reference used by the DAC.
(VLDL_ - VGS) sets the source current by +10mA/V.
(VLDH_ - VGS) sets the sink current by -10mA/V.
The high-speed differential input LDEN_ and 3 bits of
the control word (LDCAL, LDDIS, and LLEAK) control
the load (Table 4). When the load is enabled, the internal source and sink current sources connect to the
diode bridge. When the load is disabled, the internal
current sources shunt to ground and the top and bottom of the bridge float (see the Functional Diagram).
LLEAK places the load in low-leakage mode. LLEAK
overrides LDEN_, LDDIS, and LDCAL. See the LowLeakage Mode, LLEAK section for more detailed information.
LDDIS and LDCAL
In some tester configurations, the load enable is driven
with the complement of the driver high-impedance signal
(RCV_), so disabling the driver enables the load and vice
versa. The LDDIS and LDCAL signals disable and enable
the load independently of the state of LDEN_. This allows
the load and driver to be simultaneously enabled and disabled for diagnostic purposes (Table 4).
Low-Leakage Mode, LLEAK
Asserting LLEAK through the serial port or with RST
places the MAX9967 into a very low-leakage state (see
the Electrical Characteristics). The comparators function at full speed, but the driver, clamps, and active
load are disabled. This mode is convenient for making
IDDQ and PMU measurements without the need for an
output disconnect relay. LLEAK is programmed independently for each channel.
When DUT_ is driven with a high-speed signal while
LLEAK is asserted, the leakage current momentarily
increases beyond the limits specified for normal operation. The low-leakage recovery specification in the
Electrical Characteristics table indicates device behavior under this condition.
Table 3. Comparator Logic
DUT_ > CHV_
DUT_ > CLV_
CH_
CL_
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
______________________________________________________________________________________
23
MAX9967
Table 1. Driver Logic
MAX9967
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
DUT_
CH_
8mA
CHV_
NCH_
VEE
4 x 50Ω
OPTIONAL
VCCO_
CL_
8mA
CLV_
NCL_
VEE
Figure 3. Open-Collector Comparator Outputs
CH_
106Ω
DUT_
CHV_
106Ω
NCH_
VCCO_
CL_
106Ω
CLV_
106Ω
NCL_
Figure 4. Open-Emitter Comparator Outputs
24
______________________________________________________________________________________
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
MAX9967
Table 4. Active Load Programming
EXTERNAL
CONNECTIONS
INTERNAL CONTROL REGISTER
MODE
LDEN_
LDCAL
LDDIS
LLEAK
0
0
0
0
Normal operating mode, load disabled
1
0
0
0
Normal operating mode, load enabled
X
1
0
0
Load enabled for diagnostics
X
X
1
0
Load disabled
X
X
X
1
Low-leakage mode
SCLK
SHIFT
REGISTER
0
DIN
1
2
3
4
5
6
7
ENABLE
CS
F/F
F/F
5
7
D
5
Q
6
ENABLE
D
Q
ENABLE
SET
SET
RST
F/F
F/F
0-4
7
20kΩ
THR
VTHRINT = 1.25V
D
0-4
Q
6
ENABLE
5
LDDIS, LDCAL, TMSEL,
SC0, SC1
MODE
BITS
1
LLEAK
CHANNEL 1
D
Q
ENABLE
5
1
LDDIS, LDCAL, TMSEL, LLEAK
SC0, SC1
MODE
BITS
CHANNEL 2
Figure 5. Serial Interface
______________________________________________________________________________________
25
MAX9967
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
tCH
SCLK
tCSS0
tCL
tCSS1
tCSH1
CS
tCSWH
tOH
tDS
D7
DIN
D6
D5
D4
D3
D2
D1
D0
Figure 6. Serial-Interface Timing
Serial Interface and Device Control
A CMOS-compatible serial interface controls the
MAX9967 modes (Figure 5). Control data flow into an 8bit shift register (MSB first) and are latched when CS is
taken high, as shown in Figure 6. Latches contain 6 control bits for each channel of the dual pin driver. Data
from the shift register are loaded to either or both of the
latches as determined by bits D6 and D7, and indicated
in Figure 5 and Table 5. The control bits, in conjunction
with external inputs DATA_ and RCV_, manage the fea-
tures of each channel, as shown in Tables 1 and 2. RST
sets LLEAK = 1 for both channels, forcing them into lowleakage mode. All other bits are unaffected. At powerup, hold RST low until VCC and VEE have stabilized.
Analog control input THR sets the threshold for the
input logic, allowing operation with CMOS logic as low
as 0.9V. Leaving THR unconnected results in a nominal
threshold of 1.25V from an internal reference, providing
compatibility with 2.5 to 3.3V logic.
Table 5. Shift-Register Functions
BIT
NAME
D7
CH1
Channel 1 Write Enable. Set to 1 to update the control byte for channel 1. Set to 0 to make no changes to
channel 1.
D6
CH2
Channel 2 Write Enable. Set to 1 to update the control byte for channel 2. Set to 0 to make no changes to
channel 2.
D5
LLEAK
Low-Leakage Select. Set to 1 to put driver, load, and clamps into low-leakage mode. Comparators remain
active in low-leakage mode. Set to 0 for normal operation.
D4
TMSEL
Driver Termination Select. Set to 1 to force the driver output to the DTV_ voltage when RCV_ = 1 (term). Set to
0 to place the driver into high-impedance mode when RCV_ = 1 (high-Z). See Table 1.
D3
SC1
D2
SC0
D1
LDDIS
Load Disable. Set LDDIS to 1 to disable the load. Set to 0 for normal operation. See Table 4.
D0
LDCAL
Load Calibrate. Overrides LDEN to enable load. Set LDCAL to 1 to enable load. Set LDCAL to 0 for normal
operation. See Table 4.
26
DESCRIPTION
Driver Slew-Rate Select. SC1 and SC0 set the driver slew rate. See Table 2.
______________________________________________________________________________________
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
Heat Removal
Under normal circumstances, the MAX9967 requires
heat removal through the exposed pad by use of an
external heat sink. The exposed pad is electrically at
VEE potential, and must be either connected to VEE or
isolated.
Power dissipation is highly dependent upon the application. The Electrical Characteristics Table indicates
power dissipation under the condition that the source
and sink currents are programmed to 0mA. Maximum
dissipation occurs when the source and sink currents
are both at 35mA, the VDUT_ is at an extreme of the
voltage range (-1.5V or +6.5V), and the diode bridge is
fully commutated. Under these conditions, the additional power dissipated (per channel) is:
If the DUT is sourcing current, ∆PD = (VDUT_ - VEE) x
ISOURCE + (VCC - VEE) x ISINK.
If the DUT is sinking current, ∆PD = (VCC - VDUT_) x
ISINK + (VCC - VEE) x ISOURCE.
The DUT sources the programmed (low) current when
VDUT_ > VCOM_. The path of the current is from the
DUT through the outside of the diode bridge and the
source (low) current source to VEE. The programmed
sink current flows from VCC through the sink (high) current source, the inside of the diode bridge, and the
commutation buffer to VEE.
The DUT sinks the programmed (high) current when
VDUT_ < VCOM_. The path of the current is from VCC
through the sink (high) current source and the outside
of the diode bridge to the DUT. The programmed
source current flows from VCC through the commutation
buffer, the inside of the diode bridge, and the source
(low) current source to VEE.
Theta J-C of the exposed-pad package is very low,
approximately 3°C/W to 4°C/W. Die temperature is thus
highly dependent upon the heat-removal techniques
used in the application.
Maximum total power dissipation occurs under the following conditions:
• VCC = +10.5V
• VEE = -6.5V
• ISOURCE = ISINK = 35mA for both channels
• Load enabled
• VDUT_ = +6.5V
• VCOM_ < +5.5V
Under these extreme conditions, the total power dissipation is approximately 6W. If the die temperature cannot be maintained at an acceptable level under these
conditions, use software clamping to limit the load output currents to lower values and/or reduce the supply
voltages.
Chip Information
TRANSISTOR COUNT: 5656
PROCESS: Bipolar
______________________________________________________________________________________
27
MAX9967
Temperature Monitor
The MAX9967 supplies a temperature output signal,
TEMP, that asserts a nominal output voltage of 3.43V at
a die temperature of +70°C (343K). The output voltage
increases proportionately with temperature.
MAX9967
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
Typical Application Circuits (Simplified)
RB-RE
RCOM
REFERENCE
INPUT
RXA
RXD
SENSE
IN
FORCE
FORCE
MAIN
AMP
400Ω
DHV
TO ADC
MSR
~45Ω
DTV
DLV
CURRENTSENSE AMP
10kΩ
DUT
PMU
DCL
MAX9949F
MAX9950F
DRIVER IN LOW-LEAKAGE MODE
MAX9967
SENSE
INTERFACING TO PMU WITHOUT EXTERNAL RELAYS. PMU
SOURCING 2mA OR LESS.
REFERENCE INPUTS
RB-RE
RCOM
REFERENCE
INPUT
RXA
RXD
SENSE
IN
FORCE
FORCE
MAIN
AMP
400Ω
DHV
DTV
DLV
CURRENTSENSE AMP
MSR
TO ADC
INTERFACING TO PMU WITHOUT EXTERNAL RELAYS. DCL
SOURCING UP TO 60mA.
28
10kΩ
~45Ω
DUT
PMU
DCL
MAX9949F
MAX9950F
DRIVER = DTV
MAX9967
SENSE
REFERENCE INPUTS
______________________________________________________________________________________
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
PART
ACCURACY
GRADE
HIGH-SPEED DIGITAL INPUT
TERMINATION
COMPARATOR
OUTPUT
TYPE
COMPARATOR
OUTPUT
TERMINATION
RCV_
DATA_
LDEN_
HEAT
EXTRACTION
MAX9967ADCCQ
A
Open collector
None
None
None
None
Top
MAX9967AGCCQ
A
Open collector
None
100
100
100
Top
MAX9967ALCCQ
A
Open collector
50Ω to VCCO_
100
100
100
Top
MAX9967AMCCQ
A
Open emitter
ECL/LVPECL
None
None
None
Top
MAX9967AQCCQ
A
Open emitter
ECL/LVPECL
100
100
100
Top
MAX967ARCCQ
A
Open collector
50Ω to VCCO_
None
100
100
Top
MAX9967BDCCQ
B
Open collector
None
None
None
None
Top
MAX9967BGCCQ
B
Open collector
None
100
100
100
Top
MAX9967BLCCQ
B
Open collector
50Ω to VCCO_
100
100
100
Top
MAX9967BMCCQ
B
Open emitter
ECL/LVPECL
None
None
None
Top
MAX9967BQCCQ
B
Open emitter
ECL/LVPECL
100
100
100
Top
MAX9967BRCCQ
B
Open collector
50Ω to VCCO_
None
100
100
Top
______________________________________________________________________________________
29
MAX9967
Selector Guide
82
81
N.C.
83
LDH1
84
LDL1
85
VEE
86
COM1
87
VEE
88
GND
89
VCC
90
GND
91
VCC
92
CL1
93
VCCO1
VCC
94
NCL1
CPHV1
95
CH1
CPLV1
96
NCH1
DHV1
97
GND
DTV1
98
VEE
DLV1
100 99
CLV1
CHV1
Pin Configuration
80
79
78
77
76
TEMP
1
75 TDATA1
VEE
2
74 NDATA1
GND
3
73 DATA1
VCC
4
72 TRCV1
GND
5
71 NRCV1
FORCE1
6
70 RCV1
DUT1
7
69 TLDEN1
SENSE1
8
68 NLDEN1
VEE
9
67 LDEN1
GND 10
66 VCC
VCC 11
65 DIN
VEE 12
64 SCLK
GS 13
63 THR
MAX9967
VEE 14
62 CS
VCC 15
61 RST
GND 16
60 VEE
VEE 17
59 LDEN2
SENSE2 18
58 NLDEN2
DUT2 19
57 TLDEN2
FORCE2 20
56 RCV2
42
43
44
45
46
47
48
49
50
LDH2
N.C.
41
LDL2
40
COM2
39
VEE
38
VEE
37
GND
36
VCC
35
GND
34
VCC
33
CL2
32
NCL2
31
VCCO2
30
CH2
29
NCH2
28
VEE
27
GND
26
VCC
51 TDATA2
CPLV2
GND 25
CPHV2
52 NDATA2
DHV2
53 DATA2
VEE 24
DTV2
54 TRCV2
GND 23
DLV2
55 NRCV2
VCC 22
CLV2
GND 21
CHV2
MAX9967
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
Package Information
For the latest package outline information, go to
www.maxim-ic.com/packages.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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is a registered trademark of Maxim Integrated Products, Inc.