AD ADUC7036 Integrated precision battery sensor for automotive Datasheet

Integrated Precision Battery Sensor
for Automotive
ADuC7036
FEATURES
Memory
96 kB Flash/EE memory, 6 kB SRAM
10,000-cycle Flash/EE endurance, 20-year Flash/EE
retention
In-circuit download via JTAG and LIN
On-chip peripherals
SAEJ2602/LIN 2.0-compatible (slave) support via UART
with hardware synchronization
Flexible wake-up I/O pin, master/slave SPI serial I/O
9-pin GPIO port, 3× general-purpose timers
Wake-up and watchdog timers
Power supply monitor and on-chip power-on reset
Power
Operates directly from 12 V battery supply
Current consumption
Normal mode 10 mA at 10 MHz
Low power monitor mode
Package and temperature range
48-lead, 7 mm × 7 mm LFCSP
Fully specified for −40°C to +115°C operation
High precision ADCs
Dual channel, simultaneous sampling, 16-bit, Σ-Δ ADCs
Programmable ADC throughput from 1 Hz to 8 kHz
On-chip ±5 ppm/°C voltage reference
Current channel
Fully differential, buffered input
Programmable gain from 1 to 512
ADC input range: −200 mV to +300 mV
Digital comparators with current accumulator feature
Voltage channel
Buffered, on-chip attenuator for 12 V battery inputs
Temperature channel
External and on-chip temperature sensor options
Microcontroller
ARM7TDMI core, 16-/32-bit RISC architecture
20.48 MHz PLL with programmable divider
PLL input source
On-chip precision oscillator
On-chip low power oscillator
External (32.768 kHz) watch crystal
JTAG port supports code download and debug
APPLICATIONS
Battery sensing/management for automotive systems
TMS
NTRST
TDO
TDI
TCK
FUNCTIONAL BLOCK DIAGRAM
ADuC7036
PRECISION ANALOG ACQUISITION
IIN+
PGA
BUF
IIN–
RESET
MEMORY
98kB FLASH
6kB RAM
2.6V LDO
PSM
POR
16-BIT
Σ-∆ ADC
VBAT
XTAL1
RESULT
ACCUMULATOR
MUX
VTEMP
DIGITAL
COMPARATOR
20MHz
16-BIT
Σ-∆ ADC
BUF
XTAL2
WU
GPIO PORT
UART PORT
SPI PORT
LIN
3× TIMERS
WDT
WU TIMER
PRECISION
REFERENCE
TEMPERATURE
SENSOR
PRECISION
OSC
LOW POWER
OSC
ON-CHIP PLL
ARM7TDMI
MCU
VREF
STI
LIN/BSD
07474-001
GPIO_8/IRQ5
GPIO_6/TxD
GPIO_7/IRQ4
GPIO_4/ECLK
GPIO_5/IRQ1/RxD
GPIO_3/MOSI
GPIO_2/MISO
GPIO_1/SCLK
GPIO_0/IRQ0/SS
VSS
IO_VSS
DGND
AGND
REG_DVDD
VDD
REG_AVDD
GND_SW
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2011 Analog Devices, Inc. All rights reserved.
ADuC7036
TABLE OF CONTENTS
Features .............................................................................................. 1
Interrupt System ......................................................................... 68
Applications....................................................................................... 1
Timers .............................................................................................. 71
Functional Block Diagram .............................................................. 1
Synchronization Across Asynchronous Clock Domains ...... 71
Revision History ............................................................................... 3
Programming the Timers.......................................................... 72
Specifications..................................................................................... 4
Timer0—Lifetime Timer........................................................... 74
Electrical Specifications............................................................... 4
Timer1—General-Purpose Timer ........................................... 76
Timing Specifications ................................................................ 10
Timer2—Wake-Up Timer......................................................... 78
Absolute Maximum Ratings.......................................................... 15
Timer3—Watchdog Timer........................................................ 80
ESD Caution................................................................................ 15
Timer4—STI Timer ................................................................... 82
Pin Configuration and Function Descriptions........................... 16
General-Purpose I/O ..................................................................... 84
Typical Performance Characteristics ........................................... 18
High Voltage Peripheral Control Interface ................................. 95
Terminology .................................................................................... 19
Wake-UP (WU) Pin................................................................. 102
Theory of Operation ...................................................................... 20
Overview of the ARM7TDMI Core......................................... 20
Handling Interrupts from the High Voltage Peripheral
Control Interface ...................................................................... 103
Memory Organization ............................................................... 22
Low Voltage Flag (LVF)........................................................... 103
Reset ............................................................................................. 24
High Voltage Diagnostics........................................................ 103
Flash/EE Memory........................................................................... 25
UART Serial Interface .................................................................. 104
Programming Flash/EE Memory In-Circuit .......................... 25
Baud Rate Generation.............................................................. 104
Flash/EE Control Interface........................................................ 25
UART Register Definitions ..................................................... 105
Flash/EE Memory Security ....................................................... 29
Serial Peripheral Interface ........................................................... 110
Flash/EE Memory Reliability.................................................... 31
MISO Pin................................................................................... 110
Code Execution Time from SRAM and Flash/EE ..................... 31
MOSI Pin................................................................................... 110
On-Chip Kernel .......................................................................... 32
SCLK Pin ................................................................................... 110
Memory Mapped Registers ....................................................... 35
SS Pin ......................................................................................... 110
Complete MMR Listing............................................................. 36
SPI Register Definitions .......................................................... 110
16-Bit, Σ-Δ Analog-to-Digital Converters .................................. 42
Serial Test Interface ...................................................................... 113
Current Channel ADC (I-ADC) .............................................. 42
LIN (Local Interconnect Network) Interface............................ 116
ADC Ground Switch.................................................................. 45
LIN MMR Description ............................................................ 116
ADC Noise Performance Tables............................................... 45
LIN Hardware Interface .......................................................... 120
ADC MMR Interface ................................................................. 46
Bit Serial Device (BSD) Interface ............................................... 124
ADC Power Modes of Operation............................................. 55
BSD Communication Hardware Interface............................ 124
ADC Comparator and Accumulator ....................................... 56
BSD Related MMRs ................................................................. 125
ADC Sinc3 Digital Filter Response.......................................... 56
BSD Communication Frame .................................................. 126
ADC Calibration ........................................................................ 59
BSD Data Reception................................................................. 127
ADC Diagnostics........................................................................ 60
BSD Data Transmission........................................................... 127
Power Supply Support Circuits..................................................... 61
Wake-Up from BSD Interface................................................. 127
System Clocks ................................................................................. 62
Part Identification......................................................................... 128
System Clock Registers .............................................................. 63
Schematic....................................................................................... 131
Low Power Clock Calibration................................................... 66
Outline Dimensions ..................................................................... 132
Processor Reference Peripherals................................................... 68
Ordering Guide ........................................................................ 132
Rev. C | Page 2 of 132
ADuC7036
REVISION HISTORY
2/11—Rev. B to Rev. C
Changes to IDD (MCU Normal Mode) Parameter, Table 1 ..........9
Changes to On-Chip Kernel Section ............................................32
Added Figure 16; Renumbered Sequentially ...............................34
Changes to Table 100 ....................................................................130
Changes to Ordering Guide.........................................................132
4/10—Rev. A to Rev. B
Changes to Table 6 ..........................................................................15
Changes to Timers Section ............................................................70
7/09—Rev. 0 to Rev. A
Changes to Features Section ............................................................1
Changes to Figure 1...........................................................................1
Changes to Table 1 ....................................................................4, 8, 9
Changes to Table 3 ..........................................................................11
Changes to Table 4 ..........................................................................12
Changes to Table 5 ..........................................................................13
Changes to Figure 8, Figure 9, and Figure 10..............................18
Changes to Theory of Operation Section ....................................20
Changes to Flash/EE Memory Reliability Section......................31
Changes to Table 46 ........................................................................64
Changes to Normal Interrupt (IRQ) Request Section ...............68
Changes to Timer0—Liftime Timer Section...............................71
Changes to Timer1 Section............................................................73
Changes to Timer2—Wake-Up Timer Section ...........................75
Changes to Timer3 Interface Section ...........................................77
Changes to Timer4—STI Timer Section .....................................79
Changes to BSD Communication Frame Section.....................123
Changes to Table 97 ......................................................................125
Changes to Figure 57 ....................................................................128
Changes to Ordering Guide.........................................................129
10/08—Revision 0: Initial Version
Rev. C | Page 3 of 132
ADuC7036
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VDD = 3.5 V to 18 V, VREF = 1.2 V internal reference, fCORE = 20.48 MHz (unless otherwise noted) driven from external 32.768 kHz
watch crystal or on-chip precision oscillator. All specifications TA = −40°C to +115°C, unless otherwise noted.
Table 1.
Parameter
ADC SPECIFICATIONS
Conversion Rate 1
Current Channel
No Missing Codes1
Integral Nonlinearity1, 2
Offset Error2, 3 , 4 , 5
Offset Error1, 3, 6
Offset Error1, 3
Offset Error1, 3
Offset Error Drift6
Offset Error Drift6
Offset Error Drift6
Total Gain Error1, 3, 7 , 8 , 9 , 10
Total Gain Error1, 3, 7, 9
Total Gain Error1, 3, 7, 9, 11
Gain Drift
PGA Gain Mismatch Error
Output Noise1, 12
Test Conditions/Comments
Min
Chop off, ADC normal operating mode
Chop on, ADC normal operating mode
Chop on, ADC low power mode
4
4
1
Valid for all ADC update rates and ADC modes
16
Chop off, 1 LSB = (36.6/gain) μV
Chop on
Chop on, low power or low power plus mode, MCU
powered down
Chop on, normal mode
Chop off, valid for ADC gains of 4 to 64, normal mode
Chop off, valid for ADC gains of 128 to 512, normal
mode
Chop on
Normal mode
Low power mode, using ADCREF MMR
Low power plus mode, using precision VREF
4 Hz update rate, gain = 512, ADCFLT = 0xBF1D
4 Hz update rate, gain = 512, ADCFLT = 0x3F1D
10 Hz update rate, gain = 512, ADCFLT = 0x961F
10 Hz update rate, gain = 512, ADCFLT = 0x161F
1 kHz update rate, gain ≥ 64, ADCFLT = 0x8101
1 kHz update rate, gain ≥ 64, ADCFLT = 0x0101
1 kHz update rate, gain = 512, ADCFLT = 0x0007
1 kHz update rate, gain = 32, ADCFLT = 0x0007
1 kHz update rate, gain = 8, ADCFLT = 0x8101
1 kHz update rate, gain = 8, ADCFLT = 0x0007
1 kHz update rate, gain = 8, ADCFLT = 0x0101
1 kHz update rate, gain = 4, ADCFLT = 0x0007
8 kHz update rate, gain = 32, ADCFLT = 0x0000
8 kHz update rate, gain = 4, ADCFLT = 0x0000
ADC low power mode, fADC = 10 Hz, gain = 128
ADC low power mode, fADC = 1 Hz, gain = 128
ADC low power plus mode, fADC = 1 Hz, gain = 512
ADC low power plus mode, fADC = 250 Hz, gain = 512
Rev. C | Page 4 of 132
−10
−2
100
+0.5
−0.5
−4
−1
Typ
Max
Unit
8000
2600
650
Hz
Hz
Hz
±10
±3
±0.5
−50
±60
+10
+2
−300
Bits
ppm of FSR
LSB
μV
nV
−1.25
0.03
30
−3
10
±0.1
±0.2
±0.2
3
±0.1
60
75
100
120
0.8
1
0.6
0.8
2.1
1.6
2.6
2.0
2.5
14
1.25
0.35
0.1
0.6
μV
LSB/°C
nV/°C
nV/°C
+0.5
+4
+1
%
%
%
ppm/°C
%
90
115
150
180
1.2
1.5
0.9
1.2
4.1
2.4
3.9
2.8
3.5
21
1.9
0.5
0.15
0.9
nV rms
nV rms
nV rms
nV rms
μV rms
μV rms
μV rms
μV rms
μV rms
μV rms
μV rms
μV rms
μV rms
μV rms
μV rms
μV rms
μV rms
μV rms
ADuC7036
Parameter
Voltage Channel 13
No Missing Codes1
Integral Nonlinearity1
Offset Error3, 5
Offset Error1, 3
Offset Error Drift
Total Gain Error1, 3, 7, 10, 14
Total Gain Error1, 3, 7, 10, 14
Gain Drift
Output Noise1, 12, 15
Temperature Channel
No Missing Codes1
Integral Nonlinearity1
Offset Error3, 4, 5, 16
Offset Error1, 3
Offset Error Drift
Total Gain Error1, 3, 14
Gain Drift
Output Noise1
ADC SPECIFICATIONS ANALOG INPUT
Current Channel
Absolute Input Voltage Range
Input Voltage Range 17 , 18
Input Leakage Current1
Input Offset Current1, 20
Voltage Channel
Absolute Input Voltage Range
Input Voltage Range
VBAT Input Current
Temperature Channel
Absolute Input Voltage Range
Input Voltage Range
Test Conditions/Comments
Min
Valid at all ADC update rates
16
Chop off, 1 LSB = 439.5 μV
Chop on
Chop off
Includes resistor mismatch
Temperature range = −25°C to +65°C
Includes resistor mismatch drift
4 Hz update rate, ADCFLT = 0xBF1D
10 Hz update rate, ADCFLT = 0x961F
1 kHz update rate, ADCFLT = 0x0007
1 kHz update rate, ADCFLT = 0x8101
1 kHz update rate, ADCFLT = 0x0101
8 kHz update rate, ADCFLT = 0x0000
−10
Valid at all ADC update rates
16
Chop off, 1 LSB = 19.84 μV in unipolar mode
Chop on
Chop off
Using REG_AVDD as the reference
−0.25
−0.15
−10
−5
−0.2
1 kHz update rate
Internal VREF = 1.2 V
Applies to both IIN+ and IIN−
Gain = 1 19
Gain = 219
Gain = 419
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Gain = 256
Gain = 512
Typ
Max
±10
±1
0.3
0.03
±0.06
±0.03
3
60
60
180
240
270
1600
±60
+10
1
±10
±3
+1
0.03
±0.06
3
7.5
±60
+10
+5
−200
4
11.25
3
+3
1.5
18
0 to 28.8
5.5
100
0 to
VREF
2.5
Rev. C | Page 5 of 132
+0.2
+300
0.5
VTEMP Input Current1
90
90
270
307
405
2400
±1.2
±600
±300
±150
±75
±37.5
±18.75
±9.375
±4.68
±2.3
−3
VBAT = 18 V
VREF = (REG_AVDD and GND_SW)/2
+0.25
+0.15
8
Unit
Bits
ppm of FSR
LSB
LSB
LSB/°C
%
%
ppm/°C
μV rms
μV rms
μV rms
μV rms
μV rms
μV rms
Bits
ppm of FSR
LSB
LSB
LSB/°C
%
ppm/°C
μV rms
mV
V
mV
mV
mV
mV
mV
mV
mV
mV
mV
nA
nA
V
V
μA
1300
mV
V
100
nA
ADuC7036
Parameter
VOLTAGE REFERENCE
ADC Precision Reference
Internal VREF
Power-Up Time1
Initial Accuracy1
Temperature Coefficient1, 21
Reference Long-Term Stability 22
External Reference Input Range 23
VREF Divide-by-2 Initial Error1
ADC Low Power Reference
Internal VREF
Initial Accuracy
Initial Accuracy1
Temperature Coefficient1, 21
ADC DIAGNOSTICS
VREF/1361
Voltage Attenuator Current
Source1
RESISTIVE ATTENUATOR
Divider Ratio
Resistor Mismatch Drift
ADC GROUND SWITCH
Resistance
Resistance1
Input Current
TEMPERATURE SENSOR 24
Accuracy
POWER-ON RESET (POR)
POR Trip Level
POR Hysteresis
Reset Timeout from POR
LOW VOLTAGE FLAG (LVF)
LVF Level
POWER SUPPLY MONITOR (PSM)
PSM Trip Level
WATCHDOG TIMER (WDT)
Timeout Period1
Timeout Step Size
FLASH/EE MEMORY1
Endurance 25
Data Retention 26
DIGITAL INPUTS
Input Leakage Current
Input Pull-Up Current
Input Capacitance
Input Leakage Current
Input Pull-Down Current
Test Conditions/Comments
Min
Typ
Max
1.2
0.5
Measured at TA = 25°C
−0.15
−20
±5
100
0.1
0.1
+0.15
+20
1.3
0.3
1.2
Measured at TA = 25°C
Using ADCREF, measured at TA = 25°C
−5
−300
At any gain settings
Differential voltage increase on the attenuator
when the current source is on, temperature range =
−40°C to +85°C
8.5
3.1
+300
9.4
3.8
mV
V
24
3
Direct path to ground
20 kΩ resistor selected
Allowed contunious current through the switch
with direct path to ground
After user calibration
MCU in power-down or standby mode
MCU in power-down or standby mode,
temperature range = −25°C to +65°C
10
10
20
V
ms
%
ppm/°C
ppm/1000 hr
V
%
V
%
%
ppm/°C
+5
0.1
±150
Unit
ppm/°C
30
6
±3
±2
Ω
kΩ
mA
°C
°C
Refers to voltage at VDD pin
2.85
3
300
20
3.15
V
mV
ms
Refers to voltage at VDD pin
1.9
2.1
2.3
V
Refers to voltage at VDD pin
32.768 kHz clock, 256 prescale
6
0.008
V
512
7.8
10,000
20
All digital inputs except NTRST
Input high = REG_DVDD
Input low = 0 V
−80
NTRST only: input low = 0 V
NTRST only: input high = REG_DVDD
30
Rev. C | Page 6 of 132
sec
ms
Cycles
Years
±1
−20
10
±1
55
±10
−10
±10
100
μA
μA
pF
μA
μA
ADuC7036
Parameter
LOGIC INPUTS1
VINL, Input Low Voltage
VINH, Input High Voltage
CRYSTAL OSCILLATOR1
Logic Inputs, XTAL1 Only
VINL, Input Low Voltage
VINH, Input High Voltage
XTAL1 Capacitance
XTAL2 Capacitance
ON-CHIP OSCILLATORS
Low Power Oscillator
Accuracy 27
Precision Oscillator
Accuracy
MCU CLOCK RATE
MCU START-UP TIME
At Power-On
After Reset Event
From MCU Power-Down
Oscillator Running
Wake Up from Interrupt
Wake Up from LIN
Crystal Powered Down
Wake Up from Interrupt
Internal PLL Lock Time
LIN INPUT/OUTPUT GENERAL
Baud Rate
VDD
Input Capacitance
Input Leakage Current
LIN Comparator Response Time1
ILIN_DOM_MAX
ILIN_PAS_REC
ILIN1
ILIN_PAS_DOM1
ILIN_NO_GND 28
VLIN_DOM1
VLIN_REC1
VLIN_CNT1
VHYS1
VLIN_DOM_DRV_LOSUP1
RLOAD = 500 Ω
RLOAD = 1000 Ω
VLIN_DOM_DRV_HISUP1
RLOAD = 500 Ω
RLOAD = 1000 Ω
VLIN_RECESSIVE
VBAT Shift28
GND Shift28
Test Conditions/Comments
All logic inputs
Min
Typ
Max
Unit
0.4
V
V
0.8
V
V
pF
pF
2
1.7
12
12
131.072
Includes drift data from 1000 hour life test
−3
Includes drift data from 1000 hour life test
Eight programmable core clock selections within
this range (binary divisions 1, 2, 4, 8,…64, 128)
−1
0.16
+3
131.072
Includes kernel power-on execution time
Includes kernel power-on execution time
Supply voltage range at which the LIN interface is
functional
10.24
+1
20.48
25
5
ms
ms
2
2
ms
ms
500
1
ms
ms
1000
7
20,000
18
Bits/sec
V
−400
90
200
pF
μA
μs
mA
5.5
Input (low) = IO_VSS
Using 22 Ω resistor
Current limit for driver when LIN bus is in
dominant state, VBAT = VBAT (max)
Driver off, 7 V < VLIN < 18 V, VDD = VLIN − 0.7 V
VBAT disconnected, VDD = 0 V, 0 < VLIN < 18 V
Input leakage VLIN = 0 V
Control unit disconnected from ground,
GND = VDD, 0 V < VLIN < 18 V, VBAT = 12 V
LIN receiver dominant state, VDD > 7 V
LIN receiver recessive state, VDD > 7 V
LIN receiver center voltage, VDD > 7 V
LIN receiver hysteresis voltage
LIN dominant output voltage, VDD = 7 V
−800
38
40
−20
+20
10
−1
−1
+1
0.4 VDD
0.6 VDD
0.475 VDD
kHz
%
kHz
%
MHz
0.5 VDD
0.525 VDD
0.175 VDD
μA
μA
mA
mA
V
V
V
V
1.2
V
V
2
V
V
V
V
V
0.6
LIN dominant output voltage, VDD = 18 V
LIN recessive output voltage
Rev. C | Page 7 of 132
0.8
0.8 VDD
0
0
0.1 VDD
0.1 VDD
ADuC7036
Parameter
RSLAVE
VSERIAL DIODE28
Symmetry of Transmit Propagation
Delay1
Receive Propagation Delay1
Symmetry of Receive Propagation
Delay1
LIN VERSION 1.3 SPECIFICATION
dV
dt
1
dV
dt
1
tSYM1
LIN VERSION 2.0 SPECIFICATION
D1
D2
BSD INPUT/OUTPUT 29
Baud Rate
Input leakage current
VOL, Output Low Voltage
VOH, Output High Voltage
IO(SC) Short-Circuit Output Current
VINL, Input Low Voltage
VINH, Input High Voltage
WAKE UP
VDD1
Input Leakage Current
VOH 30
VOL30
VIH
VIL
Monoflop Timeout
IO(SC) Short-Circuit Output Current
SERIAL TEST INTERFACE
Baud Rate
Input Leakage Current
VDD
VOH
VOL
VIH
VIL
Test Conditions/Comments
Slave termination resistance
Voltage drop at the serial diode, DSER_INT
VDD (min) = 7 V
Min
20
0.4
−2
VDD (min) = 7 V
VDD (min) = 7 V
−2
Bus load conditions (CBUS||RBUS):1 nF||1 kΩ;
6.8 nF||660 Ω; 10 nF||500 Ω
Slew rate
Dominant and recessive edges, VBAT = 18 V
1
Typ
30
0.7
2
Max
47
1
+2
Unit
kΩ
V
μs
6
+2
μs
μs
3
V/μs
Slew rate
Dominant and recessive edges, VBAT = 7 V
0.5
3
V/μs
Symmetry of rising and falling edge, VBAT = 18 V
Symmetry of rising and falling edge, VBAT = 7 V
−5
−4
+5
+4
μs
μs
Bus load conditions (CBUS||RBUS): 1 nF||1 kΩ;
6.8 nF||660 Ω; 10 nF||500 Ω
Duty Cycle 1,
THREC (MAX) = 0.744 × VBAT,
THDOM (MAX) = 0.581 × VBAT,
VSUP = 7 V…18 V; tBIT = 50 μs,
D1 = tBUS_REC (MIN)/(2 × tBIT)
Duty Cycle 2,
THREC (MIN) = 0.284 × VBAT,
THDOM (MIN) = 0.422 × VBAT,
VSUP = 7 V…18 V; tBIT = 50 μs,
D2 = tBUS_REC (MAX)/(2 × tBIT)
0.396
0.581
Input high = VDD, or input low = IO_VSS
1164
−50
VBSD = VDD = 12 V
0.8 VDD
50
1200
1236
+50
1.2
80
120
1.8
0.7 VDD
RLOAD = 300 Ω, CBUS = 91 nF, RLIMIT = 39 Ω
Supply voltage range at which the WU pin is
functional
Input high = VDD
Input low = IO_VSS
Output high level
Output low level
Input high level
Input low level
Timeout period
Bits/sec
μA
V
V
mA
V
V
7
18
V
0.4
−50
5
2.1
+50
mA
μA
V
V
V
V
sec
mA
2
4.6
0.6
100
1.3
140
1.2
2
RLOAD = 500 Ω, CBUS = 2.4 nF, RLIMIT = 39 Ω
Input high = VDD or input low = IO_VSS
Supply voltage range for which STI is functional
Output high level
Output low level
Input high level
Input low level
Rev. C | Page 8 of 132
−50
7
0.6 VDD
40
+70
18
0.4 VDD
0.6 VDD
0.4 VDD
kbps
μA
V
V
V
V
V
ADuC7036
Parameter
PACKAGE THERMAL SPECIFICATIONS
Thermal Shutdown1, 31
Thermal Impedance (θJA) 32
POWER REQUIREMENTS
Power Supply Voltages
VDD (Battery Supply)
REG_DVDD, REG_AVDD 33
Power Consumption
IDD (MCU Normal Mode) 34
IDD (MCU Powered Down)1
IDD (MCU Powered Down)
Test Conditions/Comments
Min
Typ
Max
Unit
140
150
45
160
°C
°C/W
2.6
18
2.7
V
V
10
20
20
30
mA
mA
300
400
μA
300
500
μA
520
700
μA
120
300
μA
120
175
μA
48-lead LFCSP, stacked die
3.5
2.5
MCU clock rate = 10.24 MHz, ADC off
MCU clock rate = 20.48 MHz, ADC off (valid for
ADuC7036CCPZ and ADuC7036DCPZ only)
ADC low power mode, measured over the range of
TA = −10°C to +40°C, continuous ADC conversion
ADC low power mode, measured over the range of
TA = −40°C to +85°C, continuous ADC conversion
ADC low power plus mode, measured over the
range of TA = −10°C to +40°C, continuous ADC
conversion
Average current, measured with wake-up and
watchdog timer clocked from the low power
oscillator, TA = −40°C to +85°C
Average current, measured with wake-up and
watchdog timer clocked from low power oscillator
over a range of TA = −10°C to +40°C
IDD (Current ADC)
IDD (Voltage/Temperature ADC)
IDD (Precision Oscillator)
1.7
0.5
400
1
mA
mA
μA
These numbers are not production tested but are guaranteed by design and/or characterization data at production release.
Valid for current ADC gain setting of PGA = 4 to 64.
3
These numbers include temperature drift.
4
Tested at gain range = 4; self-offset calibration removes this error.
5
Measured with an internal short after an initial offset calibration.
6
Measured with an internal short.
7
These numbers include internal reference temperature drift.
8
Factory-calibrated at gain = 1.
9
System calibration at a specific gain range (and temperature) removes the error at this gain range (and temperature).
10
Includes an initial system calibration.
11
Using ADC normal mode voltage reference.
12
Typical noise in low power modes is measured with chop enabled.
13
Voltage channel specifications include resistive attenuator input stage.
14
System calibration removes this error at the specified temperature.
15
RMS noise is referred to voltage attenuator input (for example, at fADC = 1 kHz, typical rms noise at the ADC input is 7.5 μV) and scaled by the attenuator (divide-by-24)
to yield these input referred noise specifications/values.
16
Valid after an initial self-calibration.
17
In ADC low power mode, the input range is fixed at ±9.375 mV. In ADC low power plus mode, the input range is fixed at ±2.34375 mV.
18
It is possible to extend the ADC input range by up to 10% by modifying the factory set value of the gain calibration register or using system calibration. This approach
can also be used to reduce the ADC input range (LSB size).
19
Limited by minimum/maximum absolute input voltage range.
20
Valid for a differential input less than 10 mV.
21
Measured using box method.
22
The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
23
References of up to REG_AVDD can be accommodated by enabling an internal divide-by-2.
24
Die temperature.
25
Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.
26
Retention lifetime equivalent at junction temperature (TJ) of 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.
27
Low power oscillator can be calibrated against either the precision oscillator or the external 32.768 kHz crystal in user code.
28
These numbers are not production tested, but are supported by LIN compliance testing.
29
BSD electrical specifications, except high and low voltage levels, are per LIN 2.0 with pull-up resistor disabled and CL = 10 nF maximum.
30
Specified after RLIMIT of 39 Ω.
31
The MCU core is not shut down but interrupted, and high voltage I/O pins are disabled in response to a thermal shutdown event.
32
Thermal impedance can be used to calculate the thermal gradient from ambient to die temperature.
33
Internal regulated supply available at REG_DVDD (ISOURCE = 5 mA), and REG_AVDD (ISOURCE = 1 mA).
34
The specification listed is typical; additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively.
2
Rev. C | Page 9 of 132
ADuC7036
TIMING SPECIFICATIONS
SPI Timing Specifications
Table 2. SPI Master Mode Timing—Phase Mode = 1
Parameter
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
2
Min
Typ
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
Max
(2 × tUCLK) + (2 × tHCLK)
0
3 × tUCLK
3.5
3.5
3.5
3.5
tHCLK depends on the clock divider (CD) bits in the POWCON MMR. tHCLK = tUCLK/2CD.
tUCLK = 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDF
MSB
MOSI
MISO
tDR
MSB IN
tDSU
BITS[6:1]
BITS[6:1]
tDHD
Figure 2. SPI Master Mode Timing—Phase Mode = 1
Rev. C | Page 10 of 132
LSB
LSB IN
07474-002
1
Description
SCLK low pulse width 1
SCLK high pulse width1
Data output valid after SCLK edge 2
Data input setup time before SCLK edge
Data input hold time after SCLK edge2
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADuC7036
Table 3. SPI Master Mode—Phase Mode = 0
Parameter
tSL
tSH
tDAV
tDOSU
tDSU
tDHD
tDF
tDR
tSR
tSF
2
Min
Typ
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
Max
(2 × tUCLK) + (2 × tHCLK)
0.5 tSL
0
3 × tUCLK
3.5
3.5
3.5
3.5
tHCLK depends on the clock divider (CD) bits in the POWCON MMR. tHCLK = tUCLK/2CD.
tUCLK = 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDF
tDOSU
MSB
MOSI
MISO
MSB IN
tDSU
tDR
BITS[6:1]
BITS[6:1]
LSB
LSB IN
07474-003
1
Description
SCLK low pulse width 1
SCLK high pulse width1
Data output valid after SCLK edge 2
Data output setup before SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge2
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
tDHD
Figure 3. SPI Master Mode Timing—Phase Mode = 0
Rev. C | Page 11 of 132
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADuC7036
Table 4. SPI Slave Mode Timing—Phase Mode = 1
Parameter
tSS
Description
SS to SCLK edge
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tSFS
SCLK low pulse width 1
SCLK high pulse width1
Data output valid after SCLK edge 2
Data input setup time before SCLK edge
Data input hold time after SCLK edge2
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
SS high after SCLK edge
2
Typ
0.5 tSL
Max
Unit
ns
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
(3 × tUCLK) + (2 × tHCLK)
0
4 × tUCLK
3.5
3.5
3.5
3.5
0.5 tSL
tHCLK depends on the clock divider (CD) bits in the POWCON MMR. tHCLK = tUCLK/2CD.
tUCLK = 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
SS
tSFS
tSS
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDF
MISO
MOSI
tDR
MSB
MSB IN
tDSU
BITS[6:1]
BITS[6:1]
tDHD
Figure 4. SPI Slave Mode Timing—Phase Mode = 1
Rev. C | Page 12 of 132
LSB
LSB IN
07474-004
1
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADuC7036
Table 5. SPI Slave Mode Timing (Phase Mode = 0)
Parameter
tSS
Description
SS to SCLK edge
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tDOCS
tSFS
SCLK low pulse width 1
SCLK high pulse width1
Data output valid after SCLK edge1, 2
Data input setup time before SCLK edge
Data input hold time after SCLK edge1, 2
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
Data output valid after SS edge2
SS high after SCLK edge
2
Typ
0.5 tSL
Max
Unit
ns
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
(3 × tUCLK) + (2 × tHCLK)
0
4 × tUCLK
3.5
3.5
3.5
3.5
(3 × tUCLK) + (2 × tHCLK)
0.5 tSL
tHCLK depends on the clock divider (CD) bits in the POWCON MMR. tHCLK = tUCLK/2CD.
tUCLK = 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
SS
tSFS
SCLK
(POLARITY = 0)
tSS
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDOCS
tDF
MSB
MISO
MOSI
MSB IN
tDSU
tDR
BITS[6:1]
BITS[6:1]
LSB
LSB IN
07474-005
1
Min
tDHD
Figure 5. SPI Slave Mode Timing—Phase Mode = 0
Rev. C | Page 13 of 132
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADuC7036
LIN Timing Specifications
RECESSIVE
TRANSMIT
(INPUT TO
TRANSMITTING NODE)
tBIT
tBIT
tBIT
DOMINANT
tLIN_DOM (MAX)
tLIN_REC (MIN)
THRESHOLDS OF
RECEIVING NODE 1
THREC (MAX)
THDOM (MAX)
VSUP
LIN
BUS
(TRANSCEIVER SUPPLY
OF TRANSMITTING NODE)
THRESHOLDS OF
RECEIVING NODE 2
THREC (MIN)
THDOM (MIN)
tLIN_DOM (MIN)
tLIN_REC (MAX)
RxD
(OUTPUT OF RECEIVING NODE 1)
tRX_PDR
RxD
(OUTPUT OF RECEIVING NODE 2)
tRX_PDR
Figure 6. LIN 2.0 Timing Specification
Rev. C | Page 14 of 132
tRX_PDF
07474-006
tRX_PDF
ADuC7036
ABSOLUTE MAXIMUM RATINGS
TA = −40°C to +115°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 6.
Parameter
AGND to DGND to VSS to IO_VSS
VBAT to AGND
VDD to VSS
VDD to VSS for 1 sec
LIN to IO_VSS
STI and WU to IO_VSS
Wake-Up Continuous Current
High Voltage I/O Pins Short-Circuit
Current
Digital I/O Voltage to DGND
VREF to AGND
ADC Inputs to AGND
ESD Human Body Model (HBM) Rating
HBM-ADI0082 (Based on
ANSI/ESD STM5.1-2007).
All Pins except LIN and VBAT.
LIN and VBAT
IEC 61000-4-2 for LIN and VBAT
Storage Temperature
Junction Temperature
Transient
Continuous
Lead Temperature
Soldering Reflow (15 sec)
Rating
−0.3 V to +0.3 V
−22 V to +40 V
−0.3 V to +33 V
−0.3 V to +40 V
−16 V to +40 V
−3 V to +33 V
50 mA
100 mA
ESD CAUTION
−0.3 V to REG_DVDD + 0.3 V
−0.3 V to REG_AVDD + 0.3 V
−0.3 V to REG_AVDD + 0.3 V
1 kV
±6 kV
±7 kV
125°C
150°C
130°C
260°C
Rev. C | Page 15 of 132
ADuC7036
48
47
46
45
44
43
42
41
40
39
38
37
LIN/BSD
IO_VSS
STI
NC
VSS
NC
VDD
WU
NC
NC
NC
XTAL2
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RESET
GPIO_5/IRQ1/RxD
1
2
ADuC7036
TOP VIEW
(Not to Scale)
36
35
34
33
32
31
30
29
28
27
26
25
XTAL1
DGND
DGND
REG_DVDD
NC
GPIO_4/ECLK
GPIO_3/MOSI
GPIO_2/MISO
GPIO_1/SCLK
GPIO_0/IRQ0/SS
NC
NC
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD SHOULD BE CONNECTED TO DGND.
07474-007
VBAT
VREF
GND_SW
NC
NC
VTEMP
IIN+
IIN–
AGND
AGND
NC
REG_AVDD
13
14
15
16
17
18
19
20
21
22
23
24
GPIO_6/TxD 3
GPIO_7/IRQ4 4
GPIO_8/IRQ5 5
TCK 6
TDI 7
DGND 8
NC 9
TDO 10
NTRST 11
TMS 12
PIN 1
INDICATOR
Figure 7. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
Mnemonic
RESET
Type 1
I
2
GPIO_5/IRQ1/RxD
I/O
3
GPIO_6/TxD
I/O
4
GPIO_7/IRQ4
I/O
5
GPIO_8/IRQ5
I/O
6
TCK
I
7
TDI
I
8, 34, 35
9, 16, 17,
23, 25, 26,
32, 38 to
40, 43, 45
10
DGND
NC
S
TDO
O
Description
Reset Input Pin. Active low. This pin has an internal, weak pull-up resistor to REG_DVDD and
should be left unconnected when not in use. For added security and robustness, it is
recommended that this pin be strapped via a resistor to REG_DVDD.
General-Purpose Digital I/O 5/External Interrupt Request 1/Receive Data for UART Serial Port. By
default and after a power-on reset, this pin configures as an input. The pin has an internal, weak
pull-up resistor and should be left unconnected when not in use.
General-Purpose Digital I/O 6/Transmit Data for UART Serial Port. By default and after a poweron reset, this pin configures as an input. The pin has an internal, weak pull-up resistor and
should be left unconnected when not in use.
General-Purpose Digital I/O 7/External Interrupt Request 4. By default and after a power-on
reset, this pin configures as an input. The pin has an internal, weak pull-up resistor and should
be left unconnected when not in use.
General-Purpose Digital I/O 8/External Interrupt Request 5. By default and after a power-on
reset, this pin configures as an input. The pin has an internal, weak pull-up resistor and should
be left unconnected when not in use.
JTAG Test Clock. This clock input pin is one of the standard 5-pin JTAG debug ports on the part.
TCK is an input pin only and has an internal, weak pull-up resistor. This pin is left unconnected
when not in use.
JTAG Test Data Input. This data input pin is one of the standard 5-pin JTAG debug ports on the
part. TDI is an input pin only and has an internal, weak pull-up resistor. This pin can be left
unconnected when not in use.
Ground Reference for On-Chip Digital Circuits.
No Connect. These pins are not internally connected and are reserved for possible future use.
Therefore, do not externally connect these pins. These pins can be grounded, if required.
JTAG Test Data Output. This data output pin is one of the standard 5-pin JTAG debug ports on
the part. TDO is an output pin only. At power-on, this output is disabled and pulled high via an
internal, weak pull-up resistor. This pin is left unconnected when not in use.
Rev. C | Page 16 of 132
ADuC7036
Pin No.
11
Mnemonic
NTRST
Type 1
I
12
TMS
I
13
14
VBAT
VREF
I
I
15
GND_SW
I
18
19
20
21, 22
24
27
VTEMP
IIN+
IIN−
AGND
REG_AVDD
GPIO_0/IRQ0/SS
I
I
I
S
S
I/O
28
GPIO_1/SCLK
I/O
29
GPIO_2/MISO
I/O
30
GPIO_3/MOSI
I/O
31
GPIO_4/ECLK
I/O
33
36
37
REG_DVDD
XTAL1
XTAL2
S
O
I
41
WU
I/O
42
44
46
VDD
VSS
STI
S
S
I/O
47
48
EPAD
IO_VSS
LIN/BSD
Exposed pad
S
I/O
1
Description
JTAG Test Reset. This reset input pin is one of the standard 5-pin JTAG debug ports on the part.
NTRST is an input pin only and has an internal, weak pull-down resistor. This pin remains
unconnected when not in use. NTRST is also monitored by the on-chip kernel to enable LIN
boot load mode.
JTAG Test Mode Select. This mode select input pin is one of the standard 5-pin JTAG debug ports
on the part. TMS is an input pin only and has an internal, weak pull-up resistor. This pin is left
unconnected when not in use.
Battery Voltage Input to Resistor Divider.
External Reference Input Terminal. When this input is not used, connect it directly to the AGND
system ground. It can also be left unconnected.
Switch to Internal Analog Ground Reference. This pin is the negative input for the external
temperature channel and external reference. When this input is not used, connect it directly to
the AGND system ground.
External Pin for NTC/PTC Temperature Measurement.
Positive Differential Input for Current Channel.
Negative Differential Input for Current Channel.
Ground Reference for On-Chip Precision Analog Circuits.
Nominal 2.6 V Output from On-Chip Regulator.
General-Purpose Digital I/O 0/External Interrupt Request 0/Slave Select Input for SPI Interface.
By default and after power-on reset, this pin is configured as an input. The pin has an internal,
weak pull-up resistor and should be left unconnected when not in use.
General-Purpose Digital I/O 1/Serial Clock Input for SPI Interface. By default and after a poweron reset, this pin is configured as an input. The pin has an internal, weak pull-up resistor and
should be left unconnected when not in use.
General-Purpose Digital I/O 2/Master Input, Slave Output for SPI Interface. By default and after a
power-on reset, this pin is configured as an input. The pin has an internal, weak pull-up resistor
and should be left unconnected when not in use.
General-Purpose Digital I/O 3/Master Output, Slave Input for SPI Interface. By default and after a
power-on reset, this pin is configured as an input. The pin has an internal, weak pull-up resistor
and should be left unconnected when not in use.
General-Purpose Digital I/O 4/2.56 MHz Clock Output. By default and after a power-on reset, this
pin is configured as an input. The pin has an internal, weak pull-up resistor and should be left
unconnected when not in use.
Nominal 2.6 V Output from the On-Chip Regulator.
Crystal Oscillator Output. If an external crystal is not used, this pin is left unconnected.
Crystal Oscillator Input. If an external crystal is not used, connect this pin to the DGND system
ground.
High Voltage Wake-Up Pin. This high voltage I/O pin has an internal, 10 kΩ pull-down resistor
and a high-side driver to VDD. If this pin is not being used, it should not be connected externally.
Battery Power Supply to On-Chip Regulator.
Ground Reference. This is the ground reference for the internal voltage regulators.
High Voltage Serial Test Interface Output Pin. If this pin is not used, externally connect it to the
IO_VSS ground reference.
Ground Reference for High Voltage I/O Pins.
Local Interconnect Network I/O/Bit Serial Device I/O. This is a high voltage pin.
The exposed pad should be connected to DGND.
I = input, O = output, I/O = input/output, S = supply.
Rev. C | Page 17 of 132
ADuC7036
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
CORE OFF
–0.2
CD = 1
–0.5
VDD = 4V
OFFSET (µV)
OFFSET (µV)
–0.4
–0.6
–1.0
CD = 0
–1.5
–0.8
VDD = 18V
–10
20
50
80
115
140
TEMPERATURE (°C)
07474-008
–1.2
–40
Figure 8. ADC Current Channel Offset vs. Temperature, 10 MHz MCU
0
–40°C
–0.5
–1.0
+115°C
–1.5
–2.0
–2.5
4
6
8
10
12
14
16
18
20
VDD (V)
07474-009
OFFSET (µV)
+25°C
Figure 9. ADC Current Channel Offset vs. VDD, 10 MHz MCU
Rev. C | Page 18 of 132
–2.5
4
6
8
10
12
14
16
18
VDD (V)
Figure 10. ADC Current Channel Offset vs. VDD @ 25°C
20
07474-010
–2.0
–1.0
ADuC7036
TERMINOLOGY
Conversion Rate
The conversion rate specifies the rate at which an output result
is available from the ADC after the ADC has settled.
The Σ-Δ conversion techniques used on this part mean that
while the ADC front-end signal is oversampled at a relatively
high sample rate, a subsequent digital filter is used to decimate
the output, providing a valid 16-bit data conversion result for
output rates from 1 Hz to 8 kHz.
Note that when software switches from one input to another on
the same ADC, the digital filter must first be cleared and then
allowed to average a new result. Depending on the configuration
of the ADC and the type of filter, this may require multiple
conversion cycles.
Integral Nonlinearity (INL)
INL is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB
below the first code transition, and full scale, a point ½ LSB
above the last code transition (111...110 to 111...111).
The error is expressed as a percentage of full scale.
No Missing Codes
No missing codes is a measure of the differential nonlinearity
of the ADC. The error is expressed in bits (as 2N bits, where N
is no missing codes) and specifies the number of codes (ADC
results) that are guaranteed to occur through the full ADC
input range.
Offset Error
Offset error is the deviation of the first code transition ADC
input voltage from the ideal first code transition.
Offset Error Drift
Offset error drift is the variation in absolute offset error with
respect to temperature. This error is expressed as LSBs per
degrees Celsius.
Gain Error
Gain error is a measure of the span error of the ADC. It is a
measure of the difference between the measured and the ideal
span between any two points in the transfer function.
Output Noise
The output noise is specified as the standard deviation (that is,
1 × Σ) of the distribution of ADC output codes that are collected
when the ADC input voltage is at a dc voltage. It is expressed
as microvolts rms (μV rms). The output, or rms noise, can be
used to calculate the effective resolution of the ADC as defined
by the following equation:
Effective Resolution = log2(Full-Scale Range/RMS Noise)
where Effective Resolution is expressed in bits.
The peak-to-peak noise is defined as the deviation of codes that
fall within 6.6 × Σ of the distribution of ADC output codes that
are collected when the ADC input voltage is at dc. The peak-topeak noise is therefore calculated as 6.6 times the rms noise.
The peak-to-peak noise can be used to calculate the ADC
(noise-free code) resolution for which there is no code flicker
within a 6.6 × Σ limit, as defined by the following equation:
Noise-Free Code Resolution = log2(Full-Scale Range/Peak-toPeak Noise)
where Noise-Free Code Resolution is expressed in bits.
Rev. C | Page 19 of 132
ADuC7036
THEORY OF OPERATION
The ADuC7036 is a complete system solution for battery monitoring in 12 V automotive applications. These devices integrate
all of the required features to precisely and intelligently monitor,
process, and diagnose 12 V battery parameters, including battery
current, voltage, and temperature, over a wide range of operating
conditions.
Minimizing external system components, the device is powered
directly from the 12 V battery. An on-chip, low dropout regulator generates the supply voltage for two integrated, 16-bit, Σ-Δ
ADCs. The ADCs precisely measure battery current, voltage,
and temperature to characterize the state of the health and
charge of the car battery.
A Flash/EE memory-based ARM7™ microcontroller (MCU) is
also integrated on chip. It is used to both preprocess the acquired
battery variables and to manage communications from the
ADuC7036 to the main electronic control unit (ECU) via a local
interconnect network (LIN) interface that is integrated on chip.
Both the MCU and the ADC subsystem can be individually
configured to operate in normal or flexible power saving modes
of operation.
In its normal operating mode, the MCU is clocked indirectly
from an on-chip oscillator via the phase-locked loop (PLL) at
a maximum clock rate of 20.48 MHz. In its power saving operating modes, the MCU can be totally powered down, waking
up only in response to an ADC conversion result ready event, a
digital comparator event, a wake-up timer event, a POR event,
or an external serial communication event.
The ADC can be configured to operate in a normal (full power)
mode of operation, interrupting the MCU after various sample
conversion events. The current channel features two low power
modes—low power and low power plus—generating conversion
results to a lower performance specification.
On-chip factory firmware supports in-circuit Flash/EE reprogramming via the LIN or JTAG serial interface ports, and
nonintrusive emulation is also supported via the JTAG interface.
These features are incorporated into a low cost QuickStart™
development system supporting the ADuC7036.
The ADuC7036 operates directly from the 12 V battery supply
and is fully specified over a temperature range of −40°C to
+115°C. The ADuC7036 is functional, but with degraded
performance, at temperatures from 115°C to 125°C.
OVERVIEW OF THE ARM7TDMI CORE
The ARM7 core is a 32-bit, reduced instruction set computer
(RISC), developed by ARM Ltd. The ARM7TDMI® is a
von Neumann-based architecture, meaning that it uses a single
32-bit bus for instruction and data. The length of the data can be
eight, 16, or 32 bits, and the length of the instruction word is either
16 bits or 32 bits, depending on the mode in which the core is
operating.
The ARM7TDMI is an ARM7 core with four additional features,
as listed in Table 8.
Table 8. ARM7TDMI
Feature
T
D
M
I
Description
Support for the Thumb® (16-bit) instruction set
Support for debug
Enhanced multiplier
Includes the EmbeddedICE™ module to support
embedded system debugging
Thumb Mode (T)
An ARM instruction is 32 bits long. The ARM7TDMI processor
supports a second instruction set compressed into 16 bits, the
Thumb instruction set. Faster code execution from 16-bit
memory and greater code density can be achieved by using the
Thumb instruction set, making the ARM7TDMI core
particularly well-suited for embedded applications.
However, the Thumb mode has three limitations.
•
Relative to ARM, the Thumb code usually requires more
instructions to perform a task. Therefore, ARM code is
best for maximizing the performance of time-critical code
in most applications.
•
The Thumb instruction set does not include some
instructions that are needed for exception handling, so
ARM code may be required for exception handling.
•
When an interrupt occurs, the core vectors to the interrupt
location in memory and executes the code present at that
address. The first command is required to be in ARM code.
Multiplier (M)
The ARM7TDMI instruction set includes an enhanced
multiplier with four extra instructions to perform 32-bit by
32-bit multiplication with a 64-bit result, or 32-bit by 32-bit
multiplication-accumulation (MAC) with a 64-bit result.
EmbeddedICE (I)
The EmbeddedICE module provides integrated on-chip debug
support for the ARM7TDMI. The EmbeddedICE module
contains the breakpoint and watchpoint registers that allow
nonintrusive user code debugging. These registers are controlled through the JTAG test port. When a breakpoint or
watchpoint is encountered, the processor halts and enters the
debug state. Once in a debug state, the processor registers can
be interrogated, as can the Flash/EE, SRAM, and memory
mapped registers.
Rev. C | Page 20 of 132
ADuC7036
The ARM7 supports five types of exceptions with a privileged
processing mode associated with each type. The five types of
exceptions are as follows:
•
Normal interrupt or IRQ. This is provided to service
general-purpose interrupt handling of internal and
external events.
•
Fast interrupt or FIQ. This is provided to service data
transfer or a communication channel with low latency.
FIQ has priority over IRQ.
•
Memory abort (prefetch and data).
•
Attempted execution of an undefined instruction.
•
Software interrupt (SWI) instruction that can be used to
make a call to an operating system.
and descends. When programming using high level languages,
such as C, it is necessary to ensure that the stack does not overflow.
This is dependent on the performance of the compiler that is used.
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (R13) and the link register (R14) as represented
in Figure 11. The FIQ mode has more registers (R8 to R12)
supporting faster interrupt processing. With the increased
number of noncritical registers, the interrupt can be processed
without the need to save or restore these registers, thereby
reducing the response time of the interrupt handling process.
More information relative to the model of the programmer and
the ARM7TDMI core architecture can be found in ARM7TDMI
technical and ARM architecture manuals available directly from
ARM Ltd.
Typically, the programmer defines interrupts as IRQ, but for
higher priority interrupts, the programmer can define interrupts
as the FIQ type.
R0
R3
R4
Table 9. Exception Priorities and Vector Addresses
R7
1
Exception
Hardware reset
Memory abort (data)
FIQ
IRQ
Memory abort (prefetch)
Software interrupt1
Undefined instruction1
R5
R6
R8
Address
0x00
0x10
0x1C
0x18
0x0C
0x08
0x04
A software interrupt and an undefined instruction exception have the same
priority and are mutually exclusive.
The list of exceptions in Table 9 are located from 0x00 to 0x1C,
with a reserved location at 0x14. This location is required to be
written with either 0x27011970 or the checksum of Page 0,
excluding Location 0x14. If this is not done, user code does not
execute and LIN download mode is entered.
ARM Registers
The ARM7TDMI has 16 standard registers. R0 to R12 are used
for data manipulation, R13 is the stack pointer, R14 is the link
register, and R15 is the program counter that indicates the
instruction currently being executed. The link register contains
the address from which the user has branched (if the branch
and link command was used) or the command during which an
exception occurred.
The stack pointer contains the current location of the stack. As
a general rule, on an ARM7TDMI, the stack starts at the top of
the available RAM area and descends using the area as required.
A separate stack is defined for each of the exceptions. The size of
each stack is user configurable and is dependent on the target
application. On the ADuC7036, the stack begins at 0x00040FFC
SYSTEM MODES ONLY
R2
The priority of these exceptions and vector address are listed in
Table 9.
Priority
1
2
3
4
5
6
6
USABLE IN USER MODE
R1
R9
R10
R11
R12
R13
R14
R8_FIQ
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R13_SVC
R14_SVC
R13_ABT
R14_ABT
R13_IRQ
R14_IRQ
R13_UND
R14_UND
R15 (PC)
CPSR
SPSR_FIQ
FIQ
MODE
USER MODE
SPSR_SVC
SVC
MODE
SPSR_ABT
ABORT
MODE
SPSR_IRQ
IRQ
MODE
SPSR_UND
UNDEFINED
MODE
07474-011
ARM7 Exceptions
Figure 11. Register Organization
Interrupt Latency
The worst-case latency for an FIQ consists of the longest possible
time for the request to pass through the synchronizer, for the
longest instruction to complete (the longest instruction is an LDM)
and load all the registers including the PC, and for the data abort
entry and the FIQ entry to complete. At the end of this time, the
ARM7TDMI executes the instruction at Address 0x1C (the FIQ
interrupt vector address). The maximum FIQ latency is 50 processor cycles or just over 2.44 μs in a system using a continuous
20.48 MHz processor clock.
The maximum IRQ latency calculation is similar but must allow
for the fact that FIQ has higher priority and may delay entry into
the IRQ handling routine for an arbitrary length of time. This
time can be reduced to 42 cycles if the LDM command is not
used; some compilers have an option to compile without using
this command. Another option is to run the part in Thumb
mode, which reduces the time to 22 cycles.
Rev. C | Page 21 of 132
ADuC7036
The minimum latency for FIQ or IRQ interrupts is five cycles.
This consists of the shortest time the request can take through
the synchronizer plus the time to enter the exception mode.
RESERVED
0xFFFF0FFF
0xFFFF0000
Note that the ARM7TDMI initially (first instruction) runs in
ARM (32-bit) mode when an exception occurs. The user can
immediately switch from ARM mode to Thumb mode if
required, for example, when executing interrupt service routines.
RESERVED
0x00097FFF
FLASH/EE
0x00080000
MEMORY ORGANIZATION
RESERVED
The ARM7 MCU core, which has a von Neumann-based
architecture, sees memory as a linear array of 232 byte locations.
As shown in Figure 13, the ADuC7036 maps this into four
distinct user areas: a memory area that can be remapped, an
SRAM area, a Flash/EE area, and a memory mapped register
(MMR) area.
•
•
•
The first 94 kB of this memory space is used as an area into
which the on-chip Flash/EE or SRAM can be remapped.
The ADuC7036 features a second 4 kB area at the top of
the memory map used to locate the MMRs, through which
all on-chip peripherals are configured and monitored.
The ADuC7036 features an SRAM size of 6 kB.
The ADuC7036 features 96 kB of on-chip Flash/EE memory,
94 kB of which are available to the user and 2 kB of which
are reserved for the on-chip kernel.
Any access, either a read or a write, to an area not defined in the
memory map results in a data abort exception.
Memory Format
The ADuC7036 memory organization is configured in little
endian format: the least significant byte is located in the lowest
byte address and the most significant byte in the highest byte
address.
BIT 31
BIT 0
BYTE 3
.
.
.
BYTE 2
.
.
.
BYTE 1
.
.
.
BYTE 0
.
.
.
B
A
9
8
7
6
5
4
0x00000004
3
2
1
0
0x00000000
32 BITS
Figure 12. Little Endian Format
07474-012
0xFFFFFFFF
0x00417FF
0x00040000
SRAM
RESERVED
0x0017FFF
REMAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)
0x00000000
07474-013
•
MMRs
Figure 13. Memory Map
SRAM
The ADuC7036 features 6 kB of SRAM, organized as
1536 × 32 bits, that is, 1536 words located at 0x00040000.
The RAM space can be used as data memory and also as a volatile
program space.
ARM code can run directly from SRAM at full clock speed
because the SRAM array is configured as a 32-bit-wide memory
array. SRAM is readable/writeable in 8-, 16-, and 32-bit segments.
Remap
The ARM exception vectors are situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020.
By default, after a reset, the Flash/EE memory is logically
mapped to Address 0x00000000.
It is possible to logically remap the SRAM to Address 0x00000000.
This is accomplished by setting Bit 0 of the SYSMAP0 MMR
located at 0xFFFF0220. To revert Flash/EE to 0x00000000, Bit 0
of SYSMAP0 is cleared.
It may be desirable to remap RAM to 0x00000000 to optimize the
interrupt latency of the ADuC7036 because code can run in full
32-bit ARM mode and at maximum core speed. It should be noted
that when an exception occurs, the core defaults to ARM mode.
Rev. C | Page 22 of 132
ADuC7036
Remap Operation
SYSMAP0 Register
When a reset occurs on the ADuC7036, execution starts
automatically in the factory-programmed internal configuration
code. This so-called kernel is hidden and cannot be accessed by
user code. If the ADuC7036 is in normal mode, it executes the
power-on configuration routine of the kernel and then jumps to
the reset vector, Address 0x00000000, to execute the reset
exception routine of the user. Because the Flash/EE is mirrored at
the bottom of the memory array at reset, the reset routine must
always be written in Flash/EE.
Name: SYSMAP0
The remap command must be executed from the absolute
Flash/EE address and not from the mirrored, remapped
segment of memory, which may be replaced by SRAM. If a
remap operation is executed while operating code from the
mirrored location, prefetch/data aborts may occur or the user
may observe abnormal program operation.
Table 10. SYSMAP0 MMR Bit Designations
Address: 0xFFFF0220
Default Value: Updated by the kernel
Access: Read/write access
Function: This 8-bit register allows user code to remap either
RAM or Flash/EE space into the bottom of the ARM memory
space, starting at Address 0x00000000.
Bit
7 to 1
0
Any kind of reset remaps the Flash/EE memory to the bottom
of the memory array.
Rev. C | Page 23 of 132
Description
Reserved. These bits are reserved and should be written
as 0 by user code.
Remap bit.
Set by the user to remap the SRAM to 0x00000000.
Cleared automatically after a reset to remap the
Flash/EE memory to 0x00000000.
ADuC7036
RESET
RSTCLR Register
There are four kinds of resets: external reset, power-on reset,
watchdog reset, and software reset. The RSTSTA register indicates
the source of the last reset and can be written to by user code to
initiate a software reset event. The bits in this register can be
cleared to 0 by writing to the RSTCLR MMR at 0xFFFF0234.
The bit designations in RSTCLR mirror those of RSTSTA.
These registers can be used during a reset exception service
routine to identify the source of the reset. The implications of
all four kinds of reset events are shown in Table 12.
Name: RSTCLR
RSTSTA Register
Address: 0xFFFF0234
Access: Write only
Function: This 8-bit, write only register clears the corresponding
bit in RSTSTA.
Table 11. RSTSTA/RSTCLR MMR Bit Designations
Bit
7 to 4
3
Name: RSTSTA
Address: 0xFFFF0230
Default Value: Varies according to type of reset (see Table 11)
2
Access: Read/write access
Function: This 8-bit register indicates the source of the last reset
event and can be written to by user code to initiate a software reset.
1
0
1
Description
Not used. These bits are not used and always read as 0.
External reset.
Set automatically to 1 when an external reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
Software reset.
Set to 1 by user code to generate a sofware reset.
Cleared by setting the corresponding bit in RSTCLR.1
Watchdog timeout.
Set automatically to 1 when a watchdog timeout occurs.
Cleared by setting the corresponding bit in RSTCLR.
Power-on reset.
Set automatically when a power-on reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
If the software reset bit in RSTSTA is set, any write to RSTCLR that does not
clear this bit generates a software reset.
Table 12. Device Reset Implications
Impact
Reset
POR
Watchdog
Software
External Pin
1
2
Reset
External Pins
to Default
State
Yes
Yes
Yes
Yes
Execute
Kernel
Yes
Yes
Yes
Yes
Reset All
External MMRs
(Excluding RSTSTA)
Yes
Yes
Yes
Yes
Reset All HV
Indirect
Registers
Yes
Yes
Yes
Yes
Reset
Peripherals
Yes
Yes
Yes
Yes
Reset
Watchdog
Timer
Yes
No
No
No
Valid
RAM 1
Yes/No 2
Yes
Yes
Yes
RSTSTA Status
(After a Reset
Event)
RSTSTA[0] = 1
RSTSTA[1] = 1
RSTSTA[2] = 1
RSTSTA[3] = 1
RAM is not valid in the case of a reset following a LIN download.
The impact on RAM is dependent on the HVMON[3] contents if LVF is enabled. When LVF is enabled using HVCFG0[2], RAM has not been corrupted by the POR
mechanism if the LVF status bit, HVMON[3], is 1. See the Low Voltage Flag (LVF) section for more information.
Rev. C | Page 24 of 132
ADuC7036
FLASH/EE MEMORY
The ADuC7036 incorporates Flash/EE memory technology on
chip to provide the user with nonvolatile, in-circuit reprogrammable memory space.
Like EEPROM, flash memory can be programmed in-system
at a byte level, although it must first be erased, with the erasure
performed in page blocks. Therefore, flash memory is often and
more correctly referred to as Flash/EE memory.
Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes nonvolatility, in-circuit programmability, high density, and low cost. Incorporated within the
ADuC7036, Flash/EE memory technology allows the user to
update program code space in-circuit without the need to
replace one-time programmable (OTP) devices at remote
operating nodes.
The Flash/EE memory is located at Address 0x80000. Upon
a hard reset, the Flash/EE memory maps to Address 0x00000000.
The factory-set default contents of all Flash/EE memory locations
is 0xFF. Flash/EE can be read in 8-, 16-, and 32-bit segments
and written in 16-bit segments. The Flash/EE is rated for 10,000
endurance cycles. This rating is based on the number of times
that each byte is cycled, that is, erased and programmed. Implementing a redundancy scheme in the software ensures that none
of the flash locations reach 10,000 endurance cycles.
The user can also write data variables to the Flash/EE memory
during run-time code execution, for example, for storing
diagnostic battery parameter data.
The entire Flash/EE is available to the user as code and nonvolatile data memory. There is no distinction between data
and program space during ARM code processing. The real
width of the Flash/EE memory is 16 bits, meaning that in
ARM mode (32-bit instruction), two accesses to the Flash/EE
are necessary for each instruction fetch. When operating at
speeds of less than 20.48 MHz, the Flash/EE memory controller
can transparently fetch the second 16-bit halfword (part of the
32-bit ARM operation code) within a single core clock period.
Therefore, for speeds less than 20.48 MHz (that is, CD > 0), it is
recommended to use ARM mode. For 20.48 MHz operation
(that is, CD = 0), it is recommended to operate in Thumb mode.
Serial Downloading (In-Circuit Programming)
The ADuC7036 facilitates code download via the LIN/BSD pin.
JTAG Access
The ADuC7036 features an on-chip JTAG debug port to
facilitate code downloading and debugging.
ADuC7036 Flash/EE Memory
The total 96 kB of Flash/EE is organized as 47,000 × 16 bits. Of
this total, 94 kB is designated as user space, and 2 kB is reserved
for boot loader/kernel space.
FLASH/EE CONTROL INTERFACE
The access to and control of the Flash/EE memory on the
ADuC7036 are managed by an on-chip memory controller. The
controller manages the Flash/EE memory as two separate blocks
(Block 0 and Block 1).
Block 0 consists of the 32 kB of Flash/EE memory that is mapped
from Address 0x00090000 to Address 0x00097FFF, including the
2 kB kernel space that is reserved at the top of this block.
Block 1 consists of the 64 kB of Flash/EE memory that is mapped
from Address 0x00080000 to Address 0x0008FFFF.
It should be noted that the MCU core can continue to execute code
from one memory block while an active erase or program cycle
is being carried out on the other block. If a command operates on
the same block as the code currently executing, the core is halted
until the command is complete. This also applies to code execution.
User code, LIN, and JTAG programming use the Flash/EE
control interface, consisting of the following MMRs:
•
•
•
•
•
•
FEExSTA (x = 0 or 1): Read only register. Reflects the
status of the Flash/EE control interface.
FEExMOD (x = 0 or 1): Sets the operating mode of the
Flash/EE control interface.
FEExCON (x = 0 or 1): 8-bit command register. The
commands are interpreted as described in Table 13.
FEExDAT (x = 0 or 1): 16-bit data register.
FEExADR (x = 0 or 1): 16-bit address register.
FEExSIG (x = 0 or 1): Holds the 24-bit code signature as
a result of the signature command being initiated.
FEExHID (x = 0 or 1): Protection MMR. Controls read and
write protection of the Flash/EE memory code space. If
previously configured via the FEExPRO register, FEExHID
may require a software key to enable access.
FEExPRO (x= 0 or 1): A buffer of the FEExHID register.
Stores the FEExHID value and is automatically downloaded to the FEExHID registers on subsequent reset and
power-on events.
The page size of this Flash/EE memory is 512 bytes. Typically,
it takes the Flash/EE controller 20 ms to erase a page, regardless
of CD. Writing a 16-bit word at CD = 0, 1, 2, or 3 requires 50 μs;
at CD = 4 or 5, 70 μs; at CD = 6, 80 μs; and at CD = 7, 105 μs.
•
It is possible to write to a single 16-bit location only twice
between erasures; that is, it is possible to walk bytes, not bits.
If a location is written to more than twice, the contents of the
Flash/EE page may become corrupt.
•
PROGRAMMING FLASH/EE MEMORY IN-CIRCUIT
Note that user software must ensure that the Flash/EE controller
completes any erase or write cycle before the PLL is powered
down. If the PLL is powered down before an erase or write cycle
is completed, the Flash/EE page or byte may be corrupted.
The Flash/EE memory can be programmed in-circuit, using a
serial download mode via the LIN interface or the integrated
JTAG port.
Rev. C | Page 25 of 132
ADuC7036
The FEE0CON and FEE1CON Registers section to the FEE0MOD and FEE1MOD Registers section provide detailed descriptions of the
bit designations for each of the Flash/EE control MMRs.
FEE0CON and FEE1CON Registers
Name: FEE0CON and FEE1CON
Address: 0xFFFF0E08 and 0xFFFF0E88
Default Value: 0x07
Access: Read/write access
Function: These 8-bit registers are written by user code to control the operating modes of the Flash/EE memory controllers for Block 0
(32 kB) and Block 1 (64 kB).
Table 13. Command Codes in FEE0CON and FEE1CON
Code
0x00 2
0x012
0x022
0x032
0x042
Command
Reserved
Single read
Single write
Erase write
Single verify
0x052
0x062
Single erase
Mass erase
0x07
0x08
0x09
0x0A
0x0B
Reserved
Reserved
Reserved
Signature
0x0C
Protect
0x0D
0x0E
0x0F
Reserved
Reserved
Ping
1
2
Description 1
Reserved. This command should not be written by user code.
Load FEExDAT with the 16-bit data indexed by FEExADR.
Write FEExDAT at the address pointed by FEExADR. This operation takes 50 μs.
Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation takes 20 ms.
Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the comparison is
returned in FEExSTA, Bit 1 or Bit 0.
Erase the page indexed by FEExADR.
Erase Block 0 (32 kB) or Block 1 (64 kB) of user space. The 2 kB kernel is protected. This operation takes 1.2 sec. To
prevent accidental execution, a command sequence is required to execute this instruction (see the Command
Sequence for Executing a Mass Erase section).
Default command.
Reserved. This command should not be written by user code.
Reserved. This command should not be written by user code.
Reserved. This command should not be written by user code.
FEE0CON: This command results in the generation of a 24-bit linear feedback shift register (LFSR)-based signature
that is loaded into FEE0SIG.
If FEE0ADR is less than 0x97800, this command results in a 24-bit LFSR-based signature of the user code space from
the page specified in FEE0ADR upwards, including the kernel, security bits, and Flash/EE key.
If FEE0ADR is greater than 0x97800, the kernel and manufacturing data are signed. This operation takes 120 μs.
FEE1CON: This command results in the generation of a 24-bit LFSR-based signature, beginning at FEE1ADR and
ending at the end of the 63,500 block, that is loaded into FEE1SIG. The last page of this block is not included in the
sign generation.
This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase
(0x06) or with the software protection key.
Reserved. This command should not be written by user code.
Reserved. This command should not be written by user code.
No operation, interrupt generated.
The x represents 0 or 1, designating Flash/EE Block 0 or Block 1.
The FEE0CON register reads 0x07 immediately after the execution of this command.
Rev. C | Page 26 of 132
ADuC7036
Table 14. FEE0STA and FEE1STA MMR Bit Designations
Command Sequence for Executing a Mass Erase
Given the significance of the mass erase command, the following
specific code sequence must be executed to initiate this
operation:
Bit
7 to 4
3
Set Bit 3 in FEExMOD.
Write 0xFFC3 in FEExADR.
Write 0x3CFF in FEExDAT.
2
Run the mass erase command (Code 0x06) in FEExCON.
This sequence is illustrated by the following example:
Int a = FEExSTA; // Ensure FEExSTA is
cleared
FEExMOD = 0x08
FEExADR = 0xFFC3
FEExDAT = 0x3CFF
FEExCON = 0x06;
// Mass erase command
while (FEExSTA & 0x04){} //Wait for command
to finish
It should be noted that to run the mass erase command via
FEE0CON, the write protection on the lower 64 kB must be
disabled. That is, FEE1HID/FEE1PRO are set to 0xFFFFFFFF.
This setting can be accomplished by first removing the protection or by erasing the lower 64 kB.
1
0
1
Description1
Not used. These bits are not used and always read as 0.
Flash/EE interrupt status bit.
Set automatically when an interrupt occurs, that is,
when a command is complete and the Flash/EE
interrupt enable bit in the FEExMOD register is set.
Cleared automatically when the FEExSTA register is read
by user code.
Flash/EE controller busy.
Set automatically when the Flash/EE controller is busy.
Cleared automatically when the controller is not busy.
Command fail.
Set automatically when a command written to FEExCON
completes unsuccessfully.
Cleared automatically when the FEExSTA register is read
by user code.
Command successful.
Set automatically by the MCU when a command is
completed successfully.
Cleared automatically when the FEE0STA register is read
by user code.
The x represents 0 or 1, designating Flash/EE Block 0 or Flash/EE Block 1.
FEE0STA and FEE1STA Registers
Name: FEE0STA and FEE1STA
FEE0ADR and FEE1ADR Registers
Address: 0xFFFF0E00 and 0xFFFF0E80
Name: FEE0ADR and FEE1ADR
Default Value: 0x20
Address: 0xFFFF0E10 and 0xFFFF0E90
Access: Read only
Default Value: 0x0000 (FEE1ADR). For FEE0ADR, see the
System Identification FEE0ADR section.
Function: These 8-bit, read only registers can be read by user
code, and they reflect the current status of the Flash/EE
memory controllers.
Access: Read/write access
Function: These 16-bit registers dictate the address acted upon
when a Flash/EE command is executed via FEExCON.
Rev. C | Page 27 of 132
ADuC7036
FEE0DAT and FEE1DAT Registers
FEE0MOD and FEE1MOD Registers
Name: FEE0DAT and FEE1DAT
Name: FEE0MOD and FEE1MOD
Address: 0xFFFF0E0C and 0xFFFF0E8C
Address: 0xFFFF0E04 and 0xFFFF0E84
Default Value: 0x0000
Default Value: 0x00
Access: Read/write access
Access: Read/write access
Function: This 16-bit register contains the data either read from
or to be written to the Flash/EE memory.
Function: These registers are written by user code to configure
the mode of operation of the Flash/EE memory controllers.
Table 15. FEE0MOD and FEE1MOD MMR Bit Designations
Bit
15 to 7
6, 5
4
3
2
1
0
1
Description 1
Not used. These bits are reserved for future functionality and should be written as 0 by user code.
Flash/EE security lock bits. These bits must be written as [6:5] = 10 to complete the Flash/EE security protect sequence.
Flash/EE controller command complete interrupt enable.
Set to 1 by user code to enable the Flash/EE controller to generate an interrupt upon completion of a Flash/EE command.
Cleared to disable the generation of a Flash/EE interrupt upon completion of a Flash/EE command.
Flash/EE erase/write enable.
Set by user code to enable the Flash/EE erase and write access via FEExCON.
Cleared by user code to disable the Flash/EE erase and write access via FEExCON.
Reserved. Should be written as 0.
Flash/EE controller abort enable.
Set to 1 by user code to enable the Flash/EE controller abort functionality.
Reserved. Should be written as 0.
The x represents 0 or 1, designating Flash/EE Block 0 or Flash/EE Block 1.
Rev. C | Page 28 of 132
ADuC7036
FLASH/EE MEMORY SECURITY
Temporary Protection
The 94 kB of Flash/EE memory available to the user can be read
and write protected using the FFE0HID and FEE1HID registers.
Temporary protection can be set and removed by writing
directly into the FEExHID MMR. This register is volatile and,
therefore, protection is in place only while the part remains
powered on. This protection is not reloaded after a power cycle.
In Block 0, the FEE0HID MMR protects the 30 kB. Bits[0:28] of
this register protect Page 0 to Page 57 from writing. Each bit
protects two pages, that is, 1 kB. Bits[29:30] protect Page 58 and
Page 59, respectively; that is, each bit write protects a single page
of 512 bytes. The MSB of this register (Bit 31) protects Block 0
from being read via JTAG.
The FEE0PRO register mirrors the bit definitions of the FEE0HID
MMR. The FEE0PRO MMR allows user code to lock the protecttion or security configuration of the Flash/EE memory so that the
protection configuration is automatically loaded on subsequent
power-on or reset events. This flexibility allows the user to set
and test protection settings temporarily using the FEE0HID
MMR and, subsequently, lock the required protection configuration (using FEE0PRO) when shipping protection systems into
the field.
In Block 1 (64 kB), the FEE1HID MMR protects the 64 kB.
Bits[0:29] of this register protect Page 0 to Page 119 from writing.
Each bit protects four pages, that is, 2 kB. Bit 30 protects Page 120
to Page 127; that is, Bit 30 write protects eight pages of 512 bytes.
The MSB of this register (Bit 31) protects Flash/EE Block 1 from
being read via JTAG.
As with Block 0, the FEE1PRO register mirrors the bit definitions
of the FEE1HID MMR. The FEE1PRO MMR allows user code
to lock the protection or security configuration of the Flash/EE
memory so that the protection configuration is automatically
loaded on subsequent power-on or reset events.
There are three levels of protection: temporary protection,
keyed permanent protection, and permanent protection.
Int a = FEExSTA;
FEExPRO =0 xFFFFFFFB;
FEExADR = 0x66BB;
FEExDAT = 0xAA55;
FEExMOD = 0x0048
FEExCON = 0x0C;
while (FEExSTA & 0x04){}
Keyed Permanent Protection
Keyed permanent protection can be set via FEExPRO, which is
used to lock the protection configuration. The software key
used at the start of the required FEExPRO write sequence is
saved once and must be used for any subsequent access of the
FEExHID or FEExPRO MMRs. A mass erase sets the key back
to 0xFFFF but also erases the entire user code space.
Permanent Protection
Permanent protection can be set via FEExPRO, in a manner
similar to the way keyed permanent protection is set, with the
only difference being that the software key used is 0xDEADDEAD.
When the FEExPRO write sequence is saved, only a mass erase
sets the key back to 0xFFFFFFFF. The mass erase also erases the
entire user code space.
Sequence to Write the Key and Set Permanent Protection
1.
Write FEExPRO corresponding to the pages to be
protected.
2.
Write the new (user-defined) 32-bit key in FEExADR,
Bits[31:16] and FEExDAT, Bits[15:0].
3.
Write Bits[6:5] = 0x10 in FEExMOD.
4.
Run the write key command (Code 0x0C) in FEExCON.
To remove or modify the protection, the same sequence can be
used with a modified value of FEExPRO.
The previous sequence for writing the key and setting permanent
protection is illustrated in the following example sequence,
which protects writing Page 4 and Page 5 of the Flash/EE.
//Ensure FEExSTA is cleared
//Protect Page 4 and Page 5
//32-bit key value (Bits[31:16])
//32-bit key value (Bits[15:0])
//Lock security sequence
//Write key command
//Wait for command to finish
Rev. C | Page 29 of 132
ADuC7036
Block 0, Flash/EE Memory Protection Registers
Name: FEE0HID and FEE0PRO
Address: 0xFFFF0E20 (for FEE0HID) and 0xFFFF0E1C (for FEE0PRO)
Default Value: 0xFFFFFFFF (for FEE0HID) and 0x00000000 (for FEE0PRO)
Access: Read/write access
Function: These registers are written by user code to configure the protection of the Flash/EE memory.
Table 16. FEE0HID and FEE0PRO MMR Bit Designations
Bit
31
30
29
28 to 0
1
Description 1
Read protection bit.
Set by user code to allow reading the 32 kB Flash/EE block code via JTAG read access.
Cleared by user code to protect the 32 kB Flash/EE block code via JTAG read access.
Write protection bit.
Set by user code to allow writes to Page 59.
Cleared by user code to write protect Page 59.
Write protection bit.
Set by user code to allow writes to Page 58.
Cleared by user code to write protect Page 58.
Write protection bits.
Set by user code to allow writes to Page 0 to Page 57 of the 30 kB Flash/EE code memory. Each bit write protects two pages, and
each page consists of 512 bytes.
Cleared by user code to write protect Page 0 to Page 57 of the 30 kB Flash/EE code memory. Each bit write protects two pages, and
each page consists of 512 bytes.
The x represents 0 or 1, designating Flash/EE Block 0 or Flash/EE Block 1.
Block 1, Flash/EE Memory Protection Registers
Name: FEE1HID and FEE1PRO
Address: 0xFFFF0EA0 (for FEE1HID) and 0xFFFF0E9C (for FEE1PRO)
Default Value: 0xFFFFFFFF (for FEE1HID) and 0x00000000 (for FEE1PRO)
Access: Read/write access
Function: These registers are written by user code to configure the protection of the Flash/EE memory.
Table 17. FEE1HID and FEE1PRO MMR Bit Designations
Bit
31
30
29 to 0
Description
Read protection bit.
Set by user code to allow reading of the 64 kB Flash/EE block code via JTAG read access.
Cleared by user code to read protect the 64 kB Flash/EE block code via JTAG read access.
Write protection bit. Write protects eight pages. Each page consists of 512 bytes.
Set by user code to allow writes to Page 120 to Page 127 of the 64 kB Flash/EE code memory.
Cleared by user code to write protect Page 120 to Page 127 of the 64 kB Flash/EE code memory.
Write protection bits.
Set by user code to allow writes to Page 0 to Page 119 of the 64 kB Flash/EE code memory. Each bit write protects four pages, and
each page consists of 512 bytes.
Cleared by user code to write protect Page 0 to Page 119 of the 64 kB Flash/EE code memory. Each bit write protects two pages,
and each page consists of 512 bytes.
Rev. C | Page 30 of 132
ADuC7036
FLASH/EE MEMORY RELIABILITY
CODE EXECUTION TIME FROM SRAM AND FLASH/EE
The Flash/EE memory array on the part is fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
This section describes SRAM and Flash/EE access times during
execution for applications where execution time is critical.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as initial page erase sequence, read/verify
sequence, byte program sequence, and second read/verify
sequence.
Fetching instructions from SRAM takes one clock cycle because
the access time of the SRAM is 2 ns, and a clock cycle is 49 ns
minimum. However, when the instruction involves reading or
writing data to memory, one extra cycle must be added if the
data is in SRAM. If the data is in Flash/EE, two cycles must be
added: one cycle to execute the instruction and two cycles to
retrieve the 32-bit data from Flash/EE. A control flow instruction,
such as a branch instruction, takes one cycle to fetch and two
cycles to fill the pipeline with the new instructions.
In reliability qualification, every halfword (16-bit wide) location
of the three pages (top, middle, and bottom) in the Flash/EE
memory is cycled 10,000 times from 0x0000 to 0xFFFF. As shown
in Table 1, the Flash/EE memory endurance qualification of the
part is carried out in accordance with JEDEC Retention Lifetime
Specification A117. The results allow the specification of a
minimum endurance figure over supply and temperature of
10,000 cycles.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the part is
qualified in accordance with the formal JEDEC Retention
Lifetime Specification A117 at a specific junction temperature
(TJ = 85°C). As part of this qualification procedure, the
Flash/EE memory is cycled to its specified endurance limit,
described previously, before data retention is characterized.
This means that the Flash/EE memory is guaranteed to retain
its data for its fully specified retention lifetime every time the
Flash/EE memory is reprogrammed. In addition, note that
retention lifetime, based on an activation energy of 0.6 eV, derates
with TJ as shown in Figure 14.
Execution from SRAM
Execution from Flash/EE
In Thumb mode, where instructions are 16 bits, one cycle is
needed to fetch any instruction.
In ARM mode, with CD = 0, two cycles are needed to fetch the
32-bit instructions. With CD > 0, no extra cycles are required
for the fetch because the Flash/EE memory continues to be
clocked at full speed. In addition, some dead time is needed
before accessing data for any value of CD bits.
Timing is identical in both modes when executing instructions
that involve using the Flash/EE for data memory. If the instruction
to be executed is a control flow instruction, an extra cycle is needed
to decode the new address of the program counter, and then
four cycles are needed to fill the pipeline if CD = 0.
A data processing instruction involving only the core register
does not require any extra clock cycles. Data transfer instructions
are more complex and are summarized in Table 18.
Table 18. Typical Execution Cycles in ARM/Thumb Mode
Instructions
LD
LDH
LDM/PUSH
STR
STRH
STRM/POP
450
300
150
0
Fetch Cycles
2/1
2/1
2/1
2/1
2/1
2/1
Dead Time
1
1
N
1
1
N
Data Access
2
1
2×N
2 × 50 μs
50 μs
2 × N × 50 μs
With 1 < N ≤ 16, N is the number of data to load or store in the
multiple load/store instruction.
25
40
55
70
85
100
115
130
JUNCTION TEMPERATURE (°C)
Figure 14. Flash/EE Memory Data Retention
145
07474-014
RETENTION (Years)
600
By default, Flash/EE code execution is suspended during any
Flash/EE erase or write cycle. A page (512 bytes) erase cycle takes
20 ms and a write (16 bits) word command takes 50 μs. However,
the Flash/EE controller allows erase/write cycles to be aborted
if the ARM core receives an enabled interrupt during the current
Flash/EE erase/write cycle. The ARM7 can, therefore, immediately service the interrupt and then return to repeat the Flash/EE
command. The abort operation typically requires 10 clock cycles.
If the abort operation is not feasible, the user can run Flash/EE
programming code and the relevant interrupt routines from
SRAM, allowing the core to immediately service the interrupt.
Rev. C | Page 31 of 132
ADuC7036
ON-CHIP KERNEL
The ADuC7036 features an on-chip kernel resident in the top 2 kB
of the Flash/EE code space. After any reset event, this kernel
copies the factory-calibrated data from the manufacturing data
space into the various on-chip peripherals. The peripherals
calibrated by the kernel are as follows:
•
•
•
•
•
•
•
•
Power supply monitor (PSM)
Precision oscillator
Low power oscillator
REG_AVDD/REG_DVDD
Low power voltage reference
Normal mode voltage reference
Current ADC (offset and gain)
Voltage/temperature ADC (offset and gain)
Normal kernel execution time, excluding LIN download, is
approximately 5 ms. It is possible to enter and leave LIN
download mode only through a reset.
SRAM is not modified during normal kernel execution; rather,
SRAM is modified during a LIN download kernel execution.
User MMRs that can be modified by the kernel and differ from
their POR default values are as follows:
•
•
•
•
•
•
•
•
After a POR, the watchdog timer is disabled once the kernel
code is exited. For the duration of the kernel execution, the
watchdog timer is active with a timeout period of 500 ms. This
ensures that when an error occurs in the kernel, the ADuC7036
automatically resets. After any other reset, the watchdog timer
maintains user code configuration for the period of the kernel
and is refreshed just prior to kernel exit. A minimum watchdog
period of 30 ms is required to allow correct LIN downloader
operation. If LIN download mode is entered, the watchdog is
periodically refreshed.
R0 to R15
GP0CON/GP2CON
SYSCHK
ADCMDE/ADC0CON
FEE0ADR/FEE0CON/FEE0SIG
HVDAT/HVCON
HVCFG0/HVCFG1
T3LD
Note that even with NTRST = 0, user code is not executed unless
Address 0x14 contains either 0x27011970 or the checksum of
Page 0, excluding Address 0x14. If Address 0x14 does not contain
this information, user code is not executed and LIN download
mode is entered. During kernel execution, JTAG access is disabled.
With NTRST = 1, user code is always executed.
The ADuC7036DCPZ allows for user-defined bootloader
functionality. The bootloader can be of any size up to 30 kB but
must be located at the top of user flash. The top-most three
words must be the following:
The ADuC7036 also features an on-chip LIN downloader. The
derivatives ADuC7036BCPZ and ADuC7036CCPZ use Protocol 4
for programming Flash/EE memory via LIN, where Protocol 6 is
used on derivative ADuC7036DCPZ. The protocols are described
in Application Note AN-881 (Protocol 4) and Application Note
AN-946 (Protocol 6).
Flowcharts of the execution of the kernel are shown in Figure 15
and Figure 16. The current revision of the kernel can be derived
from SYSSER1, as described in Table 99.
•
•
•
Address 0x977FC must contain the checksum of the
bootloader.
Address 0x977F8 must contain the lowest address of the
bootloader block.
Address 0x977F4 must contain the entry point of the
bootloader code.
The kernel uses the values at these addresses in determining if
the bootloader is valid.
Note that this bootloader checksum is the sum of all half words
from the value pointed to by 0x977F8 up to the half word at
0x977F6.
Rev. C | Page 32 of 132
ADuC7036
INITIALIZE ON-CHIP
PERIPHERALS TO FACTORYCALIBRATED STATE
NO
NO
PAGE ERASED?
0x14 = 0xFFFFFFFF
JTAG MODE?
NTRST = 1
KEY PRESENT?
0x14 = 0x27011970
YES
YES
NO
YES
CHECKSUM PRESENT?
0x14 = CHECKSUM
YES
EXECUTE
USER CODE
NO
FLAG PAGE 0 ERROR
NO
NO
YES
RESET
COMMAND
07474-015
LIN COMMAND
Figure 15. ADuC7036BCPZ and ADuC7036CCPZ Kernel Flowchart
Rev. C | Page 33 of 132
ADuC7036
INITIALIZE ON-CHIP
PERIPHERALS TO FACTORYCALIBRATED STATE
NO
PAGE ERASED?
0x14 = 0xFFFFFFFF
JTAG MODE?
NTRST = 1
NO
KEY PRESENT?
0x14 = 0x27011970
YES
YES
NO
YES
PAGE 0
CHECKSUM PRESENT?
0x14 = PG0-CKS
YES
EXECUTE
USER CODE
NO
NO
BOOT LOADER
LOW ADDR IN RANGE?
0x177F8 ≤ 0x10000
YES
BOOT LOADER
CHECKSUM PRESENT?
0x177FC = BL-CKS
YES
EXECUTE
BOOT LOADER
USER CODE
NO
NO
NO
YES
RESET
COMMAND
07474-116
LIN COMMAND
Figure 16. ADuC7036DCPZ Kernel Flowchart
Rev. C | Page 34 of 132
ADuC7036
0xFFFFFFFF
MEMORY MAPPED REGISTERS
The memory mapped register (MMR) space is mapped into the
top 4 kB of the MCU memory space and accessed by indirect
addressing, loading, and storage commands through the ARM7
banked registers. An outline of the memory mapped register
bank for the ADuC7036 is shown in Figure 17.
0xFFFF1000
0xFFFF0E00
0xFFFF0D50
GPIO
0xFFFF0D00
0xFFFF0A14
SPI
The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers except the ARM7 core registers
(described in the ARM Registers section) reside in the MMR area.
0xFFFF0A00
As shown in Table 19 to Table 30 in the Complete MMR Listing
section, the MMR data widths vary from one byte (eight bits) to
four bytes (32 bits). The ARM7 core can access any of the MMRs
(single byte or multiple byte width registers) with a 32-bit read
or write access.
0xFFFF0810
The resultant read, for example, is aligned per little endian format,
as described in the ARM Registers section. However, errors result
if the ARM7 core tries to access 4-byte (32-bit) MMRs with
a 16-bit access. In the case of a 16-bit write access to a 32-bit
MMR, the 16 most significant bits (the upper 16 bits) are
written as 0s. The case of a 16-bit read access to a 32-bit MMR,
only 16 of the MMR bits can be read.
FLASH CONTROL
INTERFACE
0xFFFF0894
0xFFFF0880
SERIAL TEST
INTERFACE
HV INTERFACE
0xFFFF0800
0xFFFF079C
0xFFFF0780
LIN/BSD
HARDWARE
0xFFFF0730
UART
0xFFFF0700
0xFFFF0580
ADC
0xFFFF0500
0xFFFF044C
0xFFFF0400
0xFFFF0394
0xFFFF0380
0xFFFF0370
0xFFFF0360
0xFFFF0350
0xFFFF0340
0xFFFF0334
0xFFFF0320
PLL AND
OSCILLATOR CONTROL
GENERAL-PURPOSE
TIMER4
WATCHDOG
TIMER3
WAKE-UP
TIMER2
GENERAL-PURPOSE
TIMER1
0xFFFF0318
TIMER0
0xFFFF0300
0xFFFF0244
REMAP AND
SYSTEM CONTROL
0xFFFF0110
0xFFFF0000
INTERRUPT
CONTROLLER
Figure 17. Top-Level MMR Map
Rev. C | Page 35 of 132
07474-016
0xFFFF0220
ADuC7036
COMPLETE MMR LISTING
In Table 19 to Table 30, addresses are listed in hexadecimal code. Access types include R for read, W for write, and RW for read and write.
Table 19. IRQ Address Base = 0xFFFF0000
Address
0x0000
0x0004
Name
IRQSTA
IRQSIG 1
Byte
4
4
Access
Type
R
R
Default Value
0x00000000
N/A
0x0008
0x000C
0x0010
IRQEN
IRQCLR
SWICFG
4
4
4
RW
W
W
0x00000000
N/A
N/A
0x0100
0x0104
FIQSTA
FIQSIG1
4
4
R
R
0x00000000
N/A
0x0108
0x010C
FIQEN
FIQCLR
4
4
RW
W
0x00000000
N/A
1
Description
Active IRQ source. See the Interrupt System section and Table 50.
Current state of all IRQ sources (enabled and disabled). See the Interrupt System
section and Table 50.
Enabled IRQ sources. See the Interrupt System section and Table 50.
MMR to disable IRQ sources. See the Interrupt System section and Table 50.
Software interrupt configuration MMR. See the Programmed Interrupts section
and Table 51.
Active IRQ source. See the Interrupt System section and Table 50.
Current state of all IRQ sources (enabled and disabled). See the Interrupt System
section and Table 50.
Enabled IRQ sources. See the Interrupt System section and Table 50.
MMR to disable IRQ sources. See the Interrupt System section and Table 50.
Depends on the level on the external interrupt pins (GPIO_0, GPIO_5, GPIO_7, and GPIO_8).
Table 20. System Control Address Base = 0xFFFF0200
Address
0x0220
0x0230
Name
SYSMAP0
RSTSTA
Byte
1
1
Access
Type
RW
RW
0x0234
0x0238
RSTCLR
SYSSER0 1
1
4
W
RW
Default Value
N/A
Varies;
depends on
type of reset
N/A
N/A
0x023C
SYSSER11
4
RW
N/A
0x0560
0x0240
SYSALI1
SYSCHK1
4
4
R
RW
N/A
N/A
1
Description
Remap control register. See the Remap Operation section and Table 10.
Reset status MMR. See the Reset section and Table 11 and Table 12.
RSTSTA clear MMR. See the Reset section and Table 11 and Table 12.
System Serial Number 0. See the Part Identification section and Table 98 for
details.
System Serial Number 1. See the Part Identification section and Table 99 for
details.
System assembly lot ID. See the Part Identification section for details.
Kernel checksum. See the System Kernel Checksum section.
Updated by kernel.
Table 21. Timer Address Base = 0xFFFF0300
Address
0x0300
Name
T0LD
Byte
2
Access
Type
RW
Default Value
0x0000
0x0304
T0VAL0
2
R
0x0000
0x0308
T0VAL1
4
R
0x00000000
0x030C
T0CON
4
RW
0x00000000
0x0310
T0CLRI
1
W
N/A
0x0314
T0CAP
2
R
0x0000
0x0320
0x0324
0x0328
0x032C
T1LD
T1VAL
T1CON
T1CLRI
4
4
4
1
RW
R
RW
W
0x00000000
0xFFFFFFFF
0x01000000
N/A
0x0330
T1CAP
4
R
0x00000000
Description
Timer0 load register. See the Timer0—Lifetime Timer and Timer0 Load Register
sections.
Timer0 Value Register 0. See the Timer0—Lifetime Timer and Timer0 Value
Registers sections.
Timer0 Value Register 1. See the Timer0—Lifetime Timer and Timer0 Value
Registers sections.
Timer0 control MMR. See the Timer0—Lifetime Timer and Timer0 Control
Register sections.
Timer0 interrupt clear register. See the Timer0—Lifetime Timer and Timer0
Load Register sections.
Timer0 capture register. See the Timer0—Lifetime Timer and Timer0 Capture
Register sections.
Timer1 load register. See the Timer1 and Timer1 Load Register sections.
Timer1 value register. See the Timer1 and Timer1 Value Register sections.
Timer1 control MMR. See the Timer1 and Timer1 Control Register sections.
Timer1 interrupt clear register. See the Timer1 and Timer1 Clear Register
sections.
Timer1 capture register. See the Timer1 and Timer1 Capture Register sections.
Rev. C | Page 36 of 132
ADuC7036
Address
0x0340
Name
T2LD
Byte
4
Access
Type
RW
Default Value
0x00000000
0x0344
T2VAL
4
R
0xFFFFFFFF
0x0348
T2CON
2
RW
0x0000
0x034C
T2CLRI
1
W
N/A
0x0360
T3LD
2
RW
0x0040
0x0364
T3VAL
2
R
0x0040
0x0368
T3CON
2
RW
0x0000
0x036C
T3CLRI 1
1
W
N/A
0x0380
T4LD
2
RW
0x0000
0x0384
T4VAL
2
R
0xFFFF
0x0388
T4CON
4
RW
0x00000000
0x038C
T4CLRI
1
W
N/A
0x0390
T4CAP
2
R
0x0000
1
Description
Timer2 load register. See the Timer2—Wake-Up Timer and Timer2 Load
Register sections.
Timer2 value register. See the Timer2—Wake-Up Timer and Timer2 Value
Register sections.
Timer2 control MMR. See the Timer2—Wake-Up Timer and Timer2 Control
Register sections and Table 55.
Timer2 interrupt clear register. See the Timer2—Wake-Up Timer and Timer2
Clear Register sections.
Timer3 load register. See the Timer3—Watchdog Timer and Timer3 Load
Register sections.
Timer3 value register. See the Timer3—Watchdog Timer and Timer3 Value
Register sections.
Timer3 control MMR. See the Timer3—Watchdog Timer, Timer3 Value Register,
and Timer 3 Control Register sections and Table 56.
Timer3 interrupt clear register. See the Timer3—Watchdog Timer and Timer3
Clear Register sections.
Timer4 load register. See the Timer4—STI Timer and Timer4 Load Register
sections.
Timer4 value register. See the Timer4—STI Timer and Timer4 Value Register
sections.
Timer4 control MMR. See the Timer4—STI Timer and Timer4 Control Register
sections and Table 57.
Timer4 interrupt clear register. See the Timer4—STI Timer and Timer4 Clear
Register sections.
Timer4 capture register. See the Timer4—STI Timer section.
Updated by kernel.
Table 22. PLL Base Address = 0xFFFF0400
Address
0x0400
0x0404
0x0408
0x040C
0x0410
0x0414
0x0418
0x042C
0x0440
0x0444
0x0448
Name
PLLSTA
POWKEY0
POWCON
POWKEY1
PLLKEY0
PLLCON
PLLKEY1
OSC0TRM
OSC0CON
OSC0STA
0SC0VAL0
Byte
1
4
1
4
4
1
4
1
1
1
2
Access
Type
R
W
RW
W
W
RW
W
RW
RW
R
R
Default Value
N/A
N/A
0x79
N/A
N/A
0x00
N/A
0xX8
0x00
0x00
0x0000
0x044C
OSC0VAL1
2
R
0x0000
Description
PLL status MMR. See the PLLSTA Register section and Table 44.
POWCON prewrite key. See the POWCON Prewrite Key section.
Power control and core speed control register. See the POWCON Register section.
POWCON postwrite key. See the POWCON Postwrite Key section.
PLLCON prewrite key. See the PLLCON Prewrite Key section.
PLL clock source selection MMR. See the PLLCON Register section.
PLLCON postwrite key. See the PLLCON Postwrite Key section.
Low power oscillator trim bits MMR. See the OSC0TRM Register section.
Low power oscillator calibration control MMR. See the OSC0CON Register section.
Low power oscillator calibration status MMR. See the OSC0STA Register section.
Low power oscillator calibration Counter 0 MMR. See the OSC0VAL0 Register
section.
Low power oscillator calibration Counter 1 MMR. See the OSC0VAL1 Register
section.
Rev. C | Page 37 of 132
ADuC7036
Table 23. ADC Address Base = 0xFFFF0500
Address
0x0500
0x0504
Name
ADCSTA
ADCMSKI
Byte
2
1
Access
Type
R
RW
Default Value
0x0000
0x00
0x0508
0x050C
ADCMDE
ADC0CON
1
2
RW
RW
0x00
0x0000
0x0510
ADC1CON
2
RW
0x0000
0x0518
0x051C
ADCFLT
ADCCFG
2
1
RW
RW
0x0007
0x00
0x0520
0x0524
0x0528
0x0530
ADC0DAT
ADC1DAT
ADC2DAT
ADC0OF1 1
2
2
2
2
R
R
R
RW
0x0000
0x0000
0x0000
N/A
0x0534
ADC1OF1
2
RW
N/A
0x0538
ADC2OF1
2
RW
N/A
0x053C
ADC0GN1
2
RW
N/A
0x0540
ADC1GN1
2
RW
N/A
0x0544
ADC2GN1
2
RW
N/A
0x0548
ADC0RCL
2
RW
0x0001
0x054C
ADC0RCV
2
R
0x0000
0x0550
ADC0TH
2
RW
0x0000
0x0554
ADC0TCL
1
RW
0x01
0x0558
ADC0THV
1
R
0x00
0x055C
ADC0ACC
4
R
0x00000000
0x057C
ADCREF1
2
RW
N/A
1
Description
ADC status MMR. See the ADC Status Register section and Table 35.
ADC interrupt source enable MMR. See the ADC Interrupt Mask Register
section.
ADC mode register. See the ADC Mode Register section and Table 36.
Current ADC control MMR. See the Current Channel ADC Control Register
section and Table 37.
V-/T-ADC control MMR. See the Voltage/Temperature Channel ADC Control
Register section and Table 38.
ADC filter control MMR. See the ADC Filter Register section and Table 39.
ADC configuration MMR. See the ADC Configuration Register section and
Table 42.
Current ADC result MMR. See the Current Channel ADC Data Register section.
V-ADC result MMR. See the Voltage Channel ADC Data Register section.
T-ADC result MMR. See the Temperature Channel ADC Data Register section.
Current ADC offset MMR. See the Current Channel ADC Offset Calibration
Register section.
Voltage ADC offset MMR. See the Voltage Channel ADC Offset Calibration
Register section.
Temperature ADC offset MMR. See the Temperature Channel ADC Offset
Calibration Register section.
Current ADC gain MMR. See the Current Channel ADC Gain Calibration
Register section.
Voltage ADC gain MMR. See the Voltage Channel ADC Gain Calibration
Register section.
Temperature ADC gain MMR. See the Temperature Channel ADC Gain
Calibration Register section.
Current ADC result count limit. See the Current Channel ADC Result Counter
Limit Register section.
Current ADC result count value. See the Current Channel ADC Result Count
Register section.
Current ADC result threshold. See the Current Channel ADC Threshold
Register section.
Current ADC result threshold count limit. See the Current Channel ADC
Threshold Count Limit Register section.
Current ADC result threshold count limit value. See the Current Channel ADC
Threshold Count Register section.
Current ADC result accumulator. See the Current Channel ADC Accumulator
Register section.
Low power mode voltage reference scaling factor. See the Low Power Voltage
Reference Scaling Factor section.
Updated by kernel.
Rev. C | Page 38 of 132
ADuC7036
Table 24. UART Base Address = 0XFFFF0700
Address
0x0700
Name
COMTX
COMRX
COMDIV0
Byte
1
1
1
Access
Type
W
R
RW
Default Value
N/A
0x00
0x00
0x0704
COMIEN0
1
RW
0x00
COMDIV1
1
RW
0x00
0x0708
COMIID0
1
R
0x01
0x070C
COMCON0
1
RW
0x00
0x0710
COMCON1
1
RW
0x00
0x0714
COMSTA0
1
R
0x60
0X072C
COMDIV2
2
RW
0x0000
Description
UART transmit register. See the UART Tx Register section.
UART receive register. See the UART Rx Register section.
UART Standard Baud Rate Generator Divisor Value 0. See the UART
Divisor Latch Register 0 section.
UART interrupt enable MMR 0. See the UART Interrupt Enable
Register 0 section and Table 84.
UART Standard Baud Rate Generator Divisor Value 1. See the UART
Divisor Latch Register 1 section.
UART Interrupt Identification 0. See the UART Interrupt
Identification Register 0 section and Table 85.
UART Control Register 0. See the UART Control Register 0 section
and Table 81.
UART Control Register 1. See the UART Control Register 1 section
and Table 82.
UART Status Register 0. See the UART Status Register 0 section and
Table 83.
UART fractional divider MMR. See the UART Fractional Divider
Register section and Table 86.
Table 25. LIN Hardware Sync Base Address = 0XFFFF0780
Address
0x0780
Name
LHSSTA
Byte
4
Access
Type
R
Default Value
0x00000000
0x0784
LHSCON0
2
RW
0x0000
0x0788
LHSVAL0
2
R
0x0000
0x078C
LHSCON1
1
RW
0x32
0x0790
LHSVAL1
2
RW
0x0000
0x0794
LHSCAP
2
R
0x0000
0x0798
LHSCMP
2
RW
0x0000
Description
LHS status MMR. See the LIN Hardware Synchronization Status
Register section and Table 92.
LHS Control MMR 0. See the LIN Hardware Synchronization
Control Register 0 section and Table 93.
LHS Timer0 MMR. See the LIN Hardware Synchronization Timer0
Register section.
LHS Control MMR 1. See the LIN Hardware Synchronization Control
Register 1 section and Table 94.
LHS Timer1 MMR. See the LIN Hardware Synchronization Break
Timer1 Register section.
LHS capture MMR. See the LIN Hardware Synchronization Capture
Register section.
LHS compare MMR. See the LIN Hardware Synchronization
Compare Register section.
Table 26. High Voltage Interface Base Address = 0xFFFF0800
Address
0x0804
Name
HVCON
Byte
1
Access Type
RW
Default Value
N/A
0x080C
HVDAT
2
RW
N/A
Description
High voltage interface control MMR. See the High Voltage Interface
Control Register section and Table 71 and Table 72.
High voltage interface data MMR. See the High Voltage Data Register
section and Table 73.
Rev. C | Page 39 of 132
ADuC7036
Table 27. STI Base Address = 0xFFFF0880
Address
0x0880
0x0884
Name
STIKEY0
STICON
Byte
4
2
Access
Type
W
RW
Default
Value
N/A
0x0000
0x0888
0x088C
0x0890
0x0894
STIKEY1
STIDAT0
STIDAT1
STIDAT2
4
2
2
2
W
RW
RW
RW
N/A
0x0000
0x0000
0x0000
Description
STICON prewrite key. See the Serial Test Interface Key0 Register section.
Serial test interface control MMR. See the Serial Test Interface Control Register
section and Table 91.
STICON postwrite key. See the Serial Test Interface Key1 Register section.
STI Data MMR 0. See the Serial Test Interface Data0 Register section.
STI Data MMR 1. See the Serial Test Interface Data1 Register section.
STI Data MMR 2. See the Serial Test Interface Data2 Register section.
Table 28. SPI Base Address = 0xFFFF0A00
Address
0x0A00
0x0A04
0x0A08
0x0A0C
0x0A10
Name
SPISTA
SPIRX
SPITX
SPIDIV
SPICON
Byte
1
1
1
1
2
Access
Type
R
R
W
RW
RW
Default
Value
0x00
0x00
N/A
0x1B
0x0000
Description
SPI status MMR. See the SPI Status Register section and Table 90.
SPI receive MMR. See the SPI Receive Register section.
SPI transmit MMR. See the SPI Transmit Register section.
SPI baud rate select MMR. See the SPI Divider Register section.
SPI control MMR. See the SPI Control Register section and Table 89.
Table 29. GPIO Base Address = 0xFFFF0D00
Address
0x0D00
0x0D04
0x0D08
0x0D20
0x0D24
0x0D28
0x0D30
0x0D34
0x0D38
0x0D40
0x0D44
0x0D48
1
Name
GP0CON
GP1CON
GP2CON
GP0DAT1
GP0SET
GP0CLR
GP1DAT1
GP1SET
GP1CLR
GP2DAT1
GP2SET
GP2CLR
Byte
4
4
4
4
4
4
4
4
4
4
4
4
Access
Type
RW
RW
RW
RW
W
W
RW
W
W
RW
W
W
Default
Value
0x11100000
0x10000000
0x01000000
0x000000XX
N/A
N/A
0x000000XX
N/A
N/A
0x000000XX
N/A
N/A
Description
GPIO Port0 control MMR. See the GPIO Port0 Control Register section and Table 59.
GPIO Port1 control MMR. See the GPIO Port1 Control Register section and Table 60.
GPIO Port2 control MMR. See the GPIO Port2 Control Register section and Table 61.
GPIO Port0 data control MMR. See the GPIO Port0 Data Register section and Table 62.
GPIO Port0 data set MMR. See the GPIO Port0 Set Register section and Table 65.
GPIO Port0 data clear MMR. See the GPIO Port0 Clear Register section and Table 68.
GPIO Port1 data control MMR. See the GPIO Port1 Data Register section and Table 63.
GPIO Port1 data set MMR. See the GPIO Port1 Set Register section and Table 66.
GPIO Port1 data clear MMR. See the GPIO Port1 Clear Register section and Table 69.
GPIO Port2 data control MMR. See the GPIO Port2 Data Register section and Table 64.
GPIO Port2 data set MMR. See the GPIO Port2 Set Register section and Table 67.
GPIO Port2 data clear MMR. See the GPIO Port2 Clear Register section and Table 70.
Depends on the level on the external GPIO pins.
Rev. C | Page 40 of 132
ADuC7036
Table 30. Flash/EE Base Address = 0xFFFF0E00
Address
0x0E00
0x0E04
0x0E08
0x0E0C
0x0E10
0x0E18
0x0E1C
0x0E20
0x0E80
0x0E84
0x0E88
0x0E8C
0x0E90
0x0E98
0x0E9C
0x0EA0
Name
FEE0STA
FEE0MOD
FEE0CON
FEE0DAT
FEE0ADR
FEE0SIG
FEE0PRO
FEE0HID
FEE1STA
FEE1MOD
FEE1CON
FEE1DAT
FEE1ADR
FEE1SIG
FEE1PRO
FEE1HID
Byte
1
1
1
2
2
3
4
4
1
1
1
2
2
3
4
4
Access
Type
R
RW
RW
RW
RW
R
RW
RW
R
RW
RW
RW
RW
R
RW
RW
Default
Value
0x20
0x00
0x07
0x0000
Nonzero
0xFFFFFF
0x00000000
0xFFFFFFFF
0x20
0x00
0x07
0x0000
0x0000
0xFFFFFF
0x00000000
0xFFFFFFFF
Description
Flash/EE status MMR.
Flash/EE control MMR.
Flash/EE control MMR. See Table 13.
Flash/EE data MMR.
Flash/EE address MMR.
Flash/EE LFSR MMR.
Flash/EE protection MMR. See the Flash/EE Memory Security section and Table 16.
Flash/EE protection MMR. See the Flash/EE Memory Security section and Table 16.
Flash/EE status MMR.
Flash/EE control MMR.
Flash/EE control MMR. See Table 13.
Flash/EE data MMR.
Flash/EE address MMR.
Flash/EE LFSR MMR.
Flash/EE protection MMR. See the Flash/EE Memory Security section and Table 17.
Flash/EE protection MMR. See the Flash/EE Memory Security section and Table 17.
Rev. C | Page 41 of 132
ADuC7036
16-BIT, Σ-Δ ANALOG-TO-DIGITAL CONVERTERS
The ADuC7036 incorporates two independent Σ-Δ analog-todigital converters (ADCs): the current channel ADC (I-ADC)
and the voltage/temperature channel ADC (V-/T-ADC). These
precision measurement channels integrate on-chip buffering, a
programmable gain amplifier, 16-bit, Σ-Δ modulators, and
digital filtering for precise measurement of current, voltage,
and temperature variables in 12 V automotive battery systems.
The Σ-Δ modulator converts the sampled input signal into a
digital pulse train whose duty cycle contains the digital information. A modified Sinc3, programmable, low-pass filter is
then used to decimate the modulator output data stream to give
a valid 16-bit data conversion result at programmable output
rates from 4 Hz to 8 kHz in normal mode and from 1 Hz to
2 kHz in low power mode.
CURRENT CHANNEL ADC (I-ADC)
The I-ADC also incorporates counter, comparator, and accumulator logic. This allows the I-ADC result to generate an
interrupt after a predefined number of conversions has elapsed
or the I-ADC result exceeds a programmable threshold value.
A fast ADC overrange feature is also supported. Once enabled,
a 32-bit accumulator automatically sums the 16-bit I-ADC results.
The I-ADC converts battery current sensed through an external
100 μΩ shunt resistor. On-chip programmable gain means that
the I-ADC can be configured to accommodate battery current
levels from ±1 A to ±1500 A.
As shown in Figure 18, the I-ADC employs a Σ-Δ conversion
technique to attain 16 bits of no missing codes performance.
The time to a first valid (fully settled) result on the current channel
is three ADC conversion cycles with chop mode disabled and
two ADC conversion cycles with chop mode enabled.
Rev. C | Page 42 of 132
Figure 18. Current ADC, Top-Level Overview
Rev. C | Page 43 of 132
07474-017
VREF/136 VOLTAGE INPUT.
ANALOG INPUT
DIAGNOSTIC
VOLTAGE SOURCE
GND
VREF/136
IIN–
IIN+
REG_AVDD REG_AVDD
TWO 50µA IIN+ AND IIN–
CURRENT SOURCES.
ANALOG INPUT DIAGNOSTIC
CURRENT SOURCES
CHOP
BUF
THE INTERNAL 5ppm/°C
REFERENCE IS ROUTED TO
THE ADC BY DEFAULT. AN
EXTERNAL REFERENCE ON
THE VREF PIN CAN ALSO
BE SELECTED.
VREF
INTERNAL
REFERENCE
Σ-∆
MODULATOR
GAIN
COEFFICIENT
OFFSET
COEFFICIENT
THE ADC RESULT IS
COMPARED TO A
PRESET THRESHOLD.
DIGITAL COMPARATOR
THE SINC3 FILTER REMOVES
QUANTIZATION NOISE INTRODUCED
BY THE MODULATOR. THE UPDATE
RATE AND BANDWIDTH OF THIS
FILTER ARE PROGRAMMABLE VIA
THE ADCFLT MMR.
PROGRAMMABLE
DIGITAL FILTER
THE OUTPUT WORD FROM
THE DIGITAL FILTER IS
SCALED BY THE CALIBRATION
COEFFICIENTS BEFORE BEING
PROVIDED AS THE
CONVERSION RESULT.
OUTPUT SCALING
PROGRAMMABLE
DIGITAL FILTER
CHOP
THE Σ-∆
ARCHITECTURE
ENSURES 16 BITS
NO MISSING CODES.
ADC
THRESHOLD
ADC
RESULT
OUTPUT
FORMAT
OUTPUT
AVERAGE
Σ-∆ ADC
Σ-∆ MODULATOR
THE MODULATOR PROVIDES A
HIGH FREQUENCY, 1-BIT DATA
STREAM (THE OUTPUT OF
WHICH IS ALSO CHOPPED) TO
THE DIGITAL FILTER, THE DUTY
CYCLE OF WHICH REPRESENTS
THE SAMPLED ANALOG INPUT
VOLTAGE.
Σ-∆ ADC
THE PROGRAMMABLE
GAIN AMPLIFIER ALLOWS
EIGHT BIPOLAR INPUT
RANGES FROM ±2.3mV TO
±1.2V (INT VREF = +1.2V).
PROGRAMMABLE GAIN
AMPLIFIER
PRECISION REFERENCE
THE BUFFER
AMPLIFIER PRESENTS
A HIGH IMPEDANCE
INPUT STAGE FOR
THE PGA DRIVING THE
Σ-∆ MODULATOR.
BUFFER AMPLIFIER
PGA
THE INPUTS ARE
ALTERNATELY REVERSED
THROUGH THE
CONVERSION CYCLE.
ANALOG INPUT
PROGRAMMABLE
CHOPPING
OUTPUT AVERAGE
COUNTS UP IF ADC
RESULTS > THRESHOLD;
COUNTS DOWN/RESETS IF
ADC RESULT < THRESHOLD.
GENERATES AN INTERRUPT
ON COUNTER OVERFLOW.
THRESHOLD COUNTER
THRESHOLD
COUNTER
ADC RESULT
COUNTER
ADC
RESULT
ADC RESULT COUNTER
GENERATES AN ADC
RESULT FROM ANY
ONE OF FOUR
SOURCES.
ADC INTERRUPT
GENERATOR
ACCUMULATES THE
ADC RESULT.
ADC ACCUMULATOR
COUNTS ADC RESULTS,
GENERATES AN INTERRUPT
ON COUNTER OVERFLOW.
ADC RESULT
ACCUMULATOR
GENERATES AN ADC
INTERRUPT IF THE CURRENT
INPUT IS GROSSLY
OVERRANGED.
ADC FAST OVERRANGE
AS PART OF THE CHOPPING
IMPLEMENTATION, EACH
DATA-WORD OUTPUT FROM
THE FILTER IS SUMMED AND
AVERAGED WITH ITS
PREDECESSOR.
ADC
INTERRUPT
ADuC7036
ADuC7036
Voltage/Temperature Channel ADC (V-/T-ADC)
The external battery voltage (VBAT) is routed to the ADC input
via an on-chip, high voltage (divide-by-24), resistive attenuator.
The voltage attenuator buffers are automatically enabled when
the voltage attenuator input is selected.
The voltage/temperature channel ADC (V-/T-ADC) converts
additional battery parameters, such as voltage and temperature.
The input to this channel can be multiplexed from one of three
input sources: an external voltage, an external temperature
sensor circuit, or an on-chip temperature sensor.
The battery temperature can be derived through the on-chip
temperature sensor or an external temperature sensor input.
The time to a first valid (fully settled) result after an input
channel switch on the voltage/temperature channel is three
ADC conversion cycles with chop mode disabled.
As with the current channel ADC (I-ADC), the V-/T-ADC
employs an identical Σ-Δ conversion technique, including
a modified Sinc3 low-pass filter to provide a valid 16-bit data
conversion result at programmable output rates from 4 Hz to
8 kHz. An external RC filter network is not required because
this is internally implemented in the voltage channel.
DIFFERENTIAL
ATTENUATOR
BUFFER AMPLIFIERS
DIVIDE-BY-24 INPUT
ATTENUATOR
THE BUFFER AMPLIFIERS
PRESENT A HIGH
IMPEDANCE INPUT STAGE
FOR THE ANALOG INPUT.
This ADC is again buffered but, unlike the current channel, has
a fixed input range of 0 V to VREF on VTEMP and 0 V to 28.8 V
on VBAT (assuming an internal 1.2 V reference). A top-level
overview of this ADC signal chain is shown in Figure 19.
ANALOG INPUT
PROGRAMMABLE CHOPPING
THE INPUTS ARE
ALTERNATELY REVERSED
THROUGH THE CONVERSION
CYCLE.
Σ-∆ MODULATOR
Σ-∆ ADC
OUTPUT AVERAGE
THE MODULATOR PROVIDES A
HIGH FREQUENCY, 1-BIT DATA
STREAM (THE OUTPUT OF
WHICH IS ALSO CHOPPED) TO
THE DIGITAL FILTER, THE DUTY
CYCLE OF WHICH REPRESENTS
THE SAMPLED ANALOG INPUT
VOLTAGE.
THE Σ-∆
ARCHITECTURE
ENSURES 16 BITS OF
NO MISSING CODES.
AS PART OF THE CHOPPING
IMPLEMENTATION, EACH
DATA-WORD OUTPUT FROM
THE FILTER IS SUMMED AND
AVERAGED WITH ITS
PREDECESSOR.
VBAT
45Ω
BUF
Σ-∆ ADC
Σ-∆
MODULATOR
1Ω
BUF
CHOP
MUX
VTEMP
INTERNAL
TEMPERATURE
OUTPUT
AVERAGE
PROGRAMMABLE
DIGITAL FILTER
CHOP
OFFSET
COEFFICIENT
INTERNAL
REFERENCE
GAIN
COEFFICIENT
VREF
PRECISION REFERENCE
THE INTERNAL 5ppm/°C
REFERENCE IS ROUTED TO
THE ADC BY DEFAULT. AN
EXTERNAL REFERENCE ON
THE VREF PIN CAN ALSO
BE SELECTED.
OUTPUT SCALING
THE OUTPUT WORD FROM
THE DIGITAL FILTER IS
SCALED BY THE CALIBRATION
COEFFICIENTS BEFORE BEING
PROVIDED AS THE
CONVERSION RESULT.
OUTPUT
FORMAT
ADC
RESULT
ADC
INTERRUPT
PROGRAMMABLE
DIGITAL FILTER
THE SINC3 FILTER REMOVES
QUANTIZATION NOISE INTRODUCED
BY THE MODULATOR. THE UPDATE
RATE AND BANDWIDTH OF THIS
FILTER ARE PROGRAMMABLE VIA
THE ADCFLT MMR.
ADC INTERRUPT GENERATOR
GENERATES AN ADC
INTERRUPT AFTER A VOLTAGE
OR TEMPERATURE
CONVERSION IS COMPLETED.
Figure 19. Voltage/Temperature ADC, Top-Level Overview
Rev. C | Page 44 of 132
TO VOLTAGE OR
TEMPERATURE
DATA MMR
07474-018
2Ω
ADuC7036
ADC GROUND SWITCH
GND_SW
The ADuC7036 features an integrated ground switch pin,
GND_SW (Pin 15). This switch allows the user to dynamically
disconnect ground from external devices and, instead, use either
a direct connection to ground or a connection to ground using
a 20 kΩ resistor. This additional resistor can be used to reduce
the number of external components required for an NTC circuit.
The ground switch feature can be used for reducing power
consumption on application-specific boards.
ADCCFG[7]
20kΩ
07474-020
Figure 21. Internal Ground Switch Configuration
The possible combinations of ADCCFG[7] and ADCMDE[6]
are shown in Table 31.
An example application is shown in Figure 20.
REG_AVDD
REG_AVDD
Table 31. GND_SW Configuration
RREF
VTEMP
ADCCFG[7]
0
0
1
1
VTEMP
NTC
NTC
GND_SW
07474-019
GND_SW
20kΩ
ADCMDE[6]
Figure 20. Example External Temperature Sensor Circuits
ADCMDE[6]
0
1
0
1
GND_SW
Floating
Floating
Direct connection to ground
Connected to ground via 20 kΩ
resistor
ADC NOISE PERFORMANCE TABLES
Figure 20 shows an external NTC used in two modes, with one
using the internal 20 kΩ resistor and the second showing a direct
connection to ground via GND_SW.
Table 32, Table 33, and Table 34 list the output rms noise in
microvolts for some typical output update rates on the I-ADC
and V-/T-ADC. The numbers are typical and are generated at
a differential input voltage of 0 V. The output rms noise is specified
as the standard deviation (or 1 Σ) of the distribution of ADC
output codes collected when the ADC input voltage is at a dc
voltage. It is expressed in microvolts rms (μV rms).
ADCCFG[7] controls the connection of the ground switch to
ground, and ADCMDE[6] controls GND_SW resistance, as
shown in Figure 21.
Table 32. Typical Output RMS Noise of Current Channel ADC in Normal Power Mode
ADCFLT
0xBF1D
0x961F
0x007F
0x0007
0x0000
1
Data
Update
Rate
4 Hz
10 Hz
50 Hz
1 kHz
8 kHz
±2.3 mV
(512)
±4.6 mV
(256)
±4.68 mV
(128)
±18.75 mV
(64)
ADC Input Range
±37.5 mV ±75 mV
(32)
(16)
±150 mV
(8)
±300 mV
(4 1 )
0.040 μV
0.060 μV
0.142 μV
0.620 μV
2.000 μV
0.040 μV
0.060 μV
0.142 μV
0.620 μV
2.000 μV
0.043 μV
0.060 μV
0.144 μV
0.625 μV
2.000 μV
0.045 μV
0.065 μV
0.145 μV
0.625 μV
2.000 μV
0.087 μV
0.087 μV
0.170 μV
0.770 μV
2.650 μV
0.35 μV
0.35 μV
0.380 μV
1.650 μV
8.020 μV
0.7 μV
0.7 μV
0.7 μV
2.520 μV
15.0 μV
0.175 μV
0.175 μV
0.305 μV
1.310 μV
4.960 μV
The maximum absolute input voltage allowed is −200 mV to +300 mV, relative to ground.
Table 33. Typical Output RMS Noise (Referred to ADC Voltage Attenuator Input) of Voltage Channel ADC
ADCFLT
0xBF1D
0x961F
0x0007
0x0000
Data Update Rate
4 Hz
10 Hz
1 kHz
8 kHz
28.8 V ADC Input Range
65 μV
65 μV
180 μV
1600 μV
Table 34. Typical Output RMS Noise of Temperature Channel ADC
ADCFLT
0xBF1D
0x961F
0x0007
0x0000
Data Update Rate
4 Hz
10 Hz
1 kHz
8 kHz
0 V to 1.2 V ADC Input Range
2.8 μV
2.8 μV
7.5 μV
55 μV
Rev. C | Page 45 of 132
±600 mV
(21)
1.4 μV
1.4 μV
2.3 μV
7.600 μV
55.0 μV
±1.2 V
(11)
2.8 μV
2.8 μV
2.8 μV
7.600 μV
55.0 μV
ADuC7036
ADC MMR INTERFACE
The ADC is controlled and configured using several MMRs that
are described in detail in the ADC Status Register section to the
Low Power Voltage Reference Scaling Factor section.
All bits defined in the top eight MSBs (Bits[8:15]) of the ADCSTA
MMR are used as flags only and do not generate interrupts. All
bits defined in the lower eight LSBs (Bits[0:7]) of this MMR are
logic OR’ed to produce a single ADC interrupt to the MCU core.
In response to an ADC interrupt, user code should interrogate
the ADCSTA MMR to determine the source of the interrupt.
Each ADC interrupt source can be individually masked via the
ADCMSKI MMR described in the ADC Interrupt Mask Register
section.
All ADC result ready bits are cleared by a read of the ADC0DAT
MMR. If the current channel ADC is not enabled, all ADC result
ready bits are cleared by a read of the ADC1DAT or ADC2DAT
MMRs. To ensure that I-ADC and V-/T-ADC conversion data
are synchronous, user code should first read the ADC1DAT MMR
and then the ADC0DAT MMR. New ADC conversion results
are not written to the ADCxDAT MMRs unless the respective
ADC result ready bits are first cleared. The only exception to
this rule is the data conversion result updates when the ARM
core is powered down. In this mode, ADCxDAT registers always
contain the most recent ADC conversion result, even though
the ready bits have not been cleared.
ADC Status Register
Name: ADCSTA
Address: 0xFFFF0500
Default Value: 0x0000
Access: Read only
Function: This read only register holds general status information
related to the mode of operation or current status of the ADCs.
Table 35. ADCSTA MMR Bit Designations
Bit
15
14
13
12
11 to 5
4
3
2
1
0
Description
ADC calibration status.
Set automatically in hardware to indicate that an ADC calibration cycle has been completed.
Cleared after ADCMDE is written to.
ADC temperature conversion error.
Set automatically in hardware to indicate that a temperature conversion overrange or underrange has occurred. The conversion
result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case.
Cleared when a valid (in-range) temperature conversion result is written to the ADC2DAT register.
ADC voltage conversion error.
Set automatically in hardware to indicate that a voltage conversion overrange or underrange has occurred. The conversion result is
clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case.
Cleared when a valid (in-range) voltage conversion result is written to the ADC1DAT register.
ADC current conversion error.
Set automatically in hardware to indicate that a current conversion overrange or underrange has occurred. The conversion result is
clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case.
Cleared when a valid (in-range) current conversion result is written to the ADC0DAT register.
Not used. These bits are reserved for future functionality and should not be monitored by user code.
Current channel ADC comparator threshold. Valid only if the current channel ADC comparator is enabled via the ADCCFG MMR.
Set by hardware if the absolute value of the I-ADC conversion result exceeds the value written in the ADC0TH MMR. However, if the
ADC threshold counter is used (ADC0TCL), this bit is set only when the specified number of I-ADC conversions equals the value in
the ADC0THV MMR.
Cleared automatically by hardware when reconfiguring the ADC or if the comparator is disabled.
Current channel ADC overrange bit.
Set by hardware if the overrange detect function is enabled via the ADCCFG MMR and the I-ADC input is grossly (>30%
approximate) over range. This bit is updated every 125 μs.
Cleared by software only when ADCCFG[2] is cleared to disable the function, or the ADC gain is changed via the ADC0CON MMR.
Temperature conversion result ready bit.
Set by hardware, if the temperature channel ADC is enabled, as soon as a valid temperature conversion result is written in the
temperature data register (ADC2DAT MMR). It is also set at the end of a calibration.
Cleared by reading either ADC2DAT or ADC0DAT.
Voltage conversion result ready bit.
Set by hardware, if the voltage channel ADC is enabled, as soon as a valid voltage conversion result is written in the voltage data
register (ADC1DAT MMR). It is also set at the end of a calibration.
Cleared by reading either ADC1DAT or ADC0DAT.
Current conversion result ready bit.
Set by hardware, if the current channel ADC is enabled, as soon as a valid current conversion result is written in the current data
register (ADC0DAT MMR). It is also set at the end of a calibration.
Cleared by reading ADC0DAT.
Rev. C | Page 46 of 132
ADuC7036
ADC Interrupt Mask Register
Name: ADCMSKI
Address: 0xFFFF0504
Default Value: 0x00
Access: Read/write
Function: This register allows the ADC interrupt sources to be individually enabled. The bit positions in this register are the same as the
lower eight bits in the ADCSTA MMR. If a bit is set by user code to 1, the respective interrupt is enabled. By default, all bits are 0,
meaning all ADC interrupt sources are disabled.
ADC Mode Register
Name: ADCMDE
Address: 0xFFFF0508
Default Value: 0x00
Access: Read/write
Function: This 8-bit register configures the mode of operation of the ADC subsystem.
Table 36. ADCMDE MMR Bit Designations
Bit
7
6
5
4 to 3
2 to 0
Description
Not used. This bit is reserved for future functionality and should be written as 0 by user code.
20 kΩ resistor select.
Set to 1 to select the 20 kΩ resistor as shown in Figure 21.
Set to 0 to select the direct path to ground as shown in Figure 21 (default).
Low power mode reference select.
Set to 1 to enable the precision voltage reference in either low power mode or low power plus mode, thereby increasing current
consumption.
Set to 0 to enable the low power voltage reference in either low power mode or low power plus mode (default).
ADC power mode configuration.
00 = ADC normal mode. If enabled, the ADC operates with normal current consumption yielding optimum electrical performance.
01 = ADC low power mode. If enabled, the I-ADC operates with reduced current consumption. This limitation in current
consumption is achieved (at the expense of ADC noise performance) by fixing the gain to 128 and using the on-chip low power
(131 kHz) oscillator to directly drive the ADC circuits.
10 = ADC low power plus mode. If enabled, the ADC operates with reduced current consumption. In this mode, the gain is fixed to
512 and the current consumed is approximately 200 μA more than the ADC low power mode. The additional current consumed
also ensures that the ADC noise performance is better than that achieved in ADC low power mode.
11 = not defined.
ADC operation mode configuration.
000 = ADC power-down mode. All ADC circuits (including internal reference) are powered down.
001 = ADC continuous conversion mode. In this mode, any enabled ADC continuously converts.
010 = ADC single conversion mode. In this mode, any enabled ADC performs a single conversion. The ADC enters idle mode when
the single shot conversion is complete. A single conversion takes two to three ADC clock cycles depending on the chop mode.
011 = ADC idle mode. In this mode, the ADC is fully powered on but is held in reset.
100 = ADC self-offset calibration. In this mode, an offset calibration is performed on any enabled ADC using an internally
generated 0 V. The calibration is carried out at the user programmed ADC settings; therefore, as with a normal single ADC
conversion, it takes two to three ADC conversion cycles before a fully settled calibration result is ready. The calibration result is
automatically written to the ADCxOF MMR of the respective ADC. The ADC returns to idle mode and the calibration and
conversion ready status bits are set at the end of an offset calibration cycle.
101 = ADC self-gain calibration. In this mode, a gain calibration against an internal reference voltage is performed on all enabled
ADCs. A gain calibration is a two-stage process and takes twice the time of an offset calibration. The calibration result is
automatically written to the ADCxGN MMR of the respective ADC. The ADC returns to idle mode, and the calibration and
conversion ready status bits are set at the end of a gain calibration cycle. An ADC self-gain calibration should only be carried out
on the current channel ADC. Preprogrammed, factory calibration coefficients (downloaded automatically from internal Flash/EE)
should be used for voltage temperature measurements. If an external NTC is used, an ADC self-calibration should be performed
on the temperature channel.
110 = ADC system zero-scale calibration. In this mode, a zero-scale calibration is performed on enabled ADC channels against an
external zero-scale voltage driven at the ADC input pins. The calibration is carried out at the user programmed ADC settings;
therefore, as with a normal, single ADC conversion, it takes three ADC conversion cycles before a fully settled calibration result is ready.
111 = ADC system full-scale calibration. In this mode, a full-scale calibration is performed on enabled ADC channels against an
external full-scale voltage driven at the ADC input pins.
Rev. C | Page 47 of 132
ADuC7036
Current Channel ADC Control Register
Name: ADC0CON
Address: 0xFFFF050C
Default Value: 0x0000
Access: Read/write
Function: This 16-bit register is used to configure the I-ADC.
Note that if the current ADC is reconfigured via ADC0CON, the voltage ADC and temperature ADC are also reset.
Table 37. ADC0CON MMR Bit Designations
Bit
15
14, 13
12 to 10
9
8
7, 6
5, 4
3 to 0
Description
Current channel ADC enable.
Set to 1 by user code to enable the I-ADC.
Cleared to 0 to power down the I-ADC and reset the respective ADC ready bit in the ADCSTA MMR to 0.
IIN current source enable.
00 = current sources off.
01 = enables the 50 μA current source on IIN+.
10 = enables the 50 μA current source on IIN−.
11 = enables the 50 μA current source on both IIN− and IIN+.
Not used. These bits are reserved for future functionality and should be written as 0.
Current channel ADC output coding.
Set to 1 by user code to configure I-ADC output coding as unipolar.
Cleared to 0 by user code to configure I-ADC output coding as twos complement.
Not used. This bit is reserved for future functionality and should be written as 0.
Current channel ADC input select.
00 = IIN+, IIN− are selected.
01 = IIN−, IIN− are selected. Diagnostic, internal short configuration.
10 = VREF/136, 0 V, diagnostic, test voltage for gain settings ≤ 128. Note that if (REG_AVDD, AGND) divided-by-2 reference is
selected, REG_AVDD is used for VREF in this mode. This leads to ADC0DAT scaled by 2.
11 = not defined.
Current channel ADC reference select.
00 = internal, 1.2 V precision reference selected. In ADC low power mode, the voltage reference selection is controlled by
ADCMDE[5].
01 = external reference inputs (VREF, GND_SW) selected.
10 = external reference inputs divided-by-2 (VREF, GND_SW)/2 selected, which allows an external reference up to REG_AVDD.
11 = (REG_AVDD, AGND) divided-by-2 selected.
Current channel ADC gain select. The nominal I-ADC full-scale input voltage = (VREF/gain).
0000 = I-ADC gain of 1.
0001 = I-ADC gain of 2.
0010 = I-ADC gain of 4.
0011 = I-ADC gain of 8.
0100 = I-ADC gain of 16.
0101 = I-ADC gain of 32.
0110 = I-ADC gain of 64.
0111 = I-ADC gain of 128.
1000 = I-ADC gain of 256.
1001 = I-ADC gain of 512.
1xxx = I-ADC gain is undefined.
Rev. C | Page 48 of 132
ADuC7036
Voltage/Temperature Channel ADC Control Register
Name: ADC1CON
Address: 0xFFFF0510
Default Value: 0x0000
Access: Read/write
Function: This 16-bit register is used to configure the V-/T-ADC.
Note that when selecting the VBAT attenuator input, the voltage attenuator buffers are automatically enabled.
Table 38. ADC1CON MMR Bit Designations
Bit
15
14, 13
12 to 10
9
8
7, 6
5, 4
3 to 0
Description
Voltage/temperature channel ADC enable.
Set to 1 by user code to enable the V-/T-ADC.
Cleared to 0 to power down the V-/T-ADC.
VTEMP current source enable.
00 = current sources off.
01 = enables 50 μA current source on VTEMP.
10 = enables 50 μA current source on GND_SW.
11 = enables 50 μA current source on both VTEMP and GND_SW.
Not used. These bits are reserved for future functionality and should not be modified by user code.
Voltage/temperature channel ADC output coding.
Set to 1 by user code to configure V-/T-ADC output coding as unipolar.
Cleared to 0 by user code to configure V-/T-ADC output coding as twos complement.
Not used. This bit is reserved for future functionality and should be written as 0 by user code.
Voltage/temperature channel ADC input select.
00 = VBAT/24, AGND. VBAT attenuator selected. The high voltage buffers are enabled automatically in this configuration.
01 = VTEMP, GND_SW. External temperature input selected, conversion result written to ADC2DAT.
10 = internal sensor. Internal temperature sensor input selected, conversion result written to ADC2DAT. The temperature
gradient is 0.33 mV/°C; this is only applicable to the internal temperature sensor.
11 = internal short. Shorted input.
Voltage/temperature channel ADC reference select.
00 = internal, 1.2 V precision reference selected.
01 = external reference inputs (VREF, GND_SW) selected.
10 = external reference inputs divided-by-2 (VREF, GND_SW)/2 selected. This allows an external reference up to REG_AVDD.
11 = (REG_AVDD, AGND)/2 selected for the voltage channel. (REG_AVDD, GND_SW)/2 selected for the temperature channel.
Not used. These bits are reserved for future functionality and should not be written as 0 by user code.
Rev. C | Page 49 of 132
ADuC7036
ADC Filter Register
Name: ADCFLT
Address: 0xFFFF0518
Default Value: 0x0007
Access: Read/write
Function: This 16-bit register controls the speed and resolution of the on-chip ADCs.
Note that if ADCFLT is modified, the current and voltage/temperature ADCs are reset.
Table 39. ADCFLT MMR Bit Designations
Bit
15
14
13 to 8
7
6 to 0
1
2
Description
Chop enable.
Set by the user to enable system chopping of all active ADCs. When this bit is set, the ADC has very low offset errors and
drift, but the ADC output rate is reduced by a factor of three if AF = 0 (see Sinc3 decimation factor, Bits[6:0], in this table).
If AF > 0, then the ADC output update rate is the same with chop on or off. When chop is enabled, the settling time is two
output periods.
Running average.
Set by the user to enable a running-average-by-two function reducing ADC noise. This function is automatically enabled
when chopping is active. It is an optional feature when chopping is inactive, and if enabled (when chopping is inactive),
does not reduce the ADC output rate but does increase the settling time by one conversion period.
Cleared by the user to disable the running average function.
Averaging factor (AF). The values written to these bits are used to implement a programmable first-order Sinc3 postfilter.
The averaging factor can further reduce ADC noise at the expense of output rate, as described in Bits[6:0], Sinc3
decimation factor, in this table.
Sinc3 modify.
Set by the user to modify the standard Sinc3 frequency response to increase the filter stop-band rejection by
approximately 5 dB. This is achieved by inserting a second notch (NOTCH2) a fNOTCH2 = 1.333 × fNOTCH, where fNOTCH is the
location of the first notch in the response.
Sinc3 decimation factor (SF). 1 The value (SF) written in these bits controls the oversampling (decimation factor) of the
Sinc3 filter. The output rate from the Sinc3 filter is given by fADC = (512,000/([SF + 1] × 64)) Hz 2 , when the chop bit (Bit 15,
chop enable) = 0 and the averaging factor (AF) = 0. This is valid for all SF values ≤ 125.
For SF = 126, fADC is forced to 60 Hz.
For SF = 127, fADC is forced to 50 Hz.
For information on calculating the fADC for SF (other than 126 and 127) and AF values, refer to Table 40.
Due to limitations on the digital filter internal data path, there are some limitations on the combinations of the Sinc3 decimation factor (SF) and averaging factor (AF)
that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in normal power mode to 4 Hz or 1 Hz in lower power mode.
In low power mode and low power plus mode, the ADC is driven directly by the low power oscillator (131 kHz) and not 512 kHz. All fADC calculations should be divided
by 4 (approximately).
Rev. C | Page 50 of 132
ADuC7036
Table 40. ADC Conversion Rates and Settling Times
Chop
Enabled
No
Averaging Factor
No
Running
Average
No
No
No
Yes
No
Yes
No
tSETTLING 1
fADC
512,000
[SF + 1]× 64
3
f ADC
512,000
[SF + 1]× 64
4
f ADC
1
512,000
[SF + 1] × 64 × [3 + AF ]
f ADC
No
Yes
Yes
512,000
[SF + 1] × 64 × [3 + AF ]
2
f ADC
Yes
N/A
N/A
512,000
[SF + 1] × 64 × [3 + AF ] + 3
2
f ADC
1
An additional time of approximately 60 μs per ADC is required before the first ADC is available.
Table 41. Allowable Combinations of SF and AF
AF Range
SF
0 to 31
32 to 63
64 to 127
0
Yes
Yes
Yes
1 to 7
Yes
Yes
No
Rev. C | Page 51 of 132
8 to 63
Yes
No
No
ADuC7036
ADC Configuration Register
Name: ADCCFG
Address: 0xFFFF051C
Default Value: 0x00
Access: Read/write
Function: This 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs.
Table 42. ADCCFG MMR Bit Designations
Bit
7
6, 5
4, 3
2
1
0
Description
Analog ground switch enable.
Set to 1 by user software to connect the external GND_SW pin (Pin 15) to an internal analog ground reference point. This bit can
be used to connect and disconnect external circuits and components to ground under program control and, thereby, minimize dc
current consumption when the external circuit or component is not used. This bit is used in conjunction with ADCMDE[6] to select
a 20 kΩ resistor to ground.
Cleared by user code to disconnect the external GND_SW pin.
Current channel (32-bit) accumulator enable.
00 = accumulator disabled and reset to 0. The accumulator must be disabled for a full ADC conversion (ADCSTA[0] set twice)
before the accumulator can be reenabled to ensure that the accumulator is reset.
01 = accumulator active.
Positive current values are added to the accumulator total; the accumulator can overflow if allowed to run for >65,535
conversions.
Negative current values are subtracted from the accumulator total; the accumulator is clamped to a minimum value of 0.
10 = accumulator active.
Positive current values are added to the accumulator total; the accumulator can overflow if allowed to run for >65,535 conversions.
The absolute values of negative current are subtracted from the accumulator total; the accumulator in this mode continues to
accumulate negatively, below 0.
11 = not defined.
Current channel ADC comparator enable.
00 = comparator disabled.
01 = comparator active, interrupt asserted if absolute value of I-ADC conversion result is |I| ≥ ADC0TH.
10 = comparator count mode active, interrupt asserted if absolute value of an I-ADC conversion result is |I| ≥ ADC0TH for the
number of ADC0TCL conversions. A conversion value of |I| < ADC0TH resets the threshold counter value (ADC0THV) to 0.
11 = comparator count mode active, interrupt asserted if absolute value of an I-ADC conversion result is |I| ≥ ADC0TH for the
number of ADC0TCL conversions. A conversion value of |I| < ADC0TH decrements the threshold counter value (ADC0THV) toward 0.
Current channel ADC overrange enable.
Set by user to enable a coarse comparator on the current channel ADC. If the current reading is grossly (>30% approximate)
overrange for the active gain setting, then the overrange bit in the ADCSTA MMR is set.
The current must be outside this range for greater than 125 μs for the flag to be set. This feature should not be used in ADC low
power mode.
Cleared by user code to disable the overrange feature.
Not used. This bit is reserved for future functionality and should be written as 0 by user code.
Current channel ADC, result counter enable.
Set by user to enable the result count mode. In this mode, an I-ADC interrupt is generated only when ADC0RCV = ADC0RCL. This
allows the I-ADC to continuously monitor current but only interrupt the MCU core after a defined number of conversions. The
voltage/temperature ADC also continues to convert if enabled, but again, only the last conversion result is available (intermediate
V-/T-ADC conversion results are not stored) when the ADC counter interrupt occurs.
Rev. C | Page 52 of 132
ADuC7036
Current Channel ADC Data Register
Voltage Channel ADC Offset Calibration Register
Name: ADC0DAT
Name: ADC1OF
Address: 0xFFFF0520
Address: 0xFFFF0534
Default Value: 0x0000
Default Value: Part specific, factory programmed
Access: Read only
Access: Read/write
Function: This ADC data MMR holds the 16-bit conversion
result from the I-ADC. The ADC does not update this MMR if
the ADC0 conversion result ready bit (ADCSTA[0]) is set. A
read of this MMR by the MCU clears all asserted ready flags
(ADCSTA[2:0]).
Address: 0xFFFF0524
Function: This offset MMR holds a 16-bit offset calibration
coefficient for the voltage channel. The register is configured at
power-on with a factory default value. However, this register is
automatically overwritten if an offset calibration of the voltage
channel is initiated by the user via bits in the ADCMDE MMR.
User code can write to this calibration register only if the ADC
is in idle mode. An ADC must be enabled and in idle mode
before being written to any offset or gain register. The ADC
must be in idle mode for at least 23 μs.
Default Value: 0x0000
Temperature Channel ADC Offset Calibration Register
Access: Read only
Name: ADC2OF
Function: This ADC data MMR holds the 16-bit voltage
conversion result from the V-/T-ADC. The ADC does not
update this MMR if the voltage conversion result ready bit
(ADCSTA[1]) is set. If I-ADC is not active, a read of this MMR
by the MCU clears all asserted ready flags (ADCSTA[2:1]).
Address: 0xFFFF0538
Voltage Channel ADC Data Register
Name: ADC1DAT
Temperature Channel ADC Data Register
Name: ADC2DAT
Address: 0xFFFF0528
Default Value: 0x0000
Access: Read only
Function: This ADC data MMR holds the 16-bit temperature
conversion result from the V-/T-ADC. The ADC does not
update this MMR if the temperature conversion result ready bit
(ADCSTA[2]) is set. If I-ADC and V-ADC are not active, a read
of this MMR by the MCU clears all asserted ready flags
(ADCSTA[2]). A read of this MMR clears ADCSTA[2].
Default Value: Part specific, factory programmed
Access: Read/write
Function: This ADC offset MMR holds a 16-bit offset
calibration coefficient for the temperature channel. The register
is configured at power-on with a factory default value. However,
this register is automatically overwritten if an offset calibration
of the temperature channel is initiated by the user via bits in the
ADCMDE MMR. User code can write to this calibration register
only if the ADC is in idle mode. An ADC must be enabled and
in idle mode before being written to any offset or gain register.
The ADC must be in idle mode for at least 23 μs.
Current Channel ADC Gain Calibration Register
Name: ADC0GN
Address: 0xFFFF053C
Default Value: Part specific, factory programmed
Current Channel ADC Offset Calibration Register
Access: Read/write
Name: ADC0OF
Function: This gain MMR holds a 16-bit gain calibration
coefficient for scaling the I-ADC conversion result. The register
is configured at power-on with a factory default value. However,
this register is automatically overwritten if a gain calibration of
the I-ADC is initiated by the user via bits in the ADCMDE
MMR. User code can write to this calibration register only if the
ADC is in idle mode. An ADC must be enabled and in idle
mode before being written to any offset or gain register. The
ADC must be in idle mode for at least 23 μs.
Address: 0xFFFF0530
Default Value: Part specific, factory programmed
Access: Read/write
Function: This ADC offset MMR holds a 16-bit offset calibration
coefficient for the I-ADC. The register is configured at poweron with a factory default value. However, this register automatically overwrites if an offset calibration of the I-ADC is initiated
by the user via bits in the ADCMDE MMR. User code can write
to this calibration register only if the ADC is in idle mode. An
ADC must be enabled and in idle mode before being written to
any offset or gain register. The ADC must be in idle mode for at
least 23 μs.
Rev. C | Page 53 of 132
ADuC7036
Voltage Channel ADC Gain Calibration Register
Current Channel ADC Result Count Register
Name: ADC1GN
Name: ADC0RCV
Address: 0xFFFF0540
Address: 0xFFFF054C
Default Value: Part specific, factory programmed
Default Value: 0x0000
Access: Read/write
Access: Read only
Function: This gain MMR holds a 16-bit gain calibration
coefficient for scaling a voltage channel conversion result. The
register is configured at power-on with a factory default value.
However, this register is automatically overwritten if a gain
calibration of the voltage channel is initiated by the user via bits
in the ADCMDE MMR. User code can write to this calibration
register only if the ADC is in idle mode. An ADC must be
enabled and in idle mode before being written to any offset or
gain register. The ADC must be in idle mode for at least 23 μs.
Temperature Channel ADC Gain Calibration Register
Function: This 16-bit, read only MMR holds the current number
of I-ADC conversion results. It is used in conjunction with
ADC0RCL to mask I-ADC interrupts, generating a lower interrupt
rate. When ADC0RCV = ADC0RCL, the value in ADC0RCV
resets to 0 and recommences counting. It can also be used in
conjunction with the accumulator (ADC0ACC) to allow an
average current calculation to be undertaken. The result counter is
enabled via ADCCFG[0]. This MMR is also reset to 0 when the
I-ADC is reconfigured, that is, when the ADC0CON or ADCMDE
is written.
Name: ADC2GN
Current Channel ADC Threshold Register
Address: 0xFFFF0544
Name: ADC0TH
Default Value: Part specific, factory programmed
Address: 0xFFFF0550
Access: Read/write
Default Value: 0x0000
Function: This gain MMR holds a 16-bit gain calibration
coefficient for scaling a temperature channel conversion result.
The register is configured at power-on with a factory default
value. However, this register is automatically overwritten if a
gain calibration of the temperature channel is initiated by the
user via bits in the ADCMDE MMR. User code can write to this
calibration register only if the ADC is in idle mode. An ADC
must be enabled and in idle mode before being written to any
offset or gain register. The ADC must be in idle mode for at
least 23 μs.
Access: Read/write
Current Channel ADC Result Counter Limit Register
Access: Read/write
Name: ADC0RCL
Function: This 8-bit MMR determines how many cumulative
(that is, values that are below the threshold decrement or that
reset the count to 0) I-ADC conversion result readings above
ADC0TH must occur before the I-ADC comparator threshold
bit is set in the ADCSTA MMR, generating an ADC interrupt.
The I-ADC comparator threshold bit is asserted as soon as
ADC0THV = ADC0TCL.
Address: 0xFFFF0548
Default Value: 0x0001
Access: Read/write
Function: This 16-bit MMR sets the number of conversions
that are required before an ADC interrupt is generated. By
default, this register is set to 0x0001. The ADC counter function
must be enabled via the ADC result counter enable bit in the
ADCCFG MMR.
Function: This 16-bit MMR sets the threshold against which the
absolute value of the I-ADC conversion result is compared. In
unipolar mode, ADC0TH[15:0] are compared, and in twos
complement mode, ADC0TH[14:0] are compared.
Current Channel ADC Threshold Count Limit Register
Name: ADC0TCL
Address: 0xFFFF0554
Default Value: 0x01
Current Channel ADC Threshold Count Register
Name: ADC0THV
Address: 0xFFFF0558
Default Value: 0x00
Access: Read only
Function: This 8-bit MMR is incremented every time the
absolute value of an I-ADC conversion result is |I| ≥ ADC0TH.
This register is decremented or reset to 0 every time the
absolute value of an I-ADC conversion result is |I| < ADC0TH.
The configuration of this function is enabled via the current
channel ADC comparator bits in the ADCCFG MMR.
Rev. C | Page 54 of 132
ADuC7036
Current Channel ADC Accumulator Register
Name: ADC0ACC
Address: 0xFFFF055C
Default Value: 0x00000000
Access: Read only
Function: This 32-bit MMR holds the current accumulator
value. The I-ADC ready bit in the ADCSTA MMR should be
used to determine when it is safe to read this MMR. The MMR
value is reset to 0 by disabling the accumulator in the ADCCFG
MMR or reconfiguring the current channel ADC.
Low Power Voltage Reference Scaling Factor Register
Name: ADCREF
Address: 0xFFFF057C
Default Value: Part specific, factory programmed
Access: Read/write. Care should be taken not to write to this
register.
Function: This MMR allows user code to correct for the initial
error of the LPM reference. Value 0x8000 corresponds to no
error when compared to the normal mode reference. The magnitude of the ADC result should be multiplied by the value in
ADCREF and divided by 0x8000 to compensate for the actual
value of the low power reference. If the LPM voltage reference
is 1% below 1.2 V, the value of ADCREF is approximately
0x7EB9. If the LPM voltage reference is 1% above 1.2 V, the
value of ADCREF is approximately 0x8147.
This register corrects the effective value of the LPM reference at
the temperature at which the reference is measured during the
Analog Devices, Inc., production flow, which is 25°C. There is
no change to the temperature coefficient of the LPM reference
when using the ADCREF MMR.
This register should not be used if the precision reference is
being used in low power mode (if ADCMDE[5] is set).
ADC POWER MODES OF OPERATION
The ADCs can be configured into various reduced or full
power modes of operation by changing the configuration of
ADCMDE[4:3], and the ARM7 MCU can be configured in low
power modes of operation (POWCON[5:3]). The core power
modes are independently controlled and are not related to the
ADC power modes described in the following sections.
ADC Normal Power Mode
In normal mode, the current and voltage/temperature channels
are fully enabled. The ADC modulator clock is 512 kHz and
enables the ADCs to provide regular conversion results at a rate
between 4 Hz and 8 kHz (see the ADC Filter Register section).
Both channels are under full control of the MCU and can be
reconfigured at any time. The default ADC update rate for all
channels in this mode is 1 kHz.
Note that the I-ADC and V-/T-ADC channels can be
configured to initiate periodic single conversion cycles in
normal power mode with high accuracy before returning to
ADC full power-down mode. This flexibility is facilitated by
full MCU control via the ADCMDE MMR, which ensures the
feasibility of continuous periodic monitoring of battery current,
voltage, and temperature settings while minimizing the average
dc current consumption.
In ADC normal mode, the PLL must not be powered down.
ADC Low Power Mode
In ADC low power mode, the I-ADC is enabled in a reduced
power and reduced accuracy configuration. The ADC modulator clock is driven directly from the on-chip 131 kHz low
power oscillator, which allows the ADC to be configured at
update rates as low as 1 Hz (ADCFLT). The gain of the ADC
in this mode is fixed at 128.
All ADC peripheral functions (result counter, digital comparator
and accumulator) described in the ADC Normal Power Mode
section can also be enabled in low power mode.
Typically, in low power mode, only the I-ADC is configured to
run at a low update rate, continuously monitoring battery current.
The MCU is in power-down mode and wakes up when the I-ADC
interrupts the MCU. Such an interrupt occurs after the I-ADC
detects a current conversion beyond a preprogrammed threshold,
a setpoint, or a set number of conversions.
It is also possible to select either the ADC precision voltage
reference or the ADC low power mode voltage reference via
ADCMDE[5].
ADC Low Power Plus Mode
In low power plus mode, the I-ADC channel is enabled in a
mode almost identical to low power mode (ADCMDE[4:3]).
However, in this mode, the I-ADC gain is fixed at 512, and the
ADC consumes an additional 200 μA (approximately) to yield
improved noise performance relative to the low power mode
setting.
All ADC peripheral functions (result counter, digital comparator,
and accumulator) described in the ADC Normal Power Mode
section can also be enabled in low power plus mode.
As in low power mode, only the I-ADC is configured to run at
a low update rate, continuously monitoring battery current. The
MCU is in power-down mode and wakes up only when the I-ADC
interrupts the MCU. This happens after the I-ADC detects a
current conversion result that exceeds a preprogrammed
threshold or a setpoint.
It is also possible to select either the ADC precision voltage
reference or the ADC low power mode voltage reference via
ADCMDE[5].
Rev. C | Page 55 of 132
ADuC7036
0
ADC COMPARATOR AND ACCUMULATOR
By also incorporating a 32-bit accumulator (ADC0ACC) function
that can be configured via ADCCFG[6:5], the I-ADC can add or
subtract multiple I-ADC sample results. User code can read the
accumulated value directly (ADC0ACC) without any further
software processing.
–30
–40
–50
–60
–70
–80
–90
–100
0
500
1000 1500 2000 2500 3000 3500 4000 4500 5000
FREQUENCY (kHz)
07474-021
Every I-ADC result can be compared with a preset threshold
level (ADC0TH) that is set via ADCCFG[4:3]. In this case, an
MCU interrupt is generated if the absolute (sign independent)
value of the ADC result is greater than the preprogrammed
comparator threshold level. Alternatively, as an extended
function of the comparator, user code can configure a threshold
counter (ADC0THV) to monitor the number of I-ADC results
that have occurred above or below the preset threshold level. In
this case, an ADC interrupt is generated when the threshold
counter reaches a preset value that is set via ADC0TCL.
–20
ATTENUATION (dB)
The incorporation of comparator logic on the I-ADC allows the
I-ADC result to generate an interrupt after a predefined number of
conversions has elapsed or a programmable threshold value has
been exceeded.
–10
Figure 22. Typical Digital Filter Response at fADC = 1 kHz
(ADCFLT = 0x0007)
In addition, a Sinc3 modify bit (ADCFLT[7]) is available in the
ADCFLT register. This bit is set by user code and modifies the
standard Sinc3 frequency response to increase the filter stopband rejection by approximately 5 dB. This is achieved by
inserting a second notch at the location determined by
fNOTCH2 = 1.333 × fNOTCH
ADC SINC3 DIGITAL FILTER RESPONSE
There is a slight increase in ADC noise if the Sinc3 modify bit is
active. Figure 23 shows the modified 1 kHz filter response when
the Sinc3 modify bit is active. The new notch is clearly visible at
1.33 kHz, as is the improvement in stop-band rejection when
compared with the standard 1 kHz response.
0
–10
–20
By default, setting ADCFLT = 0x0007 configures the ADCs for
a throughput of 1 kHz with all other filtering options (chop,
running average, averaging factor, and Sinc3 modify) disabled.
A typical filter response based on this default configuration is
shown in Figure 22.
Rev. C | Page 56 of 132
–30
–40
–50
–60
–70
–80
–90
–100
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
FREQUENCY (kHz)
Figure 23. Modified Sinc3 Digital Filter Response at fADC = 1 kHz
(ADCFLT = 0x0087)
07474-022
The overall frequency response and the ADC throughput is
dominated by the configuration of the Sinc3 filter decimation
factor (SF) bits (ADCFLT[6:0]) and the averaging factor (AF)
bits (ADCFLT[13:8]). Due to limitations on the digital filter
internal data path, there are some limitations on the allowable
combinations of SF and AF that can be used to generate a required
ADC output rate. This restriction limits the minimum ADC
update to 4 Hz in normal power mode and to 1 Hz in low power
mode. The calculation of the ADC throughput rate is detailed
in the ADCFLT bit designations table (see Table 39), and the
restrictions on allowable combinations of AF and SF values are
outlined in Table 41.
where fNOTCH is the location of the first notch in the response.
ATTENUATION (dB)
The overall frequency response on all ADuC7036 ADCs is
dominated by the low-pass filter response of the on-chip Sinc3
digital filters. The Sinc3 filters are used to decimate the ADC
Σ-Δ modulator output data bit stream to generate a valid 16-bit
data result. The digital filter response is identical for all ADCs
and is configured via the 16-bit ADC filter register (ADCFLT).
This register determines the overall throughput rate of the ADCs.
The noise resolution of the ADCs is determined by the programmed ADC throughput rate. In the case of the current
channel ADC, the noise resolution is determined by throughput
rate and selected gain.
ADuC7036
For example, with the chop enable bit (ADCFLT[15]) set to 1,
the SF value (ADCFLT[6:0]) increases to 0x1F (31 decimal) and
an AF value (ADCFLT[13:8]) of 0x16 (22 decimal) is selected,
resulting in an ADC throughput of 10 Hz. The frequency
response in this case is shown in Figure 26.
0
–10
–20
–20
–30
–30
–40
–50
–60
–70
–40
–50
–60
–70
–80
–80
–90
–90
–100
0
2
4
6
8
10
12
14
16
18
20
22
24
FREQUENCY (kHz)
–100
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY (kHz)
07474-025
ATTENUATION (dB)
0
–10
07474-023
ATTENUATION (dB)
In ADC normal power mode, the maximum ADC throughput
rate is 8 kHz. This is configured by setting the SF and AF bits in
the ADCFLT MMR to 0, with all other filtering options disabled.
As a result, 0x0000 is written to ADCFLT. Figure 24 shows a
typical 8 kHz filter response based on these settings.
Figure 24. Typical Digital Filter Response at fADC = 8 kHz (ADCFLT = 0x0000)
Figure 26. Typical Digital Filter Response at fADC = 10 Hz (ADCFLT = 0x961F)
A modified version of the 8 kHz filter response can be configured
by setting the running average bit (ADCFLT[14]). As a result,
an additional running-average-by-two filter is introduced on all
ADC output samples, which further reduces the ADC output
noise. In addition, by maintaining an 8 kHz ADC throughput
rate, the ADC settling time is increased by one full conversion
period. The modified frequency response for this configuration
is shown in Figure 25.
Changing SF to 0x1D and setting AF to 0x3F with the chop enable
bit still enabled configures the ADC with its minimum throughput
rate of 4 Hz in normal mode. The digital filter frequency response
with this configuration is shown in Figure 27.
–10
–20
ATTENUATION (dB)
0
–10
–20
–30
–40
–40
–50
–60
–70
–80
–50
–90
–60
–100
–70
0
20
40
FREQUENCY (kHz)
–80
60
Figure 27. Typical Digital Filter Response at fADC = 4 Hz (ADCFLT = 0xBF1D)
0
2
4
6
8
10
12
14
16
FREQUENCY (kHz)
18
20
22
24
07474-024
–90
–100
–30
07474-026
ATTENUATION (dB)
0
Figure 25. Typical Digital Filter Response at fADC = 8 kHz (ADCFLT = 0x4000)
At very low throughput rates, the chop enable bit in the
ADCFLT register can be enabled to minimize offset errors and,
more importantly, temperature drift in the ADC offset error.
With chop enabled, there are two primary variables (Sinc3
decimation factor and averaging factor) available to allow the
user to select an optimum filter response, but there is a trade-off
between filter bandwidth and ADC noise.
In ADC low power mode, the Σ-Δ modulator clock of the ADC
is no longer driven at 512 kHz, but is driven directly from the
on-chip, low power, 131 kHz oscillator. Subsequently, if normal
mode is used for the same ADCFLT configuration, all filter values
should be scaled by a factor of approximately 4. Therefore, it is
possible to configure the ADC for 1 Hz throughput in low power
mode. The filter frequency response for this configuration is shown
in Figure 28.
Rev. C | Page 57 of 132
ADuC7036
0
In general, it is possible to program different values of SF and
AF in the ADCFLT register and achieve the same ADC update
rate. However, in practical terms, users should consider the tradeoff between frequency response and ADC noise for any value of
ADCFLT. For optimum filter response and ADC noise when
using combinations of SF and AF, best practice suggests choosing
an SF in the range of 16 decimal to 40 decimal, or 0x10 to 0x28,
and then increasing the AF value to achieve the required ADC
throughput. Table 43 provides information about some common
ADCFLT configurations.
–10
ATTENUATION (dB)
–20
–30
–40
–50
–60
–70
–80
–100
0
2
4
6
8
10
12
14
FREQUENCY (kHz)
16
18
20
07474-027
–90
Figure 28. Typical Digital Filter Response at fADC = 1 Hz (ADCFLT = 0xBD1F)
Table 43. Common ADCFLT Configurations
ADC Mode
Normal
Normal
Normal
Normal
Normal
Normal
Low Power
Low Power
Low Power
SF
0x1D
0x1F
0x07
0x07
0x03
0x00
0x10
0x10
0x1F
AF
0x3F
0x16
0x00
0x00
0x00
0x00
0x03
0x09
0x3D
Other Configuration
Chop on
Chop on
None
Sinc3 modify
Running average
Running average
Chop on
Chop on
Chop on
Rev. C | Page 58 of 132
ADCFLT
0xBF1D
0x961F
0x0007
0x0087
0x4003
0x4000
0x8310
0x8910
0xBD1F
fADC
4 Hz
10 Hz
1 kHz
1 kHz
2 kHz
8 kHz
20 Hz
10 Hz
1 Hz
tSETTLE
0.5 sec
0.2 sec
3 ms
3 ms
2 ms
0.5 ms
100 ms
200 ms
2 sec
ADuC7036
ADC CALIBRATION
As shown in detail in the top-level diagrams (Figure 18 and
Figure 19), the signal flow through all ADC channels can be
described as follows:
1.
2.
3.
4.
5.
6.
An input voltage is applied through an input buffer (and
through PGA in the case of the I-ADC) to the Σ-Δ modulator.
The modulator output is applied to a programmable digital
decimation filter.
The filter output result is then averaged if chopping is used.
An offset value (ADCxOF) is subtracted from the result.
This result is scaled by a gain value (ADCxGN).
The result is formatted as twos complement/offset binary
and rounded to 16 bits or clamped to ±full scale.
Each ADC has a specific offset and gain correction or calibration coefficient associated with it that are stored in MMR-based
offset and gain registers (ADCxOF and ADCxGN). The offset
and gain registers can be used to remove offsets and gain errors
within the part, as well as system-level offset and gain errors
external to the part.
These registers are configured at power-on with a factoryprogrammed calibration value. These factory-set calibration
values vary from part to part, reflecting the manufacturing
variability of internal ADC circuits. However, these registers
can also be overwritten by user code if the ADC is in idle mode
and are automatically overwritten if an offset or gain calibration
cycle is initiated by the user through the ADC operation mode
configuration bits in the ADCMDE[2:0] MMR. Two types of
automatic calibration are available to the user: self-calibration
or system calibration.
Self-Calibration
In self-calibration of offset errors, the ADC generates its
calibration coefficient based on an internally generated 0 V,
whereas in self-calibration of gain errors, the coefficient is
based on the full-scale voltage. Although self-calibration
can correct offset and gain errors within the ADC, it cannot
compensate for external errors in the system, such as shunt
resistor tolerance/drift and external offset voltages.
Note that in self-calibration mode, ADC0GN must contain the
values for PGA = 1 before a calibration scheme is started.
immediately halted, the calibration is automatically performed
at the ADC update rate programmed in ADCFLT, and the ADC
is always returned to idle after any calibration cycle. It is strongly
recommended that ADC calibration be initiated at as low an
ADC update rate as possible (and, therefore, requires a high SF
value in ADCFLT) to minimize the impact of ADC noise during
calibration.
Using the Offset and Gain Calibration
If the chop enable bit, ADCFLT[15], is enabled, internal ADC
offset errors are minimized and an offset calibration may not be
required. If chopping is disabled, however, an initial offset
calibration is required and may need to be repeated, particularly
after a large change in temperature.
Depending on system accuracy requirements, a gain calibration,
particularly in the context of the I-ADC (with internal PGA), may
need to be performed at all relevant system gain ranges. If it is
not possible to apply an external full-scale current on all gain
ranges, apply a lower current and then scale the result produced
by the calibration. For example, apply a 50% current, and then
divide the resulting ADC0GN value by 2 and write this value back
into ADC0GN. Note that there is a lower limit for the input signal
that can be applied during a system calibration because
ADC0GN is only a 16-bit register. The input span (that is, the
difference between the system zero-scale value and the system
full-scale value) should be greater than 40% of the nominal fullscale-input range (that is, >40% of VREF/gain).
The on-chip Flash/EE memory can be used to store multiple
calibration coefficients. These calibration coefficients can be copied
directly into the relevant calibration registers by user code and
are based on the system configuration. In general, the simplest
way to use the calibration registers is to let the ADC calculate the
values required as part of the ADC automatic calibration modes.
A factory-programmed or end-of-line calibration for the I-ADC
is a two-step procedure.
1.
2.
System Calibration
In system calibration of offset errors, the ADC generates its
calibration coefficient based on an externally generated zeroscale voltage, whereas in system calibration of gain errors, the
coefficient is based on the full-scale voltage. The calibration
coefficient is applied to the external ADC input for the duration
of the calibration cycle.
The duration of an offset calibration is a single conversion cycle
(3/fADC chop off, 2/fADC chop on) before returning the ADC to
idle mode. A gain calibration is a two-stage process and, therefore, takes twice as long as an offset calibration cycle. When a
calibration cycle is initiated, any ongoing ADC conversion is
Apply 0 A current. Configure the ADC in the required PGA
setting, and write to ADCMDE[2:0] to perform a system
zero-scale calibration. This writes a new offset calibration
value into ADC0OF.
Apply a full-scale current for the selected PGA setting. Write
to ADCMDE to perform a system full-scale calibration. This
writes a new gain calibration value into ADC0GN.
Understanding the Offset and Gain Calibration Registers
The output of a typical block in the ADC signal flow (described
in the ADC Sinc3 Digital Filter Response section through the
Using the Offset and Gain Calibration section) can be considered a fractional number with a span for a ±full-scale input of
approximately ±0.75. The span is less than ±1 because there is
attenuation in the modulator to accommodate some overrange
capacity on the input signal. The exact value of the attenuation
varies slightly from part to part because of manufacturing
tolerances.
Rev. C | Page 59 of 132
ADuC7036
The offset coefficient is read from the ADC0OF calibration
register and is a 16-bit, twos complement number. The range of
this number, in terms of the signal chain, is effectively ±1.
Therefore, 1 LSB of the ADC0OF register is not the same as
1 LSB of the ADC0DAT register.
A positive value of ADC0OF indicates that when offset is
subtracted from the output of the filter, a negative value is added.
The nominal value of this register is 0x0000, indicating zero
offset is to be removed. The actual offset of the ADC can vary
slightly from part to part and at different PGA gains. The offset
within the ADC is minimized if the chopping mode is enabled
(that is, ADCFLT[15] = 1).
The gain coefficient is read from the ADC0GN register and is a
unitless scaling factor. The 16-bit value in this register is divided
by 16,384 and then multiplied by the offset-corrected value. The
nominal value of this register equals 0x5555, corresponding to a
multiplication factor of 1.3333, and scales the nominal ±0.75 signal
to produce a full-scale output signal of ±1. The resulting output
signal is checked for overflow/underflow and converted to twos
complement or unipolar mode before being output to the data
register.
The actual gain and the required scaling coefficient for zero
gain error vary slightly from part to part at different PGA settings in normal and low power modes. The value downloaded into
ADC0GN during a power-on reset represents the scaling factor
for a PGA gain of 1. If a different PGA setting is used, however,
some gain error may be present. To correct this error, overwrite
the calibration coefficients via user code or perform an ADC
calibration.
The simplified ADC transfer function can be described as
For the current channel ADC,
⎡ V × PGA
⎤
ADCxGN
− K × ADCxOF ⎥ ×
ADC OUT = ⎢ IN
⎣ VREF
⎦ ADCxGN NOM
where K is dependent on the PGA gain setting and ADC mode.
Normal Mode
In normal mode, K = 1 for PGA gains of 1, 4, 8, 16, 32, and 64;
K = 2 for PGA gains of 2 and 128; K = 4 for a PGA gain of 256;
and K = 8 for a PGA gain of 512.
Low Power Mode
In low power mode, K = 32 for a PGA gain of 128. In addition,
if the REG_AVDD/2 reference is used, the K factor doubles.
Low Power Plus Mode
In low power plus mode, K = 8 for a PGA gain of 512. In addition,
if the REG_AVDD/2 reference is used, the K factor doubles.
ADC DIAGNOSTICS
The ADuC7036 features a diagnostic capability and opencircuit detection on both ADCs.
Current ADC Diagnostics
The ADuC7036 features the capability to detect open-circuit
conditions on the current channel inputs. This is accomplished
using the two current sources on IIN+ and IIN−, which are
controlled via ADC0CON[14:13].
Note that the IIN+ and IIN− current sources have a tolerance of
±30%. Therefore, a PGA gain ≥ 2 (ADC0CON[3:0] ≥ 0001) must
be used when current sources are enabled.
Temperature ADC Diagnostics
⎡ V × PGA
⎤
ADCxGN
− ADCxOF ⎥ ×
ADC OUT = ⎢ IN
⎣ VREF
⎦ ADCxGN NOM
where the equation is valid for the voltage/temperature channel ADC.
The ADuC7036 features the capability to detect open-circuit
conditions on the temperature channel inputs. This is
accomplished using the two current sources on VTEMP and
GND_SW, which are controlled via ADC1CON[14:13].
Voltage ADC Diagnostics
The ADuC7036 features the capability to detect open-circuit
conditions on the voltage channel input. This is accomplished
using the current source on the voltage attenuator, controlled by
the high voltage register HVCFG1[7].
Rev. C | Page 60 of 132
ADuC7036
POWER SUPPLY SUPPORT CIRCUITS
The ADuC7036 incorporates two on-chip low dropout (LDO)
regulators that are driven directly from the battery voltage to
generate a 2.6 V internal supply. This 2.6 V supply is then used
as the supply voltage for the ARM7 MCU and the peripherals,
including the on-chip precision analog circuits.
The digital LDO functions with two output capacitors (2.2 μF
and 0.1 μF) in parallel on REG_DVDD, whereas the analog LDO
functions with an output capacitor (0.47 μF) on REG_AVDD.
The ESR of the output capacitor affects stability of the LDO
control loop. An ESR of 5 Ω or less for frequencies greater than
32 kHz is recommended to ensure the stability of the regulators.
In addition, the power-on reset (POR), power supply monitor
(PSM), and low voltage flag (LVF) functions are integrated to
ensure safe operation of the MCU, as well as continuous
monitoring of the battery power supply.
The POR circuit is designed to operate with a VDD (0 V to 12 V)
power-on time of greater than 100 μs. It is, therefore, recommended that the external power supply decoupling components
be carefully selected to ensure that the VDD supply power-on
time can always be guaranteed to be greater than 100 μs, regardless
of the VBAT power-on conditions. The series resistor and
decoupling capacitor combination on VDD should be chosen
to result in an RC time constant of at least 100 μs (for example,
10 Ω and 10 μF, as shown on Figure 60).
As shown in Figure 29, when the supply voltage on VDD reaches
a typical operating voltage of 3 V, a POR signal keeps the ARM
core in reset state for 20 ms. This ensures that the regulated
power supply voltage (REG_DVDD) applied to the ARM core
and associated peripherals is greater than the minimum operational voltage, thereby guaranteeing full functionality. A POR
flag is set in the RSTSTA MMR to indicate a POR event has
occurred.
The ADuC7036 also features a PSM function. When enabled
through HVCFG0[3], the PSM continuously monitors the voltage
at the VDD pin. If this voltage drops below 6 V typical, the PSM
flag is automatically asserted and can generate a system interrupt
if the high voltage IRQ is enabled via IRQEN[16] or FIQEN[16].
An example of this operation is shown in Figure 29.
At voltages below the POR level, an additional low voltage flag
can be enabled (HVCFG0[2]). This flag can be used to indicate
that the contents of the SRAM remain valid after a reset event.
The operation of the low voltage flag is shown in Figure 29. When
HVCFG0[2] is enabled, the status of this bit can be monitored
via HVMON[3]. If the HVCFG0[2] bit is set, the SRAM contents
are valid. If this bit is cleared, the SRAM contents may become
corrupted.
12V
PSM TRIP 6V TYP
VDD
3V TYP
POR TRIP 3V TYP
LVF TRIP 2.1V TYP
2.6V
REG_DVDD
20ms TYP
POR_TRIP
RESET_CORE
(INTERNAL SIGNAL)
07474-028
ENABLE_PSM
ENABLE_LVF
Figure 29. Typical Power-On Cycle
Rev. C | Page 61 of 132
ADuC7036
SYSTEM CLOCKS
The ADuC7036 integrates a very flexible clocking system that
allows clock generation from one of three sources: an integrated
on-chip precision oscillator, an integrated on-chip low power
oscillator, or an external watch crystal. These three options are
shown in Figure 30.
turn, is driven by a clock divider (set by the CD bits in the
POWCON register). By default, the CD bits are configured to
divide the PLL output by 2, thereby generating a core clock of
10.24 MHz. The divide factor can be modified to generate a
binary-weighted divider factor in the range of 1 to 128 that can
be altered dynamically by user code.
Each of the internal oscillators is divided by 4 to generate a clock
frequency of 32.768 kHz. The PLL locks onto a multiple (625)
of 32.768 kHz, supplied by either of the internal oscillators or
the external crystal to provide a stable 20.48 MHz clock for the
system. The core can operate at this frequency or at a binary
submultiple of this frequency, thereby allowing power saving
when peak performance is not required.
The ADC is driven by the output of the PLL, which is divided to
provide an ADC clock source of 512 kHz. In low power mode,
the ADC clock source is switched from the standard 512 kHz to
the low power 131 kHz oscillator.
Note that the low power oscillator drives both the watchdog and
core wake-up timers through a divide-by-4 circuit. A detailed
block diagram of the ADuC7036 clocking system is shown in
Figure 30.
By default, the PLL is driven by the low power oscillator that
generates a 20.48 MHz clock source. The ARM7TDMI core, in
PRECISION
131kHz
EXTERNAL CRYSTAL
(OPTIONAL)
EXTERNAL
32.768kHz
CRYSTAL
CIRCUITRY
PRECISION
131kHz
EXTERNAL
32.768kHz
PRECISION
OSCILLATOR
LOW POWER
131kHz
LOW POWER
OSCILLATOR
LOW POWER
OSCILLATOR
PRECISION
32.768kHz
PRECISION
32.768kHz
DIV 4
LOW POWER
32.768kHz
TIMER0
LIFETIME
CORE CLOCK
PLLCON
PLL
LOW POWER
CALIBRATION
COUNTER
EXTERNAL
32.768kHz
LOW POWER
32.768kHz
DIV 4
HIGH ACCURCY
CALIBRATION
COUNTER
GPIO_5
GPIO_8
ECLK 2.5MHz
CORE CLOCK
TIMER1
GENERAL-PURPOSE
LOW POWER
32.768kHz
CLOCK
DIVIDER
PLL OUTPUT
20.48MHz
CORE CLOCK
EXTERNAL
32.768kHz
PLL LOCK
ADCMDE
FLASH
CONTROLLER
LOW POWER
32.768kHz
CORE
CLOCK
ADC
CLOCK
MCU
LOW POWER
32.768kHz
ADC
CORE CLOCK
UART
PLL OUTPUT
(5MHz)
Figure 30. System Clock Generation
Rev. C | Page 62 of 132
WATCHDOG
TIMER3
TIMER4
STI
CORE CLOCK
LOW POWER
32.768kHz
CORE CLOCK
SPI
TIMER2
WAKE-UP
LOW POWER
32.768kHz
1
2CD
PLL OUTPUT
(20.48MHz)
PRECISION
32.768kHz
LIN H/W
SYNCHRONIZATION
07474-029
1
8
ADuC7036
The operating mode, clocking mode, and programmable clock
divider are controlled using two MMRs, PLLCON and POWCON,
and the status of the PLL is indicated by PLLSTA. PLLCON
controls the operating mode of the clock system, and POWCON
controls both the core clock frequency and the power-down mode.
PLLSTA indicates the presence of an oscillator on the XTAL1 pin
and provides information about the PLL lock status and the PLL
interrupt.
Before powering down the ADuC7036, it is recommended that the
clock source for the PLL be switched to the low power 131 kHz
oscillator to reduce wake-up time. The low power oscillator is
always active.
When the ADuC7036 wakes up from power-down, the MCU
core begins executing code as soon as the PLL starts oscillating.
This code execution occurs before the PLL has locked to a frequency of 20.48 MHz. To ensure that the Flash/EE memory
controller is executing with a valid clock, the controller is driven
with a PLL output divide-by-8 clock source while the PLL is
locking. When the PLL locks, the PLL output is switched from
the PLL output divide-by-8 to the locked PLL output.
If user code requires an accurate PLL output, user code must poll
the PLL lock status bit (PLLSTA[1]) after a wake-up before
resuming normal code execution.
The PLL is locked within 2 ms if the PLL is clocked from an
active clock source, such as a low power 131 kHz oscillator,
after waking up.
PLLCON is a protected MMR with two 32-bit keys: PLLKEY0
(prewrite key) and PLLKEY1 (postwrite key). They key values
are as follows:
An example of writing to both MMRs is as follows:
POWKEY0
=
0x01
//POWCON key
POWCON
=
0x00
//Full power-down
POWKEY1
=
0xF4
//POWCON KEY
iA1*iA2
//Dummy cycle to
clear the pipeline, where iA1 and iA2 are
defined as longs and are not 0
PLLKEY0
=
0xAA
//PLLCON key
PLLCON
=
0x0
//Switch to Low
Power Osc.
PLLKEY1
=
0x55
//PLLCON key
iA1*iA2
//Dummy cycle to
prevent Flash/EE access during clock change
SYSTEM CLOCK REGISTERS
PLLSTA Register
Name: PLLSTA
Address: 0xFFFF0400
Default Value: N/A
Access: Read only
Function: This 8-bit register allows user code to monitor the
lock state of the PLL and the status of the external crystal.
Table 44. PLLSTA MMR Bit Designations
Bit
7 to 3
2
1
PLLKEY0 = 0x000000AA
PLLKEY1 = 0x00000055
POWCON is a protected MMR with two 32-bit keys: POWKEY0
(prewrite key) and POWKEY1 (postwrite key).
0
POWKEY0 = 0x00000001
POWKEY1 = 0x000000F4
Rev. C | Page 63 of 132
Description
Reserved.
XTAL clock. This read only bit is a live representation of
the current logic level on XTAL1. It indicates if an external
clock source is present by alternating between high and
low at a frequency of 32.768 kHz.
PLL lock status bit. This is a read only bit.
Set when the PLL is locked and outputting 20.48 MHz.
Cleared when the PLL is not locked and outputting an
fCORE divide-by-8 clock source.
PLL interrupt.
Set if the PLL lock status bit signal goes low.
Cleared by writing 1 to this bit.
ADuC7036
PLLCON Prewrite Key
Table 45. PLLCON MMR Bit Designations
Name: PLLKEY0
Bit
7 to 2
1 to 0
Address: 0xFFFF0410
Access: Write only
Key: 0x000000AA
Function: This keyed register requires a 32-bit key value to be
written before and after PLLCON. PLLKEY0 is the prewrite key.
PLLCON Postwrite Key
1
Name: PLLKEY1
Description
Reserved. These bits should be written as 0 by user code.
PLL clock source.1
00 = lower power, 131 kHz oscillator.
01 = precision 131 kHz oscillator.
10 = external 32.768 kHz crystal.
11 = reserved.
If the user code switches MCU clock sources, a dummy MCU cycle should be
included after the clock switch is written to PLLCON.
POWCON Prewrite Key
Address: 0xFFFF0418
Name: POWKEY0
Access: Write only
Address: 0xFFFF0404
Key: 0x00000055
Access: Write only
Function: This keyed register requires a 32-bit key value to be
written before and after PLLCON. PLLKEY1 is the postwrite key.
Key: 0x00000001
PLLCON Register
Name: PLLCON
Function: This keyed register requires a 32-bit key value to be
written before and after POWCON. POWKEY0 is the prewrite key.
POWCON Postwrite Key
Address: 0xFFFF0414
Name: POWKEY1
Default Value: 0x00
Address: 0xFFFF040C
Access: Read/write
Access: Write only
Function: This 8-bit register allows user code to dynamically
select the PLL source clock from three different oscillator sources.
Key: 0x000000F4
Function: This keyed register requires a 32-bit key value to
be written before and after POWCON. POWKEY1 is the postwrite key.
Rev. C | Page 64 of 132
ADuC7036
POWCON Register
Name: POWCON
Address: 0xFFFF0408
Default Value: 0x79
Access: Read/write
Function: This 8-bit register allows user code to dynamically enter various low power modes and modify the CD divider that controls the
speed of the ARM7TDMI core.
Table 46. POWCON MMR Bit Designations
Bit
7
6
5
4
3
2 to 0
Description
Precision 131 kHz input enable.
Set by the user to enable the precision 131 kHz input enable. The precision 131 kHz oscillator must also be enabled using HVCFG0[6].
Setting this bit increases current consumption by approximately 50 μA. It should be disabled when not in use.
Cleared by the user to power-down the precision 131 kHz input enable.
XTAL power-down.
Set by the user to enable the external crystal circuitry.
Cleared by the user to power down the external crystal circuitry.
PLL power-down. Timer peripherals power down if driven from the PLL output clock. Timers driven from an active clock source
remain in normal power mode.
Set by default and set by hardware on a wake-up event.
Cleared to 0 to power down the PLL. The PLL cannot be powered down if either the core or peripherals are enabled: Bit 3, Bit 4,
and Bit 5 must be cleared simultaneously.
Peripherals power-down. The peripherals that are powered down by this bit are as follows: SRAM, Flash/EE memory and GPIO
interfaces, and SPI and UART serial ports.
Set by default and/or by hardware on a wake-up event. The wake-up timer (Timer2) can still be active if driven from a low power
oscillator even if this bit is set.
Cleared to power down the peripherals. The peripherals cannot be powered down if the core is enabled: Bit 3 and Bit 4 must be
cleared simultaneously. LIN can still respond to wake-up events even if this bit is cleared.
Core power-down. If user code powers down the MCU, include a dummy MCU cycle after the power-down command is written to
POWCON.
Set by default, and set by hardware on a wake-up event.
Cleared to power down the ARM core.
CD core clock divider bits.
000 = 20.48 MHz, 48.83 ns.
001 = 10.24 MHz, 97.66 ns (this is default setting on power up).
010 = 5.12 MHz, 195.31 ns.
011 = 2.56 MHz, 390.63 ns.
100 = 1.28 MHz, 781.25 ns.
101 = 640 kHz, 1.56 μs.
110 = 320 kHz, 3.125 μs.
111 = 160 kHz, 6.25 μs.
Rev. C | Page 65 of 132
ADuC7036
LOW POWER CLOCK CALIBRATION
The low power 131 kHz oscillator can be calibrated using either
the precision 131 kHz oscillator or an external 32.768 kHz watch
crystal. Two dedicated calibration counters and an oscillator
trim register are used to implement this feature.
The first counter (Counter 0) is nine bits wide and is clocked by
an accurate clock oscillator, either the precision oscillator or an
external watch crystal. The second counter (Counter 1) is 10 bits
wide and is clocked by the low power oscillator, either directly
at 131 kHz or through a divide-by-4 block generating 32.768 kHz.
The source for each calibration counter should be of the same
frequency. The trim register (OSC0TRM) is an 8-bit-wide register,
the lower four bits of which are user-accessible trim bits. Increasing
the value in OSC0TRM decreases the frequency of the low power
oscillator. Conversely, decreasing the value in OSC0TRM increases
the frequency. Based on a nominal frequency of 131 kHz, the
typical trim range is between 127 kHz and 135 kHz.
When the value in OSC0TRM has been changed, the routine
should be run again, and the new frequency should be checked.
Using the internal precision 131 kHz oscillator requires approximately 4 ms to execute the calibration routine. If the external
32.768 kHz crystal is used, the time increases to 16 ms.
Prior to the start of the clock calibration routine, the user must
switch to either the precision 131 kHz oscillator or the external
32.768 kHz watch crystal to serve as the PLL clock source. If this
is not done, the PLL may lose lock each time OSC0TRM is
modified, thereby increasing the time required to calibrate the
low power oscillator.
The clock calibration mode is configured and controlled by the
following MMRs:
OSC0CON: control bits for calibration.
OSC0STA: calibration status register.
OSC0VAL0: 9-bit counter, Counter 0.
OSC0VAL1: 10-bit counter, Counter 1.
OSC0TRM: oscillator trim register.
•
OSC0VAL0 < OSC0VAL1
OSC0VAL0 > OSC0VAL1
OSC0VAL0 = OSC0VAL1
INCREASE
OSC0TRM
A calibration routine flowchart is shown in Figure 31. User code
configures and enables the calibration sequence using OSC0CON.
When the OSC0VAL0 precision power oscillator calibration
counter reaches 0x1FF, both counters are disabled. User code
then reads back the value of the low power oscillator calibration
counter. There are three possible scenarios:
•
•
WHILE
OSC0STA[0] = 1
OSC0VAL0 = OSC0VAL1. No further action is required.
OSC0VAL0 > OSC0VAL1. The low power oscillator is
running slow. OSC0TRM must be decreased.
OSC0VAL0 < OSC0VAL1. The low power oscillator is
running fast. OSC0TRM must be increased.
Rev. C | Page 66 of 132
NO
DECREASE
OSC0TRM
IS ERROR WITHIN
DESIRED LEVEL?
YES
END
CALIBRATION
ROUTINE
Figure 31. OSC0TRM Calibration Routine
07474-030
•
•
•
•
•
BEGIN
CALIBRATION
ROUTINE
ADuC7036
OSC0TRM Register
OSC0STA Register
Name: OSC0TRM
Name: OSC0STA
Address: 0xFFFF042C
Address: 0xFFFF0444
Default Value: 0xX8
Default Value: 0x00
Access: Read/write
Access: Read only
Function: This 8-bit register controls the low power oscillator trim.
Function: This 8-bit register gives the status of the low power
oscillator calibration routine.
Table 47. OSC0TRM MMR Bit Designations
Bit
7 to 4
3 to 0
Table 49. OSC0STA MMR Bit Designations
Description
Reserved. Should be written as 0.
User trim bits.
Bit
7 to 2
1
OSC0CON Register
Name: OSC0CON
0
Address: 0xFFFF0440
Default Value: 0x00
OSC0VAL0 Register
Access: Read/write
Function: This 8-bit register controls the low power oscillator
calibration routine.
3
2
1
0
Name: OSC0VAL0
Address: 0xFFFF0448
Default Value: 0x0000
Table 48. OSC0CON MMR Bit Designations
Bit
7 to 5
4
Description
Reserved.
Calibration complete.
Set by hardware on full completion of a calibration cycle.
Cleared by a read of OSC0VAL1.
Set if calibration is in progress.
Cleared if calibration is complete.
Description
Reserved. Should be written as 0.
Calibration source.
Set to select external 32.768 kHz crystal.
Cleared to select internal precision 131 kHz oscillator.
Calibration reset.
Set to reset the calibration counters and disable the
calibration logic.
Set to clear OSC0VAL1.
Set to clear OSC0VAL0.
Calibration enable.
Set to begin calibration.
Cleared to abort calibration.
Access: Read only
Function: This 9-bit counter is clocked from either the 131 kHz
precision oscillator or the 32.768 kHz external crystal.
OSC0VAL1 Register
Name: OSC0VAL1
Address: 0xFFFF044C
Default Value: 0x0000
Access: Read only
Function: This 10-bit counter is clocked from the low power,
131 kHz oscillator.
Rev. C | Page 67 of 132
ADuC7036
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 16 interrupt sources on the ADuC7036 that are controlled by the interrupt controller. Most interrupts are generated
from the on-chip peripherals, such as the ADC and UART. The
ARM7TDMI CPU core recognizes interrupts as one of only two
types: a normal interrupt request (IRQ) and a fast interrupt
request (FIQ). All the interrupts can be masked separately.
The control and configuration of the interrupt system is managed
through nine interrupt-related registers, with four dedicated to
IRQ and four dedicated to FIQ. An additional MMR is used to
select the programmed interrupt source. The bits in each IRQ
and FIQ register represent the same interrupt source as described
in Table 50.
IRQSTA/FIQSTA should be saved immediately upon entering
the interrupt service routine (ISR) to ensure that all valid interrupt
sources are serviced.
The interrupt generation route through the ARM7TDMI core is
shown in Figure 32.
Consider an example in which Timer0 is configured to generate
a timeout every 1 ms. After the first 1 ms timeout, FIQSIG[2] or
IRQSIG[2] is set and can be cleared only by writing to T0CLRI.
If Timer0 is not enabled in either IRQEN or FIQEN, then FIQSTA/
IRQSTA[2] is not set and an interrupt does not occur. However,
if Timer0 is enabled in either IRQEN or FIQEN, then either
FIQSTA[2] or IRQSTA[2] is set or an interrupt (FIQ or IRQ)
occurs.
Note that the IRQ and FIQ bit definitions in the CPSR control
interrupt recognition only by the ARM core and not by the peripherals. For example, if Timer2 is configured to generate an
IRQ via IRQEN, the IRQ interrupt bit is set (disabled) in the
CPSR and the ADuC7036 is powered down. When an interrupt
occurs, the peripherals wake up, but the ARM core remains
powered down. This is equivalent to POWCON = 0x71. The
ARM core can then be powered up only by a reset event.
Table 50. IRQ/FIQ MMRs Bit Designations
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
All interrupts OR’ed (FIQ only)
SWI: not used in IRQEN/IRQCLR and FIQEN/FIQCLR
Timer0
Timer1
Timer2 or wake-up timer
Timer3 or watchdog timer
Timer4 or STI timer
LIN hardware
Flash/EE interrupt
PLL lock
ADC
UART
SPI master
XIRQ0 (GPIO IRQ0)
XIRQ1 (GPIO IRQ1)
Reserved
IRQ3 high voltage IRQ
17
18
19
20 to
32
SPI slave
XIRQ4 (GPIO IRQ4)
XIRQ5 (GPIO IRQ5)
Reserved
Comments
See the Timer0—Lifetime Timer section.
See the Timer1 section.
See the Timer2—Wake-Up Timer section.
See the Timer3—Watchdog Timer section.
See the Timer4—STI Timer section.
See the LIN (Local Interconnect Network) Interface section.
See the Flash/EE Control Interface section.
See the System Clocks section.
See the 16-Bit, Σ-Δ Analog-to-Digital Converters section.
See the UART Serial Interface section.
See the Serial Peripheral Interface section.
See the General-Purpose I/O section.
See the General-Purpose I/O section.
High voltage interrupt; see the High Voltage Peripheral Control Interface
section.
See the Serial Peripheral Interface section.
See the General-Purpose I/O section.
See the General-Purpose I/O section.
Reserved.
Rev. C | Page 68 of 132
ADuC7036
Normal Interrupt (IRQ) Request
IRQCLR Register
The IRQ request is the exception signal allowed to enter the
processor in IRQ mode. It is used to service general-purpose
interrupt handling of internal and external events.
Name: IRQCLR
All 32 bits of the IRQSTA MMR are OR’ed to create a single
IRQ signal to the ARM7TDMI core. The four 32-bit registers
dedicated to IRQ are described in the IRQSTA Register to the
IRQCLR Register sections.
Address: 0xFFFF000C
Access: Write only
Name: IRQSTA
Function: This register allows the IRQEN register to clear to
mask an interrupt source. Each bit set to 1 clears the corresponding
bit in the IRQEN register without affecting the remaining bits.
When used as a pair of registers, IRQEN and IRQCLR allow
independent manipulation of the enable mask without requiring
an automatic read-modify-write instruction.
Adress: 0xFFFF0000
Fast Interrupt Request (FIQ)
Default Value: 0x00000000
The FIQ is the exception signal allowed to enter the processor in
FIQ mode. It is provided to service data transfer or communication
channel tasks with low latency. The FIQ interface is identical
to the IRQ interface and provides the second-level interrupt
(highest priority). Four 32-bit registers are dedicated to FIQ:
FIQSIG, FIQEN, FIQCLR, and FIQSTA.
IRQSTA Register
Access: Read only
Function: This register provides the status of the IRQ source
that is currently enabled by IRQ source status (see Figure 32).
When a bit in this register is set to 1, the corresponding source
generates an active IRQ request to the ARM7TDMI core. There
is no priority encoder or interrupt vector generation. This
function is implemented in software in a common interrupt
handler routine.
IRQSIG Register
Name: IRQSIG
Address: 0xFFFF0004
Default Value: 0x00000000
All 32 bits of the FIQSTA MMR are OR’ed to create the FIQ signal
to the core and to Bit 0 of both the FIQ and IRQ registers (FIQ
source).
The logic for FIQEN and FIQCLR does not allow an interrupt
source to be enabled in both IRQ and FIQ masks. As a side effect,
a bit set to 1 in FIQEN clears the same bit in IRQEN. Likewise, a
bit set to 1 in IRQEN clears the same bit in FIQEN. An interrupt
source can be disabled in both IRQEN and FIQEN masks.
Programmed Interrupts
Access: Read only
Function: This 32-bit register reflects the status of the different
IRQ sources. If a peripheral generates an IRQ signal, the corresponding bit in the IRQSIG is set; otherwise, the corresponding
bit is cleared. The IRQSIG bits are cleared when the interrupt in
the particular peripheral is cleared. All IRQ sources can be masked
in the IRQEN MMR. IRQSIG is read only.
IRQEN Register
Because the programmed interrupts are not maskable, they are
controlled by another register, SWICFG, that writes into both
IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG
registers at the same time.
The 32-bit register dedicated to software interrupt is SWICFG;
it is described in Table 51. This MMR allows the control of a programmed source interrupt.
Table 51. SWICFG MMR Bit Designations
Name: IRQEN
Bit
31 to 3
2
Address: 0xFFFF0008
Default Value: 0x00000000
Access: Read/write
Function: This register provides the value of the current enable
mask. When a bit in this register is set to 1, the corresponding
source request is enabled to create an IRQ exception signal.
When a bit is set to 0, the corresponding source request is
disabled or masked and does not create an IRQ exception signal.
The IRQEN register cannot be used to disable an interrupt.
1
0
Description
Reserved.
Programmed interrupt FIQ.
Setting/clearing this bit corresponds to setting/clearing
Bit 1 of FIQSTA and FIQSIG.
Programmed interrupt IRQ.
Setting/clearing this bit corresponds to setting/clearing
Bit 1 of IRQSTA and IRQSIG.
Reserved.
Note that any interrupt signal must be active for at least the
minimum interrupt latency time to be detected by the interrupt
controller and by the user in the IRQSTA or FIQSTA register.
Rev. C | Page 69 of 132
IRQSTA
FIQSTA
IRQ
FIQ
07474-031
TIMER0
TIMER1
TIMER2
TIMER3
TIMER4
LIN H/W
FLASH/EE
PLL LOCK
ADC
UART
SPI
XIRQx
IRQEN
FIQEN
TIMER0
TIMER1
TIMER2
TIMER3
LIN H/W
FLASH/EE
PLL LOCK
ADC
UART
SPI
XIRQx
IRQSIG
FIQSIG
ADuC7036
Figure 32. Interrupt Structure
Rev. C | Page 70 of 132
ADuC7036
TIMERS
The ADuC7036 features five general-purpose timer/counters.
Table 52. Timer Event Capture
•
•
•
•
•
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Timer0, or the lifetime timer
Timer1, or general-purpose timer
Timer2, or the wake-up timer
Timer3, or the watchdog timer
Timer4, or the STI timer
The five timers in their normal mode of operation can be in
either free running mode or periodic mode.
Timers are started by writing data to the control register of the
corresponding timer (TxCON). The counting mode and speed
depend on the configuration chosen in TxCON.
In normal mode, an IRQ is generated each time the value of
the counter reaches 0 when counting down, or each time the
counter value reaches full scale when counting up. An IRQ
can be cleared by writing any value to clear the register of
that particular timer (TxCLRI).
The three timers in their normal mode of operation can be
either free-running or periodic.
In free-running mode, starting with the value in the TxLD
register, the counter decrements/increments from the maximum/
minimum value until zero/full scale and starts again at the
maximum/minimum value. This means that, in free-running
mode, TxVAL is not reloaded when the relevant interrupt bit is
set but the count simply rolls over as the counter underflows or
overflows.
In periodic mode, the counter decrements/increments from
the value in the load register (TxLD MMR) until zero/full scale
starts again from this value. This means when the relevant
interrupt bit is set, TxVAL is reloaded with TxLD and counting
starts again from this value.
Loading the TxLD register with zero is not recommended. The
value of a counter can be read at any time by accessing its value
register (TxVAL).
In addition, Timer0, Timer1, and Timer4 each have a capture
register (T0CAP, T1CAP, and T4CAP, respectively) that can
hold the value captured by an enabled IRQ event. The IRQ
events are described in Table 52.
Description
Timer0, or the lifetime timer
Timer1, or general-purpose timer
Timer2, or the wake-up timer
Timer3, or the watchdog timer
Timer4, or the STI timer
LIN hardware
Flash/EE interrupt
PLL lock
ADC
UART
SPI master
XIRQ0 (GPIO_0)
XIRQ1 (GPIO_5)
Reserved
IRQ3 high voltage interrupt
SPI slave
XIRQ4 (GPIO_7); see the General-Purpose I/O section
XIRQ5 (GPIO_8); see the General-Purpose I/O section
SYNCHRONIZATION OF TIMERS ACROSS
ASYNCHRONOUS CLOCK DOMAINS
The block diagram in Figure 33 shows the interface between
user timer MMRs and the core timer blocks. User code can
access all timer MMRs directly, including TxLD, TxVAL,
TxCON, and TxCLRI. Data must then transfer from these
MMRs to the core timers (T0, T1, T2, T3, and T4) within the
timer subsystem. Theses core timers are buffered from the
user MMR interface by the synchronization (SYNC) block.
The principal of the SYNC block is to provide a method that
ensures that data and other required control signals can cross
asynchronous clock domains correctly. An example of asynchronous clock domains is the MCU running on the 10 MHz
core clock, and Timer2 running on the low power oscillator of
32 kHz.
Rev. C | Page 71 of 132
ADuC7036
TIMER BLOCK
USER
MMR
INTERFACE
ARM7TDMI
AMBA
AMBA
CORE
CLOCK
LOW
POWER
OSCILLATOR
T0 REG
T0
SYNC
T0
T1 REG
T1
SYNC
T1
T2 REG
T2
SYNC
T2
T3 REG
T3
SYNC
T3
T4 REG
T4
SYNC
T4
T0IRQ
T1IRQ
T2IRQ
T3IRQ
WdRst
T4IRQ
0
GPIO
2
XTAL
4
07474-058
1
HIGH
PRECISION
OSCILLATOR
Figure 33. Timer Block Diagram
SYNCHRONIZER
FLIP-FLOPS
CORE CLOCK
(FCORE)
DOMAIN
SYNCHRONIZED
SIGNAL
TARGET_CLOCK
TIMER 2
LOW POWER
CLOCK DOMAIN
07474-059
UNSYNCHRONIZED
SIGNAL
Figure 34. Synchronizer for Signals Crossing Clock Domains
As shown in Figure 33, the MMR logic and core timer logic
reside in separate and asynchronous clock domains. Any data
coming from the MMR core clock domain and being passed to
the internal timer domain must be synchronized to the internal
timer clock omain to ensure it is latched correctly into the core
timer clock domain. This is achieved by using two flip-flops as
shown in Figure 34 to not only synchronize but also to double
buffer the data and thereby ensuring data integrity in the timer
clock domain.
As a result of the synchronization block, while timer control
data is latched almost immediately (with the fast, core clock) in
the MMR clock domain, this data in turn will not reach the core
timer logic for at least two periods of the selected internal timer
domain clock.
PROGRAMMING THE TIMERS
Understanding synchronization across timer domains also
requires that the user code carefully programs the timers when
stopping or starting them. The recommended code controls the
timer block when stopping and starting the timers and when
using different clock domains. This can critical, especially if
timers are enabled to generate an IRQ or FIQ exception; Timer2
is used as an example.
Halting Timer2
When halting Timer2, it is recommended that the IRQEN
bit for Timer2 be masked (using IRQCLR). This prevents
unwanted IRQs from generating an interrupt in the MCU
before the T2CON control bits have been latched in the Timer2
internal logic.
IRQCLR = WAKEUP_TIMER_BIT;
//Masking interrupts
T2CON=0x00;
//Halting the timer
Rev. C | Page 72 of 132
ADuC7036
Starting Timer2
When starting Timer2, it is recommended to first load Timer2
with the required TxLD value. Next, start the timer by setting
the T2CON bits as required. This enables the timer, but only
once the T2CON bits have been latched internally in the
Timer2 clock domain. Therefore, it is advised that a delay of
more than three clock periods (that is, 100 μs for a 32 kHz timer
clock source) is inserted to allow both the T2LD value and the
T2CON value to be latched through the synchronization logic
and reach the Timer2 domain.
After the delay, it is recommended that any (inadvertent)
Timer2 interrupts are now cleared using T2CLRI=0x00. Finally,
the Timer2 system interrupt can be unmasked by setting the
appro-priate bit in the IRQEN MMR. An example of this code
is as follows, where the assumption is that Timer2 is halted:
Example Code
T2LD = 0x1;
//Reload Timer
T2CON = 0x02CF;
//Enable T2—Low Power
Delay(100us);
//Include Delay to ensure T2CON bits take effect
T2CLRI = 0 ;
//*ClearTimerIrq
IRQEN = WAKEUP_TIMER_BIT;
//Unmask Timer2
Osc, 32768 prescaler
Rev. C | Page 73 of 132
ADuC7036
TIMER0—LIFETIME TIMER
Timer0 Load Register
Timer0 is a general-purpose, 48-bit up counter or a 16-bit up/down
counter timer with a programmable prescaler. Timer0 can be
clocked from either the core clock or the low power 32.768 kHz
oscillator with a prescaler of 1, 16, 256, or 32,768. When the core
is operating at 20.48 MHz with a prescaler of 1, a minimum resolution of 48.83 ns results.
Name: T0LD
In 48-bit mode, Timer0 counts up from 0. The current counter
value can be read from T0VAL0 and T0VAL1.
In 16-bit mode, Timer0 can count up or down. A 16-bit value
can be written to T0LD to load into the counter. The current
counter value is read from T0VAL0. Timer0 has a capture register (T0CAP) that is triggered by a selected IRQ source initial
assertion. When the capture register is triggered, the current
timer value is copied to T0CAP, and the timer continues running.
This feature can be used to determine the assertion of an event
with more accuracy than would be provided by servicing an
interrupt alone.
Timer0 reloads the value from T0LD when Timer0 overflows.
The Timer0 interface consists of six MMRS: T0LD, T0CAP,
T0VAL0, T0VAL1, T0CLRI, and T0CON. T0LD is a 16-bit
register holding the 16-bit value that is loaded into the counter.
T0LD is available only in 16-bit mode. T0CAP is a 16-bit
register that holds the 16-bit value captured by an enabled
IRQ event. T0CAP is available only in 16-bit mode. T0VAL0
and T0VAL1 are 16-bit and 32-bit registers that hold the 16 LSBs
and 32 MSBs, respectively. T0VAL0 and T0VAL1 are read only
registers. In 16-bit mode, 16-bit T0VAL0 is used. In 48-bit
mode, both 16-bit T0VAL0 and 32-bit T0VAL1 are used.
T0CLRI is an 8-bit register. Writing any value to this register
clears the interrupt. T0CLRI is available only in 16-bit mode.
T0CON is a configuration MMR and is described in Table 53.
Address: 0xFFFF0300
Default Value: 0x0000
Access: Read/write
Function: T0LD0 is the 16-bit register holding the 16-bit value
that is loaded into the counter. This register is available only in
16-bit mode.
Timer0 Clear Register
Name: T0CLRI
Address: 0xFFFF0310
Access: Write only
Function: This 8-bit, write only MMR is written (with any
value) by user code to clear the interrupt.
Timer0 Value Registers
Name: T0VAL0, T0VAL1
Address: 0xFFFF0304, 0xFFFF0308
Default Value: 0x0000, 0x00000000
Access: Read only
Function: T0VAL0 and T0VAL1 are 16-bit and 32-bit registers that
hold the 16 LSBs and 32 MSBs, respectively. T0VAL0 and T0VAL1
are read only registers. In 16-bit mode, 16-bit T0VAL0 is used.
In 48-bit mode, both 16-bit T0VAL0 and 32-bit T0VAL1 are used.
Timer0 Capture Register
Name: T0CAP
Address: 0xFFFF0314
Default Value: 0x0000
Access: Read only
Function: This 16-bit register holds the 16-bit value captured by
an enabled IRQ event. This register is available only in 16-bit mode.
16-BIT LOAD
LOW POWER
32.768kHz OSCILLATOR
EXTERNAL 32.768kHz
WATCH CRYSTAL
PRESCALER
1, 16, 256, OR 32,768
48-BIT UP COUNTER
16-BIT UP/DOWN COUNTER
CORE
CLOCK FREQUENCY
TIMER0 IRQ
TIMER0
VALUE
IRQ[31:0]
CAPTURE
Figure 35. Timer0 Block Diagram
Rev. C | Page 74 of 132
07474-032
PRECISION
32.768kHz OSCILLATOR
ADuC7036
Timer0 Control Register
Name: T0CON
Address: 0xFFFF030C
Default Value: 0x00000000
Access: Read/write
Function: This 32-bit MMR configures the mode of operation for Timer0.
Table 53. T0CON MMR Bit Designations
Bit
31 to 18
17
16 to 12
11
10 to 9
8
7
6
5
4
3 to 0
Description
Reserved.
Event select bit.
Set by user to enable time capture of an event.
Cleared by user to disable time capture of an event.
Event select range (0 to 17). The events are as defined in Table 52.
Reserved.
Clock select.
00 = core clock (default).
01 = low power 32.768 kHz oscillator.
10 = external 32.768 kHz watch crystal.
11 = precision 32.768 kHz oscillator.
Count up. Available in 16-bit mode only.
Set by user for Timer0 to count up.
Cleared by user for Timer0 to count down (default).
Timer0 enable bit.
Set by user to enable Timer0.
Cleared by user to disable Timer0 (default).
Timer0 mode.
Set by user to operate in periodic mode.
Cleared by user to operate in free running mode (default).
Reserved.
Timer0 mode of operation.
0 = 16-bit operation (default).
1 = 48-bit operation.
Prescaler.
0000 = source clock/1 (default).
0100 = source clock/16.
1000 = source clock/256.
1111 = source clock/32,768.
Rev. C | Page 75 of 132
ADuC7036
TIMER1—GENERAL-PURPOSE TIMER
Timer1 Load Register
Timer1 is a general-purpose, 32-bit up/down counter with
a programmable prescaler. The prescaler source can be the low
power 32.768 kHz oscillator, the core clock, or from one of two
external GPIOs. This source can be scaled by a factor of 1, 16,
256, or 32,768. When the core is operating at 20.48 MHz and at
CD = 0 with a prescaler of 1 (ignoring the external GPIOs), a minimum resolution of 48.83 ns results.
Name: T1LD
Address: 0xFFFF0320
Default Value: After a reset, this register contains the upper half
of the assembly lot ID (0x00000000).
Access: Read/write
Function: This 32-bit register holds the 32-bit value that is loaded
into the counter.
The counter can be formatted as a standard 32-bit value or as
time expressed as hours:minutes:seconds:hundredths.
Timer1 Clear Register
Name: T1CLRI
Timer1 has a capture register (T1CAP) that is triggered by the
initial assertion of a selected IRQ source. When the capture
register is triggered, the current timer value is copied to T1CAP,
and the timer continues to run. This feature can be used to
determine the assertion of an event with increased accuracy.
Address: 0xFFFF032C
Access: Write only
Function: This 8-bit, write only MMR is written (with any value)
by user code to clear the interrupt.
The Timer1 interface consists of five MMRS: T1LD, T1VAL,
T1CAP, T1CLRI, and T1CON. T1LD, T1VAL, and T1CAP are
32-bit registers that hold 32-bit unsigned integers. T1VAL and
T1CAP are read only. T1CLRI is an 8-bit register. Writing any
value to this register clears the Timer1 interrupt. T1CON is a
configuration MMR and is described in Table 54.
Timer1 Value Register
Name: T1VAL
Address: 0xFFFF0324
Default Value: 0xFFFFFFFF
Access: Read only
Timer1 features a postscaler that allows the user to count the
number of Timer1 timeouts between 1 and 256. To activate the
postscaler, the user sets Bit 23 and writes the desired number to
count into Bits[24:31] of T1CON. When that number of timeouts
is reached, Timer1 generates an interrupt if T1CON[18] is set.
Function: This 32-bit register holds the current value of Timer1.
Note that if the part is in a low power mode and Timer1 is clocked
from the GPIO or low power oscillator source, then Timer1
continues to operate.
Timer1 reloads the value from T1LD when Timer1 overflows.
32-BIT LOAD
LOW POWER
32.768kHz OSCILLATOR
CORE
CLOCK FREQUENCY
GPIO
PRESCALER
1, 16, 256, OR 32,768
32-BIT
UP/DOWN COUNTER
8-BIT
POSTSCALER
TIMER1 IRQ
GPIO
IRQ[31:0]
CAPTURE
Figure 36. Timer1 Block Diagram
Rev. C | Page 76 of 132
07474-033
TIMER1
VALUE
ADuC7036
Timer1 Capture Register
Timer1 Control Register
Name: T1CAP
Name: T1CON
Address: 0xFFFF0330
Address: 0xFFFF0328
Default Value: 0x00000000
Default Value: 0x01000000
Access: Read only
Access: Read/write
Function: This 32-bit register holds the 32-bit value captured by
an enabled IRQ event.
Function: This 32-bit MMR configures the Timer1 mode of
operation.
Table 54. T1CON MMR Bit Designations
Bit
31 to 24
23
22 to 20
19
18
17
16 to 12
11 to 9
8
7
6
5 to 4
3 to 0
Description
8-bit postscaler.
By writing to these eight bits, a value is written to the postscaler. Writing 0 is interpreted as a 1.
By reading these eight bits, the current value of the counter is read.
Timer1 enable postscaler.
Set to enable the Timer1 postscaler. If enabled, interrupts are generated after T1CON[31:24] periods as defined by T1LD.
Cleared to disable the Timer1 postscaler.
Reserved. These bits are reserved and should be written as 0 by user code.
Postscaler compare flag. Read only.
Set if the number of Timer1 overflows is equal to the number written to the postscaler.
Timer1 interrupt source.
Set to select interrupt generation from the postscaler counter.
Cleared to select interrupt generation directly from Timer1.
Event select bit.
Set by user to enable time capture of an event.
Cleared by user to disable time capture of an event.
Event select range (0 to 17). The events are described in Table 52.
Clock select.
000 = core clock (default).
001 = low power 32.768 kHz oscillator.
010 = GPIO_8.
011 = GPIO_5.
Count up.
Set by user for Timer1 to count up.
Cleared by user for Timer1 to count down (default).
Timer1 enable bit.
Set by user to enable Timer1.
Cleared by user to disable Timer1 (default).
Timer1 mode.
Set by user to operate in periodic mode.
Cleared by user to operate in free running mode (default).
Format.
00 = binary (default).
01 = reserved.
10 = hours:minutes:seconds:hundredths (23 hours to 0 hours).
11 = hours:minutes:seconds:hundredths (255 hours to 0 hours).
Prescaler.
0000 = source clock/1 (default).
0100 = source clock/16.
1000 = source clock/256.
1111 = source clock/32,768.
Rev. C | Page 77 of 132
ADuC7036
TIMER2—WAKE-UP TIMER
Timer2 Load Register
Timer2 is a 32-bit wake-up up/down counter timer, with a programmable prescaler. The prescaler is clocked directly from one
of four clock sources: namely, the core clock (which is the default
selection), the low power 32.768 kHz oscillator, the external
32.768 kHz watch crystal, or the precision 32.768 kHz oscillator.
The selected clock source can be scaled by a factor of 1, 16, 256,
or 32,768. The wake-up timer continues to run when the core
clock is disabled. When the core is operating at 20.48 MHz and
at CD = 0 with a prescaler of 1, a minimum resolution of 48.83 ns
results.
Name: T2LD
The counter can be formatted as a plain 32-bit value or as time
expressed as hours:minutes:seconds:hundredths.
Timer2 reloads the value from T2LD when Timer2 overflows.
The Timer2 interface consists of four MMRS: T2LD, T2VAL,
T2CLRI, and T2CON. T2LD and T2VAL are 32-bit registers
and hold 32-bit unsigned integers. T2VAL is a read only
register. T2CLRI is an 8-bit register. Writing any value to this
register clears the Timer2 interrupt. T2CON is a configuration
MMR and is described in Table 55.
Address: 0xFFFF0340
Default Value: 0x00000000
Access: Read/write
Function: This 32-bit register holds the 32-bit value that is
loaded into the counter.
Timer2 Clear Register
Name: T2CLRI
Address: 0xFFFF034C
Access: Write only
Function: This 8-bit, write only MMR is written (with any value)
by user code to clear the interrupt.
Timer2 Value Register
Name: T2VAL
Address: 0xFFFF0344
Default Value: 0xFFFFFFFF
Access: Read only
Function: This 32-bit register holds the current value of Timer2.
32-BIT LOAD
LOW POWER
32.768kHz OSCILLATOR
CORE
CLOCK
PRESCALER
1, 16, 256, OR 32,768
32-BIT
UP/DOWN COUNTER
EXTERNAL 32.768kHz
WATCH CRYSTAL
TIMER2
VALUE
Figure 37. Timer2 Block Diagram
Rev. C | Page 78 of 132
TIMER2 IRQ
07474-034
PRECISION
32.768kHz OSCILLATOR
ADuC7036
Timer2 Control Register
Name: T2CON
Address: 0xFFFF0348
Default Value: 0x0000
Access: Read/write
Function: This 16-bit MMR configures the mode of operation of Timer2.
Table 55. T2CON MMR Bit Designations
Bit
15 to 11
10 to 9
8
7
6
5 to 4
3 to 0
Description
Reserved.
Clock source select.
00 = core clock (default).
01 = low power (32.768 kHz) oscillator.
10 = external 32.768 kHz watch crystal.
11 = precision 32.768 kHz oscillator.
Count up.
Set by user for Timer2 to count up.
Cleared by user for Timer2 to count down (default).
Timer2 enable bit.
Set by user to enable Timer2.
Cleared by user to disable Timer2 (default).
Timer2 mode.
Set by user to operate in periodic mode.
Cleared by user to operate in free running mode (default).
Format.
00 = binary (default).
01 = reserved.
10 = hours:minutes:seconds:hundredths (23 hours to 0 hours). This is valid only with a 32 kHz clock.
11 = hours:minutes:seconds:hundredths (255 hours to 0 hours). This is valid only with a 32 kHz clock.
Prescaler.
0000 = source clock/1 (default).
0100 = source clock/16.
1000 = source clock/256. This setting should be used in conjunction with Timer2 in the hours:minutes:seconds:hundredths
format. See the 10 and 11 settings for the format bits (Bits[5:4]) in this table.
1111 = source clock/32,768.
Rev. C | Page 79 of 132
ADuC7036
TIMER3—WATCHDOG TIMER
Timer3 Interface
Timer3 has two modes of operation: normal mode and watchdog mode. The watchdog timer is used to recover from an
illegal software state. When enabled, Timer3 requires periodic
servicing to prevent it from forcing a reset of the processor.
The Timer3 interface consists of four MMRs: T3LD, T3VAL,
T3CLRI, and T3CON. T3LD and T3VAL are 16-bit registers
(Bit 0 to Bit 15) and hold 16-bit unsigned integers. T3VAL is a
read only register. T3CLRI is an 8-bit register. Writing any value
to this register clears the Timer3 interrupt in normal mode or
resets a new timeout period in watchdog mode. T3CON is the
configuration MMR described in Table 56.
Timer3 reloads the value from T3LD when Timer3 overflows.
Normal Mode
The Timer3 in normal mode is identical to Timer0 in 16-bit mode
of operation, except for the clock source. The clock source is the
low power 32.768 kHz oscillator, which is scalable by a factor of
1, 16, or 256.
Timer3 Load Register
Watchdog Mode
Default Value: 0x0040
Watchdog mode is entered by setting T3CON[5]. Timer3
decrements from the timeout value present in the T3LD register
until 0 is reached. The maximum timeout is 512 seconds, using
a maximum prescaler/256 and full scale in T3LD.
Access: Read/write
User software should not configure a timeout period of less
than 30 ms to avoid any conflict with Flash/EE memory page
erase cycles that require 20 ms to complete a single page erase
cycle and kernel execution.
If T3VAL reaches 0, a reset or an interrupt occurs, depending
on T3CON[1]. To avoid a reset or an interrupt event, any value
must be written to T3CLRI before T3VAL reaches 0. This
reloads the counter with T3LD and begins a new timeout period.
When watchdog mode is entered, T3LD and T3CON are
write protected. These two registers cannot be modified until
a power-on reset event resets the watchdog timer. After any
other reset event, the watchdog timer continues to count. The
watchdog timer should be configured in the initial lines of user
code to avoid an infinite loop of watchdog resets. User software
should configure only a minimum timeout period of 30 ms.
Name: T3LD
Address: 0xFFFF0360
Function: This 16-bit MMR holds the Timer3 reload value.
Timer3 Clear Register
Name: T3CLRI
Address: 0xFFFF036C
Access: Write only
Function: This 8-bit, write only MMR is written (with
any value) by user code to refresh (reload) Timer3 in watchdog
mode to prevent a watchdog timer reset event.
Timer3 Value Register
Name: T3VAL
Address: 0xFFFF0364
Default Value: 0x0040
Access: Read only
Function: This 16-bit, read only MMR holds the current Timer3
count value.
Timer3 is automatically halted during JTAG debug access and
recommences counting only after JTAG has relinquished control
of the ARM7 core. By default, Timer3 continues to count during
power-down. This can be disabled by setting Bit 0 in T3CON.
It is recommended to use the default value; that is, the watchdog
timer continues to count during power-down.
16-BIT LOAD
PRESCALER
1, 16, 256
16-BIT
UP/DOWN COUNTER
TIMER3
VALUE
Figure 38. Timer3 Block Diagram
Rev. C | Page 80 of 132
WATCHDOG RESET
TIMER3 IRQ
07474-035
LOW POWER
32.768kHz
ADuC7036
Timer 3 Control Register
Name: T3CON
Address: 0xFFFF0368
Default Value: 0x0000
Access: Read/write
Function: The 16-bit MMR configures the Timer3 mode of operation as described in Table 56.
Table 56. T3CON MMR Bit Designations
Bit
15 to 9
8
7
6
5
4
3 to 2
1
0
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Count up/count down enable.
Set by user code to configure Timer3 to count up.
Cleared by user code to configure Timer3 to count down.
Timer3 enable.
Set by user code to enable Timer3.
Cleared by user code to disable Timer3.
Timer3 operating mode.
Set by user code to configure Timer3 to operate in periodic mode.
Cleared by user code to configure Timer3 to operate in free running mode.
Watchdog timer mode enable.
Set by user code to enable watchdog mode.
Cleared by user code to disable watchdog mode.
Reserved. This bit is reserved and should be written as 0 by user code.
Timer3 clock (32.768 kHz) prescaler.
00 = source clock/1 (default).
01 = source clock/16.
10 = source clock/256.
11 = reserved.
Watchdog timer IRQ enable.
Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0.
Cleared by user code to disable the IRQ option.
PD_OFF.
Set by user code to stop Timer3 when the peripherals are powered down using Bit 4 in the POWCON MMR.
Cleared by user code to enable Timer3 when the peripherals are powered down using Bit 4 in the POWCON MMR.
Rev. C | Page 81 of 132
ADuC7036
TIMER4—STI TIMER
Timer4 Value Register
Timer4 is a general-purpose, 16-bit up/down counter timer with
a programmable prescaler. Timer4 can be clocked from the core
clock or from the low power 32.768 kHz oscillator with a prescaler
of 1, 16, 256, or 32,768.
Name: T4VAL
Timer4 has a capture register (T4CAP) that can be triggered
by the initial assertion of a selected IRQ source. After the capture
register is triggered, the current timer value is copied to T4CAP,
and the timer continues running. This feature can be used to
determine the assertion of an event with increased accuracy.
Timer4 can also be used to drive the serial test interface (STI)
peripheral.
Address: 0xFFFF0384
Default Value: 0xFFFF
Access: Read only
Function: This 16-bit register holds the current value of Timer4.
Time4 Capture Register
Name: T4CAP
Address: 0xFFFF0390
Default Value: 0x0000
The Timer4 interface consists of five MMRs: T4LD, T4VAL,
T4CAP, T4CLRI, and T4CON. T4LD, T4VAL, and T4CAP are
16-bit registers that hold 16-bit unsigned integers. T4VAL and
T4CAP are read only. T4CLRI is an 8-bit register. Writing any
value to this register clears the interrupt. T4CON is a configuration
MMR and is described in Table 57.
Access: Read only
Timer4 Load Register
Address: 0xFFFF0388
Name: T4LD
Default Value: 0x00000000
Address: 0xFFFF0380
Access: Read/write
Default Value: 0x0000
Function: This 32-bit MMR configures the mode of operation
of Timer4.
Access: Read/write
Function: This 16-bit register holds the 32-bit value captured by
an enabled IRQ event.
Timer4 Control Register
Name: T4CON
Function: This 16-bit register holds the 16-bit value that is
loaded into the counter.
Timer4 Clear Register
Name: T4CLRI
Address: 0xFFFF038C
Access: Write only
Function: This 8-bit, write only MMR is written (with any value)
by user code to clear the interrupt.
16-BIT LOAD
CORE
CLOCK FREQUENCY
PRESCALER
1, 16, 256, OR 32,768
16-BIT
UP/DOWN COUNTER
TIMER4 IRQ
STI
TIMER4
VALUE
IRQ[31:0]
CAPTURE
Figure 39. Timer4 Block Diagram
Rev. C | Page 82 of 132
07474-036
LOW POWER
32.768kHz OSCILLATOR
ADuC7036
Table 57. T4CON MMR Bit Designations
Bit
31 to 18
17
16 to 12
11 to 10
9
8
7
6
5 to 4
3 to 0
Description
Reserved.
Event select bit.
Set by user to enable time capture of an event.
Cleared by user to disable time capture of an event.
Event select range (0 to 17). The events are described in Table 52.
Reserved.
Clock select.
0 = core clock (default).
1 = low power 32.768 kHz oscillator.
Count up.
Set by user for Timer4 to count up.
Cleared by user for Timer4 to count down (default).
Timer4 enable bit.
Set by user to enable Timer0.
Cleared by user to disable Timer0 (default).
Timer4 mode.
Set by user to operate in periodic mode.
Cleared by user to operate in free running mode (default).
Reserved.
Prescaler.
0000 = source clock/1 (default).
0100 = source clock/16.
1000 = source clock/256.
1111 = source clock/32,768.
Rev. C | Page 83 of 132
ADuC7036
GENERAL-PURPOSE I/O
The ADuC7036 features nine general-purpose bidirectional input/
output (GPIO) pins. In general, many of the GPIO pins have
multiple functions that can be configured by user code. By default,
the GPIO pins are configured in GPIO mode. All GPIO pins have
an internal pull-up resistor with a sink capability of 0.8 mA and
a source capability of 0.1 mA.
External interrupts are present on GPIO_0, GPIO_5, GPIO_7,
and GPIO_8. These interrupts are level triggered and active high.
These interrupts are not latched; therefore, the interrupt source
must be present until either IRQSTA or FIQSTA are interrogated.
The interrupt source must be active for at least one CD-divided
core clock to guarantee recognition.
The nine GPIOs are grouped into three ports: Port0, Port1, and
Port2. Port0 is five bits wide. Port1 and Port2 are each two bits
wide. The GPIO assignment within each port is detailed in
Table 58. A typical GPIO structure is shown Figure 40.
All port pins are configured and controlled by three sets (one
set for each port) of four port-specific MMRs, as follows:
OUTPUT DRIVE ENABLE
GPxDAT[31:24]
REG_DVDD
OUTPUT DATA
GPxDAT[23:16]
GPIO
AVAILABLE ON GPIO_0, GPIO_5, GPIO_7, AND GPIO_8.
Figure 40. Typical GPIO Structure
07474-037
1ONLY
GPxCON: Portx control register
GPxDAT: Portx configuration and data register
GPxSET: Portx data set
GPxCLR: Portx data clear
where x corresponds to the port number (0, 1, or 2).
INPUT DATA
GPxDAT[7:0]
GPIO IRQ1
•
•
•
•
During normal operation, user code can control the function
and state of the external GPIO pins using these general-purpose
registers. All GPIO pins retain their external level (high or low)
during power-down (POWCON) mode.
Rev. C | Page 84 of 132
ADuC7036
Table 58. External GPIO Pin to Internal Port Signal Assignments
Port
Port0
GPIO Pin
GPIO_0
Port Signal
P0.0
IRQ0
SS
Functionality (Defined by GPxCON)
General-purpose I/O.
External Interrupt Request 0.
Slave select I/O for SPI.
GPIO_1
P0.1
SCLK
P0.2
MISO
P0.3
MOSI
P0.4
ECLK
P0.5 1
P0.61
P1.0
IRQ1
RxD
P1.1
TxD
Port 2.0
IRQ4
LIN output pin2
P2.1
IRQ5
LIN HV input pin2
P2.42
LINRX2
P2.52
LINTX2
P2.61
General-purpose I/O.
Serial clock I/O for SPI.
General-purpose I/O.
Master input, slave output for SPI.
General-purpose I/O.
Master output, slave input for SPI.
General-purpose I/O.
2.56 MHz clock output.
High voltage serial interface.
High voltage serial interface.
General-purpose I/O.
External Interrupt Request 1.
Pin for UART.
General-purpose I/O.
Pin for UART.
General-purpose I/O.
External Interrupt Request 4.
Used to read directly from LIN pin for conformance testing.
General-purpose I/O.
External Interrupt Request 5.
Used to directly drive LIN pin for conformance testing.
General-purpose I/O.
LIN input pin.
General-purpose I/O.
LIN output pin.
General-purpose I/O; STI data output.
GPIO_2
GPIO_3
GPIO_4
Port1
GPIO_5
GPIO_6
Port2
GPIO_7
GPIO_8
GPIO_11 2
X
GPIO_122
X
GPIO_131
1
These signals are internal signals only and do not appear on an external pin. These pins are used along with HVCON as the 2-wire interface to the high voltage
interface circuits.
2
These pins/signals are internal signals only and do not appear on an external pin. The signals are used to provide the external pin diagnostic write (GPIO_12) and
readback (GPIO_11) capability.
Rev. C | Page 85 of 132
ADuC7036
GPIO Port0 Control Register
Name: GP0CON
Address: 0xFFFF0D00
Default Value: 0x11100000
Access: Read/write
Function: This 32-bit MMR selects the pin function for each Port0 pin.
Table 59. GP0CON MMR Bit Designations
Bit
31 to 29
28
27 to 25
24
23 to 21
20
19 to 17
16
15 to 13
12
11 to 9
8
7 to 5
4
3 to 1
0
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Reserved. This bit is reserved and should be written as 1 by user code.
Reserved. These bits are reserved and should be written as 0 by user code.
Internal P0.6 enable bit. This bit must be set to 1 by user software to enable the high voltage serial interface before
using the HVCON and HVDAT registered high voltage interface.
Reserved. These bits are reserved and should be written as 0 by user code.
Internal P0.5 enable bit. This bit must be set to 1 by user software to enable the high voltage serial interface before
using the HVCON and HVDAT registered high voltage interface.
Reserved. These bits are reserved and should be written as 0 by user code.
GPIO_4 function select bit.
Set to 1 by user code to configure the GPIO_4 pin as ECLK, enabling a 2.56 MHz clock output on this pin.
Cleared by user code to 0 to configure the GPIO_4 pin as a general-purpose I/O (GPIO) pin.
Reserved. These bits are reserved and should be written as 0 by user code.
GPIO_3 function select bit.
Set to 1 by user code to configure the GPIO_3 pin as MOSI, master output, and slave input data for the SPI port.
Cleared by user code to 0 to configure the GPIO_3 pin as a general-purpose I/O (GPIO) pin.
Reserved. These bits are reserved and should be written as 0 by user code.
GPIO_2 function select bit.
Set to 1 by user code to configure the GPIO_2 pin as MISO, master input and slave output data for the SPI port.
Cleared by user code to 0 to configure the GPIO_2 pin as a general-purpose I/O (GPIO) pin.
Reserved. These bits are reserved and should be written as 0 by user code.
GPIO_1 function select bit.
Set to 1 by user code to configure the GPIO_1 pin as SCLK, serial clock I/O for the SPI port.
Cleared by user code to 0 to configure the GPIO_1 pin as a general-purpose I/O (GPIO) pin.
Reserved. These bits are reserved and should be written as 0 by user code.
GPIO_0 function select bit.
Set to 1 by user code to configure the GPIO_0 pin as SS, serial clock I/O for the SPI port.
Cleared by user code to 0 to configure the GPIO_0 pin as a general-purpose I/O (GPIO) pin.
Rev. C | Page 86 of 132
ADuC7036
GPIO Port1 Control Register
Name: GP1CON
Address: 0xFFFF0D04
Default Value: 0x10000000
Access: Read/write
Function: This 32-bit MMR selects the pin function for each Port1 pin.
Table 60. GP1CON MMR Bit Designations
Bit
31 to 5
4
3 to 1
0
Description
Reserved. These bits are reserved and should be written as 0 by user code.
GPIO_6 function select bit.
Set to 1 by user code to configure the GPIO_6 pin as TxD, transmit data for UART serial port.
Cleared by user code to 0 to configure the GPIO_6 pin as a general-purpose I/O (GPIO) pin.
Reserved. These bits are reserved and should be written as 0 by user code.
GPIO_5 function select bit.
Set by user code to 1 to configure the GPIO_5 pin as RxD. Receive data for UART serial port.
Cleared by user code to 0 to configure the GPIO_5 pin as a general-purpose I/O (GPIO) pin.
Rev. C | Page 87 of 132
ADuC7036
GPIO Port2 Control Register
Name: GP2CON
Address: 0xFFFF0D08
Default Value: 0x01000000
Access: Read/write
Function: This 32-bit MMR selects the pin function for each Port2 pin.
Table 61. GP2CON MMR Bit Designations
Bit
31 to 25
24
23 to 21
20
19 to 17
16
15 to 5
4
3 to 1
0
Description
Reserved. These bits are reserved and should be written as 0 by user code.
GPIO_13 function select bit.
Set to 1 by user code to route the STI data output to the STI pin.
If this bit is cleared to 0 by user code, then the STI data is not routed to the external STI pin even if the STI interface is enabled
correctly.
Reserved. These bits are reserved and should be written as 0 by user code.
GPIO_12 function select bit.
Set to 1 by user code to route the UART TxD (transmit data) to the LIN/BSD data pin. This configuration is used in LIN mode.
Cleared by user code to 0 to route the LIN/BSD transmit data to an internal general-purpose I/O (GPIO_12) pad, which can then
be written via the GP2DAT MMR. This configuration is used in BSD mode to allow user code to write output data to the BSD
interface, and it can also be used to support diagnostic write capability to the high voltage I/O pins (see HVCFG1[2:0] in Table 75).
Reserved. These bits are reserved and should be written as 0 by user code.
GPIO_11 function select bit.
Set to 1 by user code to route input data from the LIN/BSD interface to both the LIN/BSD hardware timing/synchronization logic
and to the UART RxD (receive data). This mode must be configured by user code when using LIN or BSD modes.
Cleared by user code to 0 to internally disable the LIN/BSD input data path. In this configuration GPIO_11 is used to support
diagnostic readback on all external high voltage I/O pins (see HVCFG1[2:0] in Table 75).
Reserved. These bits are reserved and should be written as 0 by user code.
GPIO_8 function select bit.
Set to 1 by user code to route the LIN/BSD input data to the GPIO_8 pin. This mode can be used to drive the LIN transceiver
interface as a standalone component without any interaction from MCU or UART.
Cleared by user code to 0 to configure the GPIO_8 pin as a general-purpose I/O (GPIO) pin.
Reserved. These bits are reserved and should be written as 0 by user code.
GPIO_7 function select bit.
Set by user code to 1 to route data driven into the GPIO_7 pin through the on-chip LIN transceiver to be output at the LIN/BSD
pin. This mode can be used to drive the LIN transceiver interface as a standalone component without any interaction from MCU
or UART.
Cleared by user code to 0 to configure the GPIO_7 pin as a general-purpose I/O (GPIO) pin.
Rev. C | Page 88 of 132
ADuC7036
GPIO Port0 Data Register
Name: GP0DAT
Address: 0xFFFF0D20
Default Value: 0x000000XX
Access: Read/write
Function: This 32-bit MMR configures the direction of the GPIO pins assigned to Port0 (see Table 58). This register also sets the output
value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs.
Table 62. GP0DAT MMR Bit Designations
Bit
31 to 29
28
27
26
25
24
23 to 21
20
19
18
17
16
15 to 5
4
3
2
1
0
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Port 0.4 direction select bit.
Set to 1 by user code to configure the GPIO pin assigned to Port 0.4 as an output.
Cleared to 0 by user code to configure the GPIO pin assigned to Port 0.4 as an input.
Port 0.3 direction select bit.
Set to 1 by user code to configure the GPIO pin assigned to Port 0.3 as an output.
Cleared to 0 by user code to configure the GPIO pin assigned to Port 0.3 as an input.
Port 0.2 direction select bit.
Set to 1 by user code to configure the GPIO pin assigned to Port 0.2 as an output.
Cleared to 0 by user code to configure the GPIO pin assigned to Port 0.2 as an input.
Port 0.1 direction select bit.
Set to 1 by user code to configure the GPIO pin assigned to Port 0.1 as an output.
Cleared to 0 by user code to configure the GPIO pin assigned to Port 0.1 as an input.
Port 0.0 direction select bit.
Set to 1 by user code to configure the GPIO pin assigned to Port 0.0 as an output.
Cleared to 0 by user code to configure the GPIO pin assigned to Port 0.0 as an input.
Reserved. These bits are reserved and should be written as 0 by user code.
Port 0.4 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 0.4.
Port 0.3 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 0.3.
Port 0.2 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 0.2.
Port 0.1 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 0.1.
Port 0.0 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 0.0.
Reserved. These bits are reserved and should be written as 0 by user code.
Port 0.4 data input. This bit is a read only bit that reflects the current status of the GPIO pin assigned to Port 0.4. User code should
write 0 to this bit.
Port 0.3 data input. This bit is a read only bit that reflects the current status of the GPIO pin assigned to Port 0.3. User code should
write 0 to this bit.
Port 0.2 data input. This bit is a read only bit that reflects the current status of the GPIO pin assigned to Port 0.2. User code should
write 0 to this bit.
Port 0.1 data input. This bit is a read only bit that reflects the current status of the GPIO pin assigned to Port 0.1. User code should
write 0 to this bit.
Port 0.0 data input. This bit is a read only bit that reflects the current status of the GPIO pin assigned to Port 0.0. User code should
write 0 to this bit.
Rev. C | Page 89 of 132
ADuC7036
GPIO Port1 Data Register
Name: GP1DAT
Address: 0xFFFF0D30
Default Value: 0x000000XX
Access: Read/write
Function: This 32-bit MMR configures the direction of the GPIO pins assigned to Port1 (see Table 58). This register also sets the output
value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs.
Table 63. GP1DAT MMR Bit Designations
Bit
31 to 26
25
24
23 to 18
17
16
15 to 2
1
0
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Port 1.1 direction select bit.
Set to 1 by user code to configure the GPIO pin assigned to Port 1.1 as an output.
Cleared to 0 by user code to configure the GPIO pin assigned to Port 1.1 as an input.
Port 1.0 direction select bit.
Set to 1 by user code to configure the GPIO pin assigned to Port 1.0 as an output.
Cleared to 0 by user code to configure the GPIO pin assigned to Port 1.0 as an input.
Reserved. These bits are reserved and should be written as 0 by user code.
Port 1.1 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 1.1.
Port 1.0 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 1.0.
Reserved. These bits are reserved and should be written as 0 by user code.
Port 1.1 data input. This bit is a read only bit that reflects the current status of the GPIO pin assigned to Port 1.1. User code should
write 0 to this bit.
Port 1.0 data input. This bit is a read only bit that reflects the current status of the GPIO pin assigned to Port 1.0. User code should
write 0 to this bit.
Rev. C | Page 90 of 132
ADuC7036
GPIO Port2 Data Register
Name: GP2DAT
Address: 0xFFFF0D40
Default Value: 0x000000XX
Access: Read/write
Function: This 32-bit MMR configures the direction of the GPIO pins assigned to Port2 (see Table 58). This register also sets the output
value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs.
Table 64. GP2DAT MMR Bit Designations
Bit
31
30
29
28
27 to 26
25
24
23
22
21
20 to 18
17
16
15 to 7
6
5
4
3 to 2
1
0
Description
Reserved. This bit is reserved and should be written as 0 by user code.
Port 2.6 direction select bit.
Set to 1 by user code to configure the GPIO pin assigned to Port 2.6 as an output.
Cleared to 0 by user code to configure the GPIO pin assigned to Port 2.6 as an input
Port 2.5 direction select bit.
Set to 1 by user code to configure the GPIO pin assigned to Port 2.5 as an output. This configuration is used to support
diagnostic write capability to the high voltage I/O pins.
Cleared to 0 by user code to configure the GPIO pin assigned to Port 2.5 as an input.
Port 2.4 direction select bit.
Set to 1 by user code to configure the GPIO pin assigned to Port 2.4 as an output.
Cleared to 0 by user code to configure the GPIO pin assigned to Port 2.4 as an input. This configuration is used to support
diagnostic readback capability from the high voltage I/O pins (see HVCFG1[2:0]).
Reserved. These bits are reserved and should be written as 0 by user code.
Port 2.1 direction select bit.
Set to 1 by user code to configure the GPIO pin assigned to Port 2.1 as an output.
Cleared to 0 by user code to configure the GPIO pin assigned to Port 2.1 as an input.
Port 2.0 direction select bit.
Set to 1 by user code to configure the GPIO pin assigned to Port 2.0 as an output.
Cleared to 0 by user code to configure the GPIO pin assigned to Port 2.0 as an input.
Reserved. This bit is reserved and should be written as 0 by user code.
Port 2.6 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 2.6.
Port 2.5 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 2.5.
Reserved. These bits are reserved and should be written as 0 by user code.
Port 2.1 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 2.1.
Port 2.0 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 2.0.
Reserved. These bits are reserved and should be written as 0 by user code.
Port 2.6 data input. This bit is a read only bit that reflects the current status of the GPIO pin assigned to Port 2.6. User code
should write 0 to this bit.
Port 2.5 data input. This bit is a read only bit that reflects the current status of the GPIO pin assigned to Port 2.5. User code
should write 0 to this bit.
Port 2.4 data input. This bit is a read only bit that reflects the current status of the GPIO pin assigned to Port 2.4. User code
should write 0 to this bit.
Reserved. These bits are reserved and should be written as 0 by user code.
Port 2.1 data input. This bit is a read only bit that reflects the current status of the GPIO pin assigned to Port 2.1. User code
should write 0 to this bit.
Port 2.0 data input. This bit is a read only bit that reflects the current status of the GPIO pin assigned to Port 2.0. User code
should write 0 to this bit.
Rev. C | Page 91 of 132
ADuC7036
GPIO Port0 Set Register
Name: GP0SET
Address: 0xFFFF0D24
Access: Write only
Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to set them high only. User code can accomplish
this using the GP0SET MMR without having to modify or maintain the status of the GPIO pins (as user code requires when using
GP0DAT).
Table 65. GP0SET MMR Bit Designations
Bit
31 to 21
20
19
18
17
16
15 to 0
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Port 0.4 set bit.
Set to 1 by user code to set the external GPIO_4 pin high.
Clearing this bit to 0 via user software has no effect on the external GPIO_4 pin.
Port 0.3 set bit.
Set to 1 by user code to set the external GPIO_3 pin high.
Clearing this bit to 0 via user software has no effect on the external GPIO_3 pin.
Port 0.2 set bit.
Set to 1 by user code to set the external GPIO_2 pin high.
Clearing this bit to 0 via user software has no effect on the external GPIO_2 pin.
Port 0.1 set bit.
Set to 1 by user code to set the external GPIO_1 pin high.
Clearing this bit to 0 via user software has no effect on the external GPIO_1 pin.
Port 0.0 set bit.
Set to 1 by user code to set the external GPIO_0 pin high.
Clearing this bit to 0 via user software has no effect on the external GPIO_0 pin.
Reserved. These bits are reserved and should be written as 0 by user code.
GPIO Port1 Set Register
Name: GP1SET
Address: 0xFFFF0D34
Access: Write only
Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to set them high only. User code can accomplish
this using the GP1SET MMR without having to modify or maintain the status of the GPIO pins (as user code requires when using
GP1DAT).
Table 66. GP1SET MMR Bit Designations
Bit
31 to 18
17
16
15 to 0
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Port 1.1 set bit.
Set to 1 by user code to set the external GPIO_6 pin high.
Clearing this bit to 0 via user software has no effect on the external GPIO_6 pin.
Port 1.0 set bit.
Set to 1 by user code to set the external GPIO_5 pin high.
Clearing this bit to 0 via user software has no effect on the external GPIO_5 pin.
Reserved. These bits are reserved and should be written as 0 by user code.
Rev. C | Page 92 of 132
ADuC7036
GPIO Port2 Set Register
Name: GP2SET
Address: 0xFFFF0D44
Access: Write only
Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to set them high only. User code can accomplish this
using the GP2SET MMR without having to modify or maintain the status of the GPIO pins (as user code requires when using GP2DAT).
Table 67. GP2SET MMR Bit Designations
Bit
31 to 23
22
21
20 to 18
17
16
15 to 0
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Port 2.6 set bit.
Set to 1 by user code to set the external GPIO_13 pin high.
Clearing this bit to 0 via user software has no effect on the external GPIO_13 pin.
Port 2.5 set bit.
Set to 1 by user code to set the external GPIO_12 pin high.
Clearing this bit to 0 via user software has no effect on the external GPIO_12 pin.
Reserved. These bits are reserved and should be written as 0 by user code.
Port 2.1 set bit.
Set to 1 by user code to set the external GPIO_8 pin high.
Clearing this bit to 0 via user software has no effect on the external GPIO_8 pin.
Port 2.0 set bit.
Set to 1 by user code to set the external GPIO_7 pin high.
Clearing this bit to 0 via user software has no effect on the external GPIO_7 pin.
Reserved. These bits are reserved and should be written as 0 by user code.
GPIO Port0 Clear Register
Name: GP0CLR
Address: 0xFFFF0D28
Access: Write only
Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to clear them low only. User code can accomplish
this using the GP0CLR MMR without having to modify or maintain the status of the GPIO pins (as user code requires when using GP0DAT).
Table 68. GP0CLR MMR Bit Designations
Bit
31 to 21
20
19
18
17
16
15 to 0
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Port 0.4 clear bit.
Set to 1 by user code to clear the external GPIO_4 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_4 pin.
Port 0.3 clear bit.
Set to 1 by user code to clear the external GPIO_3 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_3 pin.
Port 0.2 clear bit.
Set to 1 by user code to clear the external GPIO_2 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_2 pin.
Port 0.1 clear bit.
Set to 1 by user code to clear the external GPIO_1 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_1 pin.
Port 0.0 clear bit.
Set to 1 by user code to clear the external GPIO_0 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_0 pin.
Reserved. These bits are reserved and should be written as 0 by user code.
Rev. C | Page 93 of 132
ADuC7036
GPIO Port1 Clear Register
Name: GP1CLR
Address: 0xFFFF0D38
Access: Write only
Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to clear them low only. User code can accomplish
this using the GP1CLR MMR without having to modify or maintain the status of the GPIO pins (as user code requires when using GP1DAT).
Table 69. GP1CLR MMR Bit Designations
Bit
31 to 18
17
16
15 to 0
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Port 1.1 clear bit.
Set to 1 by user code to clear the external GPIO_6 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_6 pin.
Port 1.0 clear bit.
Set to 1 by user code to clear the external GPIO_5 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_5 pin.
Reserved. These bits are reserved and should be written as 0 by user code.
GPIO Port2 Clear Register
Name: GP2CLR
Address: 0xFFFF0D48
Access: Write only
Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to clear them low only. User code can accomplish
this using the GP2CLR MMR without having to modify or maintain the status of the GPIO pins (as user code requires when using GP2DAT).
Table 70. GP2CLR MMR Bit Designations
Bit
31 to 23
22
21
20 to 18
17
16
15 to 0
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Port 2.6 clear bit.
Set to 1 by user code to clear the external GPIO_13 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_8 pin.
Port 2.5 clear bit.
Set to 1 by user code to clear the external GPIO_12 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_7 pin.
Reserved. These bits are reserved and should be written as 0 by user code.
Port 2.1 clear bit.
Set to 1 by user code to clear the external GPIO_8 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_8 pin.
Port 2.0 clear bit.
Set to 1 by user code to clear the external GPIO_7 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_7 pin.
Reserved. These bits are reserved and should be written as 0 by user code.
Rev. C | Page 94 of 132
ADuC7036
HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE
The ADuC7036 integrates several high voltage circuit functions
that are controlled and monitored through a registered interface
consisting of two MMRs: HVCON and HVDAT. The HVCON
register acts as a command byte interpreter, allowing the
microcontroller to indirectly read or write 8-bit data (the value
in HVDAT) from or to one of four high voltage status or configuration registers. These high voltage registers are not MMRs
but are registers commonly referred to as indirect registers; that
is, they can be accessed (as the name suggests) only indirectly
via the HVCON and HVDAT MMRs.
The physical interface between the HVCON register and the
indirect high voltage registers is a 2-wire (data and clock) serial
interface based on a 2.56 MHz serial clock. Therefore, there is a
finite, 10 μs (maximum) latency between the MCU core writing
a command into HVCON and that command or data reaching
the indirect high voltage registers. There is also a finite 10 μs
latency between the MCU core writing a command into HVCON
and the indirect register data being read back into the HVDAT
register. A busy bit (for example, Bit 0 of the HVCON when
read by MCU) can be polled by the MCU to confirm when
a read/write command is complete.
The following high voltage circuit functions are controlled and
monitored via this interface. Figure 41 shows the top-level
architecture of the high voltage interface and the following
related circuits:
•
•
•
•
•
•
•
•
•
Precision oscillator
Wake-up (WU) pin functionality
Power supply monitor (PSM)
Low voltage flag (LVF)
LIN operating modes
STI diagnostics
High voltage diagnostics
High voltage attenuator buffers circuit
High voltage (HV) temperature monitor
(INDIRECT)
HIGH VOLTAGE
REGISTERS
HIGH VOLTAGE
INTERFACE
MMRs
HVCON
HVDAT
HVCFG0
SERIAL
DATA
SERIAL
CLOCK
HVCFG0[6]
PRECISION
OSCILLATOR
HVCFG0[3]
PSM
HVCFG0[2]
LVF
HVCFG1
SERIAL
INTERFACE
CONTROLLER
HVSTA
HVMON
PSM—HVSTA[5]
WU—HVSTA[4]
IRQ3
(IRQEN[16])
HIGH VOLTAGE
INTERRUPT
CONTROLLER
ARM7
MCU
AND
PERIPHERALS
OVER TEMP—HVSTA[3]
LIN S-SCT—HVSTA[2]
STI S-SCT—HVSTA[1]
WU S-SCT—HVSTA[0]
HVCFG0[5]
HVCFG0[1:0]
WU DIAGNOSTIC INPUT
HVCFG0[4]
STI DIAGNOSTIC INPUT
P2.6
WU DIAGNOSTIC OUTPUT
HVMON[7]
HIGH VOLTAGE
DIAGNOSTIC
CONTROLLER
LIN DIAGNOSTIC INPUT
P2.5
STI DIAGNOSTIC OUTPUT
HVMON[5]
HVCFG0[4]
HVCFG1[4]
LIN DIAGNOSTIC OUTPUT
P2.4
HVCFG1[4]
LIN
MODES
WU I/O
CONTROL
STI I/O
CONTROL
HVCFG1[3]
HVCFG1[6]
HVCFG1[5]
ATTENUATOR
AND
BUFFER
HV TEMP
MONITOR
Figure 41. High Voltage Interface, Top-Level Block Diagram
Rev. C | Page 95 of 132
HVCFG1[3]
07474-038
HVCFG1[7]
ADuC7036
High Voltage Interface Control Register
Name: HVCON
Address: 0xFFFF0804
Default Value: Updated by kernel
Access: Read/write
Function: This 8-bit register acts as a command byte interpreter for the high voltage control interface. Bytes written to this register are
interpreted as read or write commands to a set of four indirect registers related to the high voltage circuits. The HVDAT register is used to
store data to be written to, or read back from, the indirect registers.
Table 71. HVCON MMR Write Bit Designations
Bit
7 to 0
Description
Command byte. Interpreted as
0x00 = read back High Voltage Register HVCFG0 into HVDAT.
0x01 = read back High Voltage Register HVCFG1 into HVDAT.
0x02 = read back High Voltage Status Register HVSTA into HVDAT.
0x03 = read back High Voltage Status Register HVMON into HVDAT.
0x08 = write the value in HVDAT to the High Voltage Register HVCFG0.
0x09 = write the value in HVDAT to the High Voltage Register HVCFG1.
Table 72. HVCON MMR Read Bit Designations
Bit
7 to 3
2
1
0
Description
Reserved.
Transmit command to high voltage die status.
1 = command completed successfully.
0 = command failed.
Read command from high voltage die status.
1 = command completed successfully.
0 = command failed.
Busy bit (read only). When user code reads this register, Bit 0 should be interpreted as the busy signal for the high voltage
interface. This bit can be used to determine if a read request has completed. High voltage (read/write) commands as
described in this table should not be written to HVCON unless busy = 0.
Busy = 1, high voltage interface is busy and has not completed the previous command written to HVCON. Bit 1 and Bit 2
are not valid.
Busy = 0, high voltage interface is not busy and has completed the command written to HVCON. Bit 1 and Bit 2 are valid.
Rev. C | Page 96 of 132
ADuC7036
High Voltage Data Register
Name: HVDAT
Address: 0xFFFF080C
Default Value: Updated by kernel
Access: Read/write
Function: This 12-bit register holds data to be written indirectly to, and read indirectly from, the following high voltage interface registers.
Table 73. HVDAT MMR Bit Designations
Bit
11 to 8
7 to 0
Description
Command with which High Voltage Data HVDAT[7:0] is associated. These bits are read only and should be written as 0s.
0x00 = read back High Voltage Register HVCFG0 into HVDAT.
0x01 = read back High Voltage Register HVCFG1 into HVDAT.
0x02 = read back High Voltage Status Register HVSTA into HVDAT.
0x03 = read back High Voltage Status Register HVMON into HVDAT.
0x08 = write the value in HVDAT to the High Voltage Register HVCFG0.
0x09 = write the value in HVDAT to the High Voltage Register HVCFG1.
High voltage data to read/write.
Rev. C | Page 97 of 132
ADuC7036
High Voltage Configuration0 Register
Name: HVCFG0
Address: Indirectly addressed via the HVCON high voltage interface
Default Value: 0x00
Access: Read/write
Function: This 8-bit register controls the function of high voltage circuits on the ADuC7036. This register is not an MMR and does not
appear in the MMR memory map. It is accessed via the HVCON register interface. Data to be written to this register is loaded via the
HVDAT MMR, and data is read back from this register via the HVDAT MMR.
Table 74. HVCFG0 Bit Designations
Bit
7
6
5
4
3
2
1 to 0
Description
Wake-up/STI thermal shutdown disable.
Set to 1 to disable the automatic shutdown of the wake-up/STI driver when a thermal event occurs.
Cleared to 0 to enable the automatic shutdown of the wake-up/STI driver when a thermal event occurs.
Precision oscillator enable bit.
Set to 1 to enable the precision 131 kHz oscillator. The oscillator start-up time is typically 70 μs (including a high
voltage interface latency of 10 μs).
Cleared to 0 to power down the precision 131 kHz oscillator.
Bit serial device (BSD) mode enable bit.
Set to 1 to disable the internal (LIN) pull-up and configure the LIN/BSD pin for BSD operation.
Cleared to 0 to enable the internal (LIN) pull-up resistor on the LIN/BSD pin.
Wake-up (WU) assert bit.
Set to 1 to assert the external WU pin high.
Cleared to 0 to pull the external WU pin low via an internal 10 kΩ pull-down resistor.
Power supply monitor (PSM) enable bit.
Set to 1 to enable the power supply (voltage at the VDD pin) monitor. If IRQ3 (IRQEN[16]) is enabled, the PSM
generates an interrupt if the voltage at the VDD pin drops below 6 V.
Cleared to 0 to disable the power supply (voltage at the VDD pin) monitor.
Low voltage flag (LVF) enable bit.
Set to 1 to enable the LVF function. The low voltage flag can be interrogated via HVMON[3] after power-up to
determine if the REG_DVDD voltage previously dropped below 2.1 V.
Cleared to 0 to disable the LVF function.
LIN operating mode. These bits enable/disable the LIN driver.
00 = LIN disabled.
01 = reserved (not LIN V2.0 compliant).
10 = LIN enabled.
11 = reserved, not used.
Rev. C | Page 98 of 132
ADuC7036
High Voltage Configuration1 Register
Name: HVCFG1
Address: Indirectly addressed via the HVCON high voltage interface
Default Value: 0x00
Access: Read/write
Function: This 8-bit register controls the function of high voltage circuits on the ADuC7036. This register is not an MMR and does not
appear in the MMR memory map. It is accessed via the HVCON register interface. Data to be written to this register is loaded through
HVDAT, and data is read back from this register using HVDAT.
Table 75. HVCFG1 Bit Designations
Bit
7
6
5
4
3
2
1
0
Description
Voltage attenuator diagnostic enable bit.
Set to 1 to turn on a 1.29 μA current source that adds 170 mV differential voltage to the voltage channel measurement.
Cleared to 0 to disable the voltage attenuator diagnostic.
High voltage temperature monitor. The high voltage temperature monitor is an uncalibrated temperature monitor
located on chip, close to the high voltage circuits. This monitor is completely separate to the on-chip, precision
temperature sensor (controlled via ADC1CON[7:6]) and allows user code to monitor die temperature change close to
the hottest part of the ADuC7036 die. The monitor generates a typical output voltage of 600 mV at 25°C and has a
negative temperature coefficient of typically −2.1 mV/°C.
Set to 1 to enable the on-chip, high voltage temperature monitor. When enabled, this voltage output temperature
monitor is routed directly to the voltage channel ADC.
Cleared to 0 to disable the on-chip, high voltage temperature monitor.
Voltage channel short enable bit.
Set to 1 to enable an internal short (at the attenuator, before the ADC input buffers) on the voltage channel ADC and to
allow noise to be measured as a self-diagnostic test.
Cleared to 0 to disable an internal short on the voltage channel.
WU and STI readback enable bit.
Set to 1 to enable input capability on the external WU and STI pins. In this mode, a rising or falling edge transition on
the WU and STI pins generates a high voltage interrupt. When this bit is set, the state of the WU and STI pins can be
monitored via the HVMON register (HVMON[7] and HVMON[5]).
Cleared to 0 to disable input capability on the external WU and STI pins.
High voltage I/O driver enable bit.
Set to 1 to reenable high voltage I/O pins (LIN/BSD, STI, and WU) that have been disabled as a result of a short-circuit
current event (the event must last longer than 20 μs for the LIN/BSD and STI pins and longer than 400 μs for the WU
pin). This bit must also be set to 1 to reenable the WU and STI pins if they were disabled by a thermal event. It should
be noted that this bit must be set to clear any pending interrupt generated by the short-circuit event (even if the event
has passed) as well as reenabling the high voltage I/O pins.
Cleared to 0 automatically.
Enable/disable short-circuit protection (LIN/BSD and STI).
Set to 1 to enable passive short-circuit protection on the LIN pin. In this mode, a short-circuit event on the LIN/BSD pin
generates a high voltage interrupt, IRQ3 (if enabled in IRQEN[16]), and asserts the appropriate status bit in HVSTA but
does not disable the short-circuiting pin.
Cleared to 0 to enable active short-circuit protection on the LIN/BSD pin. In this mode, during a short-circuit event, the
LIN/BSD pin generates a high voltage interrupt (IRQ3), asserts HVSTA[16], and automatically disables the shortcircuiting pin. When disabled, the I/O pin can only be reenabled by writing to HVCFG1[3].
WU pin timeout (monoflop) counter enable/disable.
Set to disable the WU I/O timeout counter.
Cleared to enable a timeout counter that automatically deasserts the WU pin 1.3 sec after user code has asserted the
WU pin via HVCFG0[4].
WU open-circuit diagnostic enable.
Set to enable an internal WU I/O diagnostic pull-up resistor to the VDD pin, thus allowing detection of an open-circuit
condition on the WU pin.
Cleared to disable an internal WU I/O diagnostic pull-up resistor.
Rev. C | Page 99 of 132
ADuC7036
High Voltage Monitor Register
Name: HVMON
Address: Indirectly addressed via the HVCON high voltage interface
Default Value: 0x00
Access: Read only
Function: This 8-bit, read only register reflects the current status of enabled high voltage related circuits and functions on the ADuC7036.
This register is not an MMR and does not appear in the MMR memory map. It is accessed via the HVCON register interface, and data is
read back from this register via HVDAT.
Table 76. HVMON Bit Designations
Bit
7
6
5
4
3
2
1
0
Description
WU pin diagnostic readback. When enabled via HVCFG1[4], this read only bit reflects the state of the external WU pin.
Overtemperature.
0 = a thermal shutdown event has not occurred.
1 = a thermal shutdown event has occurred.
STI pin diagnostic readback. When enabled via HVCFG1[4], this read only bit reflects the state of the external STI pin.
Buffer enabled.
0 = the voltage channel ADC input buffer is disabled.
1 = the voltage channel ADC input buffer is enabled.
Low voltage flag status bit. Valid only if enabled via HVCFG0[2].
0 (at power-on) = REG_DVDD has dropped below 2.1 V. In this state, RAM contents can be deemed corrupt.
1 (at power-on) = REG_DVDD has not dropped below 2.1 V. In this state, RAM contents can be deemed valid. It is only
cleared by reenabling the low voltage flag in HVCFG0[2].
LIN/BSD short-circuit status flag.
0 = the LIN/BSD driver is operating normally.
1 = the LIN/BSD driver has experienced a short-circuit condition and is cleared automatically by writing to HVCFG1[3].
STI short-circuit status flag.
0 = the STI driver is operating normally.
1 = the STI driver has experienced a short-circuit condition and is cleared automatically by writing to HVCFG1[3].
Wake-up short-circuit status flag.
0 = the wake-up driver is operating normally.
1 = the wake-up driver has experienced a short-circuit condition.
Rev. C | Page 100 of 132
ADuC7036
High Voltage Status Register
Name: HVSTA
Address: Indirectly addressed via the HVCON high voltage interface
Default Value: 0x00
Access: Read only, this register should only be read on a high voltage interrupt
Function: This 8-bit, read only register reflects a change of state for all the corresponding bits in the HVMON register. This register is not
an MMR and does not appear in the MMR memory map. It is accessed through the HVCON registered interface, and data is read back
from this register via HVDAT. In response to a high voltage interrupt event, the high voltage interrupt controller simultaneously and
automatically loads the current value of the high voltage status register (HVSTA) into the HVDAT register.
Table 77. HVSTA Bit Designations
Bit
7 to 6
5
4
3
2
1
0
Description
Reserved. These bits should not be used and are reserved for future use.
PSM status bit. Valid only if enabled via HVCFG0[3]. This bit is not latched and the IRQ needs to be enabled to detect it.
0 = the voltage at the VDD pin stays above 6 V.
1 = the voltage at the VDD pin drops below 6 V.
WU request status bit. Valid only if enabled via HVCFG1[4].
0 = the WU pin has not generated a high voltage interrupt.
1 = a rising or falling edge transition on the WU pin generated a high voltage interrupt (when enabled via HVCFG1[4]).
Overtemperature. This bit is always enabled.
0 = a thermal shutdown event has not occurred.
1 = a thermal shutdown event has occurred. All high voltage (LIN/BSD, WU, and STI) pin drivers are automatically
disabled once a thermal shutdown has occurred.
LIN/BSD short-circuit status flag.
0 = normal LIN/BSD operation. Cleared automatically by reading the HVSTA register.
1 = a LIN/BSD short circuit is detected. In this condition, the LIN driver is automatically disabled.
STI short-circuit status flag.
0 = normal STI driver operation. Cleared automatically by reading the HVSTA register.
1 = the STI driver has experienced a short-circuit condition.
Wake-up short-circuit status flag.
0 = normal wake-up operation.
1 = a wake-up short-circuit is detected.
Rev. C | Page 101 of 132
ADuC7036
By default, the monoflop is enabled and disables the wake-up
driver after 1.3 sec. It is possible to disable the monoflop through
HVCFG1[1]. If the wake-up monoflop is disabled, the wake-up
driver should be disabled after 1.3 sec.
WAKE-UP (WU) PIN
The wake-up (WU) pin is a high voltage GPIO controlled
through HVCON and HVDAT.
Wake-Up (WU) Pin Circuit Description
The WU pin also features a short-circuit detection feature. When
the wake-up pin sources more than 100 mA typically for 400 μs,
a high voltage interrupt is generated, and HVMON[0] is set.
By default, the WU pin is configured as an output with an
internal 10 kΩ pull-down resistor and high-side FET driver.
In its default mode of operation, the WU pin is specified to
generate an active high system wake-up request by forcing the
external system WU bus high. User code can assert the WU
output by writing directly to HVCFG0[4].
A thermal shutdown event disables the WU driver. The WU
driver must be reenabled manually after using HVCFG1[3]
after a thermal event.
The WU pin can be configured in I/O mode by writing a 1 to
HVCFG1[4]. In this mode, a rising or falling edge immediately
generates a high voltage interrupt. HVMON[7] directly reflects
the state of the external WU pin and indicates if the external
wake-up bus (including RLOAD = 1 kΩ, CLOAD = 91 nF, and RLIMIT =
39 Ω) is above or below a typical voltage of 3 V.
Note that the output responds only after a 10 μs latency has elapsed;
this latency is inherent in a serial communication between the
HVCON or HVDAT MMR and the high voltage interface (see
the High Voltage Peripheral Control Interface section).
The internal FET is capable of sourcing significant current;
therefore, substantial on-chip self-heating may occur if this
driver is asserted for a long time period. For this reason,
a monoflop (that is, a 1.3 sec timeout timer) is included.
VDD
SHORT-CIRCUIT
TRIP REFERENCE
400µs
GLITCH
IMMUNITY
INTERNAL
SENSE
RESISTOR
NORMAL
HVCFG0[4]
HVCFG1[0]
6kΩ
~1V
NORMAL
HVMON[7]
R1
6.6kΩ
R2
3.3kΩ
ENABLE
READBACK
HVCFG1[4]
OPEN-CIRCUIT
DIAGNOSTIC
RESISTOR
INTERNAL
10kΩ
RESISTOR
IO_VSS
Figure 42. WU Circuit, Block Diagram
Rev. C | Page 102 of 132
EXTERNAL
WU PIN
EXTERNAL
CURRENT-LIMIT
RESISTOR
39Ω
CLOAD
91nF
RLOAD
1kΩ
EXTERNAL
WAKE-UP
BUS
07474-039
SHORT-CIRCUIT
PROTECTION
OUTPUT CONTROL
HVMON[0]
ADuC7036
HANDLING INTERRUPTS FROM THE HIGH
VOLTAGE PERIPHERAL CONTROL INTERFACE
An interrupt controller is integrated with the high voltage circuits.
If the interrupt controller is enabled through IRQEN[16], one of
six high voltage sources can assert the high voltage interrupt
(IRQ3) signal and interrupt the MCU core.
Although the normal MCU response to this interrupt event is
to vector to the IRQ or FIQ vector address, the high voltage
interrupt controller simultaneously and automatically loads the
current value of the high voltage status register (HVSTA) into the
HVDAT register. During this time, the busy bit in HVCON[0] is
set to indicate that a transfer is in progress and then is cleared
after 10 μs to indicate the HVSTA contents are available in HVDAT.
The interrupt handler, therefore, can poll the busy bit in HVCON
until it deasserts. After the busy bit is cleared, HVCON[1] must
be checked to ensure that the data was read correctly. Next, the
HVDAT register can be read. At this time, HVDAT holds the value
of the HVSTA register. The status flags can then be interrogated
to determine the exact source of the high voltage interrupt, and
the appropriate action can be taken.
LOW VOLTAGE FLAG (LVF)
The ADuC7036 features a low voltage flag (LVF) that allows the
user to monitor REG_DVDD. When enabled via HVCFG0[2],
the low voltage flag can be monitored through HVMON[3]. If
REG_DVDD drops below 2.1 V, HVMON[3] is cleared and the
RAM contents are corrupted. After the low voltage flag is enabled,
it is reset only by REG_DVDD dropping below 2.1 V or by
disabling the LVF functionality using HVCFG0[2].
HIGH VOLTAGE DIAGNOSTICS
It is possible to diagnosis fault conditions on the WU, LIN, and
STI pins, as described in Table 78.
Table 78. High Voltage Diagnostics
High
Voltage Pin
LIN or STI
WU
Fault Condition
Short between LIN or
STI and VBAT
Short between LIN or
STI and GND
Short between wake-up
and VBAT
Short between wake-up
and GND
Open circuit
Method
Drive LIN or STI low
Drive LIN or STI high
Result
LIN or STI short-circuit interrupt is generated after 20 μs if
more than 100 mA is continuously drawn.
LIN or STI readback reads back low.
Drive WU low
Readback high in HVMON[7].
Drive WU high
WU short-circuit interrupt is generated after 400 μs if more
than 100 mA typically is sourced.
HVMON[7] is cleared if the load is connected and set if WU is
open-circuited.
Enable OC diagnostic resistor
with WU disabled
Rev. C | Page 103 of 132
ADuC7036
UART SERIAL INTERFACE
The ADuC7036 features a 16,450-compatible UART. The UART
is a full-duplex, universal, asynchronous receiver/transmitter. A
UART performs serial-to-parallel conversion on data characters
received from a peripheral device and performs parallel-to-serial
conversion on data characters received from the ARM7TDMI.
The UART features a fractional divider that facilitates high accuracy baud rate generation and a network addressable mode. The
UART functionality is available on the GPIO_5/IRQ1/RxD and
GPIO_6/ TxD pins of the ADuC7036.
Fractional Divider
The serial communication adopts an asynchronous protocol that
supports various word lengths, stop bits, and parity generation
options selectable in the configuration register.
Calculation of the baud rate using a fractional divider is as follows:
The fractional divider, combined with the normal baud rate
generator, allows the generation of accurate, high speed baud rates.
/16DL
Baud Rate =
20.48 MHz
2
CD
× 16 × 2 × DL
(1)
UART
Figure 43. Fractional Divider Baud Rate Generation
Baud Rate =
The ADuC7036 features two methods of generating the UART
baud rate: normal 450 UART baud rate generation and ADuC7036
fractional divider baud rate generation.
The baud rate is a divided version of the core clock using the
value in COMDIV0 and COMDIV1 MMRs (each is a 16-bit
value, DL). The standard baud rate generator formula is
FBEN
/(M+N/2048)
BAUD RATE GENERATION
Normal 450 UART Baud Rate Generation
/2
07474-040
CORE
CLOCK
M+
20.48 MHz
2 CD × 16 × DL × 2 × ( M +
N
)
2048
(2)
20.48 MHz
N
=
2048 Baud Rate × 2 CD × 16 × DL × 2
where:
CD is the clock divider.
DL is the divisor latch.
M is the integer part of the divisor; a fractional divider divides
an input by a nonwhole number, M.N.
N is the fractional part of the divisor; a fractional divider
divides an input by a nonwhole number, M.N.
Table 80 lists common baud rate values.
Table 79 lists common baud rate values.
Table 80. Baud Rate Using the Fractional Baud Rate Generator
Table 79. Baud Rate Using the Standard Baud Rate Generator
Baud Rate
(bps)
9600
19,200
115,200
Baud Rate (bps)
9600
19,200
115,200
9600
19,200
115,200
CD
0
0
0
3
3
3
DL
0x43
0x21
0x6
0x8
0x4
0x1
Actual Baud Rate
9552
19,394
106,667
10,000
20,000
80,000
% Error
0.50%
1.01%
7.41%
4.17%
4.17%
30.56%
Rev. C | Page 104 of 132
CD
0
0
0
DL
0x42
0x21
0x5
M
1
1
1
N
21
21
228
Actual
Baud Rate
9598.55
19,197.09
115,177.51
% Error
0.015%
0.015%
0.0195%
ADuC7036
UART REGISTER DEFINITIONS
UART Rx Register
The UART interface consists of the following registers:
Name: COMRX
•
•
•
•
•
•
•
•
•
•
Address: 0xFFFF0700
COMTX: 8-bit transmit register
COMRX: 8-bit receive register
COMDIV0: divisor latch (low byte)
COMDIV1: divisor latch (high byte)
COMCON0: line control register
COMCON1: line control register
COMSTA0: line status register
COMIEN0: interrupt enable register
COMIID0: interrupt identification register
COMDIV2: 16-bit fractional baud divide register
Default Value: 0x00
Access: Read only
Function: This 8-bit register is read from to receive data
transmitted using the UART.
UART Divisor Latch Register 0
Name: COMDIV0
Address: 0xFFFF0700
Default Value: 0x00
COMTX, COMRX, and COMDIV0 share the same address
location. COMTX, COMIEN0, and COMRX can be accessed
when Bit 7 in the COMCON0 register is cleared, and
COMDIV0 and COMDIV1 can be accessed when Bit 7 of
COMCON0 is set.
UART Tx Register
Name: COMTX
Address: 0xFFFF0700
Access: Write only
Function: Writing to this 8-bit register transmits data using
the UART.
Access: Read/write
Function: This 8-bit register contains the least significant byte
of the divisor latch that controls the baud rate at which the
UART operates.
UART Divisor Latch Register 1
Name: COMDIV1
Address: 0xFFFF0704
Default Value: 0x00
Access: Read/write
Function: This 8-bit register contains the most significant byte
of the divisor latch that controls the baud rate at which the
UART operates.
Rev. C | Page 105 of 132
ADuC7036
UART Control Register 0
Name: COMCON0
Address: 0xFFFF070C
Default Value: 0x00
Access: Read/write
Function: This 8-bit register controls the operation of the UART in conjunction with COMCON1.
Table 81. COMCON0 MMR Bit Designations
Bit
7
Name
DLAB
6
BRK
5
SP
4
EPS
3
PEN
2
Stop
1 to 0
WLS
Description
Divisor latch access.
Set by user to enable access to COMDIV0 and COMDIV1.
Cleared by user to disable access to COMDIV0 and COMDIV1 and to enable access to COMRX, COMTX, and
COMIEN0.
Set break.
Set by user to force TxD to 0.
Cleared to operate in normal mode.
Stick parity. Set by user to force parity to defined values.
1 if EPS = 1 and PEN = 1.
0 if EPS = 0 and PEN = 1.
Even parity select bit.
Set for even parity.
Cleared for odd parity.
Parity enable bit.
Set by user to transmit and check the parity bit.
Cleared by user for no parity transmission or checking.
Stop bit.
Set by user to transmit 1.5 stop bits if the word length is five bits, or two stop bits if the word length is six, seven, or
eight bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected.
Cleared by the user to generate one stop bit in the transmitted data.
Word length select.
00 = five bits.
01 = six bits.
10 = seven bits.
11 = eight bits.
UART Control Register 1
Name: COMCON1
Address: 0xFFFF0710
Default Value: 0x00
Access: Read/write
Function: This 8-bit register controls the operation of the UART in conjunction with COMCON0.
Table 82. COMCON1 MMR Bit Designations
Bit
7 to 6
Name
SMS
5
4
3 to 0
LOOPBACK
Description
UART input mux.
00 = RxD driven by LIN input; required for LIN communications using the LIN pin.
01 = reserved.
10 = RxD driven by GP5; required for serial communications using the GPIO_5/IRQ1/RxD pin (RxD).
11 = reserved.
Reserved. Not used.
Loopback. Set by user to enable loopback mode. In loopback mode, the TxD is forced high.
Reserved. Not used.
Rev. C | Page 106 of 132
ADuC7036
UART Status Register 0
Name: COMSTA0
Address: 0xFFFF0714
Default Value: 0x60
Access: Read only
Function: This 8-bit, read only register reflects the current status of the UART.
Table 83. COMSTA0 MMR Bit Designations
Bit
7
6
Name
TEMT
5
THRE
4
BI
3
FE
2
PE
1
OE
0
DR
Description
Reserved.
COMTX and shift register empty status bit.
Set automatically if COMTX and the shift register are empty. This bit indicates that the data has been
transmitted; that is, no more data is present in the shift register.
Cleared automatically by writing to COMTX.
COMTX empty status bit.
Set automatically if COMTX is empty. COMTX can be written as soon as the THRE bit is set, but the
previous data may not have been transmitted yet and may still be present in the shift register.
Cleared automatically by writing to COMTX.
Break indicator.
Set when SIN is held low for more than the maximum word length.
Cleared automatically.
Framing error.
Set when the stop bit is invalid.
Cleared automatically.
Parity error.
Set when a parity error occurs.
Cleared automatically.
Overrun error.
Set automatically if data is overwritten before being read.
Cleared automatically.
Data ready.
Set automatically when COMRX is full.
Cleared by reading COMRX.
Rev. C | Page 107 of 132
ADuC7036
UART Interrupt Enable Register 0
Name: COMIEN0
Address: 0xFFFF0704
Default Value: 0x00
Access: Read/write
Function: This 8-bit register enables and disables the individual UART interrupt sources.
Table 84. COMIEN0 MMR Bit Designations
Bit
7 to 4
3
2
Name
1
ETBEI
0
ERBFI
EDSSI
ELSI
Description
Reserved. Not used.
Reserved. This bit should be written as 0.
RxD status interrupt enable bit.
Set by the user to enable generation of an interrupt if any of the COMSTA0[3:1] register bits are set.
Cleared by the user.
Enable transmit buffer empty interrupt.
Set by the user to enable an interrupt when the buffer is empty during a transmission, that is, when
COMSTA0[5] is set.
Cleared by the user.
Enable receive buffer full interrupt.
Set by the user to enable an interrupt when the buffer is full during a reception.
Cleared by the user.
UART Interrupt Identification Register 0
Name: COMIID0
Address: 0xFFFF0708
Default Value: 0x01
Access: Read only
Function: This 8-bit register reflects the source of the UART interrupt.
Table 85. COMIID0 MMR Bit Designations
Bits[2:1]
Status Bits
00
11
10
01
00
Bit 0 NINT
1
0
0
0
0
Priority
1
2
3
4
Definition
No interrupt
Receive line status interrupt
Receive buffer full interrupt
Transmit buffer empty interrupt
Reserved
Rev. C | Page 108 of 132
Clearing Operation
Read COMSTA0
Read COMRX
Write data to COMTX or read COMIID0
Reserved
ADuC7036
UART Fractional Divider Register
Name: COMDIV2
Address: 0xFFFF072C
Default Value: 0x0000
Access: Read/write
Function: This 16-bit register controls the operation of the fractional divider for the ADuC7036.
Table 86. COMDIV2 MMR Bit Designations
Bit
15
Name
FBEN
14 to 13
12 to 11
FBM[1:0]
10 to 0
FBN[10:0]
Description
Fractional baud rate generator enable bit.
Set by the user to enable the fractional baud rate generator.
Cleared by the user to generate the baud rate using the standard 450 UART baud rate generator.
Reserved.
Fractional Divider M. If FBM = 0, M = 4. See Equation 2 for the calculation of the baud rate using
the M fractional divider and Table 80 for common baud rate values.
Fractional Divider N. See Equation 2 for the calculation of the baud rate using a fractional divider
and Table 80 for common baud rate values.
Rev. C | Page 109 of 132
ADuC7036
SERIAL PERIPHERAL INTERFACE
The ADuC7036 features a complete hardware serial peripheral
interface (SPI) on chip. SPI is an industry-standard synchronous
serial interface that allows eight bits of data to be synchronously
transmitted and received simultaneously, that is, full duplex.
The SPI interface is operational only with core clock divider bits
(POWCON[2:0] = 0000 or 001).
The SPI port can be configured for master or slave operation
and consists of four pins that are multiplexed with four GPIOs.
The four SPI pins are MISO, MOSI, SCLK, and SS. The pins to
which these signals are connected are shown in Table 87.
Table 87. SPI Output Pins
Pin
GP0 (GPIO Mode 1)
GP1 (GPIO Mode 1)
GP2 (GPIO Mode 1)
GP3 (GPIO Mode 1)
SPI
Pin Function
SS
SCLK
MISO
MOSI
Description
Chip select
Serial clock
Master input, slave output
Master output, slave input
In master mode, polarity and phase of the clock is controlled by
the SPICON register, and the bit rate is defined in the SPIDIV
register using the SPI baud rate calculation, as follows:
f SERIAL CLOCK =
20.48 MHz
(3)
2 × (1 + SPIDIV )
The maximum speed of the SPI clock is dependent on the clock
divider bits and is summarized in Table 88.
Table 88. SPI Speed vs. Clock Divider Bits in Master Mode
Setting of CD Bits
0
1
SPIDIV
0x05
0x0B
Maximum SCLK (MHz)
1.667
0.833
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data of up to 5.12 Mb from an external master when
CD = 0. The formula to determine the maximum speed is as
follows:
MISO PIN
f SERIAL CLOCK =
f HCLK
4
(4)
The MISO (master input, slave output) pin is configured as an
input line in master mode and as an output line in slave mode.
The MISO line on the master (data in) should be connected to
the MISO line in the slave device (data out). The data is transferred
as byte-wide (8-bit) serial data, MSB first.
In both master and slave modes, data is transmitted on one edge
of the SCL signal and sampled on the other. Therefore, it is
important to use the same polarity and phase configurations for
the master and slave devices.
MOSI PIN
SS PIN
The MOSI (master output, slave input) pin is configured as an
output line in master mode and as an input line in slave mode.
The MOSI line on the master (data out) should be connected to
the MOSI line in the slave device (data in). The data is transferred
as byte-wide (8-bit) serial data, MSB first.
In SPI slave mode, a transfer is initiated by the assertion of SS,
an active low input signal. The SPI port transmits and receives
eight bits of data, and then the transfer is concluded by the
deassertion of SS. In slave mode, SS is always an input.
SCLK PIN
The SCLK (master serial clock) pin is used to synchronize the
data being transmitted and received through the MOSI SCLK
period. Therefore, a byte is transmitted/received after eight
SCLK periods. The SCLK pin is configured as an output in
master mode and as an input in slave mode.
SPI REGISTER DEFINITIONS
The following MMR registers are used to control the SPI
interface:
•
•
•
•
•
SPICON: 16-bit control register
SPISTA: 8-bit, read only status register
SPIDIV: 8-bit, serial clock divider register
SPITX: 8-bit, write only transmit register
SPIRX: 8-bit, read only receive register
Rev. C | Page 110 of 132
ADuC7036
SPI Control Register
Name: SPICON
Address: 0xFFFF0A10
Default Value: 0x0000
Access: Read/write
Function: This 16-bit MMR configures the serial peripheral interface.
Table 89. SPICON MMR Bit Designations
Bit
15 to 13
12
11
10
9
8
7
6
5
4
3
2
1
0
Description
Reserved.
Continuous transfer enable.
Set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in
the SPITX register. SS is asserted and remains asserted for the duration of each 8-bit serial transfer until SPITX is empty.
Cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data
exists in the SPITX register, a new transfer is initiated after a stall period.
Loopback enable.
Set by the user to connect MISO to MOSI and test software.
Cleared by the user to be in normal mode.
Slave output enable.
Set by the user to enable the slave output.
Cleared by the user to disable the slave output.
Slave select input enable.
Set by the user in master mode to enable the output.
Cleared by the user to disable the output.
SPIRX overflow overwrite enable.
Set by the user; the valid data in the SPIRX register is overwritten by the new serial byte received.
Cleared by the user; the new serial byte received is discarded.
SPITX underflow mode.
Set by the user to transmit the previous data.
Cleared by the user to transmit 0.
Transfer and interrupt mode (master mode).
Set by the user to initiate a transfer with a write to the SPITX register. An interrupt occurs when SPITX is empty.
Cleared by the user to initiate a transfer with a read of the SPIRX register. An interrupt occurs when SPIRX is full.
LSB first transfer enable bit.
Set by the user; the LSB is transmitted first.
Cleared by the user; the MSB is transmitted first.
Reserved.
Serial clock polarity mode bit.
Set by the user; the serial clock idles high.
Cleared by the user; the serial clock idles low.
Serial clock phase mode bit.
Set by the user; the serial clock pulses at the beginning of each serial bit transfer.
Cleared by the user; the serial clock pulses at the end of each serial bit transfer.
Master mode enable bit.
Set by the user to enable master mode.
Cleared by the user to enable slave mode.
SPI enable bit.
Set by the user to enable the SPI.
Cleared by the user to disable the SPI.
Rev. C | Page 111 of 132
ADuC7036
SPI Status Register
SPI Receive Register
Name: SPISTA
Name: SPIRX
Address: 0xFFFF0A00
Address: 0xFFFF0A04
Default Value: 0x00
Default Value: 0x00
Access: Read only
Access: Read only
Function: This 8-bit MMR represents the current status of the
serial peripheral interface.
Function: This 8-bit MMR contains the data received using the
serial peripheral interface.
Table 90. SPISTA MMR Bit Designations
SPI Transmit Register
Bit
7 to 6
5
Name: SPITX
4
3
2
1
0
Description
Reserved.
SPIRX data register overflow status bit.
Set if SPIRX is overflowing.
Cleared by reading the SPIRX register.
SPIRX data register IRQ.
Set automatically if Bit 3 or Bit 5 is set.
Cleared by reading the SPIRX register.
SPIRX data register full status bit.
Set automatically if valid data is present in the SPIRX
register.
Cleared by reading the SPIRX register.
SPITX data register underflow status bit.
Set automatically if SPITX is underflowing.
Cleared by writing in the SPITX register.
SPITX data register IRQ.
Set automatically if Bit 0 is cleared or Bit 2 is set.
Cleared either by writing in the SPITX register or, if the
transmission is finished, by disabling the SPI.
SPITX data register empty status bit.
Set by writing to SPITX to send data. This bit is set
during transmission of data.
Cleared when SPITX is empty.
Address: 0xFFFF0A08
Access: Write only
Function: Write to this 8-bit MMR to transmit data using the
serial peripheral interface.
SPI Divider Register
Name: SPIDIV
Address: 0xFFFF0A0C
Default Value: 0x1B
Access: Read/write
Function: The 8-bit MMR represents the frequency at which the
serial peripheral interface is operating. For more information
on the calculation of the baud rate, refer to Equation 3.
Rev. C | Page 112 of 132
ADuC7036
SERIAL TEST INTERFACE
STICON. STIKEY0 must be written with 0x0007 immediately
before STICON is written to ensure the STICON write sequence
complets successfully. If STIKEY1 is not written, is written out
of sequence, or is written incorrectly, any previous write to the
STICON MMR is ignored.
The ADuC7036 incorporates single-pin, serial test interface
(STI) ports that can be used for end-customer evaluation or
diagnostics on finished production units.
The STI port transmits from one byte to six bytes of data in 12-bit
packets. As shown in Figure 44, each transmission packet includes
a start bit, the transmitted byte (eight bits), an even parity bit, and
two stop bits. The STI data is transmitted on the STI pin, and
the baud rate is determined by the overflow rate of Timer4.
Serial Test Interface Data0 Register
Name: STIDAT0
Address: 0xFFFF088C
The STI port is configured and controlled via six MMRs.
Default Value: 0x0000
STIKEY0: Serial Test Interface Key0
STIKEY1: Serial Test Interface Key1
STIDAT0: Data0 (16-bit) holds two bytes
STIDAT1: Data1 (16-bit) holds two bytes
STIDAT2: Data2 (16-bit) holds two bytes
STICON: controls the serial test interface
Access: Read/write
Function: The STIDAT0 MMR is a 16-bit register that holds the
first and second data bytes that are to be transmitted on the STI pin
as soon as the STI port is enabled. The first byte to be transmitted
occupies Bits[0:7], and the second byte occupies Bits[8:15].
Serial Test Interface Data1 Register
Serial Test Interface Key0 Register
Name: STIDAT1
Name: STIKEY0
Address: 0xFFFF0890
Address: 0xFFFF0880
Default Value: 0x0000
Access: Write only
Access: Read/write
Function: The STIKEY0 MMR is used in conjunction with the
STIKEY1 MMR to protect the STICON MMR. STIKEY0 must
be written with 0x0007 immediately before any attempt to write
to STICON. STIKEY1 must be written with 0x00B9 immediately after STICON is written to ensure the STICON write
sequence completes successfully. If STIKEY0 is not written, is
written out of sequence, or is written incorrectly, any subsequent
write to the STICON MMR is ignored.
Function: The STIDAT1 MMR is a 16-bit register that holds the
third and fourth data bytes that are to be transmitted on the STI pin
when the STI port is enabled. The third byte to be transmitted
occupies Bits[0:7], and the fourth byte occupies Bits[8:15].
Serial Test Interface Data2 Register
Name: STIDAT2
Address: 0xFFFF0894
Serial Test Interface Key1 Register
Default Value: 0x0000
Name: STIKEY1
Access: Read/write
Address: 0xFFFF0888
Function: The STIDAT2 MMR is a 16-bit register that is used to
hold the fifth and sixth data bytes that are to be transmitted on
the STI pin when the STI port is enabled. The fifth byte to be
transmitted occupies Bits[0:7], and the sixth byte occupies
Bits[8:15].
Access: Write only
Function: The STIKEY1 MMR is used in conjunction with the
STIKEY0 MMR to protect the STICON MMR. STIKEY1 must
be written with 0x00B9 immediately after any attempt to write to
STI BYTE0
STI BYTE1
PARITY BIT
START BIT
STI BYTE2
PARITY BIT
WITH TWO STOP BITS
Figure 44. Serial ADC Test Interface Example, 3-Byte Transmission
Rev. C | Page 113 of 132
07474-041
•
•
•
•
•
•
ADuC7036
Serial Test Interface Control Register
Name: STICON
Address: 0xFFFF0884
Default Value: 0x0000
Access: Read/write access, write protected by two key registers (STIKEY0 and STIKEY1). A write access to STICON is completed
correctly only if the following triple write sequence is followed:
1.
2.
3.
STIKEY0 MMR is written with 0x0007.
STICON is written.
The sequence is completed by writing 0x00B9 to STIKEY1.
Function: The STI Control MMR is an 16-bit register that configures the mode of operation of the serial test interface.
Note that the GPIO_13 must be configured for STI operation in GP2CON for STI communications.
Table 91. STICON MMR Bit Designations
Bit
15 to 9
8 to 5
4 to 2
1
0
Description
Reserved. These bits are reserved for future use and should be written as 0 by user code.
State bits, read only. If the interface is in the middle of a transmission, these bits are not 0.
Number of bytes to transmit. These bits select the number of bytes to be transmitted. User code must subsequently
write the bytes to be transmitted into the STIDAT0, STIDAT1, and STIDAT2 MMRs.
000 = 1-byte transmission.
001 = 2-byte transmission.
010 = 3-byte transmission.
011 = 4-byte transmission.
100 = 5-byte transmission.
101 = 6-byte transmission.
Reset serial test interface.
1 = resets the serial test interface. A subsequent read of STICON returns all 0s.
0 = operates in normal mode (default).
Serial test interface enable. This bit is set by user code.
1 = enables the serial test interface.
0 = disables the serial test interface.
Rev. C | Page 114 of 132
ADuC7036
Serial Test Interface Output Structure
The serial test interface is a high voltage output that incorporates
a low-side driver, short-circuit protection, and diagnostic pin
readback capability. The output driver circuit configuration is
shown in Figure 45.
REF1
STI PIN
READBACK
HVMON[5]
STI
TRANSMIT
GP2CON[24]
07474-042
T4LD =
Figure 45. STI Output Structure
Using the Serial Test Interface
Data begins transmission only when the STI port is configured
as follows:
•
•
•
For example, if the ADC is sampling at 1 kHz, the baud rate
must be sufficient to output 36 bits as follows: (3 × 8 bits (16-bit
ADC result and a checksum byte, for example)) + (3 × 1 start
bit) + (3 × 1 parity bit) + (3 × 2 stop bits) = 36 bits.
Therefore, the serial test interface must transmit data at greater
than 36 kbps. The closest standard baud rate is 38.4 kbps; as such,
the reload value written to the Timer4 load MMR (T4LD) is
0x0106 (267 decimal). This value is based on a prescaler of 1
and is calculated as follows, using a core clock of 10.24 MHz:
STI
SHORT-CIRCUIT
PROTECTION CONTROL
HVCFG1[2]
cient to output each ADC result (16-bits) before the next ADC
conversion result is available.
Configure Timer4 for baud rate generation.
Correctly enable STICON using STIKEY0 and STIKEY1
for secure access.
Required bytes to be transmitted are written into
STIDAT0, STIDAT1, and STIDAT2.
Timer4 is configured with the correct load value to generate an
overflow at the required baud rate. If the STI port is being used
to transmit ADC conversion results, the baud rate must be suffi-
Core Clock Frequency
Desired Baud Rate
=
10.24 MHz
38.4 kbps
= 267
When the Timer4 load value is written and the timer itself is
configured and enabled using the T4CON MMR, the STI port
must be configured. This is accomplished by writing to the
STICON MMR in a specific sequence using the STIKEY0 and
STIKEY1 MMRs as described in the previous sections.
Finally, the STI port does not begin transmission until the required
number of transmit bytes are written into the STIDATx MMRs. As
soon as STI starts transmitting, the value in the STICON MMR
changes from the value initially written to this register. User code
can ensure that all data is transmitted by continuously polling
the STICON MMR until it reverts back to the value originally
written to it. To disable the serial interface, user code must write
a 0 to STICON[0].
Example Code
An example code segment configuring the STI port to transmit five bytes and then to transmit two bytes follows:
T4LD = 267;
T4CON = 0xC0;
// Timer4 reload value
// Enable T4, selecting core clock in periodic mode
STIKEY0 = 07;
STICON = 0x11;
STIKEY1 = 0xb9;
// STICON start write sequence
// Enable and transmit five bytes
// STICON complete write
STIDAT0 = 0xAABB;
STIDAT1 = 0xCCDD;
STIDAT2 = 0xFF;
// Five bytes for
// transmission
while(STICON != 0x09)
{}
// Wait for transmission to complete
STIKEY0 = 07;
STICON = 0x05;
STIKEY1 = 0xb9;
// STICON start write sequence
// Enable and transmit two bytes
// STICON complete write
STIDAT0 = 0xEEFF;
// Two bytes for transmission
while(STICON != 0x09)
{}
// Wait for transmission to complete
Rev. C | Page 115 of 132
ADuC7036
LIN (LOCAL INTERCONNECT NETWORK) INTERFACE
The ADuC7036 features high voltage physical interfaces between
the ARM7 MCU core and an external LIN bus. The LIN interface operates as a slave only interface, operating from 1 kBaud
to 20 kBaud, and it is compatible with the LIN 2.0 standard.
The pull-up resistor required for a slave node is on chip,
reducing the need for external circuitry. The LIN protocol is
emulated using the on-chip UART, an IRQ, a dedicated LIN
timer, and the high voltage transceiver (also incorporated on
chip) as shown in Figure 46. The LIN is clocked from the low
power oscillator for the break timer, and a 5 MHz output from
the PLL is used for the synchronous byte timing.
LIN MMR DESCRIPTION
The LIN hardware synchronization (LHS) functionality is controlled through five MMRs. The function of each MMR is as
follows:
•
•
•
•
•
LHS
INTERRUPT
LOGIC
LHS
HARDWARE
5MHz
LHSVAL0
131kHz
LHSVAL1
FOUR LIN
INTERRUPT
SOURCES:
BREAK LHSSTA[0]
START LHSSTA[1]
STOP LHSSTA[2]
BREAK
ERROR LHSSTA[4]
VDD
INPUT
VOLTAGE
THRESHOLD
REFERENCE
RxD ENABLE
LHSCON0[8]
VDD
LIN ENABLE
(INTERNAL
PULL-UP)
HVCFG0[5]
EXTERNAL
LIN PIN
RxD
UART
GPIO_12
GP2DAT[29]
AND
GPSDAT[21]
MASTER ECU
PULL-UP
CLOAD
LIN MODE
HVCFG0[1:0]
OVERVOLTAGE SCR
PROTECTION
TxD
GPIO_12
FUNCTION
SELECT
GP2CON[20]
MASTER ECU
PROTECTION
DIODE
OUTPUT
DISABLE
BPF
INTERNAL
SHORT-CIRCUIT
SENSE
RESISTOR
SHORT-CIRCUIT
CONTROL
HVCFG1[2]
INTERNAL
SHORT-CIRCUIT
TRIP REFERENCE
Figure 46. LIN I/O Block Diagram
Rev. C | Page 116 of 132
IO_VSS
07474-043
LHS INTERRUPT
IRQEN[7]
LHSSTA: LHS status register. This MMR contains information flags that describe the current status on the
interface.
LHSCON0: LHS Control Register 0. This MMR controls
the configuration of the LHS timer.
LHSCON1: LHS start and stop edge control register. This
MMR dictates on which edge of the LIN synchronization
byte the LHS starts/stops counting.
LHSVAL0: LHS synchronization 16-bit timer. This MMR is
controlled by LHSCON0.
LHSVAL1: LHS break timer register.
ADuC7036
LIN Hardware Synchronization Status Register
Name: LHSSTA
Address: 0xFFFF0780
Default Value: 0x00000000
Access: Read only
Function: This LHS status register is a 32-bit register whose bits reflect the current operating status of the LIN interface.
Table 92. LHSSTA MMR Bit Designations
Bit
31 to 7
6
5
4
3
2
1
0
Description
Reserved. These read only bits are reserved for future use.
Rising edge detected (BSD mode only).
Set to 1 by hardware to indicate a rising edge has been detected on the BSD bus.
Cleared to 0 after user code reads the LHSSTA MMR.
LHS reset complete flag.
Set to 1 by hardware to indicate an LHS reset command has completed successfully.
Cleared to 0 after user code reads the LHSSTA MMR.
Break field error.
Set to 1 by hardware and generates an LHS interrupt (IRQEN[7]) when the 12-bit break timer (LHSVAL1) register
overflows to indicate the LIN bus has stayed low too long, thus indicating a possible LIN bus error.
Cleared to 0 after user code reads the LHSSTA MMR.
LHS compare interrupt.
Set to 1 by hardware when the value in LHSVAL0 (LIN synchronization bit timer) equals the value in the LHSCMP register.
Cleared to 0 after user code reads the LHSSTA MMR.
Stop condition interrupt.
Set to 1 by hardware when a stop condition is detected.
Cleared to 0 after user code reads LHSSTA MMR.
Start condition interrupt.
Set to 1 by hardware when a start condition is detected.
Cleared to 0 after user code reads LHSSTA MMR.
Break timer compare interrupt.
Set to 1 by hardware when a valid LIN break condition is detected. A LIN break condition is generated when the LIN
break timer value reaches the break timer compare value (see the LHSVAL1 in the LIN Hardware Synchronization Break
Timer1 Register section for more information).
Cleared to 0 after user code reads the LHSSTA MMR.
Rev. C | Page 117 of 132
ADuC7036
LIN Hardware Synchronization Control Register 0
Name: LHSCON0
Address: 0xFFFF0784
Default Value: 0x00000000
Access: Read/write
Function: This 16-bit LHS control register, in conjunction with the LHSCON1 register, is used to configure the LIN mode of operation.
Table 93. LHSCON0 MMR Bit Designations
Bit
15 to 13
12
11
10
9
8
Description
Reserved. These bits are reserved for future use and should be written as 0 by user software.
Rising edge detected interrupt disable.
Mode
Description
BSD mode
Set to 1 to disable the rising edge detected interrupt.
Cleared to 0 to enable the break rising edge detected interrupt.
LIN mode
Set to 1 to enable the rising edge detected interrupt.
Cleared to 0 to disable the break rising edge detected interrupt.
Break timer compare interrupt disable.
Set to 1 to disable the break timer compare interrupt.
Cleared to 0 to enable the break timer compare interrupt.
Break timer error interrupt disable.
Set to 1 to disable the break timer error interrupt.
Cleared to 0 to enable the break timer error interrupt.
LIN transceiver, standalone test mode.
Set to 1 by user code to enable the external GPIO_7 and GPIO_8 pins to drive the LIN Transceiver TxD and the LIN Transceiver
RxD, respectively, independent of the UART. The functions of GPIO_7 and GPIO_8 should first be configured by user code via
the GPIO_7 Function Select Bit 0 and GPIO_8 Function Select Bit 4 in the GP2CON register.
Cleared to 0 by user code to operate the LIN in normal mode, it is driven directly from the on-chip UART.
Gate UART/BSD R/W bit.
Mode
UART mode
7
6
Description
Set to 1 by user code to disable the internal UART RxD (receive data) by gating it high until both the break
field and subsequent LIN sync byte are detected. This ensures that during break or sync field periods the
UART does not receive any spurious serial data that has to be flushed out of the UART before valid data
fields can be received.
Cleared to 0 by user code to enable the internal UART RxD (receive data) after the break field and
subsequent LIN sync byte have been detected so that the UART can receive the subsequent LIN data fields.
BSD read
Set to 1 by user code to enable the generation of a break condition interrupt (LHSSTA[0]) on a rising edge of
mode 1
the BSD bus. The break timer (LHSVAL1) starts counting on the falling edge and stops counting on the rising
edge, where an interrupt is generated, allowing user code to determine if a 0, 1, or sync pulse width has
been received. Note that the break timer generates an interrupt if the value in the LIN break timer (LHSVAL1
read value) equals the break timer compare value (LHSVAL1 write value), and if the break timer overflows.
This configuration can be used in BSD read mode to detect fault conditions on the BSD bus.
BSD write mode1 Cleared to 0 by user code to disable the generation of break condition interrupts on a rising edge of the BSD
bus. The LHS compare interrupt bit (LHSSTA[3]) is used to determine when the MCU should release the BSD
bus while transmitting data. If the break condition interrupt is still enabled, it generates an unwanted
interrupt as soon as the BSD bus is deasserted. As in BSD read mode, the break timer stops counting on a
rising edge; therefore, the break timer can also be used in this mode to allow user code to confirm the pulse
width in transmitted data bits.
Sync timer stop edge type bit.
Set to 1 by user code to stop the sync timer on the rising edge count configured through the LHSCON1[7:4] register.
Cleared to 0 by user code to stop the sync timer on the falling edge count configured through the LHSCON1[7:4] register.
Mode of operation bit.
Set to 1 by user code to select BSD mode of operation.
Cleared to 0 by user code to select LIN mode of operation.
Rev. C | Page 118 of 132
ADuC7036
Bit
5
4
3
2
1
0
1
Description
Enable compare interrupt bit.
Set to 1 by user code to generate an LHS interrupt (IRQEN[7]) when the value in LHSVAL0 (the LIN synchronization bit timer)
equals the value in the LHSCMP register. The LHS compare interrupt bit, LHSSTA[3], is set when this interrupt occurs. This
configuration is used in BSD write mode to allow user code to correctly time the output pulse widths of BSD bits to be transmitted.
Cleared to 0 by user code to disable compare interrupts.
Enable stop interrupt.
Set to 1 by user code to generate an interrupt when a stop condition occurs.
Cleared to 0 by user code to disable interrupts when a stop condition occurs.
Enable start interrupt.
Set to 1 by user code to generate an interrupt when a start condition occurs.
Cleared to 0 by user code to disable interrupts when a start condition occurs.
LIN sync enable bit.
Set to 1 by user code to enable LHS functionality.
Cleared to 0 by user code to disable LHS functionality.
Edge counter clear bit.
Set to 1 by user code to clear the internal edge counters in the LHS peripheral.
Cleared automatically to 0 after a 15 μs delay.
LHS reset bit.
Set to 1 by user code to reset all LHS logic to default conditions.
Cleared automatically to 0 after a 15 μs delay.
In BSD mode, LHSCON0[6] is set to 1. Because of the finite propagation delay in the BSD transmit (from the MCU to the external pin) and receive (from the external pin
to the MCU) paths, user code must not switch between BSD write and read modes until the MCU confirms that the external BSD pin is deasserted. Failure to adhere to
this recommendation may result in the generation of an inadvertent break condition interrupt after user code switches from BSD write mode to BSD read mode. A
stop condition interrupt can be used to ensure that this scenario is avoided.
LIN Hardware Synchronization Control Register 1
Name: LHSCON1
Address: 0xFFFF078C
Default Value: 0x00000032
Access: Read/write
Function: This 32-bit LHS control register, in conjunction with the LHSCON0 register, is used to configure the LIN mode of operation.
Table 94. LHSCON1 MMR Bit Designations
Bit
31 to 8
7 to 4
3 to 0
Description
Reserved. These bits are reserved for future use and should be written as 0 by user software.
LIN stop edge count. Set by user code to the number of falling or rising edges on which to stop the internal LIN
synchronization counter. The stop value of this counter can be read by user code using LHSVAL0. The type of edge, either
rising or falling, is configured by LHSCON0[7]. The default value of these bits is 0x3, which configures the hardware to
stop counting on the third falling edge. Note that the first falling edge is considered to be the falling edge at the start of
the LIN break pulse.
LIN start edge count. These four bits are set by user code to the number of falling edges that must occur before the
internal LIN synchronization timer starts counting. The stop value of this counter can be read by user code using
LHSVAL0. The default value of these bits is 0x2, which configures the hardware to start counting on the second falling
edge. Note that the first falling edge is considered to be the falling edge at the start of the LIN break pulse.
Rev. C | Page 119 of 132
ADuC7036
LIN Hardware Synchronization Timer0 Register
LIN HARDWARE INTERFACE
Name: LHSVAL0
LIN Frame Protocol
Address: 0xFFFF0788
The LIN frame protocol is broken into four main categories:
break symbol, sync byte, protected identifier, and data bytes.
Default Value: 0x0000
Access: Read only
Function: This 16-bit, read only register holds the value of the
internal LIN synchronization timer. The LIN synchronization
timer is clocked from an internal 5 MHz clock and is independent of core clock and baud rate frequency. In LIN mode, the value
read by user code from the LHSVAL0 register can be used to
calculate the master LIN baud rate. This calculation is then used
to configure the internal UART baud rate to ensure correct LIN
communication via the UART from the ADuC7036 slave to the
LIN master node.
LIN Hardware Synchronization Break Timer1 Register
Name: LHSVAL1
Address: 0xFFFF0790
Default Value: 0x0000
The format of the frame header, break symbol, synchronization
byte, and protected identifier is shown in Figure 47. Essentially,
the embedded UART, the LIN hardware synchronization logic,
and the high voltage transceiver interface all combine on chip to
support and manage LIN-based transmissions and receptions.
LIN Frame Break Symbol
As shown in Figure 48, the LIN break symbol, which lasts at
least 13 bit periods, is used to signal the start of a new frame. The
slave must be able to detect a break symbol even while expecting or
receiving data. The ADuC7036 accomplishes this by using the
LHSVAL1 break condition and break error detect functionality
as described in the LIN Hardware Synchronization Break
Timer1 Register section. The break period does not have to be
accurately measured, but if a bus fault condition (bus held low)
occurs, it must be flagged.
LIN Frame Synchronization Byte
Access: Read/write
Function: When user code reads this location, the 12-bit value
returned is the value of the internal LIN break timer, which is
clocked directly from the on-chip low power 131 kHz oscillator
and times the LIN break pulse. A negative edge on the LIN bus
or user code reading the LHSVAL1 results in the timer and the
register contents being reset to 0.
When user code writes to this location, the 12-bit value is written
not to the LIN break timer but to a LIN break compare register.
In LIN mode of operation, the value in the compare register is
continuously compared to the break timer value. A LIN break
interrupt (IRQEN[7] and LHSSTA[0]) is generated when the
timer value reaches the compare value. After the break condition
interrupt, the LIN break timer continues to count until the
rising edge of the break signal. If a rising edge is not detected
and the 12-bit timer overflows (4096 × 1/131 kHz = 31 ms),
a break field error interrupt (IRQEN[7] and LHSSTA[4]) is
generated. By default, the value in the compare register is 0x0047,
corresponding to 11 bit periods (that is, the minimum pulse
width for a LIN break pulse at 20 kbps). For different baud rates,
this value can be changed by writing to LHSVAL1. Note that if
a valid break interrupt is not received, subsequent sync pulse
timing through the LHSVAL0 register does not occur.
The baud rate of the communication using LIN is calculated
from the sync byte, as shown in Figure 49. The time between
the first falling edge of the sync field and the fifth falling edge
of the sync field is measured and then divided by 8 to determine
the baud rate of the data that is to be transmitted. The ADuC7036
implements the timing of this sync byte in hardware. For more
information about this feature, see the LIN Hardware
Synchronization Status Register section.
LIN Frame Protected Identifier
After receiving the LIN sync field, the required baud rate for the
UART is calculated. The UART is then configured, allowing the
ADuC7036 to receive the protected identifier, as shown in
Figure 50. The protected identifier consists of two subfields: the
identifier and the identifier parity. The 6-bit identifier contains
the identifier of the target for the frame. The identifier signifies
the number of data bytes to be either received or transmitted. The
number of bytes is user configurable at the system-level design.
The parity is calculated on the identifier and is dependent on
the revision of LIN for which the system is designed.
LIN Frame Data Byte
The data byte frame carries between one and eight bytes of data.
The number of bytes contained in the frame is dependent on
the LIN master. The data byte frame is split into data bytes, as
shown in Figure 51.
Rev. C | Page 120 of 132
ADuC7036
LIN Frame Data Transmission and Reception
To manage data on the LIN bus requires use of the following
UART MMRs:
• COMTX: 8-bit transmit register
• COMRX: 8-bit receive register
• COMCON0: line control register
• COMSTA0: line status register
When the break symbol and synchronization byte have been
correctly received, data is transmitted and received via the COMTX
and COMRX MMRs, after UART is configured to the required
baud rate. To configure the UART for use with LIN requires the
use of the following UART MMRs:
>1tBIT
8tBIT
2tBIT
2tBIT
STA S0
BREAK
Under software control, it is possible to multiplex the UART data
lines (TxD and RxD) to the external GPIO_7/IRQ4 and
GPIO_8/IRQ5 pins. For more information, see the GPIO Port1
Control Register (GP1CON) section.
S1
S2
2tBIT
S3
S4
2tBIT
S5
S6
S7 STO
SYNC
PROTECTED ID
07474-044
> = 14tBIT
13tBIT
In addition, transmitting data on the LIN bus requires that the
relevant data be placed into COMTX, and reading data received
on the LIN bus requires the monitoring of COMRX. To ensure
that data is received or transmitted correctly, COMSTA0 should
be monitored. For more information, see the UART Serial
Interface and UART Register Definitions sections.
Figure 47. LIN Interface Timing
tBREAK > 13tBIT
BREAK
DELIMIT
07474-045
START
BIT
Figure 48. LIN Break Field
START
BIT
STOP
BIT
07474-046
tBIT
Figure 49. LIN Sync Byte Field
tBIT
START
BIT
ID0
ID1
ID2
ID3
ID4
ID5
P0
P1
STOP
BIT
07474-047
•
COMDIV0: divisor latch (low byte).
COMDIV1: divisor latch (high byte).
COMDIV2: 16-bit fractional baud divide register. The
required values for COMDIV0, COMDIV1, and COMDIV2
are derived from the LHSVAL0, to generate the required
baud rate.
COMCON0: line control register. As soon as the UART is
correctly configured, the LIN protocol for receiving and
transmitting data is identical to the UART specification.
BIT6
BIT7
STOP
BIT
07474-048
•
•
•
Figure 50. LIN Identifier Byte Field
tBIT
START
BIT
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
Figure 51. LIN Data Byte Field
Rev. C | Page 121 of 132
ADuC7036
Example LIN Hardware Synchronization Routine
falling edges of the sync byte. When this number of falling edges is
received, a stop condition interrupt is generated. It is at this point
that the UART is configured to receive the protected identifier.
Using the following C-source code LIN initialization routine,
LHSVAL1 begins to count on the first falling edge received on
the LIN bus. If LHSVAL1 exceeds the value written to LHSVAL1,
in this case 0x3F, a break compare interrupt is generated.
The UART must be gated through LHSCON0[8] before the LIN
bus returns high. If the LIN bus returns high when UART is not
gated, UART communication errors may occur. This process is
shown in detail in Figure 52. Example code to ensure the success
of this process follows Figure 49.
On the next falling edge, LHSVAL0 begins counting. LHSVAL0
monitors the number of falling edges and compares it to the
value written to LHSCON1[7:4]. In this example, the number of
edges to monitor is six falling edges of the LIN frame, or the five
void LIN_INIT(void )
{
char HVstatus;
GP2CON = 0x110000;
LHSCON0 = 0x1;
// Enable LHS on GPIO pins
// Reset LHS interface
do{
HVDAT = 0x02; // Enable normal LIN Tx mode
HVCON = 0x08; // Write to Config0
do{
HVstatus = HVCON;
}
while(HVstatus & 0x1); // Wait until command is finished
}
while (!(HVstatus & 0x4)); // Transmit command is correct
while((LHSSTA & 0x20) == 0 )
{
// Wait until the LHS hardware is reset
}
LHSCON1 = 0x062;
//
//
//
//
//
//
//
//
//
//
//
LHSCON0 = 0x0114;
LHSVAL1 = 0x03F;
LHSVAL1
RESETS AND
STARTS
COUNTING
LHSVAL0 STARTS
BREAK
COUNTING
COMPARE
INTERRUPT IS
GENERATED
Sets stop edge as the fifth falling edge
and the start edge as the first falling
edge in the sync byte
Gates UART Rx line, ensuring no interference
from the LIN into the UART
Selects the stop condition as a falling edge
Enables generation of an interrupt on the
stop condition
Enables the interface
Sets number of 131 kHz periods to generate a break interrupt
0x3F / 131 kHz ~ 480 μs, which is just over 9.5 Tbits
LHSVAL0 STOPS
COUNTING AND A
STOP INTERRUPT
IS GENERATED
UART IS CONFIGURED,
BEGINS
LHS INTERRUPTS
RECEIVING DATA
DISABLED EXCEPT
VIA UART
BREAK COMPARE
tBIT
STOP
BIT
START ID0
BIT
ID1
ID2
ID3
ID4
ID5
P0
P1
STOP
BIT
07474-049
START
BIT
LHSVAL1 = 0x3F
Figure 52. Example LIN Configuration
while((GP2DAT & 0x10 ) == 0 )
{}
// Wait until LIN Bus returns high
LHSCON0 = 0x4;
// Enable LHS to detect Break Condition Ungate RX Line
// Disable all Interrupts except Break Compare Interrupt
IRQEN = 0x800;
// Enable UART Interrupt
// The UART is now configured and ready to be used for LIN
Rev. C | Page 122 of 132
ADuC7036
LIN Diagnostics
The ADuC7036 features the capability to nonintrusively monitor
the current state of the LIN/BSD pin. This readback
functionality is implemented using GPIO_11. The current state
of the LIN/BSD pin is contained in GP2DAT[4].
It is also possible to drive the LIN/BSD pin high and low
through user software, allowing the user to detect open-circuit
conditions. This functionality is implemented via GPIO_12. To
enable this functionality, GPIO_12 must be configured as a
GPIO through GP2CON[20]. After it is configured, the
LIN/BSD pin can be pulled high or low using GP2DAT.
The ADuC7036 also features short-circuit protection on the
LIN/BSD pin. If a short-circuit condition is detected on the
LIN/BSD pin, HVSTA[2] is set. This bit is cleared by reenabling
the LIN driver using HVCFG1[3]. It is possible to disable this
feature through HVCFG1[2].
LIN Operation During Thermal Shutdown
When a thermal event occurs, that is, when HVSTA[3] is set,
LIN communications continue uninterrupted.
Rev. C | Page 123 of 132
ADuC7036
BIT SERIAL DEVICE (BSD) INTERFACE
BSD is a pulse-width-modulated signal with three possible states:
sync, 0, and 1. These are detailed, along with their associated
tolerances, in Table 95. The frame length is 19 bits, and communication occurs at 1200 bps ± 3%.
BSD COMMUNICATION HARDWARE INTERFACE
The ADuC7036 emulates the BSD communication protocol
using a GPIO, an IRQ, and the LIN synchronization hardware,
all of which are under software control.
Table 95. BSD Bit Level Description
Min
1164
Typ
1200
Max
1236
Unit
bps
1/16
5/16
10/16
2/16
6/16
12/16
3/16
8/16
14/16
tPERIOD
tPERIOD
tPERIOD
LHS
INTERRUPT
LOGIC
LHS INTERRUPT
IRQEN[7]
ADuC7036
LHS
HARDWARE
5MHz
LHSVAL0
131kHz
LHSVAL1
FOUR LIN
INTERRUPT
SOURCES
BREAK LHSSTA[0]
START LHSSTA[1]
STOP LHSSTA[2]
BREAK
ERROR LHSSTA[4]
VDD
VDD
LIN ENABLE
(INTERNAL
PULL-UP)
HVCFG0[5]
INPUT
VOLTAGE
THRESHOLD
REFERENCE
RxD ENABLE
LHSCON0[8]
MASTER ECU
PROTECTION
DIODE
EXTERNAL
LIN PIN
RxD
ADuC7036
UART
GPIO_12
GP2DAT[29]
AND
GPSDAT[21]
MASTER ECU
PULL-UP
CLOAD
LIN MODE
HVCFG0[1:0]
OVERVOLTAGE
PROTECTION
SCR
TxD
GPIO_12
FUNCTION
SELECT
GP2CON[20]
OUTPUT
DISABLE
BPF
INTERNAL
SHORT-CIRCUIT
SENSE
RESISTOR
SHORT-CIRCUIT
CONTROL
HVCFG1[2]
INTERNAL
SHORT-CIRCUIT
TRIP REFERENCE
Figure 53. BSD I/O Hardware Interface
Rev. C | Page 124 of 132
IO_VSS
07474-050
Parameter
TxD Rate
Bit Encoding
tSYNC
t0
t1
ADuC7036
BSD RELATED MMRS
The ADuC7036 emulates the BSD communication protocol
using a software (bit bang) interface with some hardware assistance form LIN hardware synchronization logic. In effect, the
ADuC7036 BSD interface uses the following protocols:
•
•
•
An internal GPIO signal (GPIO_12) that is routed to the
external LIN/BSD pin and is controlled directly by software
to generate 0s and 1s.
When reading bits, the LIN synchronization hardware uses
LHSVAL1 to count the width of the incoming pulses so
that user code can interpret the bits as sync, 0, or 1.
When writing bits, user code toggles a GPIO pin and uses
the LHSCAP and LHSCMP registers to time pulse widths
and generate an interrupt when the BSD output pulse width
has reached its required width.
The ADuC7036 MMRs required for BSD communication are as
follows:
•
•
•
•
•
•
•
•
•
•
•
•
LHSSTA: LIN hardware synchronization status register
LHSCON0: LIN hardware synchronization control register
LHSVAL0: LIN hardware synchronization Timer0
(16-bit timer)
LHSCON1: LIN hardware synchronization edge setup
register
LHSVAL1: LIN hardware synchronization break timer
LHSCAP: LIN hardware synchronization capture register
LHSCMP: LIN hardware synchronization compare register
IRQEN/IRQCLR: enable interrupt register
FIQEN/FIQCLR: enable fast interrupt register
GP2DAT: GPIO Port 2 data register
GP2SET: GPIO Port 2 set register
GP2CLR: GPIO Port 2 clear register
Detailed bit definitions for most of these MMRs have been
listed previously. In addition to the registers described in the
LIN MMR Description section, LHSCAP and LHSCMP are
registers that are required for the operation of the BSD
interface. Details of these registers follow.
LIN Hardware Synchronization Capture Register
Name: LHSCAP
Address: 0xFFFF0794
Default Value: 0x0000
Access: Read only
Function: This 16-bit, read only register holds the last captured
value of the internal LIN synchronization timer (LHSVAL0). In
BSD mode, LHSVAL0 is clocked directly from an internal
5 MHz clock, and its value is loaded into the capture register on
every falling edge of the BSD bus.
LIN Hardware Synchronization Compare Register
Name: LHSCMP
Address: 0xFFFF0798
Default Value: 0x0000
Access: Read/write
Function: This register is used to time BSD output pulse widths.
When enabled through LHSCON0[5], a LIN interrupt is generated
when the value in LHSCAP equals the value written in LHSCMP.
This functionality allows user code to determine how long a BSD
transmission bit (sync, 0, or 1) should be asserted on the bus.
Rev. C | Page 125 of 132
ADuC7036
To transfer data between a master and slave, or vice versa, the
construction of a BSD frame is required. A BSD frame contains
seven key components: pause/sync, a direction (DIR) bit, the
slave address, the register address, data, parity bits (P1 and P2),
and the acknowledge bit from the slave.
If the master is transmitting data, all bits except the acknowledge
bit are transmitted by the master.
If the master is transmitting data, the signal is held low for the
duration of the signal by the master. An example of a master
transmitting a 0 is shown in Figure 55. If the slave is
transmitting data, the master pulls the bus low to begin
communication. The slave must pull the bus low before tSYNC
elapses and then hold the bus low until either t0 or t1 has elapsed,
after which time the bus is released by the slave. An example of a
slave transmitting a 0 is shown in Figure 56.
If the master is requesting data from the slave, the master transmits
the pause/sync, direction bit, slave address, register address, and
P1. The slave then transmits the data bytes, the P2 bit, and the
acknowledge bit in the following sequence:
8.
t0
t1
Figure 54. BSD Bit Transmission
BUS PULLED LOW
BY MASTER
tSYNC
t0
Figure 55. BSD Master Transmitting a 0
BUS PULLED LOW
BY MASTER
tSYNC
The acknowledge bit is always transmitted by the slave to
indicate whether the information was received or transmitted.
Pause
3 bits
DIR
1 bit
Register
Address
4 bits
t0
BUS RELEASED BY
SLAVE AFTER t0
BUS HELD LOW
BY SLAVE
RELEASED BY
MASTER
Figure 56. BSD Slave Transmitting a 0
Typical BSD Program Flow
Table 96. BSD Protocol Description
Slave
Address
3 bits
BUS RELEASED BY
MASTER AFTER t0
07474-052
3.
4.
5.
6.
7.
Pause: ≥ three synchronization pulses
DIR: signifies the direction of data transfer
DIR = 0 if master sends request
DIR = 1 if slave sends request
Slave address
Register address: defines register to be read or written
Bit 3 is set to write and cleared to read
Data: 8-bit read only receive register
P1 and P2
P1 = 0 if even number of 1s in eight previous bits
P1 = 1 if odd number of 1s in eight previous bits
P2 = 0 if even number of 1s in data-word
P2 = 1 if odd number of 1s in data-word
Acknowledge bit
ACK = 0 if transmission is successful
07474-053
1.
2.
tSYNC
07474-051
BSD COMMUNICATION FRAME
P1
1 bit
Data
8 bits
P2
1 bit
ACK
1 bit
BSD Example Pulse Widths
An example of the different pulse widths is shown in Figure 54.
For each bit, the period for which the bus is held low defines
what type of bit it is. If the bit is a sync bit, the pulse is held low
for one bit. If the bit is 0, the pulse is held low for three bits. If
the bit is 1, the pulse is held low for six bits.
Because BSD is a PWM communication protocol controlled by
software, the user must construct the required data from each bit.
For example, in constructing the slave address, the slave node
receives the three bits and the user constructs the relevant address.
When BSD communication is initiated by the master, data is
transmitted and received by the slave node. A flowchart showing
this process is shown in Figure 57.
Rev. C | Page 126 of 132
ADuC7036
BSD DATA TRANSMISSION
INITIALIZE BSD
HARDWARE/
SOFTWARE
User code forces the GPIO_12 signal low for a specified time to
transmit data in BSD mode. In addition, user code uses the sync
timer (LHSVAL0), the LHS sync capture register (LHSCAP), and
the LHS sync compare register (LHSCMP) to determine the
length of time that the BSD bus should be held low for bit
transmissions in the 0 or 1 state.
RECEIVE
SYNCHRONIZATION
PULSES
RECEIVE
DIRECTION
BIT
As described in the BSD Example Pulse Widths section, even
when the slave is transmitting, the master always starts the bit
transmission period by pulling the BSD bus low. If BSD mode
is selected (LHSCON0[6] = 1), the LIN sync timer value is
captured in LHSCAP on every falling edge of the BSD bus.
The LIN sync timer runs continuously in BSD mode.
RECEIVE
SLAVE
ADDRESS
RECEIVE
REGISTER
ADDRESS
Then, user code can immediately force GPIO_12 low and read
the captured timer value from LHSCAP. Next, the user can calculate how many clock periods (with a 5 MHz clock) should elapse
before the GPIO_12 is driven high for a pulse width in the 0 or
1 state. The calcaulated number can be added to the LHSCAP
value and written into the LHSCMP register. If LHSCON0[5] is
set, the sync timer, which continues to count (being clocked by
a 5 MHz clock), eventually equals the LHSCMP value and
generates an LHS compare interrupt (LHSSTA[3]).
RECEIVE FIRST
PARITY BIT
RECEIVE SECOND
PARITY BIT
TRANSMIT SECOND
PARITY BIT
TRANSMIT
ACK/NACK
The response to this interrupt should be to force the GPIO_12
signal (and, therefore, the BSD bus) high. The software control
of the GPIO_12 signal, along with the correct use of the LIN
synchronization timers, ensures that valid pulse widths in the
0 and 1 states can be transmitted from the ADuC7036, as shown
in Figure 59. Again, care must be taken if switching from BSD
write mode to BSD read mode, as described in Table 93 (see the
LHSCON0[8] bit.)
Figure 57. BSD Slave Node State Machine
2 LHSVAL0 LOADED
INTO LHSCAP HERE
BSD DATA RECEPTION
To receive data, the LIN/BSD peripheral must first be configured in BSD mode where LHSCON0[6] = 1. In this mode,
LHSCON0[8] should be set to ensure that the LHS break timer
(see the LIN Hardware Synchronization Break Timer1 Register
section) generates an interrupt on the rising edge of the BSD bus.
BSD PERIOD
IN 0 STATE
2 LHSVAL1 STOPPED
AND GENERATES
INTERRUPT ON THIS EDGE
BSD PERIOD
IN 1 STATE
BSD PERIOD
IN 0 STATE
BSD PERIOD
IN 1 STATE
Figure 59. Master Read, Slave Transmit
WAKE-UP FROM BSD INTERFACE
The MCU core can be awakened from power-down via the BSD
physical interface. Before entering power-down mode, user code
should enable the start condition interrupt (LHSCON0[3]). When
this interrupt is enabled, a high-to-low transition on the LIN/BSD
pin generates an interrupt event and wakes up the MCU core.
07474-055
1 LHSVAL1 CLEARED
AND STARTS COUNTING
ON THIS EDGE
3 SOFTWARE ASSERTS
BSD LOW HERE
1 MASTER DRIVES
BSD BUS LOW
The LHS break timer is cleared and starts counting on the falling
edge of the BSD bus; the timer is subsequently stopped and
generates an interrupt on the rising edge of the BSD bus. Given
that the LHS break timer is clocked by the low power 131 kHz
oscillator, the value in LHSVAL1 can be interpreted by user code
to determine if the received data bit is a BSD sync pulse, 0, or 1.
4 LHSCMP = LHSVAL0
INTERRUPT GENERATED
HERE
5 SOFTWARE DEASSERTS
BSD HIGH HERE
07474-056
TRANSMIT DATA
TO MASTER
07474-054
RECEIVE DATA
FROM MASTER
Figure 58. Master Transmit, Slave Read
Rev. C | Page 127 of 132
ADuC7036
PART IDENTIFICATION
Two registers mapped into the MMR space are intended to
allow user code to identify and trace manufacturing lot ID
information, part ID number, silicon mask revision, and kernel
revision. This information is contained in the SYSSER0 and
SYSSER1 MMR (see Table 98 and Table 99 for more information).
The information contained in SYSSER0, SYSSER1, SYSALI, and
T1LD allows full traceability of each part.
In addition, the FEE0ADR MMR contains information at
power-up that can identify the ADuC7036 family member.
Table 97. Branding Example
For direct traceability, the assembly lot ID, which can be 64 bits
long, is also available. The SYSALI MMR contains the 32-bit
lower half of the assembly lot ID, and the upper half is contained
in the T1LD MMR at power-up.
The lot number is part of the branding on the package as shown
in Table 97.
Line
Line 1
Line 2
Line 3
Line 4
LFCSP
ADuC7036
BCPZ
A40 # date code
Assembly lot number
System Serial ID Register 0
Name: SYSSER0
Address: 0xFFFF0238
Default Value: 0x00000000 (updated by kernel at power-on)
Access: Read/write
Function: At power-on, this 32-bit register holds the value of the original manufacturing lot number from which this specific ADuC7036
unit was manufactured (bottom die only). Used in conjunction with SYSSER1, this lot number allows the full manufacturing history of
this part to be traced (bottom die only).
Table 98. SYSSER0 MMR Bit Designations
Bit
31 to 27
26 to 22
21 to 16
15 to 0
Description
Wafer number. The five bits read from this location give the wafer number (1 to 24) from the wafer fabrication lot ID (from which
this device originated). When used in conjunction with SYSSER0[26:0], it provides individual wafer traceability.
Wafer lot fabrication plant. The five bits read from this location reflect the manufacturing plant associated with this wafer lot.
When this information is used in conjunction with SYSSER0[21:0], it provides wafer lot traceability.
Wafer lot fabrication ID. The six bits read from this location form part of the wafer lot fabrication ID and, when used in
conjunction with SYSSER0[26:22] and SYSSER0[15:0], provide wafer lot traceability.
Wafer lot fabrication ID. These 16 LSBs hold a 16-bit number to be interpreted as the wafer fabrication lot ID number. When
used in conjunction with the value in SYSSER1, that is, the manufacturing lot ID, this number is a unique identifier for the part.
Rev. C | Page 128 of 132
ADuC7036
System Serial ID Register 1
Name: SYSSER1
Address: 0xFFFF023C
Default Value: 0x00000000 (updated by kernel at power-on)
Access: Read/write
Function: At power-on, this 32-bit register holds the values of the part ID number, silicon mask revision number, and kernel revision
number (bottom die only), as detailed in Table 99.
Table 99. SYSSER1 MMR Bit Designations
Bit
31 to 28
27 to 20
19 to 16
15 to 0
Description
Silicon mask revision ID. The four bits read from this nibble reflect the silicon mask ID number. Specifically, the hexadecimal
value in this nibble should be decoded as the lower nibble, reflecting the ASCII characters in the range of A to O. For example,
if Bits[19:16] = 0001 = 0x1, this value should be interpreted as 41, which is ASCII Character A corresponding to Silicon Mask
Revision A. If Bits[19:16] = 1011 = 0xB, the number is interpreted as 4B, which is ASCII Character K, corresponding to Silicon
Mask Revision K. The allowable range for this value is 1 to 15, which is interpreted as 41 to 4F or ASCII Character A to
Character O.
Kernel revision ID. This byte contains the hexadecimal number, which should be interpreted as an ASCII character indicating
the revision of the kernel firmware embedded in the on-chip Flash/EE memory. For example, reading 0x41 from this byte
should be interpreted as A, indicating a Revision A kernel is on chip.
Reserved. For prerelease samples, these bits refer to the kernel minor revision number of the device.
Part ID. These 16 LSBs hold a 16-bit number that is interpreted as the part ID number. When used in conjunction with the
value in SYSSER0 (that is, the manufacturing lot ID), this number is a unique identifier for the part.
System Assembly Lot ID
System Kernel Checksum
Name: SYSALI
Name: SYSCHK
Address: 0xFFFF0560
Address: 0xFFFF0240
Default Value: 0x00000000 (updated by kernel at power-on)
Default Value: 0x00000000 (updated by kernel at power-on)
Access: Read/write
Access: Read/write
Function: At power-on, this 32-bit register holds the lower half
of the assembly lot ID. For example, the assembly lot ID is
01308640, SYSALI contains 0x38363430, and T1LD contains
0x30313330 at power-on.
Function: At power-on, this 32-bit register holds the kernel
checksum.
Rev. C | Page 129 of 132
ADuC7036
System Identification FEE0ADR
Name: FEE0ADR
Address: 0xFFFF0E10
Default Value: Nonzero
Access: Read/write
Function: This 16-bit register dictates the address upon which any Flash/EE command executed via FEE0CON acts.
Note that this MMR is also used to identify the ADuC7036 family member and prerelease silicon revision.
Table 100. FEE0ADR System Identification MMR Bit Designations
Bit
15 to 4
3 to 0
Description
Reserved
ADuC703x family ID
0x2 = ADuC7032
0x3 = ADuC7033
0x4 = ADuC7034
0x6 = ADuC7036BCPZ and ADuC7036CCPZ
0x100 = ADuC7036DCPZ
Others = reserved for future use
Rev. C | Page 130 of 132
ADuC7036
SCHEMATIC
This example schematic represents a basic functional circuit implementation. Additional components need to be added to ensure that the
system meets any EMC and other overvoltage/overcurrent compliance requirements.
JTAG ADAPTOR
VBAT
10Ω
13
VBAT
42
VDD
10
12
TDO
TMS
6
11
7
TCK NTRST
TDI
REG_DVDD
RESET
10µF
LIN MASTER
1
27.4Ω
IN+
19
220pF
ADuC7036
SHUNT
20
33µH
LIN/BSD 48
IIN+
IIN–
BATTERY GROUND
TERMINAL
REG_DVDD 33
2.2µF
0.1µF
REG_AVDD
18
VTEMP
REG_AVDD 24
NTC
0.47µF
10nF
GND_SW
AGND AGND DGND DGND DGND IO_VSS VSS
22
21
8
34
35
Figure 60. Simplified Schematic
Rev. C | Page 131 of 132
47
44
07474-057
15
ADuC7036
OUTLINE DIMENSIONS
7.00
BSC SQ
0.60 MAX
37
36
PIN 1
INDICATOR
0.50 BSC
1
5.25
5.10 SQ
4.95
(BOTTOM VIEW)
25
24
13
12
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATOR
EXPOSED
PAD
6.75
BSC SQ
0.50
0.40
0.30
12° MAX
48
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
080108-A
TOP
VIEW
1.00
0.85
0.80
0.30
0.23
0.18
0.60 MAX
Figure 61. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADuC7036BCPZ
ADuC7036BCPZ-RL
ADuC7036CCPZ
ADuC7036CCPZ-RL
ADuC7036DCPZ
ADuC7036DCPZ-RL
EVAL-ADuC7036QSPZ
1
Temperature
Range
−40°C to +115°C
−40°C to +115°C
−40°C to +115°C
−40°C to +115°C
−40°C to +115°C
−40°C to +115°C
Package Description
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Z = RoHS Compliant Part.
©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07474-0-4/10(B)
Rev. C | Page 132 of 132
Model
Information
10 MHz
10 MHz
20 MHz
20 MHz
20 MHz
20 MHz
10 MHz
Package
Option
CP-48-1
CP-48-1
CP-48-1
CP-48-1
CP-48-1
CP-48-1