Cypress CY7C1483V33-150AC 2m x 36/4m x 18/1m x 72 flow-through sram Datasheet

CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
Logic Block Diagrams
CY7C1481V33 – 2M x 36
MODE
(A[1;0]) 2
BURST Q0
CE COUNTER
Q1
CLR
CLK
ADV
ADSC
ADSP
Q
A[20:0]
21
GW
19
DQd, DPd
BYTEWRITE
REGISTERS
DQc, DPc
BYTEWRITE
REGISTERS
Q
D
DQb, DPb
BYTEWRITE
REGISTERS
Q
D
DQa, DPa
BYTEWRITE
REGISTERS
Q
D
BWE
BW d
D
BWc
BWb
BWa
CE1
CE2
CE3
19
ADDRESS
CE REGISTER
D
D
ENABLE CE
REGISTER
21
2M X36
MEMORY
ARRAY
Q
36
36
Q
D ENABLE DELAY Q
REGISTER
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQa,b,c,d
DPa,b,c,d
CY7C1483V33 – 4M X 18
MODE
(A[1;0]) 2
BURST Q0
CE COUNTER
Q1
CLR
CLK
ADV
ADSC
ADSP
A[21:0]
GW
Q
22
BWE
BW b
20
DQb, DPb
BYTEWRITE
REGISTERS
DQa, DPa
BYTEWRITE
REGISTERS
Q
D
ENABLE CE
CE REGISTER
Q
D
D
BWa
CE1
CE2
CE3
ADDRESS
CE REGISTER
D
20
22
4M X 18
MEMORY
ARRAY
Q
18
D ENABLE DELAY Q
REGISTER
18
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQa,b
DPa,b
Document #: 38-05284 Rev. *A
Page 2 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
Logic Block Diagrams (continued)
CY7C1487V33 – 1M x72
MODE
(A[1;0]) 2
BURST Q0
CE COUNTER
Q1
CLR
CLK
ADV
ADSC
ADSP
A[19:0]
GW
Q
20
18
DQh, DPh
BYTEWRITE
REGISTERS
DQg, DPg
BYTEWRITE
REGISTERS
Q
D
DQf, DPf
BYTEWRITE
REGISTERS
Q
D
DQe, DPe
BYTEWRITE
REGISTERS
Q
D
DQd, DPd
BYTEWRITE
REGISTERS
DQc, DPc
BYTEWRITE
REGISTERS
Q
D
DQb, DPb
BYTEWRITE
REGISTERS
Q
D
DQa, DPa
BYTEWRITE
REGISTERS
Q
D
BWE
BW h
ADDRESS
CE REGISTER
D
D
BWg
BWf
BWe
BW d
D
BWc
BWb
BWa
20
18
1M X72
MEMORY
ARRAY
Q
Q
72
CE1
CE2
CE3
D
ENABLE CE
REGISTER
72
Q
D ENABLE DELAY Q
REGISTER
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQa,b,c,d,e,f,g,h
DPa,b,c,d,e,f,g,h
.
Selection Guide
CY7C1481V33-150 CY7C1481V33-133 CY7C1481V33-117 CY7C1481V33-100
CY7C1483V33-150 CY7C1483V33-133 CY7C1483V33-117 CY7C1483V33-100
CY7C1487V33-150 CY7C1487V33-133 CY7C1487V33-117 CY7C1487V33-100
Maximum Access Time
Unit
5.5
6.5
7.5
8.5
ns
Maximum Operating Current
TBD
TBD
TBD
TBD
mA
Maximum CMOS Standby
Current
TBD
TBD
TBD
TBD
mA
Document #: 38-05284 Rev. *A
Page 3 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-pin TQFP
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1483V33
(4M x 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document #: 38-05284 Rev. *A
A
NC
NC
VDDQ
VSSQ
NC
DPa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
A
VSS
VDD
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPb NC
NC
DQb
NC
DQb
VDDQ VDDQ
VSSQ VSSQ
NC
DQb
NC
DQb
DQb DQb
DQb
DQb
VSSQ VSSQ
VDDQ VDDQ
DQb DQb
DQb DQb
NC
VSS
VDD
NC
NC
VDD
VSS
ZZ
DQa DQb
DQa DQb
VDDQ VDDQ
VSSQ VSSQ
DQa DQb
DQa DQb
DQa DPb
NC
DQa
VSSQ VSSQ
VDDQ VDDQ
NC
DQa
NC
DQa
DQPa NC
MODE
A
A
A
A
A1
A0
CY7C1481V33
(2M X 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
A
A
VSS
VDD
A
A
A
A
A
A
A
A
A
DQPc
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DQPd
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Pin Configurations
Page 4 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
Pin Configurations (continued)
1
2
CY7C1481V33 (2M x 36)
3
4
5
A
VDDQ
B
C
NC
NC
D
E
DQc
DQc
A
DQPc
DQc
VSS
VSS
F
VDDQ
DQc
VSS
A
A
DQc
DQc
VDD
DQd
DQd
A
A
VDD
A
VSS
A
DQPb
CE1
VSS
BWc
VSS
NC
OE
ADV
GW
VDD
VSS
BWb
VSS
DQb
DQb
VSS
BWd
CLK
NC
NC
VDDQ
K
DQd
L
M
VDDQ
DQd
DQd
DQd
VSS
VSS
BWE
N
A1
DQPd
VSS
A0
DQd
7
VDDQ
ADSP
ADSC
A
A
A
G
H
J
DQc
DQc
6
A
A
NC
VSS
NC
NC
DQb
DQb
DQb
VDD
VDDQ
DQb
DQb
VDDQ
DQa
DQa
DQb
DQa
DQa
VSS
DQa
VSS
DQa
VDDQ
DQa
VSS
DQPa
DQa
BWa
P
DQd
R
NC
T
NC
A
A
MODE
A
VDD
A
NC
A
A
A
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
CY7C1483V33 (4M x 18)
1
2
3
4
5
6
7
A
VDDQ
A
ADSP
ADSC
A
A
A
A
VDDQ
NC
NC
A
A
A
B
A
DQPa
NC
DQa
C
D
A
VDD
VSS
VSS
NC
A
VSS
CE1
VSS
VSS
NC
OE
ADV
GW
VDD
E
NC
A
NC
DQb
F
VDDQ
NC
VSS
G
H
J
NC
DQb
BWb
VSS
VDDQ
K
NC
L
M
DQb
DQb
NC
VDD
DQb
NC
VSS
VSS
CLK
NC
BWa
VDDQ
BWE
DQb
DQb
NC
VSS
N
VSS
A1
A0
VDD
DQb
P
NC
DQPb
VSS
R
NC
T
A
A
A
MODE
A
U
VDDQ
TMS
TDI
Document #: 38-05284 Rev. *A
NC
NC
NC
DQa
DQa
VDD
VDDQ
DQa
NC
VDDQ
NC
DQa
DQa
NC
VSS
NC
VSS
DQa
VDDQ
NC
VSS
NC
DQa
NC
A
A
A
A
NC
ZZ
TCK
TDO
NC
VDDQ
VSS
VSS
NC
VSS
NC
Page 5 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
Pin Configurations (continued)
165-Ball Bump FBGA
(This package is offered on opportunity basis)
CY7C1481V33 (2M x 36) – 11 x 15 FBGA
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE1
BWc
BWb
CE3
BWE
ADSC
ADV
A
NC
B
C
D
E
F
G
H
J
K
L
M
N
P
NC
DPc
A
NC
CE2
VDDQ
BWd
VSS
BWa
VSS
CLK
VSS
GW
VSS
OE
VSS
ADSP
VDDQ
A
NC
144M
DPb
DQb
R
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
NC
DQd
VSS
DQd
NC
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
NC
VDDQ
NC
DQa
ZZ
DQa
DQd
DQd
DQd
DQd
VDDQ
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDDQ
VDDQ
DQa
DQa
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DPd
NC
VDDQ
VSS
NC
A
VSS
VSS
VDDQ
NC
DPa
NC
A
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
11
CY7C1483V33 (4M x 18) – 11 x 15 FBGA
1
2
3
4
5
6
7
8
9
10
A
NC
A
CE1
BWb
NC
CE3
BWE
ADSC
ADV
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC
NC
A
NC
CE2
VDDQ
NC
VSS
BWa
VSS
CLK
VSS
GW
VSS
OE
VSS
ADSP
VDDQ
A
NC
144M
DPa
NC
DQa
DQa
R
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VSS
NC
NC
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
NC
VDDQ
NC
DQa
ZZ
NC
DQb
DQb
NC
NC
VDDQ
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDDQ
VDDQ
DQa
DQa
NC
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DPb
NC
VDDQ
VSS
NC
A
VSS
VSS
VDDQ
NC
NC
NC
A
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
Document #: 38-05284 Rev. *A
Page 6 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
Pin Configurations (continued)
209-ball BGA (This package is offered on opportunity basis)
CY7C1487V33 (1M x72)
1
2
3
4
5
6
A
DQg
DQg
B
DQg
DQg
BWSc
C
DQg
DQg
BWSh
D
DQg
DQg
VSS
NC
NC
OE
E
DPg
DPc
VDDQ
VDDQ
VDD
VDD
DQc
VSS
VSS
VSS
VDDQ
VDDQ
VDD
VSS
A
CE2
7
8
9
10
11
CE3
A
DQb
DQb
ADSP ADSC
ADV
BWSg
NC
BW
A
BWSb
BWSf
DQb
DQb
BWSd
NC
CE1
NC
BWSe
BWSa
DQb
DQb
GW
NC
VSS
DQb
DQb
VDD
VDDQ
VDDQ
DPf
DPb
NC
VSS
VSS
VSS
DQf
NC
VDD
VDDQ
VDDQ
DQf
DQf
NC
VSS
VSS
VSSQ
DQf
DQf
F
DQc
G
DQc
H
DQc
DQc
VSS
VSS
J
DQc
DQc
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQf
DQf
K
NC
NC
CLK
NC
VSS
VSS
VSS
NC
NC
NC
NC
L
DQh
DQh
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQa
DQa
M
DQh
DQh
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQa
DQa
N
DQh
DQh
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQa
DQa
P
DQh
DQh
VSS
VSS
VSS
ZZ
VSS
VSS
VSS
DQa
DQa
DPh
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
NC
MODE
NC
NC
VSS
DQe
DQe
R
DPd
DQc
DPa
DQf
DPe
T
DQd
DQd
VSS
NC
U
DQd
DQd
A
A
A
A
A
A
A
DQe
DQe
V
DQd
DQd
A
A
A
A1
A
A
A
DQe
DQe
W
DQd
DQd
TMS
TDI
A
A0
A
TDO
TCK
DQe
DQe
Pin Definitions
I/O
Pin Description
A0
A1
A
Pin Name
InputSynchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0]
feed the two-bit counter.
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW
InputSynchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d,e,f,g,h and
BWE).
BWE
InputSynchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
Document #: 38-05284 Rev. *A
Page 7 of 30
PRELIMINARY
CY7C1481V33
CY7C1483V33
CY7C1487V33
Pin Definitions (continued)
I/O
Pin Description
CLK
Pin Name
InputClock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device.(TQFP Only)
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device.(TQFP Only)
OE
InputAsynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
ADV
InputSynchronous
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
ADSP
InputSynchronous
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW,
A is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is
deasserted HIGH.
ADSC
InputSynchronous
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW,
A[x:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When
ADSP and ADSC are both asserted, only ADSP is recognized.
MODE
InputStatic
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or
left floating selects interleaved burst sequence. This is a strap pin and should remain static
during device operation.
ZZ
InputAsynchronous
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved.
DQa, DPa
DQb, DPb
DQc, DPc
DQd, DPd
DQe, DPe
DQf, DPf
DQg, DPg
DQh, DPh
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx
and DPx are placed in a three-state condition. DQ a,b,c,d,e,f,g and h are 8 bits wide. DP
a,b,c,d,e,f,g and h are 1 bit wide.
TDO
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA Only)
Synchronous
TDI
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.(BGA Only)
Synchronous
TMS
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous
(BGA Only)
TCK
JTAG serial clock Serial clock to the JTAG circuit. (BGA Only)
VDD
VSS
VDDQ
Power Supply
Ground
Power supply inputs to the core of the device. Should be connected to 3.3V –5% +5% power
supply.
Ground for the core of the device. Should be connected to ground of the system.
I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 2.375V(min.) to VDD(max.)
VSSQ
I/O Ground
144M
–
NC. This pin is reserved for expansion to 144Mb.
NC
–
No connects.
Document #: 38-05284 Rev. *A
Ground for the I/O circuitry. Should be connected to ground of the system.
Page 8 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
precaution, DQx are automatically three-stated whenever a
write cycle is detected, regardless of the state of OE.
Functional Description
Single Read Accesses
Single Write Accesses Initiated by ADSC
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip enable (CE1, CE2, CE3 on TQFP, CE1 on BGA) asserted
active, and (3) the write signals (GW, BWE) are all deasserted
HIGH. ADSP is ignored if CE1 is HIGH. The address presented
to the address inputs is stored into the address advancement
logic and the Address Register while being presented to the
memory core. If the OE input is asserted LOW, the requested
data will be available at the data outputs a maximum to tCDV
after clock rise. ADSP is ignored if CE1 is HIGH.
ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) Chip Enable (CE1, CE2, CE3 on TQFP,
CE1 on BGA) asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWx) are asserted
active to conduct a write to the desired byte(s). ADSC is
ignored if ADSP is active LOW.
The address presented to A[17:0] is loaded into the address
register and the address advancement logic while being
delivered to the RAM core. The ADV input is ignored during
this cycle. If a global write is conducted, the data presented to
the DQx is written into the corresponding address location in
the RAM core. If a byte write is conducted, only the selected
bytes are written. Bytes not selected during a byte write
operation will remain unaltered. All I/Os are three-stated
during a byte write because the CY7C1481V33/
CY7C1483V33/CY7C1487V33 is a common I/O device, the
Output Enable (OE) must be deasserted HIGH before
presenting data to the DQx inputs. Doing so will three-state the
output drivers. As a safety precaution, DQx are automatically
three-stated whenever a write cycle is detected, regardless of
the state of OE.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
Chip Enable asserted active. The address presented is loaded
into the address register and the address advancement logic
while being delivered to the RAM core. The write signals (GW,
BWE, and BWx) and ADV inputs are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched
and
written
into
the
device.
The
CY7C1481V33/CY7C1483V33/CY7C1487V33 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the Byte Write Enable input (BWE) with the
selected Byte Write (BWa,b,c,d,e,f,g,h for CY7C1487V33,
BWa,b,c,d for CY7C1481V33 and BWa,b for CY7C1483V33)
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered.
All I/Os are three-stated during a byte write.
Burst Sequences
The CY7C1481V33/CY7C1483V33/CY7C1487V33 provides
a two-bit wraparound counter, fed by A[1:0], that implements
either an interleaved or linear burst sequence. to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Because the CY7C1481V33/CY7C1483V33/CY7C1487V33
is a common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQx inputs.
Doing so will three-state the output drivers. As a safety
Cycle Descriptions
Next Cycle
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
[1, 2, 3, 4]
Add. Used
ZZ
CE3
CE2
CE1
ADSP
ADSC
ADV
OE
DQ
Write
Unselected
None
0
X
X
1
X
0
X
X
Hi-Z
X
Unselected
None
0
1
X
0
0
X
X
X
Hi-Z
X
Unselected
None
0
X
0
0
0
X
X
X
Hi-Z
X
Unselected
None
0
1
X
0
1
0
X
X
Hi-Z
X
Unselected
None
0
X
0
0
1
0
X
X
Hi-Z
X
Begin Read
External
0
0
1
0
0
X
X
X
Hi-Z
X
Begin Read
External
0
0
1
0
1
0
X
X
Hi-Z
Read
Continue Read
Next
0
X
X
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
0
X
X
X
1
1
0
0
DQ
Read
Continue Read
Next
0
X
X
1
X
1
0
1
Hi-Z
Read
Continue Read
Next
0
X
X
1
X
1
0
0
DQ
Read
Suspend Read
Current
0
X
X
X
1
1
1
1
Hi-Z
Read
Notes:
1. X = “Don't Care.” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has a single chip select CE1.
Document #: 38-05284 Rev. *A
Page 9 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
Cycle Descriptions (continued)[1, 2, 3, 4]
Next Cycle
Add. Used
ZZ
CE3
CE2
CE1
ADSP
ADSC
ADV
OE
DQ
Write
Suspend Read
Current
0
X
X
X
1
1
1
0
DQ
Read
Suspend Read
Current
0
X
X
1
X
1
1
1
Hi-Z
Read
Suspend Read
Current
0
X
X
1
X
1
1
0
DQ
Read
Begin Write
Current
0
X
X
X
1
1
1
X
Hi-Z
Write
Begin Write
Current
0
X
X
1
X
1
1
X
Hi-Z
Write
Begin Write
External
0
0
1
0
1
0
X
X
Hi-Z
Continue Write
Next
0
X
X
X
1
1
0
X
Hi-Z
Write
Write
Continue Write
Next
0
X
X
1
X
1
0
X
Hi-Z
Write
Suspend Write
Current
0
X
X
X
1
1
1
X
Hi-Z
Write
Suspend Write
Current
0
X
X
1
X
1
1
X
Hi-Z
Write
ZZ “sleep”
None
1
X
X
X
X
X
X
X
Hi-Z
X
Sleep Mode
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
Description
Test Conditions
Max.
Unit
Snooze mode
standby current
ZZ > VDD – 0.2V
TBD
mA
Device operation to
ZZ
ZZ > VDD – 0.2V
2tCYC
ns
ZZ recovery time
ZZ < 0.2V
Document #: 38-05284 Rev. *A
Min.
2tCYC
ns
Page 10 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
Write Cycle Descriptions[1, 2]
Function (CY7C1481V33)
GW
BWE
BWd
BWc
BWb
BWa
Read
1
1
X
X
X
X
Read
1
0
1
1
1
1
Write Byte 0 – DQa
1
0
1
1
1
0
Write Byte 1 – DQb
1
0
1
1
0
1
Write Bytes 1, 0
1
0
1
1
0
0
Write Byte 2 – DQc
1
0
1
0
1
1
Write Bytes 2, 0
1
0
1
0
1
0
Write Bytes 2, 1
1
0
1
0
0
1
Write Bytes 2, 1, 0
1
0
1
0
0
0
Write Byte 3 – DQd
1
0
0
1
1
1
Write Bytes 3, 0
1
0
0
1
1
0
Write Bytes 3, 1
1
0
0
1
0
1
Write Bytes 3, 1, 0
1
0
0
1
0
0
Write Bytes 3, 2
1
0
0
0
1
1
Write Bytes 3, 2, 0
1
0
0
0
1
0
Write Bytes 3, 2, 1
1
0
0
0
0
1
Write All Bytes
1
0
0
0
0
0
Write All Bytes
0
X
X
X
X
X
GW
BWE
BWb
BWa
Read
1
1
X
X
Read
1
0
1
1
Write Byte 0 – DQ[7:0] and DP0
1
0
1
0
Write Byte 1 – DQ[15:8] and DP1
1
0
0
1
Write All Bytes
1
0
0
0
Write All Bytes
0
X
X
X
Function (CY7C1483V33)
Function (CY7C1487V33)[5]
GW
BWE
BWx
Read
1
1
X
Read
1
0
All BW = 1
Write Byte X
1
0
0
Write All Bytes
1
0
All BW = 0
Write All Bytes
0
X
X
Note:
5. BWx represents any byte write signal BW[0..7]. To enable any byte write BWx, a low logic signal should be applied at clock rise. Any number of byte writes
can be enabled at the same time for any given write.
Document #: 38-05284 Rev. *A
Page 11 of 30
PRELIMINARY
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1483V33/CY7C1481V33/CY7C1487V33 incorporates a serial boundary scan Test Access Port (TAP) in the
BGA package only. The TQFP package does not offer this
functionality. This port operates in accordance with IEEE
Standard 1149.1-1900, but does not have the set of functions
required for full 1149.1 compliance. These functions from the
IEEE specification are excluded because their inclusion
places an added delay in the critical speed path of the SRAM.
Note that the TAP controller functions in a manner that does
not conflict with the operation of other devices using 1149.1
fully compliant TAPs. The TAP operates using JEDEC
standard 3.3V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Test Access Port (TAP) – Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a High-Z state.
Document #: 38-05284 Rev. *A
CY7C1481V33
CY7C1483V33
CY7C1487V33
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 70-bit-long
register, and the x18 configuration has a 51-bit-long register.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
Page 12 of 30
PRELIMINARY
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller
cannot be used to load address, data, or control signals into
the SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the TAP controller, and
therefore this device is not compliant to the 1149.1 standard.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
CY7C1481V33
CY7C1483V33
CY7C1487V33
When the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
Bypass
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant.
Document #: 38-05284 Rev. *A
Page 13 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
TAP Controller State Diagram
1[6]
TEST-LOGIC
RESET
0
TEST-LOGIC/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
0
SHIFT-DR
0
SHIFT-IR
1
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
Note:
6. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05284 Rev. *A
Page 14 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
1
0
1
0
Selection
Circuitry
TDO
Instruction Register
31 30
29
.
.
2
Identification Register
.
.
.
.
.
2
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics Over the Operating Range[7, 8]
Parameter
Description
Test Conditions
Min.
VOH1
Output HIGH Voltage
IOH = −4.0 mA
2.4
VOH2
Output HIGH Voltage
IOH = −100 µA
3.0
VOL1
Output LOW Voltage
IOL = 8.0 mA
VOL2
Output LOW Voltage
IOL = 100 µA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input Load Current
GND ≤ VI ≤ VDDQ
TAP AC Switching Characteristics Over the Operating Range
Parameter
Description
Max.
Unit
V
V
0.4
V
0.2
V
1.8
VDD + 0.3
V
−0.5
0.8
V
−5
5
µA
[9, 10]
Min.
Max
100
Unit
tTCYC
TCK Clock Cycle Time
ns
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH
40
ns
tTL
TCK Clock LOW
40
ns
10
MHz
Notes:
7. All Voltage referenced to Ground.
8. Overshoot: VIH(AC)<VDD+1.5V for t<tTCYC/2, Undershoot: VIL(AC)<0.5V for t<tTCYC/2, Power-up: VIH<2.6V and VDD<2.4V and VDDQ<1.4V for t<200 ms.
9. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document #: 38-05284 Rev. *A
Page 15 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range (continued)[9, 10]
Parameter
Description
Min.
Max
Unit
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
10
ns
tTDIS
TDI Set-up to TCK Clock Rise
10
ns
tCS
Capture Set-up to TCK Rise
10
ns
tTMSH
TMS Hold after TCK Clock Rise
10
ns
tTDIH
TDI Hold after Clock Rise
10
ns
tCH
Capture Hold after Clock Rise
10
ns
Hold Times
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
20
0
ns
ns
TAP Timing and Test Conditions
1.25V
50Ω
ALL INPUT PULSES
TDO
Vih
Z0 = 50Ω
CL = 20 pF
0V
(a)
tTH
GND
tTL
Test Clock
TCK
tTC YC
tTMSS
tTMSH
Test Mode Select
TMS
t TDIS
t TDIH
Test Data-In
TDI
Test Data-Out
TDO
tTD OV
Document #: 38-05284 Rev. *A
tTDOX
Page 16 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
Identification Register Definitions
Instruction Field
x 18
x36
x72
Description
Revision Number (31:29)
000
000
000
Reserved for version number
Department Number (27:25)
101
101
101
Department number
Voltage (28&24)
00
00
00
Architecture (23:21)
000
000
000
Architecture type
Memory Type (20:18)
001
001
001
Defines type of memory
Device Width (17:15)
010
100
110
Defines width of the SRAM. x36 or x18
100
100
100
Defines the density of the SRAM
Device Density (14:12)
Cypress JEDEC ID (11:1)
0000011 0000011 0000011 Allows unique identification of SRAM vendor
0100
0100
0100
ID Register Presence (0)
1
1
1
Indicate the presence of an ID register
Scan Register Sizes
Register Name
Bit Size (x18)
Bit Size (x36)
Bit Size (x72)
Instruction
3
3
3
Bypass
1
1
1
ID
Boundary Scan
32
32
32
TBD
TBD
TBD
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and
TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100
Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO.
Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function
and is therefore not 1149.1 compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
Boundary Scan Order (2M x 36)
Bit #
Signal
Name
Bump
ID
Bit #
Signal
Name
Boundary Scan Order (2M x 36) (continued)
Bump
ID
Bit #
Signal
Name
Bump
ID
Bit #
Signal
Name
Bump
ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
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Document #: 38-05284 Rev. *A
Page 17 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
Boundary Scan Order (2M x 36) (continued)
Bit #
Signal
Name
Bump
ID
Bit #
Signal
Name
Bump
ID
Boundary Scan Order (4M x 18) (continued)
Bit #
Signal
Name
Bump
ID
Bit #
Signal
Name
Bump
ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
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Boundary Scan Order (4M x 18)
Bit #
Signal
Name
Bump
ID
Bit #
Signal
Name
Bump
ID
TBD
TBD
TBD
TBD
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TBD
Document #: 38-05284 Rev. *A
Page 18 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Range
DC Voltage Applied to Outputs
in High-Z State[12] ............................... –0.5V to VDDQ + 0.5V
Com’l
Ambient
Temperature[11]
0°C to +70°C
DC Input Voltage[12] ............................ –0.5V to VDDQ + 0.5V
VDD
VDDQ
3.3V + 5%/
–5%
2.375V (min.)
VDD(max.)
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
VDD
Power Supply Voltage
3.135
3.465
V
VDDQ
I/O Supply Voltage
2.375
VDD
V
VOH
Output HIGH Voltage
VOL
VIH
VIL
IX
Output LOW Voltage
VDD = Min., IOH = –4.0 mA
3.3V
2.4
V
VDD = Min., IOH = –1.0 mA
2.5V
2.0
V
VDD = Min., IOL = 8.0 mA
3.3V
0.4
V
VDD = Min., IOL = 1.0 mA
2.5V
0.4
V
Input HIGH Voltage
Input LOW
Voltage[12]
Input Load Current
3.3V
2.0
V
2.5V
1.7
V
3.3V
–0.3
0.8
V
2.5V
–0.3
0.7
V
GND < VI < VDDQ
Input Current of MODE
5
µA
30
µA
Input Current of ZZ
Input = VSS
30
µA
IOZ
Output Leakage Current
GND < VI < VDDQ, Output Disabled
5
µA
IDD
VDD Operating Supply
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
150 MHz
TBD
mA
133 MHz
TBD
mA
ISB1
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN > VIH or VIN < VIL
f = fMAX = 1/tCYC
ISB2
Automatic CE
Power-down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN < 0.3V or VIN > VDDQ –
0.3V,
f=0
ISB3
Automatic CE
Power-down
Current—CMOS Inputs
Max. VDD, Device Deselected,
or VIN < 0.3V or VIN > VDDQ –
0.3V
f = fMAX = 1/tCYC
ISB4
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN > VIH or VIN < VIL, f = 0
117 MHz
TBD
mA
100 MHz
TBD
mA
150 MHz
TBD
mA
133 MHz
TBD
mA
117 MHz
TBD
mA
100 MHz
TBD
mA
All speed grades
TBD
mA
150 MHz
TBD
mA
133 MHz
TBD
mA
117 MHz
TBD
mA
100 MHz
TBD
mA
All speed grades
TBD
mA
Shaded area contains advance information.
Notes:
11. TA is the ambient temperature.
12. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.
Document #: 38-05284 Rev. *A
Page 19 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
Capacitance[14]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
Test Conditions
Max.
Unit
TBD
pF
TBD
pF
TBD
pF
TA = 25°C, f = 1 MHz,
VDD = VDDQ = 3.3V
AC Test Loads and Waveforms
R = 317Ω
VDDQ
OUTPUT
ALL INPUT PULSES
OUTPUT
Z0 = 50Ω
RL = 50Ω
Vdd
R = 351Ω
VL = 1.5 for 3.3V VDDQ
= 1.25 for 2.5V VDDQ INCLUDING
JIG AND
SCOPE
(a)
90%
10%
90%
10%
5 pF
[13]
GND
Rise Time:
2 V/ns
Fall Time:
2 V/ns
(c)
(b)
Thermal Resistance[14]
Parameter
Description
Test Conditions
QJA
Thermal Resistance
(Junction to Ambient)
QJC
Thermal Resistance
(Junction to Case)
Still Air, soldered on a 4.25 x 1.125 inch,
4-layer printed circuit board
BGA Typ.
TQFP Typ.
Unit
TBD
TBD
°C/W
TBD
TBD
°C/W
Switching Characteristics Over the Operating Range
-150
Parameter
Description
Min.
-133
Max.
Min.
-117
Max.
Min.
-100
Max.
Min.
Max.
Unit
Clock
tCYC
Clock Cycle Time
6.7
7.5
FMAX
Maximum Operating Frequency
tCH
Clock HIGH
2.5
2.5
2.8
3.0
ns
tCL
Clock LOW
2.5
2.5
2.8
3.0
ns
150
8.5
133
10
117
ns
100
MHz
Output Times
tCDV
Data Output Valid After CLK Rise
5.5
6.5
7.5
8.5
ns
tEOV
OE LOW to Output Valid[14, 16, 18]
2.5
3.0
3.4
3.8
ns
tDOH
Data Output Hold After CLK Rise
tCHZ
Clock to High-Z[14, 15, 16, 17, 18]
tCLZ
Clock to
Low-Z[14, 15, 16, 17, 18]
tEOHZ
OE HIGH to Output High-Z[15, 16, 18]
tEOLZ
OE LOW to Output
Low-Z[15, 16, 18]
2.5
2.5
3.5
2.5
2.5
3.8
3.0
2.5
2.5
4.0
3.0
3.0
ns
4.5
3.0
3.5
ns
ns
4
ns
0
0
0
0
ns
1.5
1.5
1.5
1.5
ns
Set-up Times
tAS
Address Set-up Before CLK Rise
Shaded areas contain advance information.
Notes:
13. Input waveform should have a slew rate of > 2 V/ns.
14. Tested initially and after any design or process change that may affect these parameters.
15. Unless otherwise noted, test conditions assume signal transition time of 1.5ns, timing reference levels of 1.75V, input pulse levels of 0 to 3.3V, and output
loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
16. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
17. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
Document #: 38-05284 Rev. *A
Page 20 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)
-150
Parameter
Description
Min.
Max.
-133
Min.
Max.
-117
Min.
Max.
-100
Min.
Max.
Unit
tDS
Data Input Set-up Before CLK Rise
1.5
1.5
1.5
1.5
ns
tADS
ADSP, ADSC Set-up Before CLK Rise
1.5
1.5
1.5
1.5
ns
tWES
BWE, GW, BWx Set-up Before CLK
Rise
1.5
1.5
1.5
1.5
ns
tADVS
ADV Set-up Before CLK Rise
1.5
1.5
1.5
1.5
ns
tCES
Chip Select Set-up
1.5
1.5
1.5
1.5
ns
tAH
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tWEH
BWE, GW, BWx Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tADVH
ADV Hold after CLK Rise
0.5
0.5
0.5
0.5
ns
tCEH
Chip Select Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
Hold Times
Document #: 38-05284 Rev. *A
Page 21 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
Switching Waveforms
Write Cycle Timing[19,20]
Single Write
Burst Write
Pipelined Write
tCH
Unselected
tCYC
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADH
tADS
ADSC initiated write
ADSC
tADVH
tADVS
ADV
tAS
ADD
ADV Must Be Inactive for ADSP Write
WD1
WD3
WD2
tAH
GW
tWS
tWH
WE
tCES
tWH
tWS
tCEH
CE1 masks ADSP
CE1
tCES
tCEH
Unselected with CE2
CE2
CE3
tCES
tCEH
OE
tDH
tDS
Data In
High-Z
1a
1a
2a
= UNDEFINED
2b
2c
2d
3a
High-Z
= DON’T CARE
Notes:
19. WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Descriptions table).
20. WDx stands for Write Data to Address X.
Document #: 38-05284 Rev. *A
Page 22 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
Switching Waveforms (continued)
Read Cycle Timing[19, 21]
Burst Read
Single Read
tCYC
Unselected
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC initiated read
ADSC
tADVS
tADH
Suspend Burst
ADV
tADVH
tAS
ADD
RD1
RD3
RD2
tAH
GW
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
tCES
OE
Data Out
tCEH
tEOV
tCDV
tOEHZ
tDOH
2a
1a
1a
2b
2c 2c
2d
3a
tCLZ
tCHZ
= DON’T CARE
= UNDEFINED
Note:
21. RDx stands for Read Data from Address X.
Document #: 38-05284 Rev. *A
Page 23 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
Switching Waveforms (continued)
Read/Write Timing
tCYC
tCH
tCL
CLK
tAH
tAS
ADD
A
B
D
C
tADH
tADS
ADSP
tADH
tADS
ADSC
tADVH
tADVS
ADV
tCEH
tCES
CE1
tCEH
tCES
CE
tWEH
tWES
WE
ADSP ignored
with CE1 HIGH
OE
tEOHZ
tCLZ
Data
Q(A)
In/Out
Q(B)
Q
(B+1)
Q
(B+2)
Q
(B+3)
Q(B)
D(C)
D
(C+1)
D
(C+2)
D
(C+3)
Q(D)
tCDV
tDOH
tCHZ
Device originally
deselected
WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Description table).
CE is the combination of CE2 and CE3. All chip selects need to be active in order to select
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
= DON’T CARE
= UNDEFINED
Notes:
22. Device originally deselected.
23. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device.
Document #: 38-05284 Rev. *A
Page 24 of 30
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
Switching Waveforms (continued)
OE Timing
OE
tEOV
tEOHZ
Three-state
I/Os
tEOLZ
Ordering Information
Speed
(MHz)
150
133
117
100
Ordering Code
CY7C1481V33-150AC
CY7C1483V33-150AC
Package
Name
Package Type
Operating
Range
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
CY7C1481V33-150BGC
CY7C1483V33-150BGC
BG119
CY7C1481V33-150BZC
CY7C1483V33-150BZC
BB165C
CY7C1487V33-150BGC
BG209
CY7C1481V33-133AC
CY7C1483V33-133AC
A101
CY7C1481V33-133BGC
CY7C1483V33-133BGC
BG119
CY7C1481V33-133BZC
CY7C1483V33-133BZC
BB165C
CY7C1487V33-133BGC
BG209
CY7C1481V33-117AC
CY7C1483V33-117AC
A101
CY7C1481V33-117BGC
CY7C1483V33-117BGC
BG119
CY7C1481V33-117BZC
CY7C1483V33-117BZC
BB165C
CY7C1487V33-117BGC
BG209
CY7C1481V33-100AC
CY7C1483V33-100AC
A101
CY7C1481V33-100BGC
CY7C1483V33-100BGC
BG119
CY7C1481V33-100BZC
CY7C1483V33-100BZC
BB165C
CY7C1487V33-100BGC
BG209
Document #: 38-05284 Rev. *A
119-Ball BGA (14 x 22 x 2.4 mm)
165-Ball FBGA (15 x 17 mm)
209-Ball BGA (14 x 22 x 2.2mm)
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Ball BGA (14 x 22 x 2.4 mm)
165-Ball FBGA (15 x 17 mm)
209-Ball BGA (14 x 22 x 2.2mm)
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Ball BGA (14 x 22 x 2.4 mm)
165-Ball FBGA (15 x 17 mm)
209-Ball BGA (14 x 22 x 2.2mm)
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Ball BGA (14 x 22 x 2.4 mm)
165-Ball FBGA (15 x 17 mm)
209-Ball BGA (14 x 22 x 2.2mm)
Page 25 of 30
PRELIMINARY
CY7C1481V33
CY7C1483V33
CY7C1487V33
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05284 Rev. *A
Page 26 of 30
PRELIMINARY
CY7C1481V33
CY7C1483V33
CY7C1487V33
Package Diagrams (continued)
165-Ball FBGA (15 x 17 x 1.20 mm) BB165C
51-85165-**
Document #: 38-05284 Rev. *A
Page 27 of 30
PRELIMINARY
CY7C1481V33
CY7C1483V33
CY7C1487V33
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05284 Rev. *A
Page 28 of 30
PRELIMINARY
CY7C1481V33
CY7C1483V33
CY7C1487V33
Package Diagrams (continued)
209-Lead PBGA (14 x 22 x 2.20 mm) BG209
51-85143-*B
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05284 Rev. *A
Page 29 of 30
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1481V33
CY7C1483V33
CY7C1487V33
PRELIMINARY
Document History Page
Document Title: CY7C1481V33/CY7C1483V33/CY7C1487V33 2M x 36/4M x 18/1M x 72 Flow-through SRAM
Document Number: 38-05284
REV.
ECN NO.
Issue
Date
**
114671
08/12/02
PKS
New Data Sheet
*A
118283
01/27/03
HGK
Updated Ordering Information
Updated the features for package offering
Changed from Advance Information to Preliminary
Document #: 38-05284 Rev. *A
Orig. of
Change
Description of Change
Page 30 of 30
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