Holtek HT36B2 8-bit music synthesizer mcu Datasheet

HT36B2
8-Bit Music Synthesizer MCU
Features
· Operating voltage: 3.6V~5.0V
· Independent pan and volume mix can be assigned to
each sound component
· Operating frequency: 3.58MHz~12MHz
· Sampling rate of 44.1kHz as 11.059MHz for system
(Typ. 11.059MHz)
frequency
· 32 bidirectional I/O lines
· Eight-level subroutine nesting
· Two 16-bit programmable timer/event counters with
· HALT function and wake-up feature reduce power
overflow interrupts
consumption
· Watchdog Timer
· Bit manipulation instructions
· Built-in 8-bit MCU with 576´8 bits RAM
· 16-bit table read instructions
· Built-in 128K´16-bit ROM for program/data shared
· 63 powerful instructions
· Two High D/A converter resolution: 16 bits
· All instructions in 1 or 2 machine cycles
· Polyphonic up to 16 notes
· 28-pin SOP, 56-pin SSOP package
General Description
The HT36B2 has a built-in 8-bit microprocessor which
programs the synthesizer to generate the melody by
setting the special register from 20H~2AH. A HALT feature is provided to reduce power consumption.
The HT36B2 is an 8-bit high performance RISC architecture microcontroller specifically designed for various
music applications. It provides an 8-bit MCU and a 16
channel wavetable synthesizer. The program ROM
which can be easily programmed is composed of both
program control codes and wavetable voice codes.
Block Diagram
P A
P B
P C
P D
0 ~
0 ~
0 ~
0 ~
P A
P B
P C
P D
IN
O S C
O S C
R E S
Rev. 1.10
7
7
7
V D
V S
V D
V S
1 2 8 K ´ 1 6 - b it
R O M
7
8 - B it
M C U
T
1
2
5 7 6 ´ 8
R A M
M u ltip lie r /P h a s e
G e n e ra l
1
S te re o
1 6 - B it
D A C
D
S
D A
S A
R C H
L C H
March 10, 2005
HT36B2
Pin Assignment
1
5 6
V S S
R E S
2
5 5
O S C 1
O S C 2
P C 7
3
5 4
P C 6
4
5 3
V S S A
P C 5
5
5 2
V D D A
P C 4
6
5 1
L C H
P C 3
7
5 0
R C H
P C 2
8
4 9
P D 0
N C
9
4 8
P D 1
N C
1 0
4 7
P D 2
N C
1 1
4 6
P D 3
N C
1 2
4 5
P D 4
N C
1 3
4 4
P D 5
N C
1 4
4 3
P D 6
V S S
1
2 8
O S C 1
N C
1 5
4 2
P D 7
V D D
2
2 7
O S C 2
N C
1 6
4 1
N C
R E S
3
2 6
V S S A
N C
1 7
4 0
N C
P C 4
4
2 5
V D D A
N C
1 8
3 9
N C
P C 3
5
2 4
L C H
N C
1 9
3 8
IN T
P C 2
6
2 3
R C H
P C 1
2 0
3 7
P A 0
N C
7
2 2
P D 0
P C 0
2 1
3 6
P A 1
P C 1
8
2 1
P D 1
P B 7
2 2
3 5
P A 2
P B 2
9
2 0
IN T
P B 6
2 3
3 4
P A 3
P B 1
1 0
1 9
P A 0
P B 5
2 4
3 3
P A 4
P B 0
1 1
1 8
P A 1
P B 4
2 5
3 2
P A 5
P A 7
1 2
1 7
P A 2
P B 3
2 6
3 1
P A 6
P A 6
1 3
1 6
P A 3
P B 2
2 7
3 0
P A 7
P A 5
1 4
1 5
P A 4
P B 1
2 8
2 9
P B 0
H T 3 6 B 2
2 8 S O P -B
Rev. 1.10
V D D
H T 3 6 B 2
5 6 S S O P -A
2
March 10, 2005
HT36B2
Pad Assignment
P C 2
P C 3
P C 4
P C 6
P C 5
P C 7
R E S
V D D
V S S
O S C 1
O S C 2
V S S A
V D D A
L C H
R C H
1
4 2
4 1
4 0
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
3 9
(0 , 0 )
1 7
1 8
1 9
2 0
IN T
1 6
P A 1
P A 5
1 5
P A 0
1 4
P A 3
1 3
P A 2
1 2
P A 4
1 1
P A 7
1 0
P A 6
9
P B 1
8
P B 0
7
P B 2
P B 3
6
P B 5
5
P B 4
P C 1
P C 0
4
P B 7
3
P B 6
2
2 8
P D 0
2 7
P D 1
2 6
P D 2
2 5
P D 3
2 4
P D 4
2 3
P D 5
2 2
P D 6
2 1
P D 7
Chip size: 2975 ´ 3550 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.10
3
March 10, 2005
HT36B2
Pad Coordinates
Unit: mm
Pad No.
X
Y
Pad No.
X
Y
1
2
-1327.608
1607.250
22
1320.992
-146.680
-1321.808
-1607.630
23
1320.992
3
-1221.808
-1607.630
24
1320.992
-46.680
63.920
4
-1111.208
-1607.630
25
1320.992
163.920
5
-1011.208
-1607.630
26
1320.992
274.520
6
-900.608
-1607.630
27
1320.992
374.520
7
-800.608
-1607.630
28
1320.992
485.120
8
-690.008
-1607.630
29
1324.492
1571.300
9
-590.008
-1607.630
30
1211.492
1571.300
10
-479.408
-1607.630
31
1099.052
1571.300
11
-379.408
-1607.630
32
950.392
1571.300
12
-268.808
-1607.630
33
833.168
1571.200
13
-168.808
-1607.630
34
155.316
1571.200
14
-1607.630
35
34.192
1604.750
15
-58.208
41.792
-1607.630
36
-572.908
1604.750
16
152.392
-1607.630
37
-694.032
1607.250
17
252.392
-1607.630
38
-795.808
1607.250
18
362.992
-1607.630
39
-906.408
1607.250
19
462.992
-1607.630
40
-1006.408
1607.250
20
571.392
-1607.630
41
-1117.008
1607.250
21
1320.992
-257.280
42
-1217.008
1607.250
Pad Description
I/O
Internal
Connection
PA0~PA7
I/O
Pull-High
or None
Bidirectional 8-bit Input/Output port, wake-up by mask option
PB0~PB7
I/O
Pull-High
or None
Bidirectional 8-bit Input/Output port
PC0~PC7
I/O
Pull-High
or None
Bidirectional 8-bit Input/Output port
PD0~PD7
I/O
Pull-High
or None
Bidirectional 8-bit Input/Output port
INT
I
Pull-High
External interrupt
RCH
O
¾
R channel audio output
LCH
O
¾
L channel audio output
VDDA
¾
¾
DAC power supply
VSSA
¾
¾
Negative power supply of DAC, ground
OSC1
OSC2
I
O
¾
OSC1 and OSC2 are connected to an RC network or a crystal (by mask option) for the internal system clock. In the case of RC operation, OSC2 is the
output terminal for 1/8 system clock. The system clock may come from the
crystal, the two pins cannot be floating.
VSS
¾
¾
Negative power supply, ground
VDD
¾
¾
Positive power supply
RES
I
¾
Reset input, active low
Pad Name
Rev. 1.10
Function
4
March 10, 2005
HT36B2
Absolute Maximum Ratings
Supply Voltage .............................VSS-0.3V to VSS+6V
Storage Temperature ...........................-50°C to 125°C
Input Voltage .............................VSS-0.3V to VDD+0.3V
Operating Temperature ..........................-25°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Ta=25°C
Test Conditions
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
¾
¾
3.6
4.5
5.5
V
IDD
Operating Current
4.5V
No load,
fOSC=11.0592MHz
¾
16
32
mA
ISTB
Standby Current (WDT Disabled)
4.5V
No load,
System HALT
¾
1
3
mA
IOH
I/O Ports Source Current
4.5V
VOH=4.5V
5
¾
¾
mA
IOL
I/O Ports Sink Current
4.5V
VOL=0.5V
5
¾
¾
mA
VIH
Input High Voltage for I/O Ports
4.5V
¾
0.8VDD
¾
VDD
V
VIL
Input Low Voltage for I/O Ports
4.5V
¾
0
¾
0.2VDD
V
RPH
Pull-High Resistance of I/O Ports (INT)
4.5V
¾
30
¾
kW
VIL=0V
A.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
11.059MHz crystal
Min.
Typ.
Max.
Unit
¾
11.059
¾
MHz
MCU Interface
fOSC
System Frequency
5V
fSYS
System Clock
5V
¾
8
¾
12
MHz
tWDT
Watchdog Time-Out Period (RC)
¾
Without WDT prescaler
9
17
35
ms
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
Symbol
Parameter
Figure
Min.
Typ.
Max.
Unit
DAC Interface
fBC
DCK Bit Clock Frequency
Fig 1
¾
fSYS/16
¾
MHz
tCH
DCK Bit Clock H Level Time
Fig 1
600
¾
¾
ns
tDOS
Data Output Setup Time
Fig 1
200
¾
¾
ns
tDOH
Data Output Hold Time
Fig 1
200
¾
¾
ns
tLCS
Load Clock Setup Time
Fig 1
200
¾
¾
ns
tLCH
Load Clock Hold Time
Fig 1
200
¾
¾
ns
Rev. 1.10
5
March 10, 2005
HT36B2
Function Description
Execution Flow
incremented by one. The program counter then points
to the memory word containing the next instruction
code.
The system clock for the HT36B2 is derived from either
a crystal or an RC oscillator. The oscillator frequency divided by 2 is the system clock for the MCU and it is internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute in one cycle. If an instruction
changes the program counter, two cycles are required
to complete the instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to retrieve the proper instruction. Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Program Counter - PC
The 13-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are executed and its contents specify a maximum of 8192 addresses for each bank.
Once a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
S y s te m C lo c k o f M C U
( S y s te m C lo c k /2 )
T 1
T 2
T 3
T 4
T 1
T 2
P C
P C
T 3
T 4
T 1
T 2
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
T 3
T 4
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*16 *15 *14 *13 *12 *11 *10 *9
*8
*7
*6
*5
*4
*3
*2
*1
*0
PF3 PF2 PF1 PF0 0
0
0
0
0
0
0
0
0
0
0
0
0
Timer/Event Counter 0 Overflow PF3 PF2 PF1 PF0 0
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow PF3 PF2 PF1 PF0 0
0
0
0
0
0
0
0
0
1
1
0
0
Initial Reset
Skip
Program Counter+2
Loading PCL
PF3 PF2 PF1 PF0 *12 *11 *10 *9
*8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch
PF3 PF2 PF1 PF0 #12 #11 #10 #9
#8
Return From Subroutine
PF3 PF2 PF1 PF0 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
#7
#6
#5
#4
#3
#2
#1
#0
Program Counter
Note:
*12~*0: Bits of Program Counter
#12~#0: Bits of Instruction Code
@7~@0: Bits of PCL
Rev. 1.10
@7~@0: Bits of PCL
S12~S0: Bits of Stack Register
PF3~PF0: Bits of Bank Register
6
March 10, 2005
HT36B2
0 0 0 0 H
Program ROM
0 0 0 8 H
HT36B2 provides 17 address lines W A16~0 to read the
Program ROM which is up to 2M bits, and is comm only
used for the wavetable voice codes and the program
memory. It provides two address types, one type is for
program ROM, which is addressed by a bank pointer
PF3~0 and a 13-bit program counter PC 12~0; and the
other type is for wavetable code, which is addressed by
the start address ST15~0. On the program type,
WA16~0= PF3~0 ´ 213+ PC12~0. On the wavetable
ROM type, WA16~0=ST15~0 ´ 25.
0 0 0 C H
T im e r /e v e n t C o u n te r 0 in te r r u p t s u b r o u tin e
T im e r /e v e n t C o u n te r 1 in te r r u p t s u b r o u tin e
n 0 0 H
P ro g ra m
R O M
L o o k - u p ta b le ( 2 5 6 w o r d s )
n F F H
L o o k - u p ta b le ( 2 5 6 w o r d s )
1 F F F H
1 6 b its
Program Memory - ROM
N o te : n ra n g e s fro m
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
8192´16 bits, addressed by the bank pointer, program
counter and table pointer.
0 0 to 1 F .
Program Memory for Each Bank
of the lower-order byte in the table is well-defined, the
higher-order byte of the table word are transferred to
the TBLH. The Table Higher-order byte register
(TBLH) is read only. The Table Pointer (TBLP) is a
read/write register (07H), which indicates the table location. Before accessing the table, the location must
be placed in TBLP. The TBLH is read only and cannot
be restored. If the main routine and the ISR (Interrupt
Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are
likely to be changed by the table read instruction used
in the ISR. Errors can occur. In this case, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table
read instruction has to be applied in both the main routine and the ISR, the interrupt should be disabled prior
to the table read instruction. It will not be enabled until
the TBLH has been backed up. All table related instructions need two cycles to complete the operation.
These areas may function as normal program memory depending upon user requirements.
Certain locations in the program memory of each bank
are reserved for special usage:
· Location 000H on bank0
This area is reserved for the initialization program. After a chip reset, the program always begins execution
at location 000H on bank0.
· Location 008H
This area is reserved for the Timer/Event Counter 0 interrupt service program on each bank. If timer interrupt
results from a Timer/Event Counter 0 overflow, and if the
interrupt is enabled and the stack is not full, the program
begins execution at location 008H corresponding to its
bank.
· Location 00CH
This area is reserved for the Timer/Event Counter 1
interrupt service program on each bank. If a timer interrupt results from a Timer/Event Counter 1 overflow,
and if the interrupt is enabled and the stack is not full,
the program begins execution at location 00CH corresponding to its bank.
· Bank pointer
The program memory is organized into 16 banks and
each bank into 8192´16 bits of program ROM. PF3~0
is used as the ROM bank pointer. After an instruction
has been executed to write data to the PF register to
select a different bank, note that the new bank will not
be selected immediately. It is not until the following instruction has completed execution that the bank will
be actually selected.
· Table location
Any location in the ROM space can be used as
look-up tables. The instructions TABRDC[m] (the current page, 1 page=256 words) and TABRDL [m] (the
last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
Instruction(s)
D e v ic e in itia liz a tio n p r o g r a m
Table Location
*16
*15
*14
*13
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P16 P15 P14 P13 P12 P11 P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
P16 P15 P14 P13
1
1
@7
@6
@5
@4
@3
@2
@1
@0
1
1
1
Table Location
Note:
*12~*0: Table location bits
P12~P8: Current Program Counter bits
Rev. 1.10
@7~@0: Table pointer bits
P16~P13: Bits of bank PF3~PF0
7
March 10, 2005
HT36B2
Wavetable ROM
byte register (TMR1L;10H), the Timer/Event Counter 1
Control register (TMR1C;11H), the I/O registers
(PA;12H, PB;14H, PC;16H, PD;18H), the program ROM
bank select (PF;1CH)), the D/A converter (DAH;1DH,
DAL;1EH, DAC;1FH) and the I/O Control registers
(PAC;13H, PBC;15H, PCC;17H, PDC;19H). The
wavetable function register is defined between
20H~2AH. The remaining space before the 40H is reserved for future expansion usage and reading these lo-
The ST15~0 is used to defined the start address of each
sample on the wavetable and read the waveform data
from the location. HT36B2 provides 21 output address
lines from WA16~0, the ST15~0 is used to locate the
major 16 bits of 21 lines and the undefined data from
WA4~0 is always set to 00000b. So the start address of
each sample have to be located at a multiple of 32
bytes. Otherwise, the sample will not be read out correctly because it has a wrong starting code.
0 0 H
Stack Register - Stack
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge, the contents of the program counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program
counter is restored to its previous value from the stack.
After a chip reset, the SP will point to the top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge will be inhibited. When the stack pointer is
decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the
programmer to use the structure more easily. In a similar
case, if the stack is full and a CALL is subsequently executed, a stack overflow occurs and the first entry will be
lost (only the most recent eight return address are
stored).
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C
0 C H
T M R 0 H
0 D H
T M R 0 L
0 E H
T M R 0 C
0 F H
T M R 1 H
1 0 H
T M R 1 L
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
1 9 H
1 A H
P D C
S p e c ia l P u r p o s e
D a ta M e m ro y
P D
1 B H
1 C H
P F
1 D H
D A C H ig h B y te ( D A H )
Data Memory - RAM
1 E H
D A C
The data memory is designed with 3´256´8 bits. The
data memory is divided into three functional groups:
special function registers, wavetable function register,
and general purpose data memory (3´192´8). Most of
them are read/write, but some are read only.
2 0 H
C h a n n e l N u m b e r S e le c t ( C H A N )
2 1 H
F r e q u e n c y N u m b e r H ig h B y te ( F r e q N H )
2 2 H
F re q u e n c y N u m b e r L o w B y te (F re q N L )
2 3 H
S ta r t A d d r e s s H ig h B y te ( A d d r H )
The special function registers include the Indirect Addressing register 0/1 (00H/02H), the Memory Pointer
register (MP0;02H, MP1;04H), the RAM address bank
pointer (BP;01H), the 8-bit MCU accumulator
(ACC;05H), the Program Counter Lower-byte register
(PCL;06H), the Table Pointer (TBLP;07H), the Table
Higher-order byte register (TBLH;08H), the Watchdog
Timer option Setting register (WDTS;09H), the Status
register (STATUS;0AH), the Interrupt Control register
(INTC;0BH), the Timer/Event Counter 0 Higher-order
byte register (TMR0H;0CH), the Timer/Event Counter 0
Lower-order byte register (TMR0L;0DH), the
Timer/Event Counter 0 Control register (TMR0C;0EH),
the Timer/Event Counter 1 Higher-order byte register
(TMR1H;0FH), the Timer/Event Counter 1 Lower-order
Rev. 1.10
1 F H
L o w B y te (D A L )
D A C C o n tro l (D A C )
2 4 H
S ta rt A d d re s s L o w
2 5 H
R e p e a t N u m b e r H ig h B y te ( R e H )
B y te (A d d rL )
2 6 H
R e p e a t N u m b e r L o w B y te (R e L )
2 7 H
C o n tr o l R e g is te r ( E N V )
W a v e ta b le
F u n c tio n
R e g is te r
2 8 H
2 9 H
L e ft V o lu m e C o n tr o l ( L V C )
2 A H
2 B H
R ig h t V o lu m e C o n tr o l ( R V C )
: U n u s e d .
R e a d a s "0 0 "
3 F H
4 0 H
F F H
B a n k 2
B a n k 1
B a n k 0
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 9 2 ´ 3 B y te s )
RAM Mapping
8
March 10, 2005
HT36B2
cations will return the result 00H. The general purpose
data memory, addressed from 40H to FFH, is used for
data and control information under instruction command.
· Rotation (RL, RR, RLC, RRC)
All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data
memory can be set and reset by the SET [m].i and CLR
[m].i instructions, respectively. They are also indirectly
accessible through Memory pointer registers
(MP0;01H, MP1;03H) and BP.
The ALU not only saves the results of a data operation but
can also change the status register.
· Increment & Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF) and Watchdog time-out flag
(TO). It also records the status information and controls the
operation sequence.
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] access data memory pointed
to by MP0 (01H) and MP1 (03H) respectively. Reading
location 00H or 02H directly will return the result 00H.
And writing directly results in no operation.
With the exception of the TO and program counters, bits
in the status register can be altered by instructions like
any other register. Any data written into the status register will not change the TO or program counters. In addition it should be noted that operations related to the
status register may give different results from those intended. The TO and PDF flags can only be changed by
system power up, Watchdog Timer overflow, executing
the HALT instruction and clearing the Watchdog Timer.
The function of data movement between two indirect addressing registers, is not supported. The memory
pointer registers, MP0 (for bank0 only) and MP1, are
8-bit register which can be used to access the data
memory by combining corresponding indirect addressing registers.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or executing a subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
status are important and the subroutine can corrupt the
status register, the programmer must take precautions
to save it properly.
Accumulator
The accumulator closely relates to ALU operations. It is
mapped to location 05H of the data memory and it can
operate with immediate data. The data movement between two data memory locations must pass through
the accumulator.
Interrupt
The HT36B2 provides one external interrupt, and two internal timer/event counter interrupts on each bank. The
Interrupt Control register (INTC;0BH) contains the interrupt control bits that sets the enable/disable and the interrupt request flags.
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic operation.
The ALU provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation, otherwise C is cleared. It is also affected by a rotate through
carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction, otherwise AC is cleared.
2
Z
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa, otherwise OV is cleared.
4
PDF
PDF is cleared by either a system power-up or executing the CLR WDT instruction. PDF is set by
executing the HALT instruction.
5
TO
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by
a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logical operation is zero, otherwise Z is cleared.
STATUS (0AH) Register
Rev. 1.10
9
March 10, 2005
HT36B2
Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the programmer may set the EMI bit and the corresponding bit
of the INTC to allow interrupt nesting. If the stack is full,
the interrupt request will not be acknowledged, even if
the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must
be prevented from becoming full.
Interrupt Source
Priority
Vector
External interrupt
1
04H
Timer/event Counter 0 overflow
2
08H
Timer/event Counter 1 overflow
3
0CH
The Timer/Event Counter 0/1 interrupt request flag
(T0F/T1F), Enable Timer/Event Counter 0/1 bit
(ET0I/ET1I), Enable Master Interrupt bit (EMI) constitute an interrupt control register (INTC) which is located
at 0BH in the data memory. EMI, ET0I, ET1I are used to
control the enabling/disabling of interrupts. These bits
prevent the requested interrupt from being serviced.
Once the interrupt request flags (T0F, T1F) are set, they
will remain in the INTC register until the interrupts are
serviced or cleared by a software instruction.
All these kinds of interrupt have a wake-up capability. As
an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack and then
branching to subroutines at specified locations in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register and Status
register (STATUS) are altered by the interrupt service
program which may corrupt the desired control sequence, then the programmer must save the contents
first.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Because interrupts often occur in an unpredictable manner
or need to be serviced immediately in some applications, if only one stack is left and enabling the interrupt is
not well controlled, once the ²CALL subroutine² operates
in the interrupt subroutine, it may damage the original
control sequence.
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F;bit 5 of the INTC), caused by a
Timer/Event Counter 0 overflow. When the interrupt is
enabled, and the stack is not full and the T0F bit is set, a
subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit
cleared to disable further interrupts.
Oscillator Configuration
The HT36B2 provides two types of oscillator circuit for
the system clock, i.e., RC oscillator and crystal oscillator. No matter what type of oscillator, the signal divided
by 2 is used for the system clock. The HALT mode stops
the system oscillator and ignores external signal to conserve power. If the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the
range of the resistance should be from 30kW to 680kW.
The system clock, divided by 4, is available on OSC2
with pull-high resistor, which can be used to synchronize
external logic. The RC oscillator provides the most cost
effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself
due to process variations. It is therefore, not suitable for
timing sensitive operations where accurate oscillator
frequency is desired.
The Timer/Event Counter 1 interrupt is operated in the
same manner as Timer/Event Counter 0. The related interrupt control bits ET1I and T1F of the Timer/Event
Counter 1 are bit 3 and bit 6 of the INTC respectively.
External interrupt is initialized by setting the external request flag (EEI; bit 1 of the INTC), caused by a high-to
low voltage pulse from the INT pad. When the interrupt
is enabled, and the stack is not full and the EEI bit is set,
a subroutine call to location 04H will occur. The related
interrupt request flag (EIF) will be reset and the EMI bit
cleared to disable further interrupts.
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, the RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
On the other hand, if the crystal oscillator is selected, a
crystal across OSC1 and OSC2 is needed to provide the
feedback and phase shift required for the oscillator, and
no other external components are required. A resonator
may be connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but two ex-
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the priorities in the following table apply. These can be
masked by resetting the EMI bit.
O S C 1
V
O S C 2
fS
Y S
O S C 1
D D
O S C 2
/8
C r y s ta l O s c illa to r
R C
O s c illa to r
System Oscillator
Rev. 1.10
10
March 10, 2005
HT36B2
Bit No.
Label
Function
0
EMI
Controls the Master (Global) interrupt (1=enable; 0=disable)
1
EEI
Controls the external interrupt (1=enable; 0=disable)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable)
4
EIF
External interrupt (INT pad) request flag
5
T0F
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
7
¾
Unused bit, read as ²0²
INTC (0BH) Register
manner except that in the HALT state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. The
high nibble and bit 3 of the WDTS are reserved for user
defined flags, and the programmer may use these flags
to indicate some specified status.
ternal capacitors in OSC1 and OSC2 are required.
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works with a
period of approximately 78ms. The WDT oscillator can
be disabled by mask option to conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (MCU
system clock divided by 4), determined by mask options. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location
with unpredictable results. The Watchdog Timer can be
disabled by mask option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no
operation.
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
Once the internal WDT oscillator (RC oscillator with a
period of 78ms normally) is selected, it is first divided by
256 (8-stages) to get the nominal time-out period of approximately 20ms. This time-out period may vary with
temperature, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the
WDTS) can give different time-out periods. If WS2,
WS1, WS0 all equal to 1, the division ratio is up to 1:128,
and the maximum time-out period is 2.6 seconds.
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit TO. Whereas in the
HALT mode, the overflow will initialize a ²warm reset²
wherein only the program counter and SP are reset to
zero. To clear the WDT contents (including the WDT
prescaler ), three methods are implemented, namely,
external reset (a low level to RES), software instructions, or a HALT instruction. The software instructions
include CLR WDT and the other set - CLR WDT1 and
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
S y s te m
WS2
C lo c k /8
W D T
O S C
M a s k
O p tio n
S e le c t
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 1.10
11
March 10, 2005
HT36B2
CLR WDT2. Of these two types of instructions, only one
can be active depending on the mask option - ²CLR
WDT times selection option². If the ²CLR WDT² is selected (i.e. CLRWDT times equal one), any execution of
the CLR WDT instruction will clear the WDT. In case
²CLR WDT1² and ²CLR WDT2² are chosen (i.e.
CLRWDT times equal two), these two instructions must
be executed to clear the WDT, otherwise, the WDT may
reset the chip due to time-out.
after a dummy period has finished. If an interrupt request flag is set to ²1² before entering the HALT mode,
the wake-up function of the related interrupt will be disabled.
Power Down Operation - HALT
· RES reset during normal operation
To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
· RES reset during HALT
The HALT mode is initialize by a HALT instruction and
results in the following:
· WDT time-out reset during normal operation
· The system oscillator will turn off but the WDT oscilla-
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that just resets the program counter and SP, leaving
the other circuits in their original state. Some registers
remain unchanged during other reset conditions. Most
registers are reset to the ²initial condition² when the reset conditions are met. By examining the PDF and TO
flags, the program can distinguish between different
²chip resets².
tor keeps running (if the WDT oscillator is selected).
Watchdog Timer - WDT
· The contents of the on-chip RAM and registers remain
unchanged.
· The WDT and WDT prescaler will be cleared and
starts to count again (if the clock comes from the WDT
oscillator).
· All I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
V
· The HALT pin will output a high level signal to disable
D D
the external ROM.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². By examining the TO and PDF
flags, the cause for a chip reset can be determined. The
PDF flag is cleared when there is a system power-up or by
executing the CLR WDT instruction and it is set when a
HALT instruction is executed. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the program counter and SP, the others remain in their
original status.
R E S
Reset Circuit
V D D
R E S
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by mask option. Awakening from an I/O port
stimulus, the program will resume execution of the next
instruction. If awakening from an interrupt, two sequences may occur. If the related interrupts is disabled
or the interrupts is enabled but the stack is full, the program will resume execution at the next instruction. If the
interrupt is enabled and the stack is not full, a regular interrupt response takes place.
S T
C h ip R e s e t
Reset Timing Chart
H A L T
W D T
W D T
W a rm
R e s e t
T im e - o u t
R e s e t
R E S
Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume to normal operation. In
other words, a dummy cycle period will be inserted after
the wake-up. If the wake-up results from an interrupt acknowledge, the actual interrupt subroutine will be delayed by one more cycle. If the wake-up results in next
instruction execution, this will be executed immediately
Rev. 1.10
tS
S S T T im e - o u t
O S C I
S S T
1 0 -s ta g e
R ip p le C o u n te r
C o ld
R e s e t
P o w e r - o n D e te c tin g
Reset Configuration
12
March 10, 2005
HT36B2
The registers status is summarized in the following table:
Reset
(Power On)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)*
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
BP
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Register
Program Counter
TBLP
0000H
0000H
0000H
0000H
0000H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
--uu uuuu
--01 uuuu
--1u uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u 1uuu
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PF
---- 0000
---- 0000
---- 0000
---- 0000
---- uuuu
DAH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
DAL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
DAC
---- -000
---- -000
---- -000
---- -000
---- -uuu
CHAN
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
FreqNH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
FreqNL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
AddrH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
AddrL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ReH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ReL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ENV
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LVC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
RVC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
²-² stands for unimplemented
Rev. 1.10
13
March 10, 2005
HT36B2
TO
PDF
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Writing TMR0L only writes the data into a low byte
buffer, and writing TMR0H will write the data and the
contents of the low byte buffer into the Timer/Event
Counter 0 Preload register (16-bit) simultaneously. The
Timer/Event Counter 0 Preload register is changed by
writing TMR0H operations and writing TMR0L will keep
the Timer/Event Counter 0 Preload register unchanged.
RESET Conditions
Reading TMR0H will also latch the TMR0L into the low
byte buffer to avoid a false timing problem. Reading
TMR0L returns the contents of the low byte buffer. In
other words, the low byte of the Timer/Event Counter 0
cannot be read directly. It must read the TMR0H first to
make the low byte contents of the Timer/Event Counter
0 latched into the buffer.
Note: ²u² stands for ²unchanged²
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses during system
power up or when the system awakes from a HALT
state.
There are three registers related to the Timer/Event
Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H).
The Timer/Event Counter 1 operates in the same manner as Timer/Event Counter 0.
When a system power-up occurs, the SST delay is
added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any
wake-up from HALT will enable the SST delay.
The TMR0C is the Timer/Event Counter 0 control register, which defines the Timer/Event Counter 0 options.
The Timer/Event Counter 1 has the same options with
Timer/Event Counter 0 and is defined by TMR1C.
The functional units chip reset status are shown below.
Program counter
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After a master reset,
WDT begins counting
The Timer/event Counter control registers define the
operating mode, counting enable or disable and active
edge.
The TM0, TM1 bits define the operating mode. The
Event count mode is used to count external events,
which means the clock source comes from an external
(TMR) pin. The Timer mode functions as a normal timer
with the clock source coming from the instruction clock.
The pulse width measurement mode can be used to
count the high or low level duration of the external signal
(TMR). The counting is based on the instruction clock.
Timer/Event Counter (0/1) Off
Input/output ports
Input mode
SP
Points to the top of the
stack
Timer/Event Counter
In the Event count or Timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFFFH. Once
overflow occurs, the counter is reloaded from the
Timer/Event Counter Preload register and simultaneously generates the corresponding interrupt request
flag (T0F/T1F; bit 5/6 of the INTC).
Two timer/event counters are implemented in the
HT36B2. The Timer/Event Counter 0 and Timer/Event
Counter 1 contain 16-bit programmable count-up counters and the clock comes from the system clock divided
by 4.
There are three registers related to Timer/Event Counter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH).
Bit No.
Label
0~2
¾
Unused bit, read as ²0²
3
TE
Defines the TMR active edge of Timer/Event Counter 0
(0=active on low to high; 1=active on high to low)
4
TON
5
¾
6
7
TM0
TM1
Function
Enable/disable timer counting (0=disable; 1=enable)
Unused bit, read as ²0²
Defines the operating mode
01=Event count mode (External clock)
10=Timer mode (Internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C/TMR1C Register
Rev. 1.10
14
March 10, 2005
HT36B2
S y s te m
D a ta B u s
C lo c k /8
T M 1
T M 0
G N D
T im e r /e v e n t C o u n te r 0
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
T im e r /e v e n t
C o u n te r 0
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
T o In te rru p t
L o w B y te
B u ffe r
Timer/Event Counter 0/1
the timer/event counter is turned on, data written to the
timer/event counter will only be kept in the timer/event
counter preload register. The timer/event counter will
still operate until overflow occurs.
In pulse width measurement mode with the TON and TE
bits equal to one, once the TMR has received a transient
from low to high (or high to low; if the TE bit is 0) it will
start counting until the TMR returns to the original level
and resets the TON. The measured result will remain in
the register even if the activated transient occurs again.
In other words, only one cycle measurements can be
done. Until setting the TON, the cycle measurement will
function again as long as it receives further transient
pulse. Note that, in this operating mode, the timer/event
counter starts counting not according to the logic level
but according to the transient edges. In the case of
counter overflows, the counter is reloaded from the
timer/event counter and the preload register issues the
interrupt request just like the other two modes.
When the timer/event counter (reading TMR0H/TMR1H)
is read, the clock will be blocked to avoid errors. As this
may results in a counting error, this must be taken into
consideration by the programmer.
The two timer counters of the HT36B2 are internal clock
mode only, so only Timer mode can be selected. Therefore the (TM1, TM0) bits can only be set to (TM1,TM0) =
(1,0), and the other clock modes are invalid.
Input/Output Ports
There are 32 bidirectional input/output lines labeled
from PA to PD, which are mapped to the data memory of
[12H], [14H], [16H], [18H] respectively. All these I/O
ports can be used for input and output operations. For
input operation, these ports are non-latching, that is, the
inputs must be ready at the T2 rising edge of instruction
MOV A,[m] (m=12H, 14H, 16H or 18H). For output operation, all data is latched and remains unchanged until
the output latch is rewritten.
To enable the counting operation, the Timer ON bit
(TON; bit 4 of the TMR0C/TMR1C) should be set to 1. In
the pulse width measurement mode, the TON will be
cleared automatically after the measurement cycle is
completed. But in the other two modes the TON can only
be reset by instruction. The overflow of the timer/ event
counter is one of the wake-up sources. No matter what
the operation mode is, writing a ²0² to ET0I/ET1I can
disable the corresponding interrupt service.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS output or Schmitt Trig-
In the case of timer/event counter OFF condition, writing
data to the Timer/event Counter Preload register will
also reload that data to the timer/event counter. But if
D a ta B u s
W r ite C o n tr o l R e g is te r
V
Q
D
C K
Q
S
V
C h ip R e s e t
P A
P B
P C
P D
Q
D
C K
S
Q
M
R e a d I/O
S y s te m
W e a k
P u ll- u p
M a s k O p tio n
R e a d C o n tr o l R e g is te r
W r ite I/O
D D
D D
U
0 ~
0 ~
0 ~
0 ~
P A
P B
P C
P D
7
7
3
7
X
W a k e - U p ( P A o n ly )
M a s k O p tio n
Input/Output Ports
Rev. 1.10
15
March 10, 2005
HT36B2
After a chip reset, these input/output lines remain at high
levels or floating (mask option). Each bit of these input/output latches can be set or cleared by the SET [m].i
or CLR [m].i (m=12H, 14H, 16H or 18H) instruction.
ger input with or without pull-high resistor (mask option)
structures can be reconfigured dynamically under software control. To function as an input, the corresponding
latch of the control register must write a ²1². The
pull-high resistance will be exhibited automatically if the
pull-high option is selected. The input source also depends on the control register. If the control register bit is
²1², input will read the pad state. If the control register bit
is ²0², the contents of the latches will move to the internal
bus. The latter is possible in ²read-modify-write² instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations
13H, 15H, 17H and 19H).
Some instructions first input data and then follow the
output operations. For example, the SET [m].i, CLR
[m].i, CPL [m] and CPLA [m] instructions read the entire
port states into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability to wake-up the device.
16 Channel Wavetable Synthesizer
Wavetable Function Memory Mapping
Special Register for Wavetable Synthesizer
RAM
B7
B6
B5
B4
B3
B2
B1
B0
20H
VM
FR
¾
¾
CH3
CH2
CH1
CH0
21H
BL3
BL2
BL1
BL0
FR11
FR10
FR9
FR8
22H
FR7
FR6
FR5
FR4
FR3
FR2
FR1
FR0
23H
ST15
ST14
ST13
ST12
ST11
ST10
ST9
ST8
24H
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
25H
WBS
RE14
RE13
RE12
RE11
RE10
RE9
RE8
26H
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
27H
A_R
¾
VL9
VL8
ENV1
ENV0
VR9
VR8
29H
VL7
VL6
VL5
VL4
VL3
VL2
VL1
VL0
2AH
VR7
VR6
VR5
VR4
VR3
VR2
VR1
VR0
Wavetable Function Register Table
Register Name
Register Function
B7
B6
20H
Channel Number Selection
20H
Change Parameter Selection
VM
FR
21H
Block Number Selection
BL3
BL2
21H
22H
23H
24H
25H
25H
26H
Frequency Number Selection
Start Address Selection
Waveform Format Selection
Repeat Number Selection
27H
Envelope Type Selection
27H
Attach and Release Selection
27H
29H
27H
2AH
Rev. 1.10
Left Volume Controller
Right Volume Controller
B5
BL1
B4
B3
B2
B1
B0
CH3
CH2
CH1
CH0
FR11
FR10
FR9
FR8
BL0
FR7
FR6
FR5
FR4
FR3
FR2
FR1
FR0
ST15
ST14
ST13
ST12
ST11
ST10
ST9
ST8
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
RE14
RE13
RE12
RE11
RE10
RE9
RE8
RE6
RE5
RE4
RE3
RE2
RE1
RE0
WBS
RE7
ENV1 ENV0
A_R
VL7
VL6
VR7
VR6
16
VL9
VL8
VL5
VL4
VR5
VR4
VL3
VR3
VL2
VR2
VL1
VL0
VR9
VR8
VR1
VR0
March 10, 2005
HT36B2
· CH3~0 channel number selection
· Waveform format definition
The HT36B2 has a built-in 16 output channels and
CH3~0 is used to define which channel is selected.
When this register is written to, the wavetable synthesizer will automatically output the dedicated PCM
code. So this register is also used as a start playing
key and it has to be written to after all the other
wavetable function registers are already defined.
The HT36B2 accepts two waveform formats to ensure
a more economical data space. WBS is used to define
the sample format of each PCM code.
¨ WBS=0 means the sample format is 8-bit
¨
The 12-bit sample format allocates location to each
sample data. Refer to the waveform format statement
as shown below.
· Change parameter selection
These two bits, VM and FR, are used to define which
register will be updated on this selected channel.
There are two modes that can be selected to reduce
the process of setting the register. Refer to the following table:
VM
FR
0
0
Update all the parameter
0
1
Only update the frequency number
1
0
Only update the volume
8 - B it
1 B
2 B
3 B
4 B
5 B
6 B
7 B
8 B
A s a m p lin g d a ta c o d e ; B m e a n s o n e d a ta b y te .
1 2 - B it
Function
1 H
1 M
1 L
2 L
2 H
2 M
3 H
3 M
3 L
A s a m p lin g d a ta c o d e
N o te : " 1 H " H ig h N ib b le
" 1 M " M id d le N ib b le
" 1 L " L o w N ib b le
Waveform Format
· Output frequency definition
The data on BL3~0 and FR11~0 are used to define
the output speed of the PCM file, i.e. it can be used to
generate the tone scale. When the FR11~0 is 800H
and BL3~0 is 6H, each sample data of the PCM code
will be sent out sequentially.
When the fOSC is 12.8MHz, the formula of a tone frequency is:
50kHz
FR11 ~ 0
fOUT= fRECORD ´
´ (17 - BL3~0)
SR
2
where fOUT is the output signal frequency, fRECORD and
SR is the frequency and sampling rate on the sample
code, respectively.
So if a voice code of C3 has been recorded which has
the fRECORD of 261Hz and the SR of 11025Hz, the tone
frequency (fOUT) of G3: fOUT=196Hz.
Can be obtained by using the formula:
50kHz
FR11 ~ 0
196Hz= 261Hz ´
´ (17 - BL3~0)
11025Hz
2
A pair of the values FR11~0 and BL3~0 can be determined when the fOSC is 12.8MHz.
· Repeat number definition
The repeat number is used to define the address
which is the repeat point of the sample. When the repeat number is defined, it will be output from the start
code to the end code once and always output the
range between the repeat address to the end code
(80H) until the volume becomes close.
The RE14~0 is used to calculate the repeat address
of the PCM code. The process for setting the RE14~0
is to write the 2¢s complement of the repeat length to
RE14~0, with the highest carry ignored. The HT36B2
will retrieve the repeat address by adding the RE14~0
to the address of the end code, then jump to the address to repeat this range.
· Left and Right volume control
The HT36B2 provides the left and right volume control
independently. The left and right volume are controlled by VL9~0 and VR9~0 respectively. The chip
provides 1024 levels of controllable volume, the 000H
is the maximum and 3FFH is the minimum output volume.
· Start address definition
The HT36B2 provides two address types for extended
use, one is the program ROM address which is program counter corresponding with PF value, the other
is the start address of the PCM code.
The ST15~0 is used to define the start address of
each PCM code and reads the waveform data from
this location. The HT36B2 provides 16 input data lines
from WA15~0, the ST15~0 is used to locate the major
16 bits i.e. WA15~5 and the undefined data from
WA4~0 is always set as 00000b. In other words, the
WA15~0=ST15~0´25. So each PCM code has to be
located at a multiple of 32. Otherwise, the PCM code
will not be read out correctly because it has a wrong
start code.
Rev. 1.10
WBS=1 means the sample format is 12-bit
· Envelope type definition
The HT36B2 provides a function to easily program the
envelope by setting the data of ENV1~0 and A_R. It
forms a vibrato effect by a change of the volume to attach and release alternately.
The A_R signal is used to define the volume change in
attach mode or release mode and ENV1~0 is used to
define which volume control bit will be changeable.
On the attach mode, the control bits will be sequentially signaled down to ²0². On the release mode, the
control bits will be sequentially signaled up to ²1². The
relationship is shown in the following table.
17
March 10, 2005
HT36B2
A_R
ENV1
ENV0
Volume Control Bit
Control Bit Final Value
0
0
0
VL2~0, VR2~0
111b
0
0
1
VL1~0, VR1~0
11b
0
1
0
VL0, VR0
1b
x
1
1
No Bit
unchanged
1
0
0
VL2~0, VR2~0
000b
1
0
1
VL1~0, VR1~0
00b
1
1
0
VL0, VR0
0b
Mode
Release mode
No change mode
Attach mode
Envelope Type Definition
· The PCM code definition
Mask Option
The HT36B2 can provide the voice format of the
signed 8-bit raw PCM. And the MCU will take the
voice code 80H as the end code.
So each PCM code section must be ended with the
end code 80H.
No.
Digital to Analog Converter (DAC)
The HT36B2 provides two 16-bit current type DAC device controlled by the MCU or wavetable synthesizer for
driving the external speaker through an external NPN
transistor. It is in fact an optional object used for the
wavetable synthesizer DAC or general DAC, this is chosen by mask option and DAC control register. If general
DAC is chosen for application, then the wavetable
synthesizer is disabled because the DAC is taken up
and controlled by the MCU. If general DAC is selected,
the programmer must write the voice data to register the
DAL and DAH to get the corresponding analog data.
Mask Option
Function
1
WDT source
On-chip RC/Instruction
clock/ disable WDT
2
CLRWDT times
One time, two times
(CLR WDT1/WDT2)
3
Wake-up
PA only
4
Pull-High
PA, PB, PC, PD input
5
OSC mode
Crystal or Resistor type
6
LVR/LVD
Low voltage detection
For mask option enable DAC register and enable
SELWL and SELWR, then the table becomes useful.
Bit No.
0
Label
Function
SELWR=1: Right channel DAC
data from wavetable
SELWR
SELWR=0: Right c0hannel DAC
data from MCU (default)
DAON=1: DAC On
DAON=0: DAC Off (default)
1
DAON
2
SELWL=1: Left channel DAC
data from wavetable
SELWL
SELWL=0: Left channel DAC
data from MCU (default)
3~7
¾
Unused bit, read as ²0²
DAC (1FH) Control Register
Rev. 1.10
18
March 10, 2005
HT36B2
Application Circuits
V
D D
V
1 0 W
4 7 m F
0 .1 m F
V D D A
4 7 m F
V D D
L C H
0 .1 m F
2
2 0 k W
P A 0 ~ P A 7
O S C 2
IN
V re f
3
1 0 m F
O S C 1
1 1 .0 5 9 M H z
D D
8
V D D
O U T N
1
H T 8 2 V 7 3 3
C E
V S S
4
5
S P K
8 W
7
O U T P
P B 0 ~ P B 7
V
P C 0 ~ P C 7
D D
P D 0 ~ P D 7
V
4 7 m F
D D
R C H
0 .1 m F
2 0 k W
1 0 0 k W
R E S
IN
V re f
3
1 0 m F
V S S A
0 .1 m F
2
V S S
8
V D D
O U T N
1
H T 8 2 V 7 3 3
C E
5
V S S
4
S P K
8 W
7
O U T P
H T 3 6 B 2
V
D D
1 0 W
4 7 m F
0 .1 m F
V D D A
V
D D
V D D
L C H
O S C 1
S P K
8 W
1 k W
7 5 0 W
P A 0 ~ P A 7
P B 0 ~ P B 7
P C 0 ~ P C 7
V
V
D D
P D 0 ~ P D 7
D D
1 0 0 k W
R C H
R E S
V S S A
0 .1 m F
S P K
8 W
1 k W
7 5 0 W
V S S
H T 3 6 B 2
Rev. 1.10
19
March 10, 2005
HT36B2
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.10
20
March 10, 2005
HT36B2
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.10
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
21
March 10, 2005
HT36B2
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
22
March 10, 2005
HT36B2
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
23
March 10, 2005
HT36B2
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
24
March 10, 2005
HT36B2
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
25
March 10, 2005
HT36B2
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
PC ¬ PC+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
PC ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
26
March 10, 2005
HT36B2
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
PC ¬ PC+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
27
March 10, 2005
HT36B2
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
PC ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
PC ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
PC ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
28
March 10, 2005
HT36B2
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
29
March 10, 2005
HT36B2
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
30
March 10, 2005
HT36B2
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
31
March 10, 2005
HT36B2
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
32
March 10, 2005
HT36B2
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
33
March 10, 2005
HT36B2
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
34
March 10, 2005
HT36B2
Package Information
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
Symbol
Rev. 1.10
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
697
¾
713
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
35
March 10, 2005
HT36B2
56-pin SSOP (300mil) Outline Dimensions
2 9
5 6
B
A
2 8
1
C
C '
G
H
D
F
E
Symbol
Rev. 1.10
a
Dimensions in mil
Min.
Nom.
Max.
A
395
¾
420
B
291
¾
299
C
8
¾
12
C¢
720
¾
730
D
89
¾
99
E
¾
25
¾
F
4
¾
10
G
25
¾
35
H
4
¾
12
a
0°
¾
8°
36
March 10, 2005
HT36B2
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13+0.5
-0.2
D
Key Slit Width
330±1
2±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
Rev. 1.10
37
March 10, 2005
HT36B2
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24±0.3
P
Cavity Pitch
12±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4±0.1
P1
Cavity to Perforation (Length Direction)
2±0.1
A0
Cavity Length
10.85±0.1
B0
Cavity Width
18.34±0.1
K0
Cavity Depth
2.97±0.1
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
Rev. 1.10
21.3
38
March 10, 2005
HT36B2
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 0755-8616-9908, 8616-9308
Fax: 0755-8616-9533
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
Holtek Semiconductor Inc. (Chengdu Sales Office)
709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 028-6653-6590
Fax: 028-6653-6591
Holmate Semiconductor, Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2005 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
39
March 10, 2005