ML145026 ML145027 ML145028 Encoder and Decoder Pairs CMOS Legacy Device: Motorola/Freescale MC145026, MC145027, MC145028 These devices are designed to be used as encoder/decoder pairs in remote control applications. The ML145026 encodes nine lines of information and serially sends this information upon receipt of a transmit enable (TE) signal. The nine lines may be encoded with trinary data (low, high, or open) or binary data (low or high). The words are transmitted twice per encoding sequence to increase security. The ML145027 decoder receives the serial stream and interprets five of the trinary digits as an address code. Thus, 243 addresses are possible. If binary data is used at the encoder, 32 addresses are possible. The remaining serial information is interpreted as four bits of binary data. The valid transmission (VT) output goes high on the ML145027 when two conditions are met. First, two addresses must be consecutively received (in one encoding sequence) which both match the local address. Second, the 4 bits of data must match the last valid data received. The active VT indicates that the information at the Data output pins has been updated. The ML145028 decoder treats all nine trinary digits as an address which allows 19,683 codes. If binary data is encoded, 512 codes are possible. The VT output goes high on the ML145028 when two addresses are consecutively received (in one encoding sequence) which both match the local address. • • • • • • • Operating Temperature Range: TA = – 40 to + 85°C Very–Low Standby Current for the Encoder: 300 nA Maximum @ 25°C Interfaces with RF, Ultrasonic, or Infrared Modulators and Demodulators RC Oscillator, No Crystal Required High External Component Tolerance; Can Use ± 5% Components Internal Power–On Reset Forces All Decoder Outputs Low Operating Voltage Range: ML145026 = 2.5 to 18 V* ML145027, ML145028 = 4.5 to 18 V • For Infrared Applications, See Application Note AN1016/D P DIP 16 = EP PLASTIC DIP CASE 648 16 1 SO 16 = -5P SOG PACKAGE CASE 751B 16 1 SO 16W = -5P SOG PACKAGE CASE 751G 16 1 CROSS REFERENCE/ORDERING INFORMATION MOTOROLA PACKAGE LANSDALE P DIP 16 MC145026P ML145026EP SO 16 MC145026D ML145026-5P P DIP 16 MC145027P ML145027EP SO 16 MC145027DW ML145027-5P P DIP 16 MC145028P ML145028EP SO 16 MC145028DW ML145028-5P Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE. PIN ASSIGNMENTS ML145026 ENCODER ML145027 DECODERS ML145028 DECODERS A1 1 16 VDD A1 1 16 VDD A1 1 16 VDD A2 2 15 Dout A2 2 15 D6 A2 2 15 A6 A3 3 14 TE A3 3 14 D7 A3 3 14 A7 A4 4 13 RTC A4 4 13 D8 A4 4 13 A8 A5 5 12 CTC A5 5 12 D9 A5 5 12 A9 A6/D6 6 11 RS R1 6 11 VT R1 6 11 VT A7/D7 7 10 A9/D9 C1 7 10 R2/C2 C1 7 10 R2/C2 VSS 8 9 A8/D8 VSS 8 9 VSS 8 9 Page 1 of 19 Din www.lansdale.com Din Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 RS RTC CTC TE 11 14 12 13 3–PIN OSCILLATOR AND ENABLE 9 15 D out RING COUNTER AND 1–OF–9 DECODER 8 7 6 5 4 3 2 1 1 A1 2 A2 3 A3 4 A4 5 A5 TRINARY DETECTOR 6 A6/D6 7 A7/D7 9 A8/D8 A9/D9 DATA SELECT AND BUFFER ÷4 DIVIDER VDD = PIN 16 VSS = PIN 8 10 Figure 1. ML145026 Encoder Block Diagram CONTROL LOGIC 15 14 LATCH 4–BIT SHIFT REGISTER 11 13 12 VT D6 D7 D8 D9 SEQUENCER CIRCUIT 5 A1 A2 A3 A4 A5 4 3 2 1 1 2 3 DATA EXTRACTOR 4 5 C1 7 6 R1 9 C2 10 Din VDD = PIN 16 VSS = PIN 8 R2 Figure 2. ML145027 Decoder Block Diagram Page 2 of 19 www.lansdale.com Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 11 CONTROL LOGIC 9 A1 1 A2 2 A3 3 A4 4 A5 5 8 7 SEQUENCER CIRCUIT 6 5 4 3 2 VT 1 9–BIT SHIFT REGISTER DATA EXTRACTOR A6 15 C1 A7 14 7 6 R1 A8 13 9 C2 10 R2 Din VDD = PIN 16 VSS = PIN 8 A9 12 Figure 3. ML145028 Decoder Block Diagram MAXIMUM RATINGS* (Voltages Referenced to VSS) Rating Symbol Value Unit VDD DC Supply Voltage – 0.5 to + 18 V VDD DC Supply Voltage – 0.5 to + 10 V Vin DC Input Voltage – 0.5 to VDD + 0.5 V Vout DC Output Voltage – 0.5 to VDD + 0.5 V DC Input Current, per Pin ± 10 mA Iout DC Output Current, per Pin ± 10 mA PD Power Dissipation, per Package 500 mW Tstg Storage Temperature – 65 to + 150 °C 260 °C Iin TL Lead Temperature, 1 mm from Case for 10 Seconds This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section. Page 3 of 19 www.lansdale.com Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 ELECTRICAL CHARACTERISTICS — ML145026 *, ML145027, and ML145028 (Voltage Referenced to VSS) Guaranteed Limit Symbol Characteristic – 40°C 25°C 85°C VDD V Min Max Min Max Min Max Unit VOL Low–Level Output Voltage (Vin = VDD or 0) 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0.05 0.05 0.05 — — — 0.05 0.05 0.05 V VOH High–Level Output Voltage (Vin = 0 or VDD) 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 — — — 4.95 9.95 14.95 — — — V (Vout = 4.5 or 0.5 V) (Vout = 9.0 or 1.0 V) (Vout = 13.5 or 1.5 V) 5.0 10 15 — — — 1.5 3.0 4.0 — — — 1.5 3.0 4.0 — — — 1.5 3.0 4.0 (Vout = 0.5 or 4.5 V) (Vout = 1.0 or 9.0 V) (Vout = 1.5 or 13.5 V) 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 — — — 3.5 7.0 11 — — — (Vout = 2.5 V) (Vout = 4.6 V) (Vout = 9.5 V) (Vout = 13.5 V) 5.0 5.0 10 15 – 2.5 – 0.52 – 1.3 – 3.6 — — — — – 2.1 – 0.44 – 1.1 – 3.0 — — — — – 1.7 – 0.36 – 0.9 – 2.4 — — — — (Vout = 0.4 V) (Vout = 0.5 V) (Vout = 1.5 V) 5.0 10 15 0.52 1.3 3.6 — — — 0.44 1.1 3.0 — — — 0.36 0.9 2.4 — — — VIL VIH IOH IOL Low–Level Input Voltage V High–Level Input Voltage V High–Level Output Current mA Low–Level Output Current mA Iin Input Current — TE (ML145026, Pull–Up Device) 5.0 10 15 — — — — — — 3.0 16 35 11 60 120 — — — — — — µA Iin Input Current RS (ML145026), D in (ML145027, ML145028) 15 — ± 0.3 — ± 0.3 — ± 1.0 µA Iin Input Current A1 – A5, A6/D6 – A9/D9 (ML145026), A1 – A5 (ML145027), A1 – A9 (ML145028) 5.0 10 15 — — — — — — — — — ± 110 ± 500 ± 1000 — — — — — — Cin Input Capacitance (Vin = 0) — — — — 7.5 — — pF IDD Quiescent Current — ML145026 5.0 10 15 — — — — — — — — — 0.1 0.2 0.3 — — — — — — µA IDD Quiescent Current — ML145027, ML145028 5.0 10 15 — — — — — — — — — 50 100 150 — — — — — — µA Idd Dynamic Supply Current — ML145026 (fc = 20 kHz) 5.0 10 15 — — — — — — — — — 200 400 600 — — — — — — µA Idd Dynamic Supply Current — ML145027, ML145028 (fc = 20 kHz) 5.0 10 15 — — — — — — — — — 400 800 1200 — — — — — — µA µA * Also see next Electrical Characteristics table for 2.5 V specifications. Page 4 of 19 www.lansdale.com Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 ELECTRICAL CHARACTERISTICS — ML145026 (Voltage Referenced to VSS) Guaranteed Limit Symbol VDD V Characteristic – 40°C 25°C Min Max 85°C Min Max Min Max Unit VOL Low–Level Output Voltage (Vin = 0 V or VDD) 2.5 — 0.05 — 0.05 — 0.05 V VOH High–Level Output Voltage (Vin = 0 V or VDD) 2.5 2.45 — 2.45 — 2.45 — V VIL Low–Level Input Voltage (Vout = 0.5 V or 2.0 V) 2.5 — 0.3 — 0.3 — 0.3 V VIH High–Level Input Voltage (Vout = 0.5 V or 2.0 V) 2.5 2.2 — 2.2 — 2.2 — V IOH High–Level Output Current (Vout = 1.25 V) 2.5 0.28 — 0.25 — 0.2 — mA IOL Low–Level Output Current (Vout = 0.4 V) 2.5 0.22 — 0.2 — 0.16 — mA Iin Input Current (TE — Pull–Up Device) 2.5 — — 0.09 1.8 — — µA Iin Input Current (A1–A5, A6/D6–A9/D9) 2.5 — — — ± 25 — — µA IDD Quiescent Current 2.5 — — — 0.05 — — µA Idd Dynamic Supply Current (fc = 20 kHz) 2.5 — — — 40 — — µA SWITCHING CHARACTERISTICS — ML145026*, ML145027, and ML145028 (CL = 50 pF, TA = 25°C) Symbol tTLH, tTHL Figure No. Characteristic Output Transition Time Guaranteed Limit VDD Min Max Unit 4,8 5.0 10 15 — — — 200 100 80 ns tr Din Rise Time — Decoders 5 5.0 10 15 — — — 15 15 15 µs tf Din Fall Time — Decoders 5 5.0 10 15 — — — 15 5.0 4.0 µs fosc Encoder Clock Frequency 6 5.0 10 15 0.001 0.001 0.001 2.0 5.0 10 MHz Decoder Frequency — Referenced to Encoder Clock 12 5.0 10 15 1.0 1.0 1.0 240 410 450 kHz TE Pulse Width — Encoders 7 5.0 10 15 65 30 20 — — — ns f tw * Also see next Switching Characteristics table for 2.5 V specifications. SWITCHING CHARACTERISTICS — ML145026 (CL = 50 pF, TA = 25°C) Symbol tTLH, tTHL fosc tw Page 5 of 19 Characteristic Guaranteed Limit Figure No. VDD Output Transition Time Min Max Unit 4, 8 2.5 — 450 ns Encoder Clock Frequency 6 2.5 1.0 250 kHz TE Pulse Width 7 2.5 1.5 — µs www.lansdale.com Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 ANY OUTPUT 90% tf 10% tr VDD 90% tTLH Din tTHL 10% Figure 4. VSS Figure 5. 1 / fosc VDD TE RTC 50% 50% VSS tw Figure 6. Figure 7. TEST POINT DEVICE UNDER TEST OUTPUT CL* * Includes all probe and fixture capacitance. Figure 8. Test Circuit Page 6 of 19 www.lansdale.com Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 OPERATING CHARACTERISTICS ML145026 The encoder serially transmits trinary data as defined by the state of the A1 – A5 and A6/D6 – A9/D9 input pins. These pins may be in either of three states (low, high, or open) allowing 19,683 possible codes. The transmit sequence is initiated by a low level on the TE input pin. Upon power–up, the ML145026 can continuously transmit as long as TE remains low (also, the device can transmit two–word sequences by pulsing TE low). However, no ML145026 application should be designed to rely upon the first data word transmitted immediately after power–up because this word may be invalid. Between the two data words, no signal is sent for three data periods (see Figure 10). Each transmitted trinary digit is encoded into pulses (see Figure 11). A logic 0 (low) is encoded as two consecutive short pulses, a logic 1 (high) as two consecutive long pulses, and an open (high impedance) as a long pulse followed by a short pulse. The input state is determined by using a weak“output” device to try to force each input high then low. If only a high state results from the two tests, the input is assumed to be hard wired to VDD. If only a low state is obtained, the input is assumed to be hardwired to VSS. If both a high and alow can be forced at an input, an open is assumed and is encoded as such. The “high” and “low” levels are 70% and 30% of the supply voltage as shown in the Electrical Characteristics table. The weak “output” device sinks/sources up to110 µA at a 5 V supply level, 500 µA at 10 V, and 1 mA at 15 V. The TE input has an internal pull–up device so that a simple switch may be used to force the input low. While TE is high and the second–word transmission has timed out, the encoder is completely disabled, the oscillator is inhibited, and the current drain is reduced to quiescent current. When TE is brought low, the oscillator is started and the transmit sequence begins. The inputs are then sequentially selected, and determinations are made as to the input logic states. This information is serially transmitted via the Dout pin. ML145027 This decoder receives the serial data from the encoder and outputs the data, if it is valid. The transmitted data, consisting of two identical words, is examined bit by bit during reception. The first five trinary digits are assumed to be the address. If the received address matches the local address, the next four (data) bits are internally stored, but are not transferred to the output data latch. As the second encoded word is received, the address must again match. If a match occurs, the new data bits are checked against the previously stored data bits. If the two nibbles of data (four bits each) match, the data is transferred to the output data latch by VT and remains until new data replaces it. At the same time, the VT output pin is brought high and remains high until an error is received or until no input signal is received for four data periods (see Figure 10). Although the address information may be encoded in trinary, the data information must be either a 1 or 0. A trinary (open) data line is decoded as a logic 1. Page 7 of 19 ML145028 This decoder operates in the same manner as the ML145027 except that nine address lines are used and no data output is available. The VT output is used to indicate that a valid address has been received. For transmission security, two identical transmitted words must be consecutively received before a VT output signal is issued. The ML145028 allows 19,683 addresses when trinary levels are used. 512 addresses are possible when binary levels are used. PIN DESCRIPTIONS ML145026 ENCODER A1 – A5, A6/D6 – A9/D9 Address, Address/Data Inputs (Pins 1 – 7, 9, and 10) These address/data inputs are encoded and the data is sent serially from the encoder via the Dout pin. RS, CTC, RTC (Pins 11, 12, and 13) These pins are part of the oscillator section of the encoder (see Figure 9). If an external signal source is used instead of the internal oscillator, it should be connected to the RS input and the RTC and CTC pins should be left open. TE Transmit Enable (Pin 14) This active–low transmit enable input initiates transmission when forced low. An internal pull–up device keeps this input normally high. The pull–up current is specified in the Electrical Characteristics table. Dout Data Out (Pin 15) This is the output of the encoder that serially presents the encoded data word. VSS Negative Power Supply (Pin 8) The most–negative supply potential. This pin is usually ground. VDD Positive Power Supply (Pin 16). The most–positive power supply pin. ML145027 AND ML145028 DECODERS A1 – A5, A1 – A9 Address Inputs (Pins 1 – 5)—ML145027, Address Inputs (Pins 1 – 5, 15, 14, 13, 12)—ML145028 These are the local address inputs. The states of these pins must match the appropriate encoder inputs for the VT pin to go high. The local address may be encoded with trinary or binary data. D6 – D9 Data Outputs (Pins 15, 14, 13, 12)—ML145027 Only These outputs present the binary information that is on encoder inputs A6/D6 through A9/D9. Only binary data is www.lansdale.com Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 acknowledged; a trinary open at the ML145026 encoder is decoded as a high level (logic 1). Din Data In (Pin 9) This pin is the serial data input to the decoder. The input voltage must be at CMOS logic levels. The signal source driving this pin must be DC coupled. R1, C1 Resistor 1, Capacitor 1 (Pins 6, 7) As shown in Figures 2 and 3, these pins accept a resistor and capacitor that are used to determine whether a narrow pulse or wide pulse has been received. The time constant R1 x C1 should be set to 1.72 encoder clock periods: R1 C1 = 3.95 RTC CTC R2/C2 Resistor 2/Capacitor 2 (Pin 10) As shown in Figures 2 and 3, this pin accepts a resistor and capacitor that are used to detect both the end of a received word and the end of a transmission. The time constant R2 x C2 should be 33.5 encoder clock periods (four data periods per Figure 11): R2 C2 = 77 RTC CTC. This time constant is used to determine whether the Din pin has remained low for four data periods (end of transmission). A separate on–chip com- Page 8 of 19 parator looks at the voltage–equivalent two data periods (0.4 R2 C2) to detect the dead time between received words within a transmission. VT Valid Transmission Output (Pin 11) This valid transmission output goes high after the second word of an encoding sequence when the following conditions are satisfied: 1. the received addresses of both words match the local de-coder address, and 2. the received data bits of both words match. VT remains high until either a mismatch is received or no input signal is received for four data periods. VSS Negative Power Supply (Pin 8) The most–negative supply potential. This pin is usually ground. VDD Positive Power Supply (Pin 16) The most–positive power supply pin. www.lansdale.com Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 RS CTC 11 RTC 12 13 INTERNAL ENABLE This oscillator operates at a frequency determined by the external RC network; i.e., f≈ 1 2.3 RTC CTC′ The value for RS should be chosen to be ≥ 2 times RTC. This range ensures that current through RS is insignificant compared to current through RTC. The upper limit for RS must ensure that RS x 5 pF (input capacitance) is small compared to RTC x CTC. For frequencies outside the indicated range, the formula is less accurate. The minimum recommended oscillation frequency of this circuit is 1 kHz. Susceptibility to externally induced noise signals may occur for frequencies below 1 kHz and/or when resistors utilized are greater than 1 MΩ. (Hz) for 1 kHz ≤ f ≤ 400 kHz where: CTC′ = CTC + Clayout + 12 pF RS ≈ 2 RTC RS ≥ 20 k RTC ≥ 10 k 400 pF < CTC < 15 µF Figure 9. Encoder Oscillator Information ENCODER PWmin 2 WORD TRANSMISSION TE 1ST DIGIT 9TH DIGIT 184 182 180 178 122 120 118 116 114 90 88 86 84 82 80 30 28 26 24 22 20 18 16 6 4 2 ENCODER OSCILLATOR (PIN 12) CONTINUOUS TRANSMISSION 9TH DIGIT 1ST DIGIT Dout (PIN 15) HIGH OPEN LOW 1ST WORD 2ND WORD ENCODING SEQUENCE DECODER 1.1 (R2C2) VT (PIN 11) DATA OUTPUTS Figure 10. Timing Diagram Page 9 of 19 www.lansdale.com Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 ENCODER OSCILLATOR (PIN 12) ENCODED “ONE” Dout (PIN 15) ENCODED “ZERO” ENCODED “OPEN” DATA PERIOD Figure 11. Encoder Data Waveforms f max (kHz) (REF. TO ENCODER CLOCK) 500 400 VDD = 15 V VDD = 10 V 300 200 VDD = 5 V 100 10 20 30 40 50 Clayout (pF) ON PINS 1 – 5 (ML145027); PINS 1 – 5 AND 12 – 15 (ML145028) Figure 12. fmax vs Clayout — Decoders Only Page 10 of 19 www.lansdale.com Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 NO HAS THE TRANSMISSION BEGUN? YES DOES THE 5–BIT ADDRESS MATCH THE ADDRESS PINS? NO DISABLE VT ON THE 1ST ADDRESS MISMATCH YES STORE THE 4–BIT DATA DOES THIS DATA MATCH THE PREVIOUSLY STORED DATA? NO DISABLE VT ON THE 1ST DATA MISMATCH YES IS THIS AT LEAST THE 2ND CONSECUTIVE MATCH SINCE VT DISABLE? NO YES LATCH DATA ONTO OUTPUT PINS AND ACTIVATE VT HAVE 4–BIT TIMES PASSED? YES DISABLE VT NO NO HAS A NEW TRANSMISSION BEGUN? YES Figure 13. ML145027 Flowchart Page 11 of 19 www.lansdale.com Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 HAS THE TRANSMISSION BEGUN? NO YES DOES THE ADDRESS MATCH THE ADDRESS PINS? NO DISABLE VT ON THE 1ST ADDRESS MISMATCH AND IGNORE THE REST OF THIS WORD YES IS THIS AT LEAST THE 2ND CONSECUTIVE MATCH SINCE VT DISABLE? NO YES ACTIVATE VT HAVE 4–BIT TIMES PASSED? YES DISABLE VT NO NO HAS A NEW TRANSMISSION BEGUN? YES Figure 14. ML145028 Flowchart Page 12 of 19 www.lansdale.com Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 ML145027 AND ML145028 TIMING To verify the ML145027 or ML145028 timing, check thewaveforms on C1 (Pin 7) and R2/C2 (Pin 10) as compared to the incoming data waveform on Din (Pin 9). The R–C decay seen on C1 discharges down to 1/3 VDD before being reset to VDD. This point of reset (labelled “DOS” in Figure 15) is the point in time where the decision is made whether the data seen on Din is a 1 or 0. DOS should not be too close to the Din data edges or intermittent operation may occur. The other timing to be checked on the ML145027 and ML145028 is on R2/C2 (see Figure 16). The R–C decay is continually reset to VDD as data is being transmitted. Only between words and after the end–of–transmission (EOT) does R2/C2 decay significantly from VDD. R2/C2 can be used to identify the internal end–of–word (EOW) timing edge which is generated when R2/C2 decays to 2/3 VDD. The internal EOT timing edge occurs when R2/C2 decays to 1/3 VDD. When the waveform is being observed, the R–C decay should go down between the 2/3 and 1/3 VDD levels, but not too close to either level before data transmission on Din resumes. Verification of the timing described above should ensure a good match between the ML145026 transmitter and the ML145027 and ML145028 receivers. VDD Din 0V VDD 2/3 C1 1/3 0V DOS DOS F igure 15. R ÐC Decay on P in 7 (C 1) EOW VDD 2/3 R2/C2 1/3 0V EOT F igure 16. R ÐC Decay on P in 10 (R 2/C 2) Page 13 of 19 www.lansdale.com Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 VDD VDD VDD TE VDD A1 A2 5 TRINARY ADDRESSES A3 A4 A5 D6 4–BIT BINARY DATA D7 D8 0.1 µF 0.1 µF 14 1 2 3 4 5 6 7 9 10 16 A1 16 15 Dout Din 9 6 R1 ML 145026 13 7 RTC CTC 12 10 11 D9 RS 8 ML 145027 C1 1 2 3 4 5 15 14 13 12 11 A2 A3 A4 A5 D6 D7 D8 D9 VT C2 R2 5 TRINARY ADDRESSES 8 CT C′ = CT C + Clayout + 12 pF 100 pF ≤ CT C ≤ 15 µF RT C ≥ 10 kΩ; RS ≈ 2 RT C R1 ≥ 10 kΩ C1 ≥ 400 pF R2 ≥ 100 kΩ C2 ≥ 700 pF 1 fosc = 2.3 RT CCTC′ R1C1 = 3.95 RT CCTC R2C2 = 77 RT CCT C REPEAT OF ABOVE REPEAT OF ABOVE Example R/C Values (All Resistors and Capacitors are ± 5%) (CT C′ = CT C + 20 pF ) fos c (kHz) 362 181 88.7 42.6 21.5 8.53 1.71 RT C 10 10 10 10 10 10 50 k k k k k k k CT C′ RS 120 pF 240 pF 490 pF 1020 pF 2020 pF 5100 pF 5100 pF 20 k 20 k 20 k 20 k 20 k 20 k 100 k R1 10 10 10 10 10 10 50 k k k k k k k C1 470 pF 910 pF 2000 pF 3900 pF 8200 pF 0.02 µF 0.02 µF R2 100 100 100 100 100 200 200 C2 k k k k k k k 910 pF 1800 pF 3900 pF 7500 pF 0.015µF 0.02 µF 0.1 µF F igure 17. Typic al A pplic ation Page 14 of 19 www.lansdale.com Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 Legacy Applications Information INFRARED TRANSMITTER In Figure 18, the ML145026 encoder is set to run at an oscillator frequency of about 4 to 9 kHz. Thus, the time required for a complete two–word encoding sequence is about 20 to 40 ms. The data output from the encoder gates an RC oscillator running at 50 kHz; the oscillator shown starts rapidly enough to be used in this application. When the “send” button is not depressed, both the ML145026 and oscillator are in a low–power standby state. The RC oscillator has to be trimmed for 50 kHz and has some drawbacks for frequency stability. A superior system uses a ceramic resonator oscillator running at 400 kHz. This oscillator feeds a divider as shown in Figure 19. The unused inputs of the MC14011UB must be grounded. The MLED81 IRED is driven with the 50 kHz square wave at about 200 to 300 mA to generate the carrier. If desired, two IREDs wired in series can be used (see Application Note AN1016 for more information). The bipolar IRED switch, shown in Figure 18, offers two advantages over a FET. First, a logic FET has too much gate capacitance for the MC14011UB to drive without waveform distortion. Second, the bipolar drive permits lower supply voltages, which are an advantage in portable battery–powered applications. The configuration shown in Figure 18 operates over a supply range of 4.5 to 18 V. A low–voltage system which operates down to 2.5 V could be realized if the oscillator section of a MC74HC4060 is used in place of the MC14011UB. The data output of the ML145026 is inverted and fed to the RESET pin of the MC74HC4060. Alternately, the MC74HCU04 could be used for the oscillator. For information on the MC14011UB, MC74HCU04 and MC74HC4060 consult ON Semiconductor. INFRARED RECEIVER The receiver in Figure 20 couples an IR–sensitive diode to input preamp A1, followed by band–pass amplifier A2 with again of about 10. Limiting stage A3 follows, with an output of about 800 mV p–p. The limited 50 kHz burst is detected by comparator A4 that passes only positive pulses, and peak–detected and filtered by a diode/RC network to extract the data envelope from the burst. Comparator A5 boosts the signal to logic Page 15 of 19 levels compatible with the ML145027/28 data input. The Din pin of these decoders is a standard CMOS high–impedance input which must not be allowed to float. Therefore, direct coupling from A5 to the decoder input is utilized. Shielding should be used on at least A1 and A2, with good ground and high–sensitivity circuit layout techniques applied. For operation with supplies higher than + 5 V, limiter A4’s positive output swing needs to be limited to 3 to 5 V. This is accomplished via adding a zener diode in the negative feedback path, thus avoiding excessive system noise. The biasing resistor stack should be adjusted such that V3 is 1.25 to1.5 V. This system works up to a range of about 10 meters. The gains of the system may be adjusted to suit the individual design needs. The 100 Ω resistor in the emitter of the first 2N5088 and the 1 kΩ resistor feeding A2 may be altered if different gain is required. In general, more gain does not necessarily result in increased range. This is due to noise floor limitations. The designer should increase transmitter power and/or increase receiver aperature with Fresnal lensing to greatly improve range. See Application Note AN1016 for additional information. For information on the MC34074 contact ON Semiconductor. TRINARY SWITCH MANUFACTURERS Midland Ross–Electronic Connector Div. Greyhill Augat/Alcoswitch Aries Electronics The above companies may not have the switches in a DIP. For more information, call them or consult eem Electronic Engineers Master Catalog or the Gold Book. Ask for SPDT with center OFF. Alternative: An SPST can be placed in series between a SPDT and the Encoder or Decoder to achieve trinary action. Lansdale cannot recommend one supplier over another and in no way suggests that this is a complete listing of trinary switch manufacturers. www.lansdale.com Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 SELECT FOR 200 mA TO 300 mA MLED81 USE OF 2 MLED81s IS OPTIONAL MC 14011UB 10 kΩ MPSA13 OR MPSW13 SEND MC 14011UB Dout TE ML 145026 RS CTC RTC 9 SWITCHES 220 kΩ 0.01 µF 220 kΩ 1000 pF ADJUST/SELECT FOR f = 50 kHz (APPROX. 100 kΩ) 100 kΩ FOR APPROX. 4 kHz 47 kΩ FOR APPROX. 9 kHz F igure 18. IR E D Trans mitter Us ing R C Os c illator to G enerate C arrier F requenc y V+ MC 14011UB MC 14024 CLK Q3 RESET 50 kHZ TO DRIVER TRANSISTOR 1MΩ X1 = 400 kHz CERAMIC RESONATOR PANASONIC EFD–A400K04B OR EQUIVALENT X1 470 pF V+ MC 14011UB Dout FROM ML145026 470 pF F igure 19. Us ing a C eramic R es onator to G enerate C arrier F requenc y Page 16 of 19 www.lansdale.com Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 +5 V 10 kΩ 10 µF A1 1 mH — TOKO TYPE 7PA OR 10PA OR EQUIVALENT 10 µF 10 kΩ 22 kΩ 0.01 µF 2N5088 2N5086 2N5088 0.01 µF 1 kΩ 10 kΩ – A2 100 Ω OPTICAL FILTER 6.8 kΩ V1 2.2 kΩ + 1/4 MC34074 1 µF 1N914 0.01 µF 4.7 kΩ 1N914 1 MΩ 100 kΩ 1 MΩ – 10 kΩ A3 V1 1N914 + + 1 kΩ 22 kΩ + A4 – V2 1/4 MC34074 A5 1/4 MC34074 1000 pF 47 kΩ V3 – 1/4 MC34074 +5 V 390 kΩ FOR APPROX. 4 kHz 180 kΩ FOR APPROX. 9 kHz 1000 pF 0.01 µF 750 kΩ FOR APPROX. 4 kHz 360 kΩ FOR APPROX. 9 kHz 4.7 kΩ R1 C1 ML 145027/28 Din VDD +5 V V2 ≈ 2.7 V R2/C2 VSS 390 Ω VT V1 ≈ 2.5 V 4 DATA OUT ML145027 ONLY 9 FOR ML145027 5 FOR ML145028 2.2 kΩ 10 µF 10 µF V3 ≈ 1.3 V 10 µF 2.7 kΩ ADDRESS SWITCHES F igure 20. Infrared R ec eiver Page 17 of 19 www.lansdale.com Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 OUTLINE DIMENSIONS P DIP 16 = EP (ML145026EP, ML145027EP, ML145028EP) PLASTIC DIP (DUAL IN–LINE PACKAGE) CASE 648–08 –A – 16 9 1 8 B F C DIM A B C D F G H J K L M S L S –T – S E ATING P L ANE K H G D M J 16 P L 0.25 (0.010) M T A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. M INC HE S MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MIL L IME TE R S MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 SO 16 = -5P SOG (SMALL OUTLINE GULL–WING) PACKAGE (ML145026-5P) CASE 751B–05 –A – 16 9 1 8 –B – P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) M B S G R K F X 45 C –T – S E ATING P L ANE M D 16 P L 0.25 (0.010) Page 18 of 19 M T B S A S www.lansdale.com J DIM A B C D F G J K M P R MIL L IME TE R S MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INC HE S MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 OUTLINE DIMENSIONS SO 16W = -5P SOG (SMALL OUTLINE GULL–WING) PACKAGE (ML145027-5P, ML145028-5P) C A S E 751G –02 –A – 16 9 –B – 8X P 0.010 (0.25) 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. M B M 8 16X J D 0.010 (0.25) M T A S B S F RX 45 C –T – 14X G K S E ATING P L ANE M DIM A B C D F G J K M P R MIL L IME TE R S MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0 7 10.05 10.55 0.25 0.75 INC HE S MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0 7 0.395 0.415 0.010 0.029 Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. T Ò ypical ” parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc. Page 19 of 19 www.lansdale.com Issue 0