ON MC74LVXT8051D Analog multiplexer/demultiplexer Datasheet

MC74LVXT8051
Analog Multiplexer /
Demultiplexer
High–Performance Silicon–Gate CMOS
The MC74LVXT8051 utilizes silicon–gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
(from VCC to GND).
The LVXT8051 is similar in pinout to the high–speed HC4051A
and the metal–gate MC14051B. The Channel–Select inputs determine
which one of the Analog Inputs/Outputs is to be connected by means
of an analog switch to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The Channel–Select and Enable inputs are compatible with
TTL–type input thresholds. The input protection circuitry on this
device allows overvoltage tolerance on the input, allowing the device
to be used as a logic–level translator from 3.0V CMOS logic to 5.0V
CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic while
operating at the higher–voltage power supply.
The MC74LVXT8051 input structure provides protection when voltages
up to 7V are applied, regardless of the supply voltage. This allows the
MC74LVXT8051 to be used to interface 5V circuits to 3V circuits.
This device has been designed so that the ON resistance (Ron) is more
linear over input voltage than Ron of metal–gate CMOS analog switches.
•
•
•
•
•
•
•
•
Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
Analog Power Supply Range (VCC – GND) = 2.0 to 6.0 V
Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V
Improved Linearity and Lower ON Resistance Than Metal–Gate
Counterparts
Low Noise
In Compliance With the Requirements of JEDEC Standard No. 7A
LOGIC DIAGRAM
MC74LVXT8051
Single–Pole, 8–Position Plus Common Off
13
X0
14
X1
15
X2
ANALOG
12
INPUTS/ X3
OUTPUTS X4 1
5
X5
2
X6
4
X7
11
A
CHANNEL
10
B
SELECT
9
INPUTS
C
6
ENABLE
16–LEAD SOIC
D SUFFIX
CASE 751B
16–LEAD TSSOP
DT SUFFIX
CASE 948F
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
VCC
16
X2
X1
X0
X3
A
B
C
15
14
13
12
11
10
9
6
7
8
GND
1
2
3
4
5
X4
X6
X
X7
X5
Enable NC
For detailed package marking information, see the Marking
Diagram section on page 11 of this data sheet.
FUNCTION TABLE – MC74LVXT8051
Control Inputs
Enable
C
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
H
X
Select
B
A
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
ON Channels
X0
X1
X2
X3
X4
X5
X6
X7
NONE
X = Don’t Care
3
MULTIPLEXER/
DEMULTIPLEXER
 Semiconductor Components Industries, LLC, 1999
March, 2000 – Rev. 2
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X
COMMON
OUTPUT/
INPUT
ORDERING INFORMATION
Device
PIN 16 = VCC
PIN 8 = GND
1
Package
Shipping
MC74LVXT8051D
SOIC
48 Units/Rail
MC74LVXT8051DR2
SOIC
2500 Units/Reel
MC74LVXT8051DT
TSSOP
96 Units/Rail
MC74LVXT8051DTR2
TSSOP
2500 Units/Reel
Publication Order Number:
MC74LVXT8051/D
MC74LVXT8051
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MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
– 0.5 to + 7.0
V
Analog Input Voltage
– 0.5 to VCC + 0.5
V
Digital Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
–20
mA
500
450
mW
– 65 to + 150
_C
260
_C
VCC
Positive DC Supply Voltage
VIS
Vin
I
DC Current, Into or Out of Any Pin
PD
Power Dissipation in Still Air,
Tstg
Storage Temperature Range
TL
(Referenced to GND)
SOIC Package†
TSSOP Package†
Lead Temperature, 1 mm from Case for 10 Seconds
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
VCC
Positive DC Supply Voltage
VIS
Analog Input Voltage
(Referenced to GND)
Vin
Digital Input Voltage (Referenced to GND)
VIO*
Static or Dynamic Voltage Across Switch
TA
Operating Temperature Range, All Package Types
tr, tf
Input Rise/Fall Time
(Channel Select or Enable Inputs)
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
Max
Unit
2.0
6.0
V
0.0
VCC
V
GND
VCC
V
1.2
V
+ 85
_C
– 55
ns/V
0
0
100
20
*For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out of the switch may contain both VCC and switch input
components. The reliability of the device will be unaffected unless the Maximum Ratings are
exceeded.
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2
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
v
v
MC74LVXT8051
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND)
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V
–55 to 25°C
≤85°C
≤125°C
Unit
VIH
Minimum High–Level Input
Voltage, Channel–Select or
Enable Inputs
Ron = Per Spec
3.0
4.5
5.5
1.2
2.0
2.0
1.2
2.0
2.0
1.2
2.0
2.0
V
VIL
Maximum Low–Level Input
Voltage, Channel–Select or
Enable Inputs
Ron = Per Spec
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
Iin
Maximum Input Leakage Current,
Channel–Select or Enable Inputs
Vin = VCC or GND
5.5
± 0.1
± 1.0
± 1.0
µA
Maximum Quiescent Supply
Current (per Package)
Channel Select, Enable and
VIS = VCC or GND; VIO = 0 V
5.5
4
40
160
µA
ICC
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DC ELECTRICAL CHARACTERISTICS Analog Section
Guaranteed Limit
Symbol
Ron
Parameter
Maximum “ON” Resistance
VCC
V
– 55 to
25_C
Vin = VIL or VIH
VIS = VCC to GND
|IS|
10.0 mA (Figures 1, 2)
3.0
4.5
5.5
Vin = VIL or VIH
VIS = VCC or GND (Endpoints)
|IS|
10.0 mA (Figures 1, 2)
Vin = VIL or VIH
VIS = 1/2 (VCC – GND)
|IS|
10.0 mA
Test Conditions
85_C
125_C
40
30
25
45
32
28
50
37
30
3.0
4.5
5.5
30
25
20
35
28
25
40
35
30
3.0
4.5
5.5
15
8.0
8.0
20
12
12
25
15
15
Ω
µA
∆Ron
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Ioff
Maximum Off–Channel Leakage
Current, Any One Channel
Vin = VIL or VIH;
VIO = VCC or GND;
Switch Off (Figure 3)
5.5
0.1
0.5
1.0
Maximum Off–Channel
Leakage Current,
Common Channel
Vin = VIL or VIH;
VIO = VCC or GND;
Switch Off (Figure 4)
5.5
0.2
2.0
4.0
Maximum On–Channel
Leakage Current,
Channel–to–Channel
Vin = VIL or VIH;
Switch–to–Switch =
VCC or GND; (Figure 5)
5.5
0.2
2.0
4.0
Ion
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3
Unit
Ω
µA
MC74LVXT8051
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 3 ns)
Guaranteed Limit
VCC
V
–55 to 25°C
≤85°C
≤125°C
Unit
Maximum Propagation Delay, Channel–Select to Analog Output
(Figure 9)
2.0
3.0
4.5
5.5
30
20
15
15
35
25
18
18
40
30
22
20
ns
tPLH,
tPHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
2.0
3.0
4.5
5.5
4.0
3.0
1.0
1.0
6.0
5.0
2.0
2.0
8.0
6.0
2.0
2.0
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
3.0
4.5
5.5
30
20
15
15
35
25
18
18
40
30
22
20
ns
tPZL,
tPZH
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
3.0
4.5
5.5
20
12
8.0
8.0
25
14
10
10
30
15
12
12
ns
Symbol
Parameter
tPLH,
tPHL
Cin
Maximum Input Capacitance, Channel–Select or Enable Inputs
10
10
10
pF
CI/O
Maximum Capacitance
Analog I/O
35
35
35
pF
Common O/I
130
130
130
Feedthrough
1.0
1.0
1.0
(All Switches Off)
CPD
Typical @ 25°C, VCC = 5.0 V
Power Dissipation Capacitance (Figure 13)*
45
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC .
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4
pF
MC74LVXT8051
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Symbol
BW
—
Parameter
VCC
V
Condition
fin = 1MHz Sine Wave; Adjust fin Voltage to Obtain
0dB att VOS; IIncrease fin Frequency
0dBm
F
Until
U til dB
Meter Reads –3dB;
RL = 50Ω, CL = 10pF
3.0
4.5
5.5
80
80
80
Off–Channel Feedthrough Isolation
(Figure 7)
fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm
at VIS
fin = 10kHz, RL = 600Ω, CL = 50pF
3.0
4.5
5.5
–50
–50
–50
3.0
4.5
5.5
–37
–37
–37
3.0
4.5
5.5
25
105
135
3.0
4.5
5.5
35
145
190
3.0
4.5
5.5
–50
–50
–50
3.0
4.5
5.5
–60
–60
–60
Feedthrough Noise.
Channel–Select Input to Common
I/O (Figure 8)
Vin ≤ 1MHz Square Wave (tr = tf = 3ns); Adjust RL
at Setup so that IS = 0A;
Enable = GND
RL = 600Ω, CL = 50pF
RL = 10kΩ, CL = 10pF
—
Crosstalk Between Any Two
Switches (Figure 12)
fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm
at VIS
fin = 10kHz, RL = 600Ω, CL = 50pF
fin = 1.0MHz, RL = 50Ω, CL = 10pF
THD
25°C
Maximum On–Channel Bandwidth
or Minimum
Mi i
Frequency
F
Response
R
(Figure 6)
fin = 1.0MHz, RL = 50Ω, CL = 10pF
—
Limit*
Total Harmonic Distortion
(Figure 14)
fin = 1kHz, RL = 10kΩ, CL = 50pF
THD = THDmeasured – THDsource
VIS = 2.0VPP sine wave
VIS = 4.0VPP sine wave
VIS = 5.0VPP sine wave
3.0
4.5
5.5
Ron , ON RESISTANCE (OHMS)
40
35
30
125°C
85°C
25°C
– 55°C
20
15
10
5
00
1.0
2.0
3.0
VIN, INPUT VOLTAGE (VOLTS)
Figure 1a. Typical On Resistance, VCC = 3.0 V
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5
MHz
dB
mVPP
dB
%
*Limits not tested. Determined by design and verified by qualification.
25
Unit
4.0
0.10
0.08
0.05
MC74LVXT8051
25
25
Ron , ON RESISTANCE (OHMS)
Ron , ON RESISTANCE (OHMS)
30
125°C
85°C
25°C
– 55°C
20
15
10
5
0
0
1.0
2.0
3.0
4.0
20
125°C
85°C
15
25°C
– 55°C
10
5
0
5.0
0
1.0
2.0
Figure 1b. Typical On Resistance, VCC = 4.5 V
4.0
5.0
Figure 1c. Typical On Resistance, VCC = 5.5 V
PLOTTER
PROGRAMMABLE
POWER
SUPPLY
–
3.0
VIN, INPUT VOLTAGE (VOLTS)
VIN, INPUT VOLTAGE (VOLTS)
MINI COMPUTER
DC ANALYZER
+
VCC
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
GND
GND
Figure 2. On Resistance Test Set–Up
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6
6.0
MC74LVXT8051
VCC
VCC
VCC
16
GND
ANALOG I/O
OFF
A
VCC
VIH
OFF
VIH
6
8
Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set–Up
VCC
Figure 4. Maximum Off Channel Leakage Current,
Common Channel, Test Set–Up
VCC
16
A
VCC
16
0.1µF
fin
ON
VOS
dB
METER
ON
N/C
COMMON O/I
OFF
VCC
COMMON O/I
6
8
GND
OFF
VCC
COMMON O/I
OFF
NC
VCC
16
GND
RL
CL*
ANALOG I/O
VIL
6
6
8
8
*Includes all probe and jig capacitance
Figure 5. Maximum On Channel Leakage Current,
Channel to Channel, Test Set–Up
VCC
16
VIS
0.1µF
fin
VCC
16
VOS
dB
METER
OFF
RL
Figure 6. Maximum On Channel Bandwidth,
Test Set–Up
CL*
RL
ON/OFF
COMMON O/I
ANALOG I/O
RL
OFF/ON
RL
RL
6
6
8
VIL or VIH
VIH
VIL
CHANNEL SELECT
Vin ≤ 1 MHz
tr = tf = 3 ns
8
TEST
POINT
CL*
VCC
11
CHANNEL SELECT
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 7. Off Channel Feedthrough Isolation,
Test Set–Up
Figure 8. Feedthrough Noise, Channel Select to
Common Out, Test Set–Up
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MC74LVXT8051
VCC
16
VCC
VCC
CHANNEL
SELECT
ON/OFF
50%
COMMON O/I
ANALOG I/O
OFF/ON
GND
tPLH
TEST
POINT
CL*
tPHL
6
ANALOG
OUT
50%
8
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 9a. Propagation Delays, Channel Select
to Analog Out
Figure 9b. Propagation Delay, Test Set–Up Channel
Select to Analog Out
VCC
16
ANALOG
IN
COMMON O/I
ANALOG I/O
VCC
ON
50%
TEST
POINT
CL*
GND
tPHL
tPLH
ANALOG
OUT
6
8
50%
*Includes all probe and jig capacitance
Figure 10a. Propagation Delays, Analog In
to Analog Out
tf
tr
90%
50%
10%
ENABLE
tPZL
ANALOG
OUT
Figure 10b. Propagation Delay, Test Set–Up
Analog In to Analog Out
tPLZ
1
VCC
2
GND
1kΩ
ANALOG I/O
TEST
POINT
ON/OFF
2
CL*
VOL
tPZH tPHZ
ANALOG
OUT
1
50%
90%
VCC
16
VCC
HIGH
IMPEDANCE
10%
POSITION 1 WHEN TESTING tPHZ AND tPZH
POSITION 2 WHEN TESTING tPLZ AND tPZL
VIH
VIL
VOH
ENABLE
50%
6
8
HIGH
IMPEDANCE
Figure 11a. Propagation Delays, Enable to
Analog Out
Figure 11b. Propagation Delay, Test Set–Up
Enable to Analog Out
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MC74LVXT8051
VCC
VIS
A
VCC
16
RL
fin
16
VOS
ON
COMMON O/I
ON/OFF
NC
ANALOG I/O
0.1µF
OFF/ON
OFF
RL
RL
CL*
RL
CL*
VCC
6
6
8
8
CHANNEL SELECT
11
*Includes all probe and jig capacitance
Figure 12. Crosstalk Between Any Two
Switches, Test Set–Up
Figure 13. Power Dissipation Capacitance,
Test Set–Up
0
VIS
VCC
16
0.1µF
fin
– 10
VOS
ON
CL*
TO
DISTORTION
METER
– 30
– 40
dB
RL
FUNDAMENTAL FREQUENCY
– 20
– 50
DEVICE
– 60
6
SOURCE
– 70
8
– 80
– 90
*Includes all probe and jig capacitance
– 100
1.0
2.0
3.125
FREQUENCY (kHz)
Figure 14a. Total Harmonic Distortion, Test Set–Up
Figure 14b. Plot, Harmonic Distortion
APPLICATIONS INFORMATION
connected). However, tying unused analog inputs and
outputs to VCC or GND through a low value resistor helps
minimize crosstalk and feedthrough noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:
VCC – GND = 2 to 6 volts
When voltage transients above VCC and/or below GND
are anticipated on the analog channels, external Germanium
or Schottky diodes (Dx) are recommended as shown in
Figure 16. These diodes should be able to absorb the
maximum anticipated current surges during clipping.
The Channel Select and Enable control pins should be at
VCC or GND logic levels. VCC being recognized as a logic
high and GND being recognized as a logic low. In this
example:
VCC = +5V = logic high
GND = 0V = logic low
The maximum analog voltage swing is determined by the
supply voltage VCC. The positive peak analog voltage
should not exceed VCC. Similarly, the negative peak analog
voltage should not go below GND. In this example, the
difference between VCC and GND is five volts. Therefore,
using the configuration of Figure 15, a maximum analog
signal of five volts peak–to–peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
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MC74LVXT8051
VCC
+5V
16
+5V
ANALOG
SIGNAL
0V
ON
6
8
Dx
+5V
ANALOG
SIGNAL
VCC
16
Dx
Dx
GND
GND
8
Figure 15. Application Example
Figure 16. External Germanium or
Schottky Clipping Diodes
+3V
16
+3V
ANALOG
SIGNAL
GND
ON/OFF
ANALOG
SIGNAL
Dx
ON/OFF
0V
TO EXTERNAL LSTTL COMPATIBLE
CIRCUITRY 0 to VIH
DIGITAL SIGNALS
11
10
9
VCC
+5V
+3V
+5V
GND
GND
16
ANALOG
SIGNAL
ON/OFF
+5V
ANALOG
SIGNAL
GND
+5V
6
8
11
10
9
6
1.8V – 2.5V
CIRCUITRY
8
11
10
9
1.8V – 2.5V
CIRCUITRY
MC74VHCT1GT50 BUFFERS
VCC = 3.0V
a. Low Voltage Logic Level Shifting Control
b. 2–Stage Logic Level Shifting Control
Figure 17. Interfacing to Low Voltage CMOS Outputs
A
11
13
LEVEL
SHIFTER
14
B
10
15
LEVEL
SHIFTER
12
C
9
1
LEVEL
SHIFTER
5
ENABLE
6
2
LEVEL
SHIFTER
4
3
Figure 18. Function Diagram, LVXT8051
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10
X0
X1
X2
X3
X4
X5
X6
X7
X
MC74LVXT8051
MARKING DIAGRAMS
(Top View)
16
15
14
13
12
11
10
16 15 14 13 12 11 10
9
9
LVXT
LVXT8051
8051
AWLYWW*
1
2
3
4
ALYW*
5
6
7
8
1
16–LEAD SOIC
D SUFFIX
CASE 751B
2
3
4
5
6
7
8
16–LEAD TSSOP
DT SUFFIX
CASE 948F
*See Applications Note #AND8004/D for date code and traceability information.
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B
–
1
P 8 PL
0.25 (0.010)
8
B
M
M
G
K
F
R X 45°
C
–T
SEATING
–
PLANE
J
M
D 16 PL
0.25 (0.010)
M
T
B
S
A
S
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11
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
7°
0°
0.229 0.244
0.010 0.019
MC74LVXT8051
PACKAGE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
ÉÉ
ÇÇÇ
ÇÇÇ
ÉÉ
ÇÇÇ
ÉÉ
K
K1
2X
L/2
16
9
J1
B
–U–
L
SECTION N–N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
–V–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
M
N
F
DETAIL E
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
DETAIL E
H
D
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
G
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MC74LVXT8051/D