CHL8112A/B DIGITAL MULTI-PHASE BUCK CONTROLLER PRODUCT BRIEF PRELIMINARY The I2C/PMBus interface can communicate with up to 16 CHL8112A/B based VR loops. Device configuration and fault parameters are easily defined using the CHiL Intuitive Power Designer (IPD) GUI and stored in on-chip NVM. FEATURES 5-phase dual output PWM Controller Phases are flexibly assigned between Loops 1 & 2 AMD® SVI/G34 & Memory MPoL modes The CHL8112A/B provides extensive OVP, UVP, OCP and OTP fault protection and includes thermistor based temperature sensing with VRHOT signal. CHiL Adaptive Transient Algorithm (ATA) on both loops minimizes output bulk capacitors and system cost Designed for use with coupled inductors ISEN4 IRTN5 ISEN5 Programmable 1-phase or 2-phase for Light Loads and Active Diode Emulation for Very Light Loads IRTN4 CHiL Efficiency Shaping Features including Variable Gate Drive (CHL8112A only), Dynamic Phase Control ISEN3 Switching frequency from 200kHz to 1.2MHz per phase IRTN3 Overclocking & Gaming Mode with Vmax setting The CHL8112A/B also includes numerous features like register diagnostics for fast design cycles and platform differentiation, truly simplifying VRD design and enabling fastest time-to-market with its “set-and-forget” methodology. ISEN2 2nd Temperature Sense (CHL8112B) IRTN2 PMBus Address pin or Variable Gate Drive (CHL8112A) ISEN1 SMB_Alert Pin for Servers IRTN1 Dual OCP support for I-spike enhanced AMD CPUs 40 39 38 37 36 35 34 33 32 31 RCSP 1 30 RCSP_L2 RCSM 2 29 RCSM_L2 VCC 3 28 VCC VSEN 4 27 VSEN_L2 VRTN 5 26 VRTN_L2 RRES 6 25 PWM5 TSEN 7 24 PWM4 V18A 8 23 PWM3 22 PWM2 21 PWM1 Auto-Phase Detection with auto-compensation Per-Loop Fault Protection: OVP, UVP, OCP, OTP, CFP I2C/SMBus/PMBus system interface for telemetry of Temperature, Voltage, Current & Power for both loops CHL8112A/B 40 Pin 6x6 QFN Top View Non-Volatile Memory (NVM) for custom configuration Compatible with CHiL ATL and 3.3V tri-state Drivers +3.3V supply voltage; 0ºC to 85ºC ambient operation 1 CHiL’s unique Adaptive Transient Algorithm (ATA), based on proprietary non-linear digital PWM algorithms, minimizes output bulk capacitors. In addition, a coupled inductor mode, with phases added/dropped in pairs, enables further improvement in transient response and form factor. Trademarks and registered trademarks are the property of the respective owners. PB0012 Rev. 0.04, August 25, 2010 15 16 17 18 19 20 SMB_ALERT# SMB_DIO SMB_CLK VAR_GATE_PM_ADDR (CHL8112A) TSEN2 (CHL8112B) The CHL8112A/B includes the CHiL Efficiency Shaping Technology to deliver exceptional efficiency at minimum cost across the entire load range. CHiL Variable Gate Drive optimizes the MOSFET gate drive voltage as a function of real-time load current. CHiL Dynamic Phase Control adds/drops active phases based upon load current. The CHL8112A/B can be configured to enter 1-phase operation and active diode emulation mode automatically or by command. 14 ENABLE NVM storage saves pins and enables a small package size. 13 VR_HOT# / VRHOT_ICRIT#2 12 41 GND 1 11 NC1 / SVD2 The CHL8112A/B are dual-loop digital multi-phase buck controllers that drive up to 5 phases. The CHL8112A/B is fully AMD® SVI compliant on both loops and provides a Vtt tracking function for DDR memory. NC / SVC 10 DESCRIPTION 2 VR_READY_L212 / PWROK Notes 1 Pin definition in MPoL mode 2 Pin definition in AMD mode 1 9 NC1 / VFIXEN2 VR_READY / PWRGD2 VINSEN Pb-Free, RoHS, 6x6 40 pin QFN package Figure 1. CHL8112A & CHL8112B Packages APPLICATIONS Page 1 of 2 AMD® SVI based systems DDR Memory with Vtt tracking Overclocked & Gaming platforms One Highwood Drive, Tewksbury, MA 01876 Tel: +1(978)-640-0011 www.chilsemi.com © 2010 CHiL Semiconductor Corp. All rights reserved CHL8112A/B PRODUCT BRIEF DIGITAL MULTI-PHASE BUCK CONTROLLER 12V V TYPICAL APPLICATIONS BLOCK DIAGRAMS RCSP Rseries 2 3 28 +3.3V 21 PWM1 39 ISEN1 40 IRTN1 RCSM VCC 12V 4 VSEN 5 VRTN 6 RRES 7 V_VGD 12V PWM 2 22 37 ISEN2 38 IRTN2 TSEN Boot CHL8510 HiGate Vcc HVCC Switch LVCC PWM LoGate GND V_CPU_L1 L O A D V Rseries V_VGD CCS V RCS V RTh V 1 Boot CHL8510 HiGate Vcc HVCC Switch LVCC PWM LoGate GND PWM3 9 10 +12V RVIN_1 ISEN3 12V 23 2 V ISEN4 IRTN4 34 15 VR_HOT#1/ VRHOT_ICRIT#2 16 EN V_VGD PWM5 V V V 17 SMB_ALERT# 18 SMB_DIO 19 SMB_CLK 30 RCSP_L2 ISEN5 IRTN5 Boot CHL8510 HiGate Vcc HVCC Switch LVCC PWM LoGate GND 33 +3.3V SMBus 12V 24 V V V V CPU Serial Bus PWM4 17 NC1/VFIXEN2 18 NC1/SVD2 19 NC1/SVC2 V_VGD V RVIN_2 V 11 VINSEN From System Boot CHL8510 HiGate Vcc HVCC Switch LVCC PWM LoGate GND 35 VR_RDY_L1 /PWRGD IRTN3 36 VR_RDY_L21/PWROK2 1 V_VGD V CHL8112A 8 V18A V RTh2 25 Boot CHL8510 HiGate Vcc HVCC Switch LVCC PWM LoGate GND V_CPU_L2 L O A D 31 32 Rseries RCS Rseries CCS 29 27 26 12V V RTh RCSM_L2 Boot CHL8510 HiGate Vcc HVCC Switch LVCC PWM LoGate GND VAR_GATE_ 20 PM_ADDR VSEN_L2 V_VGD VRTN_L2 Notes 1 Pin definition in MPoL mode 2 Pin definition in AMD mode Optional Variable Gate Drive Circuit GND ORDERING INFORMATION CHL8112 - T: Tape & Reel Package type R : QFN Operating Temperature C: Commercial Standard Range R Configuration : QFN xx: file Package QFN QFN QFN QFN Tape & Reel Qty 3000 3000 3000 3000 Part Number 1 CHL8112A-00CRT 2 CHL8112A-xxCRT 1 CHL8112B-00CRT 2 CHL8112B-xxCRT Notes 1. For unprogrammed/default parts, use configuration file 00. Unprogrammed parts will not start up until programmed in order to insure a safe power up. 2. -xx indicates a customer specific configuration file Part A: CHL8112A B: CHL8112B Page 2 of 2 PB0012 Rev. 0.04, August 25, 2010