AD ADD8754 Lcd panel power, vcom, and gate modulation Datasheet

LCD Panel Power, VCOM,
and Gate Modulation
ADD8754
FEATURES
FUNCTIONAL BLOCK DIAGRAM
COMP
SS
VIN_1 VIN_2
ADD8754
FB
STEP-UP SWITCHING
REGULATOR
FREQ
LX
SHDN
UNDER VOLTAGE LOCKOUT
AND THERMAL PROTECTION
LOGIC VOLTAGE
REGULATOR
LDO_OUT
ADJ
VDD_2
POS
VCOM AMPLIFIER
OUT
NEG
APPLICATIONS
GATE PULSE
MODULATION
TFT LCD panels for monitors, TVs, and notebooks
VGH
VGH_M VDD_1 CE RE VFLK
VDPM
05110-001
Step-up switching regulator with 2 A power switch
650 kHz or 1.2 MHz switching frequency
Output adjustable to 20 V
350 mA logic voltage regulator
Selectable output voltages: 2.5 V, 2.85 V, 3.3 V
VCOM amplifier with 300 mA drive
Gate pulse modulation circuitry
Independently adjustable delay and falling slope
General
3 V to 5.5 V input
Undervoltage lockout
Thermal shutdown
24-lead, Pb-free LFCSP package
Figure 1.
GENERAL DESCRIPTION
The ADD8754 is optimized for use in TFT LCD applications,
requiring only external charge pump components to provide all
the requirements for panel power, VCOM, and gate modulation.
Included in a single chip are a high frequency step-up dc-to-dc
switching regulator, logic voltage regulator, VCOM amplifier, and
gate pulse modulation circuitry.
The step-up dc-to-dc converter provides up to 20 V output and
includes a 2 A internal switch. Either a 650 kHz or 1.2 MHz stepup switching regulator frequency can be chosen, allowing easy
filtering and low noise operation. It achieves 93% efficiency and
features soft start to limit the inrush current at startup.
The internal voltage regulator operates with an input voltage
range of 3 V to 5.5 V and delivers a load current of up to
350 mA. Three selectable output voltages are available: 2.5 V,
2.85 V, and 3.3 V.
The proprietary VCOM amplifier can deliver a peak output
current of 300 mA and is specifically designed to drive TFT
panel loads.
The gate pulse modulator allows shaping of the TFT gate high
voltage to improve image quality. The integrated switches
provide the ability to independently control the delay and slope
for the gate drive voltage.
The ADD8754 is offered in a 24-lead, Pb-free LFCSP package and
is specified over the industrial temperature range of −40 to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2005 Analog Devices, Inc. All rights reserved.
ADD8754
TABLE OF CONTENTS
Specifications..................................................................................... 3
Current-Mode, Step-Up Switching Regulator Operation..... 12
Step-Up Switching Regulator Specifications............................. 3
VCOM Amplifier ........................................................................... 16
LDO Regulator Specifications .................................................... 4
Gate Pulse Modulator Circuit................................................... 16
VCOM Amplifier Specifications .................................................... 5
Power-Up Sequence ................................................................... 17
Gate Pulse Modulator Specifications ......................................... 6
Shutdown..................................................................................... 17
General Specifications ................................................................. 6
UVLO........................................................................................... 17
Absolute Maximum Ratings............................................................ 7
Power Dissipation....................................................................... 18
ESD Caution.................................................................................. 7
Layout Guidelines....................................................................... 19
Pin Configuration and Function Descriptions............................. 8
Typical Application Circuits ......................................................... 20
Typical Performance Characteristics ............................................. 9
Outline Dimensions ....................................................................... 25
Theory of Operation ...................................................................... 12
Ordering Guide .......................................................................... 25
REVISION HISTORY
4/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADD8754
SPECIFICATIONS
STEP-UP SWITCHING REGULATOR SPECIFICATIONS
VIN_1 = VIN_2 = SHDN = 5 V, VOUT1 = VDD_1 = VDD_2 = 14 V, TA = 25°C, FREQ = GND, unless otherwise noted.
Table 1.
Parameter
SUPPLY
Input Voltage Range
OUTPUT 1
Output Voltage Range
Load Regulation
Line Regulation
Load Regulation
Line Regulation
Overall Regulation
REFERENCE
Feedback Voltage
ERROR AMPLIFIER
Transconductance
Gain
Input Bias Current
SWITCH
On Resistance
Leakage Current
Peak Current Limit
OSCILLATOR
Oscillator Frequency
Maximum Duty Cycle
SOFT START
Peak Current
1
Symbol
Conditions
Min
VIN
Typ
3.0
VOUT1
10 mA ≤ ILOAD ≤ 150 mA, VOUT1 = 10 V
ILOAD = 350 mA, 4.5 V ≤ VIN_1 ≤ 5.5 V
10 mA ≤ ILOAD ≤ 150 mA, VOUT1 = 10 V
ILOAD = 150 mA, 3.0 V ≤ VIN_1 ≤ 5.5 V
Line, load, temperature (−40°C ≤ TA ≤ +85°C)
VFB
RDS (ON)
ILKG
ICL
FOSC
DMAX
Unit
5.5
V
20
+3
V
μV/mA
mV
μV/mA
mV
%
1.220
V
200
200
−3
1.200
GMEA
AV
IB
Max
1.211
100
1000
225
μA/V
V/V
nA
VLX = 14 V, SHDN = GND
170
0.5
2.6
mΩ
μA
A
FREQ = GND
FREQ = VIN_1
VFB = 1 V
650
1.2
90
kHz
MHz
%
SS = GND
2.5
Refer to the Figure 23.
Rev. 0 | Page 3 of 28
95
μA
ADD8754
LDO REGULATOR SPECIFICATIONS
VIN_1 = VIN_2 = SHDN = 5 V, ADJ = LDO_OUT, 1 CLDO = 2.2 μF, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
INPUT
Input Voltage Range
VIN 2
ADJ = LDO_OUT1
ADJ = OPEN 3
ADJ = GND
4
Typ
Max
Unit
3.0
5.5
V
3.35
5.5
V
3.8
5.5
V
OUTPUT
Output Voltage
LDO_OUT
ILDO = 1 mA, ADJ = GND
3.31
V
ILDO = 350 mA, ADJ = GND
3.29
V
ILDO = 1 mA, ADJ = OPEN
2.86
V
ILDO = 350 mA, ADJ = OPEN
2.84
V
ILDO = 1 mA, ADJ = LDO_OUT
2.51
V
ILDO = 350 mA, ADJ = LDO_OUT
2.49
V
Voltage Accuracy
ILDO = 1 mA to 350 mA, −40°C ≤ TA ≤ +85°C
Line Regulation
ILDO = 1 mA
3
mV/V
Load Regulation
ILDO = 1 mA to 350 mA
20
mV
Dropout Voltage
VDROP
Current Limit
ILDPK
LDO_OUT = 98% of LDO_OUT(NOM), ILDO = 350 mA
−3
+3
300
350
1
Sets LDO_OUT(NOM) to 2.5 V.
VIN = VIN_1 = VIN_2.
3
Sets LDO_OUT(NOM) to 2.85 V.
4
Sets LDO_OUT(NOM) to 3.3 V.
2
Rev. 0 | Page 4 of 28
500
%
mV
mA
ADD8754
VCOM AMPLIFIER SPECIFICATIONS
VIN_1 = VIN_2 = SHDN = 5 V, VDD_2 = 14 V, POS = 4.0 V, NEG = OUT, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
INPUT CHARACTERISTICS
Min
Typ
Max
Unit
19
50
300
mV
nA
VOS
IB
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
VCM = 2 V to (VDD_2 − 3) V
60
V
dB
VOH
IOUT (source) = 50 mA
VDD_2 − 0.5
V
VOL
IOUT (sink) = 50 mA
50
mV
±300
mA
Output Current 1
POWER SUPPLY
Supply Voltage
Power Supply Rejection Ratio
Supply Current
DYNAMIC PERFORMANCE
Slew Rate 2
Gain Bandwidth
2
Conditions
Offset Voltage
Noninverting Input Bias Current
OUTPUT CHARACTERISTICS
Output Voltage Swing
1
Symbol
2
IOUT
VDD_2
PSRR
7.5 V ≤ VDD_2 ≤ 18.5 V
70
V
dB
ISY
No load, POS = VDD_2 /2
2
mA
SR
GBW
RL = 10 kΩ, CL = 10 pF
−3 dB, RL = 10 kΩ, CL = 10 pF
105
1.95
V/μs
MHz
Not short-circuit protected.
Slew rate is the average of the rising and the falling slew rates.
Rev. 0 | Page 5 of 28
8
65
VDD_2 − 3
18
ADD8754
GATE PULSE MODULATOR SPECIFICATIONS
VIN_1 = VIN_2 = SHDN = 5 V, VGH = 20 V, VDD_1 = 14 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter
Symbol
Condition
INPUT CHARACTERISTICS
VGH Voltage
VGH Input Current
VDD_1 Voltage
VGH
IVGH
VFLK = GND, VDPM = LDO_OUT
VDD_1 Input Current
IVDD_1
VFLK = VDPM = LDO_OUT
7
VLOWFLK
VHIGHFLK
IFLK
VLOWDPM
VHIGHDPM
IVDPM
SWITCHING CHARACTERISTICS
VGH to VGH_M On Resistance
VGH_M Discharge Current 1
DELAY CHARACTERISTICS
Delay Time 2
2
Typ
Max
Unit
30
V
μA
V
95
7
CONTROL INPUT CHARACTERISTICS
VFLK Voltage Low
VFLK Voltage High
VFLK Input Current
VDPM Voltage Low
VDPM Voltage High
VDPM Input Current
1
Min
VGH
0.02
μA
0.8
0.9 ≤ VFLK ≤ LDO_OUT
2.2
−1
0.9 ≤ VDPM ≤ LDO_OUT
2.2
−1
V
V
μA
V
V
μA
+1
0.8
+1
RVGH
IVGH_M
VDPM = VFLK = LDO_OUT
VFLK < 0.8 V, RE = 33 kΩ
60
8.0
Ω
mA
TDELAY
CE = 470 pF, RE = 33 kΩ
1.88
μs
Discharge current = 302.5/(RE + 5000).
Delay time = CE × 4200.
GENERAL SPECIFICATIONS
VIN_1 = VIN_2 = SHDN = 5 V, TA = 25°C, unless otherwise noted.
Table 5.
Parameter
Symbol
SHUTDOWN
Input Voltage Low
VIL
Input Voltage High
VIH
Conditions
GND ≤ SHDN ≤ 5.5 V
Total Ground Current
SHDN = GND
SHDN = GND
VUVLOR
VUVLOF
Typ
Max
Unit
0.8
V
V
+1
μA
μA
+1
μA
2.2
Shutdown Pin Input Current
Total VIN Current (IVIN_1 + IVIN_2)
UNDERVOLTAGE LOCKOUT
UVLO Rising Threshold
UVLO Falling Threshold
QUIESCENT CURRENT
Step-Up Regulator in Nonswitching State
Step-Up Regulator in Switching State
Min
VIN_1 rising
VIN_1 falling
IQ
IQSW
−1
2.0
−1
2.8
2.6
300
2
Rev. 0 | Page 6 of 28
V
V
500
3
μA
mA
ADD8754
ABSOLUTE MAXIMUM RATINGS
TA= 25°C, unless otherwise noted.
Table 6.
Parameter
RE, CE, FB, SHDN, VIN_2, FREQ,
COMP, SS, VIN_1, LDO_OUT,
ADJ, VDPM, VFLK to GND,
PGND, and AGND
OUT, NEG and POS to GND,
PGND, and AGND
LX to GND, PGND, and AGND
VDD_2 and OUT to GND, PGND,
and AGND
Voltage Between GND and
AGND, GND and PGND, and
AGND and PGND
VDD_1, VGH, and VGH_M to
GND, PGND, and AGND
Differential Voltage Between
POS and NEG
Package Power Dissipation
Thermal Resistance
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Reflow Peak Temperature
(20 sec to 40 sec)
Symbol
Rating
−0.5 V to +6.5 V
−0.5 V to +16 V
−0.5 V to +22 V
−0.5 V to +18.5
V
±0.5 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination.
−0.5 V to +32 V
±5 V
PD
θJA
TJ max
TA
TS
(TJ max − TA)/θJA
38°C/W
125°C
−40°C to +85°C
−65°C to +150°C
250°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 7 of 28
ADD8754
VGH
RE
CE
PGND
FB
SHDN
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24
23
22
21
20
19
GND 1
18
LX
VGH_M 2
17
VIN_2
COMP
VDD_1 5
14
SS
VDD_2 6
13
VIN_1
OUT
7
8
9
10
11
12
05110-002
15
LDO_OUT
TOP VIEW
(Not to Scale)
VFLK
ADJ
FREQ
VDPM 4
AGND
16
POS
ADD8754
NEG
3
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin
1
2
3
Mnemonic
GND
VGH_M
VFLK
4
VDPM
5
6
7
8
9
10
11
12
13
14
VDD_1
VDD_2
OUT
NEG
POS
AGND
ADJ
LDO_OUT
VIN_1
SS
15
COMP
16
FREQ
17
VIN_2
18
LX
19
SHDN
20
21
22
23
24
FB
PGND
CE
RE
VGH
Description
Ground.
Gate Pulse Modulator Output. This pin supplies the gate drive signal.
Gate Pulse Modulator Control Input.
Gate Pulse Modulator Enable. VGH_M is enabled when the voltage on this pin is more than 2.2 V. VGH_M goes to
GND when this pin is connected to GND.
Gate Pulse Modulator Low Voltage Input.
VCOM Amplifier Supply.
VCOM Amplifier Output.
Inverting Input of VCOM Amplifier.
Noninverting Input of VCOM Amplifier.
Analog Ground.
LDO Output Voltage Select. Refer to Table 13 for details.
LDO Output.
Supply Input. This pin supplies power to the LDO and step-up switching regulator. Typically connected to VIN_2.
Soft Start. A capacitor must be connected between GND and this pin to set the soft start time.
Compensation for the Step-Up Converter. A capacitor and resistor are connected in series between GND and this
pin for stable operation.
Frequency Select. Set the switching frequency with a logic level. The step-up switching regulator operates at 650 kHz
when this pin is connected to GND and at 1.2 MHz when connected to VIN_1.
Step-Up Switching Regulator Power Supply. This pin supplies power to the driver for the switch. Typically
connected to VIN_1.
Step-Up Switching Regulator Switch Node.
Device Shutdown Pin. This pin allows users to shut the device off when connected to GND. The normal operating
mode is to pull this pin to VIN_1.
Feedback Voltage Sense to Set the Output Voltage of the Step-Up Switching Regulator.
Step-Up Switching Regulator Power Ground.
GPM Time Delay. A capacitor must be connected between GND and this pin to set the delay time.
GPM Negative Ramp Rate. A resistor must be connected between GND and this pin to set the negative ramp rate.
Gate Pulse Modulator High Voltage Input.
Rev. 0 | Page 8 of 28
ADD8754
TYPICAL PERFORMANCE CHARACTERISTICS
100
2.90
FREQ = GND
90
2.85
ADJ = OPEN
80
70
OUTPUT VOLTAGE (V)
2.80
FREQ = VIN
VIN = 5V
VOUT = 10V
60
50
40
30
2.70
2.65
2.60
2.55
10
1
10
100
ADJ = LDO_OUT
2.50
2.45
1k
ILOAD (mA)
0
50
100
150
05110-050
05110-049
20
0
2.75
200
250
300
350
400
LOAD CURRENT (mA)
Figure 3. Efficiency vs. Load Current (mA)
Figure 6. LDO Output Voltage vs. Load Current, VIN = 3.3 V
3.4
T
3.3
OUTPUT VOLTAGE (V)
ADJ = GND
1
CH1 = VOUT 5V/DIV
CH2 = IL 1A/DIV
CH3 = SD 5V/DIV
3.2
3.1
3.0
2.9
05110-026
2
3
2.8
ADJ = OPEN
0
50
100
150
200
05110-051
VIN = 5V
VOUT = 10V
IOUT = 200mA
CSS = 0F
250
300
350
400
LOAD CURRENT (mA)
Figure 7. LDO Output Voltage vs. Load Current, VIN = 5 V
Figure 4. Start-Up Response from Shutdown, CSS = 0 F
6
5
T
SD PIN
4
CH1 = VOUT 5V/DIV
CH2 = IL 1A/DIV
CH3 = SD 5V/DIV
VOLTS (V)
1
VIN = 5V
VOUT = 10V
IOUT = 200mA
CSS = 10nF
3
2
2.2μF
OUTPUT
CAP
750nF
OUTPUT
CAP
10μF OUTPUT
CAP
1
05110-027
3
–1
–80
05110-052
0
2
–40
0
40
80
120
160
200
240
TIME (μs)
Figure 8. LDO Power-Up Response from Shutdown
Figure 5. Start-Up Response from Shutdown, CSS = 10 F
Rev. 0 | Page 9 of 28
280
ADD8754
6
3.32
5
ADJ = GND
3.28
750nF
OUTPUT
CAP
3
3.26
VOUT = 20mV/DIV
2
2.2μF OUTPUT
CAP
0
10μF OUTPUT
CAP
–1
–80
–40
0
40
80
400
ILOAD (mA)
120
160
200
240
200
05110-056
1
05110-053
VOLTS (V)
LOAD STEP FROM 30kΩ TO 10Ω
3.30
VOUT (V)
SD PIN
4
T
IOUT = 200mA/DIV
280
0
TIME (μs)
Figure 9. LDO Power-Up Response from Shutdown
Figure 12. LDO Load Transient Response, VOUT = 3.3 V
6
5
T
4
VIN (V)
3
VIN LOW = 3.8V
2
4V
3V
VOUT (V)
0
10μF OUTPUT
CAP
–1
–80
–40
0
40
80
120
160
200
240
2V
ADJ = GND
1V
280
05110-057
1
2.2μF OUTPUT
CAP
750nF
OUTPUT
CAP
05110-054
VOLTS (V)
VIN HIGH = 5.5V
SD PIN
TIME (μs)
Figure 10. LDO Power-Up Response from Shutdown
Figure 13. LDO Line Transient Response, VOUT = 3.3 V
2.52
ADJ = LDO_OUT
2.50
VOUT (V)
T
VIN HIGH = 5.5V
2.48
VIN (V)
2.46
VOUT = 20mV/DIV
VIN LOW = 3.8V
4V
300
3V
IOUT = 100mA/DIV
0
2.5V
2V
VOUT (V)
ADJ = LDO_OUT
1V
05110-058
100
05110-055
200
ILOAD (mA)
100μs
Figure 11. LDO Load Transient Response, VOUT = 2.5 V
Figure 14. LDO Line Transient Response, VOUT = 2.5 V
Rev. 0 | Page 10 of 28
ADD8754
5.0
T
Δ: 8.00V
@: 5.04V
4.5
Δ: 102ns
@: –83.2ns
4.0
DELAY TIME (μs)
3.5
0kΩ
3.0
2.5
5kΩ
2.0
10kΩ
1.5
50kΩ
0.5
05110-059
1
Ch1
2.00 V
M 40.0ns
A Ch1
0
12.0 V
Δ: 8.08V
@: 9.08V
Δ: 60.8ns
@: 1.88μs
05110-060
1
M 40.0ns
A Ch1
100
200
300
400
500
600
Figure 17. GPM Delay Time vs. CE Capacitance
T
2.00 V
0
CAPACITANCE CE (pF)
Figure 15. VCOM Rising Slew Rate, VDD_2 = 14 V
Ch1
25kΩ
05110-061
1.0
5.16 V
Figure 16. VCOM Falling Slew Rate, VDD_2 = 14 V
Rev. 0 | Page 11 of 28
700
ADD8754
THEORY OF OPERATION
COMP
SS
VIN_1
VIN_2
A 20 nF soft start capacitor results in negligible input-current
overshoot at startup, making it suitable for most applications.
However, if an unusually large output capacitor is used, a longer
soft start period is required to prevent large input inrush current.
ADD8754
REF
BIAS
gm
FB
FREQ
LX
F/F
R
SLOPE
COMP
Q
OSC
Table 8. Typical Soft Start Period
S
VIN (V)
3.3
3.3
3.3
3.3
5
5
5
5
SHDN
PGND
UVLO AND
THERMAL
PROTECTION
VIN_1
LDO_OUT
VDD_2
ADJ
REF
AGND
GND
VDD_2
POS
VOUT (V)
9
9
12
12
9
9
12
12
COUT (μF)
10
10
10
10
10
10
10
10
CSS (nF)
20
100
20
100
20
100
20
100
tSS (ms)
2.5
8.2
3.5
15
0.4
1.5
0.62
2
VCOM
OUT
NEG
On/Off Control
AGND
VGH VGH_M VDD_1 CE
RE
VFLK VDPM
05110-048
GATE HIGH
MOD. CIRCUIT
Figure 18. Detailed Functional Block Diagram
CURRENT-MODE, STEP-UP SWITCHING
REGULATOR OPERATION
The ADD8754 uses current mode to regulate the output
voltage. This current-mode regulation system allows fast
transient response while maintaining a stable output voltage. By
selecting the proper resistor-capacitor network from COMP to
GND, the regulator response can be optimized for a wide range
of input voltages, output voltages, and load conditions.
Frequency Selection
The ADD8754’s frequency is user-selectable to operate either at
650 kHz to optimize the regulator for high efficiency or at
1.2 MHz for small external components. Connect FREQ to
VIN_2 for 1.2 MHz operation, or connect FREQ to GND for
650 kHz operation.
The SHDN input turns the ADD8754 on or off. When the stepup dc-to-dc converter is turned off, there is a dc path from the
input to the output through the inductor and output diode. This
causes the output voltage to remain slightly below the input
voltage by the forward voltage of the diode, preventing the
output voltage from dropping to zero when the regulator is shut
down. See Figure 25 for the typical application circuit to
disconnect the output voltage from the input voltage at
shutdown.
Setting the Output Voltage
The ADD8754 features an adjustable output voltage range of
(VIN + 2 V) to 20 V. The output voltage is set by the resistive
voltage divider from the output voltage (VOUT) to the 1.21 V
feedback input at FB. Use the following formula to determine
the output voltage:
VOUT = 1.21 V × (1 + R1/R2)
(1)
Use an R2 resistance of 10 kΩ or less to prevent output voltage
errors due to the 10 nA FB input bias current. Choose R1 based
on the following formula:
Soft Start Capacitor
The voltage at SS ramps up slowly by charging the soft start
capacitor (CSS) with an internal 2.5 μA current source. Table 8
lists the values for the soft start period based on maximum
output current and maximum switching frequency.
The soft start capacitor limits the rate of voltage rise on the
COMP pin, which in turn limits the peak switch current at
startup. Table 8 shows a typical soft start period, tSS, at the
maximum output current, IOUT_MAX, for several conditions.
⎛V
− 1.21 V
R1 = R2 × ⎜ OUT
⎜
1.21 V
⎝
⎞
⎟
⎟
⎠
For example, R1 = 75.8 kΩ
with VOUT = 10 V and R2 = 10 kΩ
Rev. 0 | Page 12 of 28
(2)
ADD8754
The inductor ripple current (ΔIL) in steady state is
Inductor Selection
The inductor is an integral part of the step-up converter. It
stores energy during the switch-on time and transfers that
energy to the output through the output diode during the
switch-off time. Use inductance in the range of 1 μH to 22 μH.
In general, lower inductance values have higher saturation
current and lower series resistance for a given physical size.
However, lower inductance results in higher peak current,
which can lead to reduced efficiency and greater input and/or
output ripple and noise. Peak-to-peak inductor ripple current at
close to 30% of the maximum dc input current typically yields
an optimal compromise.
For determining the inductor ripple current, the input (VIN) and
output (VOUT) voltages determine the switch duty cycle (D) by
the following equation:
D=
VOUT − V IN
(3)
VOUT
ΔIL =
D
f SW
(5)
L
Solving for the inductance value, L,
L=
V IN × t ON
(6)
ΔI L
Make sure that the peak inductor current (the maximum input
current plus half of the inductor ripple current) is less than the
rated saturation current of the inductor. In addition, ensure that
the maximum rated rms current of the inductor is greater than
the maximum dc input current to the regulator.
For duty cycles greater than 50% that occur with input voltages
greater than half the output voltage, slope compensation is
required to maintain stability of the current-mode regulator.
For stable current-mode operation, ensure that the selected
inductance is equal to or greater than LMIN:
Using the duty cycle and switching frequency, fSW, determine
the on time by using the following equation:
tON =
V IN × t ON
L > L MIN =
VOUT − V IN
(7)
1.8 A × f SW
(4)
Table 9. Inductor Manufacturers
Vendor
Sumida
www.sumida.com
Coilcraft
www.coilcraft.com
Toko
www.tokoam.com
Part
CMD4D11-2R2MC
CMD4D11-4R7MC
CDRH4D28-100
CDRH5D18-220
CR43-4R7
CR43-100
DS1608-472
DS1608-103
D52LC-4R7M
D52LC-100M
L (μH)
2.2
4.7
10
22
4.7
10
4.7
10
4.7
10
Rev. 0 | Page 13 of 28
Max DC Current
0.95
0.75
1.00
0.80
1.15
1.04
1.40
1.00
1.14
0.76
Max DCR (mΩ)
116
216
128
290
109
182
60
75
87
150
Height (mm)
1.2
1.2
3.0
2.0
3.5
3.5
2.9
2.9
2.0
2.0
ADD8754
Choosing the Input and Output Capacitors
Diode Selection
The ADD8754 requires input and output bypass capacitors to
supply transient currents while maintaining a constant input
and output voltage. Use a low effective series resistance (ESR)
10 μF or greater input capacitor to prevent noise at the
ADD8754 input. Place the capacitors between VIN_1, VIN_2,
and GND and as close as possible to the ADD8754. Ceramic
capacitors are preferred because of their low ESR characteristics. Alternatively, use a high value, medium ESR capacitor in
parallel with a 0.1 μF low ESR capacitor as close as possible to
the ADD8754.
The output diode conducts the inductor current to the output
capacitor and load while the switch is off. For high efficiency,
minimize the forward voltage drop of the diode. Schottky
diodes are recommended. However, for high voltage, high
temperature applications, where the Schottky diode reverse
leakage current becomes significant and can degrade efficiency,
use an ultrafast junction diode.
The output capacitor maintains the output voltage and supplies
current to the load while the ADD8754 switch is on. The value
and characteristics of the output capacitor greatly affect the
output voltage ripple and stability of the regulator. Use a low
ESR output capacitor; ceramic dielectric capacitors are
preferred.
For very low ESR capacitors such as ceramic capacitors, the
ripple current due to the capacitance is calculated as follows.
Because the capacitor discharges during the on time, tON, the
charge removed from the capacitor, QC, is the load current
multiplied by the on time. Therefore, the output voltage ripple
(ΔVOUT) is
ΔVOUT =
QC
C OUT
=
I L × t ON
C OUT
where:
COUT is the output capacitance.
IL is the average inductor current.
D
t ON =
f SW
V
− V IN
D = OUT
VOUT
(8)
I L × (VOUT − V IN )
f SW × VOUT × ΔVOUT
D MIN =
VOUT − V IN _ MAX
(12)
VOUT
where VIN_MAX is the maximum input voltage.
For example, DMIN = 0.45 when VOUT = 10 V and VIN_MAX = 5.5 V
Table 11. Schottky Diode Manufacturers
Vendor
ON Semiconductor
Web Address
www.onsemi.com
Diodes, Inc.
www.diodes.com
Central Semiconductor Corp.
www.centralsemi.com
Sanyo
www.sanyovideo.com
Loop Compensation
(9)
(10)
Choose the output capacitor based on the following equation:
C OUT ≥
The diode must be rated to handle the average output load
current. Many diode manufacturers derate the current
capability of the diode as a function of the duty cycle. Verify
that the output diode is rated to handle the average output load
current with the minimum duty cycle. The minimum duty cycle
of the ADD8754 is
Use of external components to compensate the regulator loop
allows optimization of the loop dynamics for a given application.
A step-up converter produces an undesirable right-half plane
zero in the regulation feedback loop. This requires compensating the regulator such that the crossover frequency occurs well
below the frequency of the right-half plane zero. The right-half
plane zero is determined by the following equation:
(11)
⎛ V
FZ (RHP ) = ⎜⎜ IN
⎝ VOUT
2
⎞
R
⎟ × LOAD
⎟ 2π × L
⎠
Table 10. Capacitor Manufacturers
Vendor
AVX
Murata
Sanyo
Taiyo Yuden
Web Address
www.avxcorp.com
www.murata.com
www.sanyovideo.com
www.t-yuden.com
where:
FZ(RHP) is the right-half plane zero.
RLOAD is the equivalent load resistance, or the output voltage
divided by the load current.
Rev. 0 | Page 14 of 28
(13)
ADD8754
The regulator loop gain is
AVL
V
V
= FB × IN × G MEA × Z COMP × G CS × Z OUT
VOUT VOUT
(14)
where:
AVL is the loop gain.
VFB is the feedback regulation voltage, 1.210 V.
VOUT is the regulated output voltage.
VIN is the input voltage.
GMEA is the error amplifier transconductance gain.
ZCOMP is the impedance of the series RC network from COMP to
GND.
GCS is the current sense transconductance gain (the inductor
current divided by the voltage at COMP), which is internally set
by the ADD8754.
ZOUT is the impedance of the load and output capacitor.
To determine the crossover frequency, it is important to note
that at that frequency the compensation impedance (ZCOMP) is
dominated by the resistor and the output impedance (ZOUT) is
dominated by the impedance of the output capacitor. Therefore,
when solving for the crossover frequency, (by definition of the
crossover frequency) the equation is simplified to
AVL =
V
VFB
1
× IN × GMEA × RC × GCS ×
=1
VOUT VOUT
2π × f C × COUT
(15)
where:
fC is the crossover frequency.
RC is the compensation resistor.
Solving for RC,
RC =
2π × f C × C OUT × VOUT × VOUT
For VFB = 1.21 V, GMEA = 100 μs, and GCS = 2 sec,
RC =
2.55 × 10 4 × f C × C OUT × VOUT × VOUT
V IN
(17)
Once the compensation resistor is known, set the zero formed
by the compensation capacitor and resistor to one-fourth of the
crossover frequency, or
CC =
2
π × f C × RC
(18)
where CC is the compensation capacitor.
ERROR AMP
REF
GMEA
FB
RC
C2
CC
05110-007
To stabilize the regulator, make sure that the regulator crossover
frequency is less than or equal to one-fifth of the right-half
plane zero and less than or equal to one-fifteenth of the
switching frequency.
Figure 19. Compensation Components
The capacitor C2 is chosen to cancel the zero introduced by
output capacitance ESR.
Solving for C2,
C2 =
ESR × C OUT
(19)
RC
For low ESR output capacitance, such as with a ceramic capacitor, C2 is optional. For optimal transient performance, the RC
and CC might need to be adjusted by observing the load
transient response of the ADD8754. For most applications, the
compensation resistor should be in the range of 30 kΩ to
400 kΩ, and the compensation capacitor should be in the range
of 100 pF to 1.2 nF. Table 12 shows external component values
for several applications.
(16)
V FB × V IN × G MEA × G CS
Table 12. Recommended External Components for Various Input/Output Voltage Conditions
VIN (V)
5
VOUT (V)
9
fSW
650 kHz
L (μH)
10
COUT (μF)
10
CIN (μF)
10
R1 (kΩ)
63.4
R2 (kΩ)
10
RC (kΩ)
84.5
Cc (pF)
390
IOUT_MAX (mA)
450
5
5
9
12
1.2 MHz
650 kHz
4.7
10
10
10
10
10
63.4
88.7
10
10
178
140
100
220
450
350
5
12
1.2 MHz
4.7
10
10
88.7
10
300
100
350
3.3
3.3
3.3
9
9
12
650 kHz
1.2 MHz
650 kHz
10
4.7
10
10
10
10
10
10
10
63.4
63.4
88.7
10
10
10
71.5
150
130
820
180
420
350
350
250
3.3
12
1.2 MHz
4.7
10
10
88.7
10
280
100
250
Rev. 0 | Page 15 of 28
ADD8754
VCOM AMPLIFIER
The output of the VCOM amplifier is designed to control the
voltage on the VCOM plane of the LCD display. The VCOM
amplifier is designed to source and sink the capacitive pulse
current and ensure stable operation with high load capacitance.
The delay capacitance in farad is calculated using the following
equation:
CE = (Delay Time) × 0.000238
The RE in ohms is calculated using the following equation:
Input Overvoltage Protection
Whenever the input exceeds the supply voltage, attention must
be paid to the input overvoltage characteristics. When an
overvoltage occurs, the amplifier can be damaged, depending
on the voltage level and the magnitude of the fault current.
When the input voltage exceeds the supply voltage by more
than 0.6 V, the internal pin junctions allow current to flow from
the input to the supplies. This input current is not inherently
damaging to the device, provided it is 5 mA or less.
RE =
302
(Slew Rate × Load Capacitance ) − 5000
When the voltage on the VDPM pin is less than the turn-on
threshold value, the CE pin is internally connected to GND to
discharge the delay capacitor.
GATE HIGH
MOD. CIRCUIT
VIN_1
VGH
Short-Circuit Output Conditions
The VCOM amplifier does not have internal short-circuit protection
circuitry. As a precaution, do not short the output directly to the
positive power supply or to the ground.
VDPM
S1
L
O
G
I
C
VFLK
VGH_M
S3
CL
S2
GND
GATE PULSE MODULATOR CIRCUIT
VDD_1
The gate pulse modulator is used for LCD applications in which
shaping of the gate high voltage signal improves image quality.
A charge pump is used to generate the on voltage, VGH. A lower
gate voltage level, VDD_1, is desired during the last portion of
the gate’s on time and is provided by VOUT. The integrated gate
pulse modulator circuit provides control over the slope and delay
of the transition between these two TFT on-voltage levels.
When the control voltage VFLK switches from logic low to logic
high during normal operation with VDPM at logic high (see
Figure 21), the output voltage VGH_M transitions from VDD_1
to VGH. When the control voltage VFK switches from logic
high to logic low, the output voltage VGH_M transitions from
VGH to VDD_1 after a time delay determined by the size of a
capacitor from the CE pin to the GND and a slew rate
determined by the size of resistor from the RE pin to the GND.
GND
CE
RE
RAMP
RESISTOR
05110-008
DELAY
CAPACITOR
GND
Figure 20. Gate Pulse Modulator Functional Block Diagram
ENABLE – VDPM
LOW
SLOPE CONTROLLED BY RE
CONTROL SIGNAL – VFLK
LOW
T1
T2
VGH
OUTPUT SIGNAL – VGH_M
WITH LOAD
CAPACITANCE CL
Rev. 0 | Page 16 of 28
VDD_1
LOW
T1
T2
DELAY CONTROLLED
BY CE
Figure 21. Gate Pulse Modulator Timing Diagram
05110-009
The gate pulse modulator circuit has four input pins (VGH,
VDD_1, VDPM, and VFLK) and one output pin (VGH_M).
VFLK is a digital control signal, usually provided by the timing
controller, whose high or low level determines which of the two
input voltages, VGH or VDD_1, is passed through to VGH_M.
The gate high modulator circuit becomes active when the voltage
on pin VDPM exceeds the turn-on threshold value of 2.2 V.
VOUT/VGH
REF
S4
ADD8754
POWER-UP SEQUENCE
LDO Input Capacitor Selection
Most LCD panels require that when VIN is applied, LDO_OUT,
VGL, BOOST_OUT, VGH, and VGH_M are established
sequentially, as indicated in Figure 22. ADD8754 provides this
sequence with appropriate capacitors for the VGL and VGH
charge pumps.
For the input voltage of the ADD8754 LDO regulator (VIN_1),
a local bypass capacitor is recommended. The input capacitor
provides bypassing for the internal amplifier used in the voltage
regulation loop. Use at least a 1 μF low ESR capacitor. Larger
input capacitance and lower ESR provide better supply noise
rejection. Multilayer ceramic chip (MLCC) capacitors provide
the best combination of low ESR and small size.
VIN
LDO Output Capacitor Selection
SHDN
The output capacitor improves the regulator response to sudden
load changes. The output capacitor helps determine the performance of any LDO. The ADD8754 LDO requires at least a 2.2 μF
capacitor. Transient response is a function of output capacitance,
in that larger values of output capacitance decrease peak deviations, providing improved transient response for large load
current changes.
SHDN THRESHOLD LEVEL
VDPM
VGH_M
VGH
LDO_OUT
Choose the capacitors by comparing their lead inductance, ESR,
and dissipation factor. Output capacitance affects stability, and a
larger cap provides a greater phase margin for the ADD8754
LDO. MLCC capacitors provide the best combination of low
ESR and small size.
05110-010
BOOST_OUT
VGL
Figure 22. Power-Up Sequence Timing Diagram
LDO Regulator
The ADD8754 low dropout (LDO) regulator has three preset
output voltage settings. As shown in Table 13, by tying the ADJ
pin low, a 3.3 V nominal output is selected. By tying ADJ to the
output voltage, a 2.5 V nominal output is selected. By leaving
ADJ as an open circuit, a nominal voltage of 2.85 V is selected.
Table 13. LDO Output Voltage Selection
LDO Output Voltage
2.5 V
2.85 V
3.3 V
ADJ Pin
LDO_OUT
No connection
GND
Note that the capacitance of some capacitor types show wide
variations over temperature. A good quality dielectric X7R or
better capacitor is recommended.
SHUTDOWN
Applying a TTL high signal to the shutdown pin (tying it to the
VIN_1) turns on all outputs. Pulling SHDN down to 0.4 V or
below (tying it to GND) turns off all outputs. In shutdown
mode, quiescent current is reduced to a typical value of 300 μA.
UVLO
An undervoltage lockout (UVLO) circuit is included with a
built in hysteresis. ADD8754 turns on when VIN_1 rises above
2.8 V and shuts down when VIN_1 falls below 2.6 V.
Rev. 0 | Page 17 of 28
ADD8754
POWER DISSIPATION
VCOM Amplifier
The ADD8754’s maximum power dissipation depends on the
thermal resistance from the IC die to the ambient environment
and the ambient temperature. The thermal resistance depends
on the IC package, PC board copper area, other thermal mass,
and airflow. The ADD8754, with the exposed backside pad
soldered to a 2-layer PC board with nine 12 mil-diameter
thermal vias, can dissipate about 1.5 W into 65°C still air before
the die exceeds 125°C. More PC board copper, cooler ambient
air, and more airflow increase the dissipation capability, whereas
less copper or warmer air decreases the IC’s dissipation capability.
The major contributors to the power dissipation are the LDO
regulator and the VCOM amplifier.
The power dissipated in the VCOM amplifier depends on the
output current, the output voltage, and the supply voltage:
Step-Up Converter
The largest portions of power dissipation in the step-up
converter are the internal MOSFET, the inductor, and the output
diode. For a 90% efficiency step-up converter, about 3% to 5% of
the power is lost in the internal MOSFET, about 3% to 4% in the
inductor, and about 1% in the output diode. The rest of the 1%
to 3% is distributed among the input and output capacitors and
the PC board traces. For an input power of about 3 W, the
power lost in the internal MOSFET is about 90 mW to 150 mW.
LDO
The power dissipated in the LDO depends on the output
current, the output voltage, and the supply voltage:
PDSOURCE = IOUT (source) × (VDD_2 − VOUT)
PDSINK = IOUT (sink) × VOUT
where:
IOUT (source) is the output current sourced by the VCOM
amplifier.
IOUT (sink) is the output current that the VCOM amplifier sinks to
AGND.
In a typical case where the supply voltage is 12 V and the output
voltage is 6 V with an output source current of 20 mA, the
power dissipated is 120 mW.
Thermal Overload Protection
Thermal overload protection prevents excessive power dissipation
from overheating the ADD8754. When the junction temperature
exceeds TJ = 145°C, a thermal sensor immediately activates the
fault protection, which shuts down the device, allowing the IC
to cool. The device self-starts once the die temperature falls
below TJ = 105°C.
Thermal overload protection protects the controller in the event
of fault conditions. For continuous operation, do not exceed the
absolute maximum junction temperature rating of TJ = 125°C.
PDLDO = (VIN_1 − LDO_OUT) × ILDO_OUT
Rev. 0 | Page 18 of 28
ADD8754
LAYOUT GUIDELINES
Layout Procedure
When designing a high frequency, switching, regulated power
supply, layout is very important. Using a good layout can solve
many problems associated with these types of supplies. Some of
the main problems are loss of regulation at high output current
and/or large input-to-output voltage differentials, excessive
noise on the output and switch waveforms, and instability.
Using the following guidelines can help minimize these
problems.
To achieve high efficiency, good regulation, and stability, a good
PCB layout is required. It is recommended that the reference
board layout be followed as closely as possible because it is
already optimized for high efficiency and low noise.
Make all power (high current) traces as short, direct, and thick
as possible. It is good practice on a standard PCB board to make
the traces an absolute minimum of 15 mil (0.381 mm) per
Ampere. The inductor, output capacitors, and output diode
should be as close to each other as possible. This helps reduce
the EMI radiated by the power traces that is due to the high
switching currents through them. This also reduces lead
inductance and resistance, which in turn reduce noise spikes,
ringing, and resistive losses that produce voltage errors.
The grounds of the IC, input capacitors, output capacitors, and
output diode (if applicable), should be connected close together,
directly to a ground plane. It is also a good idea to have a ground
plane on both sides of the printed circuit board (PCB). This
reduces noise by reducing ground-loop errors and absorbing
more of the EMI radiated by the inductor.
For multilayer boards of more than two layers, a ground plane
can be used to separate the power plane (power traces and
components) and the signal plane (feedback, compensation,
and components) for improved performance. On multilayer
boards, the use of vias is required to connect traces and different
planes. If a trace needs to conduct a significant amount of current
from one plane to the other, it is good practice to use one standard
via per 200 mA of current. Arrange the components so that the
switching current loops curl in the same direction.
Use the following general guidelines when designing PCBs:
1.
Keep CIN close to the IN and GND leads of the ADD8754.
2.
Keep the high current path from CIN (through L1) to the
SW and PGND leads as short as possible.
3.
Keep the high current path from CIN (through L1), D1,
and COUT as short as possible.
4.
Keep high current traces as short and wide as possible.
5.
Keep nodes connected to SW away from sensitive traces
such as FB or COMP to prevent coupling of the traces. If
these traces need to be run near each other, place a ground
trace between the two as a shield.
6.
Place the feedback resistors as close as possible to the FB pin
to prevent noise pickup.
7.
Place the compensation components as close as possible to
the COMP pin.
8.
Avoid routing noise-sensitive traces near the high current
traces and components.
9.
Use a thermal pad size that is the same as the dimension of
the exposed pad on the bottom of the package.
Heat Sinking
When using a surface-mount power IC or external power
switches, the PCB can often be used as the heat sink. This is
done by simply using the copper area of the PCB to transfer
heat from the device.
Due to the how switching regulators operate, there are two
power states: one state when the switch is on, and one when the
switch is off. During each state, there is a current loop made by
the power components currently conducting. Place the power
components so that the current loop is conducting in the same
direction during each of the two states. This prevents magnetic
field reversal caused by the traces between the two half cycles
and reduces radiated EMI.
Rev. 0 | Page 19 of 28
ADD8754
TYPICAL APPLICATION CIRCUITS
BAV99
R5
1kΩ
D5
C7
1μF
VZ2
BZX84C28
C3
1μF
D3
C2
0.1μF
C6
0.1μF
R9
10Ω
R2
9.5kΩ
C8
0.1μF
5
6
SHDN
FB
PGND
RE
ADD8754
VDPM
COMP
VDD_1
SS
VDD_2
VIN_1
+14V FROM
VOUT
7
8
9
VCOM
+4.0V
C9
1μF
10
11
R3
100kΩ
R4
250kΩ
18
17
VIN
+5V
16
15
RC
180kΩ
14
CSS
10nF
13
CC
470pF
CIN
10μF
12
VLOGIC
+3.3V
CLDO
4.7μF
+14V FROM
VOUT
Figure 23. 1.2 MHz Application Circuit for TFT LCD Panel with Charge Pumps for VGH and VGL
Rev. 0 | Page 20 of 28
RSD
180kΩ
L
10μH
05110-003
R8
100kΩ
FREQ
LDO_
OUT
R7
250kΩ
VFLK
ADJ
4
VOUT
+14V
CSD
10μF
VIN_2
OUT
+14V FROM
VOUT
COUT
20μF
D1
1N5818
19
VGH_M
AGND
3
20
LX
POS
2
21
GND
NEG
1
22
CE
23
VGH
24
R1
100kΩ
CE
390pF
RE
33kΩ
VFLK
C5
0.1μF
D6
D7
C10
0.47μF
VZ1
BZX84C5V1
TO GATE
DRIVER
D2
C1
0.1μF
C4
0.47μF
BAV99
R6
300Ω
VGL
–5V
BAV99
D4
ADD8754
+30V
VGH
VZ2
1N7451A
CVGH
10μF
R2
10kΩ
5
6
SHDN
FB
PGND
RE
ADD8754
VDPM
COMP
VDD_1
SS
VDD_2
VIN_1
+12V FROM
VOUT
7
8
9
10
11
VZ1
BZX84C5V1
VGL
–5V
CVGL
0.1μF
17
16
VIN
+5V
15
RC
180kΩ
14
CSS
10nF
13
CC
470pF
T = TRANSTEK MAGNETICS
TMS60059CS
12
VCOM
+4.0V
C9
1μF
18
D2
1N914
CIN
10μF
LDO_
OUT
C8
0.1μF
FREQ
VFLK
ADJ
R7
250kΩ
R8
100kΩ
VIN_2
AGND
4
COUT
20μF
RVGL
50Ω
VGH_M
OUT
+12V FROM
VOUT
T
19
LX
POS
3
VFLK
20
VOUT
+12V
D1
1N5818
GND
NEG
2
TO GATE
DRIVER
21
RVGH
75Ω
VLOGIC
+3.3V
+12V FROM
VOUT
CLDO
4.7μF
R4 R12
R3
7.5kΩ 1kΩ 4.7kΩ
Figure 24. 1.2 MHz Application Circuit for TFT LCD Display with Transformer for VGH and VGL
Rev. 0 | Page 21 of 28
05110-004
1
22
CE
23
VGH
24
R1
91kΩ
CE
390pF
RE
33kΩ
D3
1N914
ADD8754
VGH
+28V
BAV99
R5
1kΩ
D5
C7
1μF
VZ2
BZX84C28
C3
1μF
D3
C2
0.01μF
D2
C1
0.01μF
C4
0.47μF
C5
0.01μF
BAV99
R6
300Ω
VGL
–5V
BAV99
D4
D6
D7
C10
0.47μF
VZ1
BZX84C5V1
C6
0.1μF
R9
10Ω
R2
9.5kΩ
1
VOUT
+14V
COUT
20μF
SHDN
19
FB
20
PGND
21
CE
22
RE
VGH
23
D1
1N5818
CE
390pF
RE
33kΩ
24
R1
100kΩ
LX
GND
18
L
10μH
CSD
10μF
RSD
180kΩ
FDC6331
6
VDD_1
SS
VDD_2
VIN_1
+14V FROM
VOUT
7
8
9
VCOM
+4.0V
C9
1μF
10
11
17
R10
10kΩ
16
VIN
+5V
15
RC
180kΩ
14
13
CSS
10nF
CC
470pF
CIN
10μF
ENABLE
12
R3
100kΩ
R4
250kΩ
VLOGIC
+3.3V
CLDO
4.7μF
+14V FROM
VOUT
Figure 25. 1.2 MHz Application Circuit for TFT LCD Display with Charge Pumps with Input Power Disconnect Switch
Rev. 0 | Page 22 of 28
05110-005
5
LDO_
OUT
C8
0.1μF
COMP
ADJ
R8
100kΩ
ADD8754
VDPM
AGND
4
R7
250kΩ
FREQ
VFLK
OUT
+14V FROM
VOUT
3
POS
VFLK
VIN_2
VGH_M
NEG
2
TO GATE
DRIVER
ADD8754
VGH
+28V
BAV99
R5
1kΩ
D5
C7
1μF
VZ2
BZX84C28
C3
1μF
D3
C2
0.01μF
C6
0.1μF
R9
10Ω
R2
9.5kΩ
6
SHDN
FB
PGND
RE
ADD8754
VDPM
COMP
VDD_1
SS
VIN_1
VDD_2
+14V FROM
VOUT
7
8
9
VCOM
+4.0V
C9
1μF
10
11
R3
100kΩ
R4
250kΩ
18
L
10μH
17
VIN
+5V
16
15
14
13
CSS
10nF
CIN
10μF
RC
180kΩ
CC
470pF
BOOST AND
CHARGE PUMP
ENABLE
R10
10kΩ
12
VLOGIC
+3.3V
CLDO
4.7μF
+14V FROM
VOUT
Figure 26. 1.2 MHz Application Circuit for TFT LCD Display with LDO_ALWAYS_ ON
Rev. 0 | Page 23 of 28
Q1
2N7000
05110-047
5
FREQ
LDO_
OUT
C8
0.1μF
VFLK
OUT
R8
100kΩ
VIN_2
ADJ
4
D1
1N5818
VGH_M
AGND
3
VFLK
VOUT
+14V
COUT
20μF
19
20
LX
POS
2
TO GATE
DRIVER
21
GND
NEG
1
22
CE
23
VGH
24
R1
100kΩ
CE
390pF
RE
33kΩ
R7
250kΩ
C5
0.01μF
D6
D7
C10
0.47μF
VZ1
BZX84C5V1
+14V FROM
VOUT
D2
C1
0.01μF
C4
0.47μF
BAV99
R6
300Ω
VGL
–5V
BAV99
D4
ADD8754
ADJUSTABLE FROM 3V TO 5V WITH
15mV PER STEP ADJUSTMENT
LDO_
OUT
ADJ
AGND
VOUT
14V
C10
2.2pF
VCOM
4.0V
POS
OUT
NEG
ADD8754
R4
315kΩ
RB
6kΩ
VDD
AD5259BRMZ10
RA
1kΩ
VLOGIC
W
B
SCL
SDA
C9
0.1μF
R10
2.2kΩ
R11
2.2kΩ
SIGNAL FROM FACTORY PC,
SOFTWARE PROVIDED BY ADI
GND AD0 AD1
05110-006
R3
10kΩ
A
Figure 27. ADD8754 with Programmable VCOM
The VCOM calibration for flicker reduction is one of the essential
steps in the panel manufacturing process. In a typical panel
production environment, such a process can take additional
time to complete and, therefore, impacts production throughput.
One additional concern is that a potentiometer typically used
only for calibration offers limited resolution. The resistance can
drift over time and can be noticeable after a few years of operation.
The production throughput, image quality, and panel reliability
concerns can all be solved by using a digital potentiometer. As
shown in Figure 27, AD5259, a low cost 256-step digital potentiometer with nonvolatile memory, can calibrate the ADD8754
VCOM voltage precisely, reliably, and time efficiently.
In the worst case, where the temperature, aging effect, and
resistance tolerance of the AD5259 are all accounted for, the
circuit in Figure 27 makes the VCOM voltage adjustable from
3.0 V to 5.0 V with 15 mV per step adjustment. A micro-
controller or I2C programmer can be used to provide the
control signal for the AD5259, but ADI provides programming
software that simplifies the calibration process. The software
can be installed in the factory computer, and two tester probes
can be connected to the computer’s parallel port to implement the
VCOM programming.
The VCOM voltage can be calculated as
VCOM
D
× R AB + R 3
256
=
× 7 × VOUT
R 4 + R AB + R 3
where:
D is the decimal code of the AD5259 programmable resistance
between the W-to-B terminals.
RAB is the AD5259 nominal resistance.
Rev. 0 | Page 24 of 28
ADD8754
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
PIN 1
INDICATOR
0.60 MAX
TOP
VIEW
0.50
BSC
3.75
BSC SQ
1.00
0.85
0.80
12° MAX
0.30
0.23
0.18
SEATING
PLANE
24 1
19
18
2.25
2.10 SQ
1.95
EXPOSED
PAD
0.50
0.40
0.30
0.80 MAX
0.65 TYP
PIN 1
INDICATOR
(BOTTOM VIEW)
13
12
7
6
0.25 MIN
2.50 REF
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 28. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 × 4 mm Body, Very Thin Quad
(CP-24-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADD8754ACPZ-Reel 1
ADD8754ACPZ-Reel71
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
Z = Pb-free part.
Rev. 0 | Page 25 of 28
Package Option
CP-24-1
CP-24-1
Quantity
5,000
1,500
ADD8754
NOTES
Rev. 0 | Page 26 of 28
ADD8754
NOTES
Rev. 0 | Page 27 of 28
ADD8754
NOTES
©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05110–0–4/05(0)
Rev. 0 | Page 28 of 28