ON MC14517BCP Dual 64−bit static shift register Datasheet

MC14517B
Dual 64−Bit Static Shift
Register
The MC14517B dual 64−bit static shift register consists of two
identical, independent, 64−bit registers. Each register has separate clock
and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data
at the data input is entered by clocking, regardless of the state of the write
enable input. An output is disabled (open circuited) when the write enable
input is high. During this time, data appearing at the data input as well as
the 16−bit, 32−bit, and 48−bit taps may be entered into the device by
application of a clock pulse. This feature permits the register to be loaded
with 64 bits in 16 clock periods, and also permits bus logic to be used.
This device is useful in time delay circuits, temporary memory storage
circuits, and other serial shift register applications.
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MARKING
DIAGRAMS
16
PDIP−16
P SUFFIX
CASE 648
1
MC14516BCP
AWLYYWWG
1
16
Features
•
•
•
•
•
•
•
•
•
Diode Protection on All Inputs
Fully Static Operation
Output Transitions Occur on the Rising Edge of the Clock Pulse
Exceedingly Slow Input Transition Rates May Be Applied to the
Clock Input
3−State Output at 64th−Bit Allows Use in Bus Logic Applications
Shift Registers of any Length may be Fully Loaded with 16 Clock
Pulses
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Symbol
Value
Unit
VDD
−0.5 to +18.0
V
Vin, Vout
−0.5 to VDD
+ 0.5
V
Iin, Iout
± 10
mA
Power Dissipation per Package (Note 1)
PD
500
mW
Operating Temperature Range
TA
−55 to +125
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Lead Temperature (8−Second Soldering)
TL
260
°C
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current (DC or Transient)
per Pin
SOIC−16
DW SUFFIX
CASE 751G
1
14517B
AWLYYWWG
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb−Free Package
1
PIN ASSIGNMENT
Q16A
1
16
VDD
Q48A
2
15
Q16B
WEA
3
14
Q48B
CA
4
13
WEB
Q64A
5
12
CB
Q32A
6
11
Q64B
DA
7
10
Q32B
VSS
8
9
DB
ORDERING INFORMATION
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
Device
Package
Shipping †
MC14517BCP
PDIP−16
25 Units/Rail
MC14517BCPG
PDIP−16
(Pb−Free)
25 Units/Rail
MC14517BDW
SOIC−16
47/Rail
MC14517BDWG
SOIC−16
(Pb−Free)
47/Rail
MC14517BDWR2
SOIC−16
1000/Tape & Reel
MC14517BDWR2G
SOIC−16 1000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 6
1
Publication Order Number:
MC14517B/D
MC14517B
FUNCTIONAL TRUTH TABLE (X = Don’t Care)
Clock
Write
Enable
Data
16−Bit Tap
32−Bit Tap
48−Bit Tap
64−Bit Tap
0
0
X
Content of 16−Bit
Displayed
Content of 32−Bit
Displayed
Content of 48−Bit
Displayed
Content of 64−Bit
Displayed
0
1
X
High Impedance
High Impedance
High Impedance
High Impedance
1
0
X
Content of 16−Bit
Displayed
Content of 32−Bit
Displayed
Content of 48−Bit
Displayed
Content of 64−Bit
Displayed
1
1
X
High Impedance
High Impedance
High Impedance
High Impedance
0
Data entered
into 1st Bit
Content of 16−Bit
Displayed
Content of 32−Bit
Displayed
Content of 48−Bit
Displayed
Content of 64−Bit
Displayed
1
Data entered
into 1st Bit
Data at tap
entered into 17−Bit
Data at tap
entered into 33−Bit
Data at tap
entered into 49−Bit
High Impedance
0
X
Content of 16−Bit
Displayed
Content of 32−Bit
Displayed
Content of 48−Bit
Displayed
Content of 64−Bit
Displayed
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
1
X
High Impedance
High Impedance
High Impedance
High Impedance
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
− 55_C
25_C
VDD
125_C
Symbol
Vdc
Min
Max
Min
Typ
(Note 2)
VOL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
VOH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
−
−
−
−
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
– 1.7
– 0.36
– 0.9
– 2.4
−
−
−
−
IOL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current
Iin
15
−
± 0.1
−
± 0.00001
± 0.1
−
± 1.0
mAdc
Input Capacitance (Vin = 0)
Cin
−
−
−
−
5.0
7.5
−
−
pF
Quiescent Current (Per Package)
IDD
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
Total Supply Current (Note 3, 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT
5.0
10
15
Three−State Leakage Current
ITL
15
Characteristic
Output Voltage
Vin = VDD or 0
“0” Level
“1” Level
Vin = 0 or VDD
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Source
Sink
Max
Min
Max
Unit
VIL
Vdc
VIH
Vdc
IOH
mAdc
IT = (4.2 mA/kHz) f + IDD
IT = (8.8 mA/kHz) f + IDD
IT = (13.7 mA/kHz) f + IDD
± 0.1
−
−
± 0.0001
± 0.1
mAdc
−
± 3.0
mAdc
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF,
V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
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2
MC14517B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic
VDD
Min
Typ
(Note 6)
Max
5.0
10
15
−
−
−
100
50
40
200
100
80
5.0
10
15
−
−
−
475
210
140
770
300
215
tWH
5.0
10
15
330
125
100
170
75
60
−
−
−
ns
fcl
5.0
10
15
−
−
−
3.0
6.7
8.3
1.5
4.0
5.3
MHz
tTLH, tTHL
5.0
10
15
Symbol
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.65 ns/pF) CL + 9.5 ns
tTLH, tTHL
Propagation Delay Time
tPLH, tPHL = (1.7 ns/pF) CL + 390 ns
tPLH, tPHL = (0.66 ns/pF) CL + 177 ns
tPLH, tPHL = (0.5 ns/pF) CL + 115 ns
tPLH, tPHL
Clock Pulse Width
Clock Pulse Frequency
Clock Pulse Rise and Fall Time
Unit
ns
ns
−
See (Note 7)
Data to Clock Setup Time
tsu
5.0
10
15
0
10
15
– 40
– 15
0
−
−
−
ns
Data to Clock Hold Time
th
5.0
10
15
150
75
35
75
25
10
−
−
−
ns
Write Enable to Clock Setup Time
tsu
5.0
10
15
400
200
110
170
65
50
−
−
−
ns
Write Enable to Clock Release Time
trel
5.0
10
15
380
180
100
160
55
40
−
−
−
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
7. When shift register sections are cascaded, the maximum rise and fall time of the clock input should be equal to or less than the rise and fall
time of the data outputs, driving data inputs, plus the propagation delay of the output driving stage.
VDD
D
fo
CL
VSS
D
C
VDD
D
(f = 1/2 fo)
CL
WE
VDD
C
CL
Q16 Q32 Q48 Q64
D
C
C
REPETITIVE WAVEFORM
CL
VSS
WE
Q16 Q32 Q48 Q64
VSS
50 mF
ID
CL
CL
CL
Figure 1. Power Dissipation Test Circuit and Waveform
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3
CL
MC14517B
Vout = VOH
VDD = VGS
Q16 Q32 Q48 Q64
D
C
Vout = VOL
VDD = VGS
Q16 Q32 Q48 Q64
D
C
WE
WE
D
C
D
C
IOH
WE
IOL
WE
Q16 Q32 Q48 Q64
Q16 Q32 Q48 Q64
EXTERNAL
POWER
SUPPLY
VSS
EXTERNAL
POWER
SUPPLY
VSS
(Output being tested should be in the high−logic state)
(Output being tested should be in the low−logic state)
Figure 2. Typical Output Source Current
Characteristics Test Circuit
tWH
PIN NO’S
tWL
1
Figure 3. Typical Output Sink Current
Characteristics Test Circuit
2
16
17
CLOCK 4 (12)
18
90%
19
10%
trel
WRITE 3 (13)
th1
th0
DATA IN 7 (9)
th1
32−BIT OUTPUT 6 (10)
33−BIT INPUT
tsu1
90%
tPHL
tsu0
th0
tsu1
16−BIT OUTPUT 1 (15)
17−BIT INPUT
tsu1
VSS
50%
th1
th1
48−BIT OUTPUT 2 (14)
49−BIT INPUT
tPLH
90%
VDD
tsu0
th0
20 ns
tsu0
th0
20 ns
VDD
50%
VSS
VDD
20 ns
tsu0
tsu1
tsu
33
tPHL
VDD
tPHL
VDD
tTLH
tPLH
90%
tTLH
tPLH
10%
64−BIT OUTPUT 5 (11)
VSS
VOH
VDD
10%
V
tTHL OL
VOH
50%
10%
VOL
tTHL
VOH
VSS
tTLH
tPLH
tPHL
20 ns
VDD
50%
tTLH
tTHL
VDD
VSS
VDD
VSS
VOL
VDD
VSS
tTHL
Figure 4. AC Test Waveforms
EXPANDED BLOCK DIAGRAM (1/2 OF DEVICE SHOWN)
CLOCK
DATA
WRITE
ENABLE
D
C
1
Q
D
C
2
Q
D
Q
C 16
3−STATE
WRITE ENABLE = 0, 16−BIT OUTPUT
WRITE ENABLE = 1, 17−BIT INPUT
D
Q
C 17
WE
D
Q
C 32
3−STATE
32−BIT OUTPUT
33−BIT INPUT
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4
D
Q
C 33
WE
D
Q
C 48
3−STATE
48−BIT OUTPUT
49−BIT INPUT
D
Q
C 49
WE
D
C 64 Q
3−STATE
64−BIT OUTPUT
HIGH IMPEDANCE
MC14517B
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
S
−T−
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
T A
M
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SO−16 WB
CASE 751G−03
ISSUE C
A
D
9
1
8
h X 45 _
E
0.25
16X
M
14X
e
T A
S
B
S
L
A
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MILLIMETERS
DIM MIN
MAX
A
2.35
2.65
A1 0.10
0.25
B
0.35
0.49
C
0.23
0.32
D 10.15 10.45
E
7.40
7.60
e
1.27 BSC
H 10.05 10.55
h
0.25
0.75
L
0.50
0.90
q
0_
7_
B
B
SEATING
PLANE
A1
H
8X
M
B
M
16
q
T
C
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5
MC14517B
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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