STMicroelectronics M48Z12-150PC1 16 kbit 2kb x 8 zeropower sram Datasheet

M48Z02
M48Z12
16 Kbit (2Kb x 8) ZEROPOWER® SRAM
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
UNLIMITED WRITE CYCLES
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48Z02: 4.50V ≤ VPFD ≤ 4.75V
– M48Z12: 4.20V ≤ VPFD ≤ 4.50V
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 2K x 8 SRAMs
24
1
PCDIP24 (PC)
Battery CAPHAT
Figure 1. Logic Diagram
DESCRIPTION
The M48Z02/12 ZEROPOWER® RAM is a 2K x 8
non-volatile static RAM which is pin and functional
compatible with the DS1220.
A special 24 pin 600mil DIP CAPHAT package
houses the M48Z02/12 silicon with a long life lithium button cell to form a highly integrated battery
backed-up memory solution.
The M48Z02/12 button cell has sufficient capacity
and storage life to maintain data and clock functionality for an accumulated time period of at least 10
years in the absence of power over the operating
temperature range.
Table 1. Signal Names
A0-A10
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground
May 1999
VCC
11
8
A0-A10
W
DQ0-DQ7
M48Z02
M48Z12
E
G
VSS
AI01186
1/12
M48Z02, M48Z12
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
TA
TSTG
TSLD
(2)
Value
Unit
Ambient Operating Temperature
–40 to 85
°C
Storage Temperature (VCC Off)
–40 to 85
°C
260
°C
Lead Solder Temperature for 10 seconds
VIO
Input or Output Voltages
–0.3 to 7
V
VCC
Supply Voltage
–0.3 to 7
V
IO
Output Current
20
mA
PD
Power Dissipation
1
W
Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
Mode
VCC
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
Write
Read
Read
E
G
W
DQ0-DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
Deselect
VSO to VPFD (min)
X
X
X
High Z
CMOS Standby
Deselect
≤ VSO
X
X
X
High Z
Battery Back-up Mode
Notes: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Figure 2. DIP Pin Connections
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
24
1
23
2
22
3
21
4
20
5
6
M48Z02 19
M48Z12 18
7
17
8
16
9
15
10
11
14
12
13
AI01187
2/12
VCC
A8
A9
W
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
DESCRIPTION (cont’d)
The M48Z02/12 is a non-volatile pin and function
equivalent to any JEDEC standard 2K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The M48Z02/12 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors the
single 5V supply for an out of tolerance condition.
When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below
approximately 3V, the control circuitry connects the
battery which maintains data and clock operation
until valid power returns.
M48Z02, M48Z12
Figure 3. Block Diagram
A0-A10
LITHIUM
CELL
POWER
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
DQ0-DQ7
2K x 8
SRAM ARRAY
E
VPFD
W
G
VSS
VCC
READ MODE
The M48Z02/12 is in the Read Mode whenever W
(Write Enable) is high and E (Chip Enable) is low.
The device architecture allows ripple-through access of data from eight of 16,384 locations in the
static storage array. Thus, the unique address
specified by the 11 Address Inputs defines which
one of the 2,048 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (tAVQV) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (tELQV) or Output Enable Access time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated
before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
AI01255
Table 4. AC Measurement Conditions
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0V to 3V
Input and Output Timing Ref. Voltages
1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Figure 4. AC Testing Load Circuit
5V
1.8kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
CL includes JIG capacitance
CL = 100pF
AI01019
3/12
M48Z02, M48Z12
Table 5. Capacitance (1)
(TA = 25 °C)
Symbol
CIN
CIO
(2)
Parameter
Test Condition
Input Capacitance
Input / Output Capacitance
Min
Max
Unit
VIN = 0V
10
pF
VOUT = 0V
10
pF
Notes: 1. Effective capacitance measured with power supply at 5V.
2. Outputs deselected
Table 6. DC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
ILI
Parameter
(1)
Input Leakage Current
(1)
Output Leakage Current
ILO
ICC
Supply Current
ICC1
Supply Current (Standby) TTL
ICC2
Supply Current (Standby) CMOS
VIL
(2)
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±5
µA
Outputs open
80
mA
E = VIH
3
mA
E = VCC – 0.2V
3
mA
Input Low Voltage
–0.3
0.8
V
VIH
Input High Voltage
2.2
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage
IOH = –1mA
2.4
V
Notes: 1. Outputs Deselected.
2. Negative spikes of –1V allowed for up to 10ns once per cycle.
Table 7. Power Down/Up Trip Points DC Characteristics (1)
(TA = 0 to 70°C or –40 to 85°C)
Symbol
Parameter
Typ
Max
Unit
VPFD
Power-fail Deselect Voltage (M48Z02)
4.5
4.6
4.75
V
VPFD
Power-fail Deselect Voltage (M48Z12)
4.2
4.3
4.5
V
VSO
Battery Back-up Switchover Voltage
tDR
Expected Data Retention Time
Note: 1. All voltages referenced to VSS.
4/12
Min
3.0
10
V
YEARS
M48Z02, M48Z12
Table 8. Power Down/Up Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C)
Symbol
Parameter
Min
Max
Unit
0
µs
VPFD (max) to VPFD (min) VCC Fall Time
300
µs
VPFD (min) to VSO VCC Fall Time
10
µs
tR
VPFD(min) to VPFD (max) VCC Rise Time
0
µs
tRB
VSO to VPFD (min) VCC Rise Time
1
µs
tREC
E or W at VIH after Power Up
2
ms
tPD
E or W at VIH before Power Down
tF (1)
tFB
(2)
Notes: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 50 µs after
VCC passes VPFD (min).
2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Figure 5. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tPD
INPUTS
tDR
tR
tFB
RECOGNIZED
tRB
DON'T CARE
tREC
NOTE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI00606
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E high as VCC rises past VPFD(min). Some systems
may perform inadvertent write cycles after VCC rises above VPFD(min) but before normal system operations begin. Even though a power on
reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
5/12
M48Z02, M48Z12
Table 9. Read Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z02 / M48Z12
Symbol
Parameter
-70
Min
-150
Max
Min
Unit
-200
Max
Min
Max
tAVAV
Read Cycle Time
tAVQV
Address Valid to Output Valid
70
150
200
ns
tELQV
Chip Enable Low to Output Valid
70
150
200
ns
tGLQV
Output Enable Low to Output Valid
35
75
80
ns
tELQX
Chip Enable Low to Output Transition
5
10
10
ns
tGLQX
Output Enable Low to Output Transition
5
5
5
ns
tEHQZ
Chip Enable High to Output Hi-Z
25
35
40
ns
tGHQZ
Output Enable High to Output Hi-Z
25
35
40
ns
tAXQX
Address Transition to Output Transition
70
10
150
200
5
ns
5
ns
Figure 6. Read Mode AC Waveforms
tAVAV
VALID
A0-A10
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI01330
Note: Write Enable (W) = High.
6/12
M48Z02, M48Z12
Table 10. Write Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z02 / M48Z12
Symbol
Parameter
-70
Min
-150
Max
Min
Unit
-200
Max
Min
Max
tAVAV
Write Cycle Time
70
150
200
ns
tAVWL
Address Valid to Write Enable Low
0
0
0
ns
tAVEL
Address Valid to Chip Enable Low
0
0
0
ns
tWLWH
Write Enable Pulse Width
50
90
120
ns
tELEH
Chip Enable Low to Chip Enable High
55
90
120
ns
tWHAX
Write Enable High to Address Transition
0
10
10
ns
tEHAX
Chip Enable High to Address Transition
0
10
10
ns
tDVWH
Input Valid to Write Enable High
30
40
60
ns
tDVEH
Input Valid to Chip Enable High
30
40
60
ns
tWHDX
Write Enable High to Input Transition
5
5
5
ns
tEHDX
Chip Enable High to Input Transition
5
5
5
ns
tWLQZ
Write Enable Low to Output Hi-Z
tAVWH
Address Valid to Write Enable High
60
120
140
ns
tAVEH
Address Valid to Chip Enable High
60
120
140
ns
tWHQX
Write Enable High to Output Transition
5
10
10
ns
WRITE MODE
The M48Z02/12 is in the Write Mode whenever W
and E are active. The start of a write is referenced
from the latter occurring falling edge of W or E. A
write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for a minimum
25
50
60
ns
of tEHAX from Chip Enable or tWHAX from Write
Enable prior to the initiation of another read or write
cycle. Data-in must be valid tDVWH prior to the end
of write and remain valid for tWHDX afterward. G
should be kept high during write cycles to avoid bus
contention; although, if the output bus has been
activated by a low on E and G, a low on W will
disable the outputs tWLQZ after W falls.
7/12
M48Z02, M48Z12
Figure 7. Write Enable Controlled, Write AC Waveforms
tAVAV
VALID
A0-A10
tAVWH
tWHAX
tAVEL
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01331
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A10
VALID
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01332B
8/12
M48Z02, M48Z12
DATA RETENTION MODE
With valid VCC applied, the M48Z02/12 operates as
a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself
when VCC falls within the VPFD(max), VPFD(min)
window. All outputs become high impedance, and
all inputs are treated as "don’t care."
Note: A power failure during a write cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM’s
content. At voltages below VPFD(min), the user can
be assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48Z02/12 may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended.
The power switching circuit connects external VCC
to the RAM and disconnects the battery when VCC
rises above VSO. As VCC rises, the battery voltage
is checked. If the voltage is too low, an internal
Battery Not OK (BOK) flag will be set. The BOK flag
can be checked after power up. If the BOK flag is
set, the first write attempted will be blocked. The
flag is automatically cleared after the first write, and
normal RAM operation resumes. Figure 9 illustrates how a BOK check routine could be structured.
POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION
ICC transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can
be reduced if capacitors are used to store energy,
which stabilizes the VCC bus. The energy stored in
the bypass capacitors will be released as low going
spikes are generated or energy will be absorbed
when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure 10) is
recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate
negative voltage spikes on VCC that drive it to
values below VSS by as much as one Volt. These
negative spikes can cause data corruption in the
SRAM while in battery backup mode. To protect
from these voltage spikes, it is recommeded to
connect a schottky diode from VCC to VSS (cathode
connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
Figure 9. Checking the BOK Flag Status
POWER-UP
READ DATA
AT ANY ADDRESS
WRITE DATA
COMPLEMENT BACK
TO SAME ADDRESS
READ DATA
AT SAME
ADDRESS AGAIN
IS DATA
COMPLEMENT
OF FIRST
READ?
(BATTERY OK)
YES
NO (BATTERY LOW)
NOTIFY SYSTEM
OF LOW BATTERY
(DATA MAY BE
CORRUPTED)
WRITE ORIGINAL
DATA BACK TO
SAME ADDRESS
CONTINUE
AI00607
Figure 10. Supply Voltage Protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
9/12
M48Z02, M48Z12
ORDERING INFORMATION SCHEME
Example:
M48Z02
Supply Voltage and Write
Protect Voltage
02
VCC = 4.75V to 5.5V
VPFD = 4.5V to 4.75V
12
VCC = 4.5V to 5.5V
VPFD = 4.2V to 4.5V
-70
PC
1
Speed
-70
70ns
-150
150ns
-200
200ns
Package
PC
PCDIP24
Temp. Range
1
0 to 70 °C
6
–40 to 85 °C
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
10/12
M48Z02, M48Z12
PCDIP24 - 24 pin Plastic DIP, battery CAPHAT
mm
Symb
Typ
inches
Min
Max
A
8.89
A1
Min
Max
9.65
0.350
0.380
0.38
0.76
0.015
0.030
A2
8.38
8.89
0.330
0.350
B
0.38
0.53
0.015
0.021
B1
1.14
1.78
0.045
0.070
C
0.20
0.31
0.008
0.012
D
34.29
34.80
1.350
1.370
E
17.83
18.34
0.702
0.722
e1
2.29
2.79
0.090
0.110
e3
25.15
30.73
0.990
1.210
eA
15.24
16.00
0.600
0.630
L
3.05
3.81
0.120
0.150
N
24
24
A2
A1
B1
B
Typ
e1
A
L
C
eA
e3
D
N
E
1
PCDIP
Drawing is not to scale.
11/12
M48Z02, M48Z12
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1999 STMicroelectronics - All Rights Reserved
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12/12
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