IK Semicon IN74HCT74AN Dual d flip-flop with set and reset high-performance silicon-gate cmo Datasheet

TECHNICAL DATA
IN74HCT74A
Dual D Flip-Flop with Set and Reset
High-Performance Silicon-Gate CMOS
The IN74HCT74A is identical in pinout to the LS/ALS74. This device
may be used as a level converter for interfacing TTL or NMOS outputs to
High Speed CMOS inputs.
This device consists of two D flip-flops with individual Set, Reset, and
Clock inputs. Information at a D-input is transferred to the corresponding Q
output on the next positive going edge of the clock input. Both Q and Q
outputs are available from each flip-flop. The Set and Reset inputs are
asynchronous.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
ORDERING INFORMATION
IN74HCT74AN Plastic
IN74HCT74AD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
PIN 14 =VCC
PIN 7 = GND
Outputs
Set
Reset
Clock
Data
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
H
X
*
H*
X
H
H
H
H
L
H
H
L
L
H
H
H
L
X
No Change
H
H
H
X
No Change
H
H
X
No Change
*Both outputs will remain high as long as Set and
Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
X = don’t care
Rev. 00
IN74HCT74A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
IOUT
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond whitch damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
Min
Max
Unit
4.5
5.5
V
0
VCC
V
-55
+125
°C
0
500
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
Rev. 00
IN74HCT74A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Symbol
Parameter
Test Conditions
Guaranteed Limit
V
25 °C
to
-55°C
≤85
°C
≤125
°C
Unit
VIH
Minimum HighLevel Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢≤ 20 µA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL
Maximum Low Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢ ≤ 20 µA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOH
Minimum HighLevel Output Voltage
VIN=VIH or VIL
⎢IOUT⎢ ≤ 20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
VIN=VIH or VIL
⎢IOUT⎢ ≤ 4.0 mA
4.5
3.98
3.84
3.7
VIN=VIH or VIL
⎢IOUT⎢ ≤ 20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
VIN=VIH or VIL
⎢IOUT⎢ ≤ 4.0 mA
4.5
0.26
0.33
0.4
VOL
Maximum LowLevel Output Voltage
V
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
5.5
±0.1
±1.0
±1.0
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA
5.5
1.0
10
40
µA
∆ICC
Additional Quiescent
Supply Current
VIN=2.4 V, Any One Input
VIN=VCC or GND, Other
Inputs
≥-55°C
25°C to
125°C
mA
2.9
2.4
IOUT=0µA
5.5
Rev. 00
IN74HCT74A
AC ELECTRICAL CHARACTERISTICS (VCC =5.0 V±10%,CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25 °C
to
-55°C
≤85°C
≤125°C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
30
24
20
MHz
tPLH, tPHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
24
30
36
ns
tPLH, tPHL
Maximum Propagation Delay, Set or Reset to Q or
Q (Figures 2 and 4)
24
30
36
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
15
19
22
ns
Maximum Input Capacitance
10
10
10
pF
CIN
CPD
Power Dissipation Capacitance (Per Enabled
Output)
Typical @25°C,VCC=5.0 V
Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
130
pF
TIMING REQUIREMENTS (VCC =5.0 V±10%,CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25 °C to-55°C
≤85°C
≤125°C
Unit
tsu
Minimum Setup Time, Data to Clock
(Figure 3)
15
19
22
ns
th
Minimum Hold Time, Clock to Data
(Figure 3)
3
3
3
ns
trec
Minimum Recovery Time, Set or
Reset Inactive to Clock (Figure 2)
6
8
9
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
15
19
22
ns
tw
Minimum Pulse Width, Set or Reset
(Figure 2)
15
19
22
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
500
500
500
ns
Rev. 00
IN74HCT74A
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
Rev. 00
IN74HCT74A
N SUFFIX PLASTIC DIP
(MS - 001AA)
A
Dimension, mm
8
14
B
7
1
Symbol
MIN
MAX
A
18.67
19.69
B
6.1
7.11
5.33
C
F
L
C
-T- SEATING
PLANE
N
G
M
K
J
H
D
0.25 (0.010) M T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
D
0.36
0.56
F
1.14
1.78
G
2.54
H
7.62
J
0°
10°
K
2.92
3.81
L
7.62
8.26
M
0.2
0.36
N
0.38
D SUFFIX SOIC
(MS - 012AB)
Dimension, mm
A
14
8
H
B
1
G
P
7
R x 45
C
-TK
D
SEATING
PLANE
J
0.25 (0.010) M T C M
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B ‑ 0.25 mm (0.010) per side.
F
M
Symbol
MIN
MAX
A
8.55
8.75
B
3.8
4
C
1.35
1.75
D
0.33
0.51
F
0.4
1.27
G
1.27
H
5.27
J
0°
8°
K
0.1
0.25
M
0.19
0.25
P
5.8
6.2
R
0.25
0.5
Rev. 00
Similar pages