TI LB176Q Differential bus transceiver Datasheet

 SLLS067G − AUGUST 1990 − REVISED APRIL 2006
D Bidirectional Transceiver
D Meets or Exceeds the Requirements of
D
D
D
D
D
D
D
D
D
D
D
D
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
FK PACKAGE
(TOP VIEW)
NC
R
NC
VCC
NC
D
ANSI Standard TIA/EIA−485−A and
ISO 8482:1987(E)
High-Speed Low-Power LinBiCMOS
Circuitry
Designed for High-Speed Operation in Both
Serial and Parallel Applications
Low Skew
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
Very Low Disabled Supply Current . . . 200
µA Maximum
Wide Positive and Negative Input/Output
Bus Voltage Ranges
Thermal-Shutdown Protection
Driver Positive-and Negative-Current
Limiting
Open-Circuit Failsafe Receiver Design
Receiver Input Sensitivity . . . ± 200 mV Max
Receiver Input Hysteresis . . . 50 mV Typ
Operates From a Single 5-V Supply
Glitch-Free Power-Up and Power-Down
Protection
Available in Q-Temp Automotive
HighRel Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
NC
RE
NC
DE
NC
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
NC
B
NC
A
NC
NC
D
NC
GND
NC
D
D, JG, OR P PACKAGE
(TOP VIEW)
NC −No internal connection
Function Tables
DRIVER
INPUT
D
H
L
X
description
The
SN55LBC176,
SN65LBC176,
SN65LBC176Q, and SN75LBC176 differential
bus transceivers are monolithic, integrated
circuits designed for bidirectional data communication on multipoint bus-transmission lines. They
are designed for balanced transmission lines and
meet ANSI Standard TIA/EIA−485−A (RS-485)
and ISO 8482:1987(E).
ENABLE
DE
H
H
L
OUTPUTS
A
B
H
L
L
H
Z
Z
RECEIVER
DIFFERENTIAL INPUTS
VID = VIA −VIB
VID ≥ 0.2 V
−0.2 V < VID < 0.2 V
VID ≤ − 0.2 V
X
Open
H = high level,
X = irrelevant,
ENABLE
RE
L
L
L
H
L
OUTPUT
R
H
?
L
Z
H
L = low level, ? = indeterminate,
Z = high impedance (off)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinBiCMOS and LinASIC are trademarks of Texas Instruments Incorporated.
Copyright  2000−2006, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
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$!. '' %$$!)
%(#"! "%' / 00121 '' %$$! $ $!$(
#'$!! *$,!$ $() '' *$ %(#"! %(#"
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1
SLLS067G − AUGUST 1990 − REVISED APRIL 2006
description (continued)
The SN55LBC176, SN65LBC176, SN65LBC176Q, and SN75LBC176 combine a 3-state, differential line driver
and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and
receiver have active-high and active-low enables, respectively, which can externally connect together to
function as a direction control. The driver differential outputs and the receiver differential inputs connect
internally to form a differential input /output (I/O) bus port that is designed to offer minimum loading to the bus
whenever the driver is disabled or VCC = 0. This port features wide positive and negative common-mode voltage
ranges, making the device suitable for party-line applications. Very low device supply current can be achieved
by disabling the driver and the receiver.
These transceivers are suitable for ANSI Standard TIA/EIA−485 (RS-485) and ISO 8482 applications to the
extent that they are specified in the operating conditions and characteristics section of this data sheet. Certain
limits contained in TIA/EIA−485−A and ISO 8482:1987 (E) are not met or cannot be tested over the entire military
temperature range.
The SN55LBC176 is characterized for operation from −55°C to 125°C. The SN65LBC176 is characterized for
operation from −40°C to 85°C, and the SN65LBC176Q is characterized for operation from − 40°C to 125°C.
The SN75LBC176 is characterized for operation from 0°C to 70°C.
logic symbol†
DE
RE
3
2
logic diagram (positive logic)
DE
EN1
4
EN2
D
6
D
R
1
4
1
1
3
7
RE
A
R
B
2
6
1
7
2
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
AVAILABLE OPTIONS
TA
0°C to 70°C
−40°C to 85°C
−40°C to 110°C
−55°C to 125°C
2
PACKAGE
PART NUMBER
PART MARKING
SOP
SN75LBC176D
7LB176
PDIP
SN75LBC176P
75LBC176
SOP
SN65LBC176D
6LB176
PDIP
SN65LBC176P
65LBC176
SOP
SN65LBC176QD
LB176Q
SOP
SN65LBC176QDR
LB176Q
LCCC
SNJ55LBC176FK
SNJ55LBC176FK
CDIP
SNJ55LBC176JG
SNJ55LBC176
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A
B
Bus
SLLS067G − AUGUST 1990 − REVISED APRIL 2006
schematics of inputs and outputs
EQUIVALENT OF D, RE, and
DE INPUTS
TYPICAL OF A AND B I/O PORTS
TYPICAL OF RECEIVER OUTPUT
VCC
VCC
VCC
100 kΩ NOM
A Port Only
3 kΩ
NOM
A or B
Output
Input
18 kΩ
NOM
100 kΩ NOM
B Port Only
1.1 kΩ
NOM
absolute maximum ratings†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10 V to 15 V
Input voltage, VI (D, DE, R, or RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.5 V
Receiver output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $10 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
THERMAL
MODEL
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 110°C
POWER RATING
Low K†
High K‡
526 mW
5.0 mW/°C
301 mW
226 mW
—
D
882 mW
8.4 mW/°C
504 mW
378 mW
—
P
840 mW
8.0 mW/°C
480 mW
360 mW
—
JG
1050 mW
8.4 mW/°C
672 mW
546 mW
210 mW
FK
1375 mW
11.0 mW/°C
880 mW
715 mW
440 mW
† In accordance with the low effective thermal conductivity metric definitions of EIA/JESD 51−3.
‡ In accordance with the high effective thermal conductivity metric definitions of EIA/JESD 51−7.
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3
SLLS067G − AUGUST 1990 − REVISED APRIL 2006
recommended operating conditions
Supply voltage, VCC
Voltage at any bus terminal (separately or common mode), VI or VIC
NOM
MAX
UNIT
4.75
5
5.25
V
12
V
−7
High-level input voltage, VIH
D, DE, and RE
Low-level input voltage, VIL
D, DE, and RE
Differential input voltage, VID (see Note 2)
2
−12
Driver
High-level output current, IOH
MIN
Receiver
V
12
V
−60
mA
µA
60
Receiver
8
Junction temperature, TJ
Operating free-air temperature, TA
0.8
−400
Driver
Low-level output current, IOL
V
140
SN55LBC176
−55
SN65LBC176
−40
85
SN65LBC176Q
−40
125
0
70
SN75LBC176
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°C
125
NOTE 2: Differential input /output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
4
mA
°C
SLLS067G − AUGUST 1990 − REVISED APRIL 2006
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VO
Input clamp voltage
Output voltage
II = − 18 mA
IO = 0
| VOD1 |
Differential output voltage
IO = 0
Differential output voltage
RL = 54 Ω,
See Note 3
| VOD2 |
VOD3
Differential output voltage
∆| VOD |
Change in magnitude of differential
output voltage †
VOC
Common-mode output voltage
∆| VOC |
Change in magnitude of
common-mode output voltage†
IO
Output current
IIH
IIL
High-level input current
IOS
Low-level input current
Short-circuit output current
See Figure 1,
Vtest = − 7 V to 12 V,
See Note 3
RL = 54 Ω or 100 Ω,
Output disabled,
See Note 4
See Figure 2,
Supply current
MAX
UNIT
V
0
6
V
1.5
6
V
55LBC176,
65LBC176,
65LBC176Q
1.1
75LBC176
1.5
55LCB176,
65LCB176,
65LBC176Q
1.1
75LBC176
1.5
5
−0.2
0.2
V
−1
3
V
−0.2
0.2
V
See Figure 1
VO = 12 V
VO = − 7 V
V
5
V
1
mA
−0.8
VI = 2.4 V
VI = 0.4 V
−100
µA
−100
µA
VO = − 7 V
VO = 0
−250
−150
mA
VO = VCC
VO = 12 V
250
Receiver disabled
and driver enabled
ICC
MIN
−1.5
VI = 0 or VCC,
No load
Receiver and driver
disabled
55LBC176,
65LBC176Q
1.75
65LBC176,
75LBC176
1.5
55LBC176,
65LBC176Q
0.25
65LBC176,
75LBC176
0.2
mA
† ∆ | VOD | and ∆ | VOC | are the changes in magnitude of VOD and VOC, respectively, that occur when the input changes from a high level to a
low level.
NOTES: 3. This device meets the VOD requirements of TIA/EIA−485−A above 0°C only.
4. This applies for both power on and off; refer to TIA/EIA−485−A for exact conditions.
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5
SLLS067G − AUGUST 1990 − REVISED APRIL 2006
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
SN55LBC176
SN65LBC176Q
TEST CONDITIONS
MIN
td(OD)
tt(OD)
Differential output delay time
tsk(p)
tPZH
Pulse skew ( | td(ODH) − td(ODL) | )
Output enable time to high level
RL = 110 Ω,
See Figure 4
tPZL
tPHZ
Output enable time to low level
RL = 110 Ω,
Output disable time from high level
RL = 110 Ω,
tPLZ
Output disable time from low level
RL = 110 Ω,
† All typical values are at VCC = 5 V, TA = 25°C.
Differential output transition time
Ω
RL = 54 Ω,
See Figure 3
TYP
8
CL = 50 pF,
MAX
MIN
31
8
12
TYP†
UNIT
MAX
25
12
6
ns
ns
65
35
ns
See Figure 5
65
35
ns
See Figure 4
105
60
ns
See Figure 5
105
35
ns
DATA SHEET PARAMETER
RS-485
VO
| VOD1 |
Voa, Vob
Vo
| VOD2 |
| VOD3 |
Vt (RL = 54 Ω)
Vt (test termination
measurement 2)
∆ | VOD |
| | Vt | − | Vt | |
VOC
∆ | VOC |
| Vos |
| Vos − Vos |
IOS
IO
None
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0
ns
6
SYMBOL EQUIVALENTS
6
SN65LBC176
SN75LBC176
SLLS067G − AUGUST 1990 − REVISED APRIL 2006
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT +
Positive-going input threshold
voltage
VO = 2.7 V,
IO = − 0.4 mA
VIT −
Negative-going input threshold
voltage
VO = 0.5 V,
IO = 8 mA
Vhys
Hysteresis voltage (VIT + − VIT −)
(see Figure 4)
VIK
Enable-input clamp voltage
II = − 18 mA
VOH
High-level output voltage
VID = 200 mV,
See Figure 6
IOH = − 400 µA,
VOL
Low-level output voltage
VID = −200 mV,
See Figure 6
IOL = 8 mA,
IOZ
High-impedance-state output
current
VO = 0.4 V to 2.4 V
II
Line input current
Other input = 0 V,
See Note 5
IIH
IIL
High-level enable-input current
rI
Input resistance
Low-level enable-input current
MIN
TYP†
MAX
0.2
−0.2‡
mV
−1.5
V
2.7
V
−20
V
20
µA
1
VIH = 2.7 V
VIL = 0.4 V
VI = 0 or VCC,
No load
Supply current
0.45
mA
−0.8
µA
−100
−100
µA
12
kΩ
Receiver enabled
and driver disabled
ICC
Receiver and
driver disabled
V
V
50
VI = 12 V
VI = − 7 V
UNIT
3.9
SN55LBC176,
SN65LBC176,
SN65LBC176Q
0.25
SN75LBC176
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet.
NOTE 5: This applies for both power on and power off. Refer to ANSI Standard RS-485 for exact conditions.
mA
mA
0.2
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 15 pF
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low- to high-level
single-ended output
tPHL
Propagation delay time, high- to low-level
single-ended output
SN55LBC176
SN65LBC176Q
SN65LBC176
SN75LBC176
TYP†
UNIT
MIN
MAX
MIN
11
37
11
33
ns
11
37
11
33
ns
VID = − 1.5 V to 1.5 V,
See Figure 7
tsk(p)
tPZH
Pulse skew ( | tPLH − tPHL | )
10
6
ns
Output enable time to high level
35
35
ns
tPZL
tPHZ
Output enable time to low level
35
30
ns
35
35
ns
35
30
ns
Output disable time from high level
tPLZ
Output disable time from low level
† All typical values are at VCC = 5 V, TA = 25°C.
See Figure 8
See Figure 8
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3
MAX
7
SLLS067G − AUGUST 1990 − REVISED APRIL 2006
PARAMETER MEASUREMENT INFORMATION
375 Ω
RL
VOD2
2
VOD3
RL
2
60 Ω
VOC
Vtest
375 Ω
Figure 1. Driver VOD and VOC
Figure 2. Driver VOD3
3V
Input
Generator
(see Note A)
RL = 54 Ω
50 Ω
1.5 V
CL = 50 pF
(see Note B)
0V
td(ODH)
Output
Output
3V
1.5 V
td(ODL)
90%
50%
≈ 2.5 V
50%
10%
≈ − 2.5 V
tt(OD)
VOLTAGE WAVEFORMS
tt(OD)
TEST CIRCUIT
Figure 3. Driver Test Circuit and Voltage Waveforms
Output
3V
S1
Input
1.5 V
1.5 V
0 V or 3 V
Generator
(see Note A)
50 Ω
tPZH
RL = 110 Ω
CL = 50 pF
(see Note B)
0V
0.5 V
VOH
Output
TEST CIRCUIT
2.3 V
tPHZ
Voff ≈ 0 V
VOLTAGE WAVEFORMS
Figure 4. Driver Test Circuit and Voltage Waveforms
5V
S1
3V
RL = 110 Ω
1.5 V
1.5 V
0V
Output
3 V or 0 V
Generator
(see Note A)
Input
tPZL
50 Ω
tPLZ
CL = 50 pF
(see Note B)
Output
2.3 V
5V
0.5 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 5. Driver Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
8
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SLLS067G − AUGUST 1990 − REVISED APRIL 2006
PARAMETER MEASUREMENT INFORMATION
VID
VOH
VOL
+ IOL
−IOH
Figure 6. Receiver VOH and VOL
3V
Input
Generator
(see Note A)
1.5 V
1.5 V
Output
51 Ω
1.5 V
0V
tPHL
tPLH
CL = 15 pF
(see Note B)
VOH
Output
0V
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 7. Receiver Test Circuit and Voltage Waveforms
THERMAL CHARACTERISTICS − D PACKAGE
PARAMETER
TEST CONDITIONS
Junction−to−ambient thermal reisistance, θJA†
Junction−to−board thermal reisistance, θJB
TYP
Low-K board, no air flow
199.4
High-K board, no air flow
119
High-K board, no air flow
67
Junction−to−case thermal reisistance, θJC
Average power dissipation, P(AVG)
MIN
MAX
UNIT
°C/W
46.6
RL = 54 Ω, input to D is 10 Mbps 50% duty
cycle square wave, VCC = 5.25 V,
TJ = 130 °C.
330
mW
Thermal shutdown junction temperature, TSD
165
°C
† See TI application note literature number SZZA003, Package Thermal Characterization Methodologies, for an explanation of this parameter.
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SLLS067G − AUGUST 1990 − REVISED APRIL 2006
PARAMETER MEASUREMENT INFORMATION
S1
1.5 V
2 kΩ
−1.5 V
S2
5V
CL = 15 pF
(see Note B)
Generator
(see Note A)
5 kΩ
1N916 or Equivalent
50 Ω
S3
TEST CIRCUIT
Input
3V
S1 to 1.5 V
S2 Open
S3 Closed
0V
1.5 V
Input
1.5 V
tPZH
tPZL
VOH
≈ 4.5 V
1.5 V
Output
3V
S1 to −1.5 V
S2 Closed
S3 Opened
0V
Output
0V
1.5 V
VOL
1.5 V
Input
3V
S1 to 1.5 V
S2 Closed
S3 Closed
0V
Input
tPHZ
3V
S1 to −1.5 V
S2 Closed
S3 Closed
0V
1.5 V
tPLZ
≈ 1.3 V
VOH
Output
0.5 V
Output
0.5 V
≈ 1.3 V
VOL
VOLTAGE WAVEFORMS
Figure 8. Receiver Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
10
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THERMAL CHARACTERISTICS OF IC PACKAGES
ΘJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient temperature
divided by the operating power
ΘJA is NOT a constant and is a strong function of
D
D
D
the PCB design (50% variation)
altitude (20% variation)
device power (5% variation)
ΘJA can be used to compare the thermal performance of packages if the specific test conditions are defined and used.
Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal
characteristics of holding fixtures. ΘJA is often misused when it is used to calculate junction temperatures for other
installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal
performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board gives best case in−use
condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. A 4%
to 50% difference in ΘJA can be measured between these two test cards
ΘJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the
operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow
from die, through the mold compound into the copper block.
ΘJC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict
junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and
junction temperatures are backed out. It can be used with ΘJB in 1-dimensional thermal simulation of a package system.
ΘJB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB
temperature at the center of the package (closest to the die) when the PCB is clamped in a cold−plate structure. ΘJB is only
defined for the high-k test card.
ΘJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance
(especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of package system
(see Figure 1).
Ambient Node
qCA Calculated
Surface Node
qJC Calculated/Measured
Junction
qJB Calculated/Measured
PC Board
Figure 1. Thermal Resistance
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SLLS067G − AUGUST 1990 − REVISED APRIL 2006
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°−ā 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047 / D 10/96
NOTES: A.
B.
C.
D.
12
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLLS067G − AUGUST 1990 − REVISED APRIL 2006
MECHANICAL INFORMATION
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINALS SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.740
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
25
5
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / C 11/95
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold-plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SLLS067G − AUGUST 1990 − REVISED APRIL 2006
MECHANICAL INFORMATION
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE PACKAGE
0.400 (10,20)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.063 (1,60)
0.015 (0,38)
0.100 (2,54)
0°−15°
0.023 (0,58)
0.015 (0,38)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
14
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
Falls within MIL-STD-1835 GDIP1-T8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
/3 MPDI001A − JANUARY 1995 − REVISED JUNE 1999
MECHANICAL INFORMATION
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
5962-9318301Q2A
ACTIVE
LCCC
FK
20
1
TBD
5962-9318301QPA
ACTIVE
CDIP
JG
8
1
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
SN65LBC176D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC176DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC176DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC176DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC176P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN65LBC176PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN65LBC176QD
ACTIVE
SOIC
D
8
75
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65LBC176QDR
ACTIVE
SOIC
D
8
2500
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN75LBC176D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC176DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC176DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC176DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC176P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN75LBC176PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SNJ55LBC176FK
ACTIVE
LCCC
FK
20
1
TBD
SNJ55LBC176JG
ACTIVE
CDIP
JG
8
1
TBD
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2007
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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