ON NB3M8T3910 Configurable differential clock fanout buffer Datasheet

NB3M8T3910G
2.5V/3.3V 3:1:10
Configurable Differential
Clock Fanout Buffer with
LVCMOS Reference Output
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Description
The NB3M8T3910G is a 3:1:10 Clock fanout buffer operating on a
2.5 V/3.3 V Core VDD and a flexible 2.5 V / 3.3 V VDDO supply
(VDDO ≤ VDD).
A 3:1 MUX selects between Crystal oscillator inputs, or either of
two differential Clock inputs capable of accepting LVPECL, LVDS,
HCSL, or SSTL levels. The MUX select lines, SEL0 and SEL1, accept
LVCMOS or LVTTL levels and select input per Table 3. The Crystal
input is disabled when a Clock input is selected.
Differential Outputs consist of two banks of five differential outputs
with each bank independently mode configurable as LVPECL, LVDS
or HCSL. Each bank of differential output pairs is configured with a
pair of SMODEAx/Bx select lines using LVCMOS or LVTTL levels
per Table 6. Clock input levels and outputs states are determined per
Table 5.
The Single−Ended LVCMOS Output, REFOUT, is synchronously
enabled by the OE_SE control line per Table 4 using LVCMOS /
LVTTL levels. For Clock frequencies above 250 MHz, the REFOUT
line should be disabled.
Features
• Crystal, Single−Ended or Differential Input Reference
•
•
•
•
•
•
•
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•
March, 2016 − Rev. 2
1
NB3M8T
3910G
AWLYYWWG
1 48
QFN48
G SUFFIX
CASE 485AJ
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 19 of
this data sheet.
• Industrial Temperature Range −40°C to 85°C
• This is a Pb−Free Device
Clocks
Differential Input Pair can Accept: LVPECL, LVDS,
HCSL, SSTL
Two Output Banks: Each has Five Differential Outputs
Configurable as LVPECL, LVDS, or HCSL by
SMODEAx/Bx Pins
One Single−Ended LVCMOS Output with Synchronous
OE Control
LVCMOS/LVTTL Interface Levels for all Control
Inputs
Clock Frequency: Up to 1400 MHz, Typical
Output Skew: 50 ps (Max)
Additive RMS Jitter <0.03 ps (156.25 MHz, Typical)
Input to Output Propagation Delay (900 ps Typical)
Operating Supply Modes VDD/VDDO: 2.5 V/2.5 V,
3.3 V/3.3 V or 3.3 V/2.5 V
© Semiconductor Components Industries, LLC, 2016
MARKING
DIAGRAM
Applications
•
•
•
•
•
•
Clock Distribution
Telecom
Networking
Backplane
High End Computing
Wireless and Wired Infrastructure
End Products
•
•
•
•
1
Servers
Ethernet Switch/Routers
ATE
Test and Measurement
Publication Order Number:
NB3M8T3910/D
NB3M8T3910G
VDDOA
VDD
BANK A
GND
QA0
GND
SMODEA1
OE_SE
VDDOC
REFOUT
GND
VDD
CLK1
CLK1
SMODEB1
IREF
GND
QA1
SMODEA0
CONTROL
QA1
SMODEA1
Exposed
Pad (EP)
48
47
46
45
44
43
42
41
40
39
38
37
QA0
QA2
QA0
1
36 QB0
SEL0
QA2
QA0
2
35 QB0
SEL1
QA3
QA1
3
34 QB1
CLK0
QA3
QA1
4
33 QB1
CLK0
QA4
CLK1
CLK1
XTAL_IN
QA4
3:1
Mux
32 VDDOB
VDDOA 5
QB0
QB0
QA2
6
QA2
7
31 QB2
NB3M8T3910G
30 QB2
29 VDDOB
VDDOA 8
OSC
QB1
XTAL_OUT
9
28 QB3
QA3 10
27 QB3
QA4 11
26 QB4
QA3
QB1
QB2
QB2
BANK B
21
CLK0
CLK0
22
23
24
GND
20
SEL1
19
SMODEB0
18
GND
17
SEL0
16
XTAL_OUT
QB4
15
XTAL_IN
QB4
14
VDD
QB3
CONTROL
SMODEB1
13
GND
QB3
SMODEB0
25 QB4
QA4 12
SMODEA0
IREF
Figure 2. QFN−48 Pinout Configuration
(Top View)
VDDOB
VDDOC
REFOUT
OE_SE
SYNC
Figure 1. Simplified Logic Diagram
Table 1. PIN DESCRIPTION
Default
(Internal
Resistors)
Number
Name
Type
Description
1, 2
QA0, QA0
Output
Bank A differential output pair Q0. Configurable as LVPECL / LVDS / HCSL
3, 4
QA1, QA1
Output
Bank A differential output pair Q1. Configurable as LVPECL / LVDS / HCSL
5, 8
VDDOA
Power
VDDOA Positive Supply pin for Bank A outputs. VDDOA pins must all be
externally connected to a power supply to guarantee proper operation.
Bypass with 0.01 mF cap to GND
29, 32
VDDOB
Power
VDDOB Positive Supply pin for Bank B outputs. VDDOB pins must all be
externally connected to a power supply to guarantee proper operation.
Bypass with 0.01 mF cap to GND
45
VDDOC
Power
VDDOC Positive Supply pin for REFOUT output. VDDOC pin must be
externally connected to a power supply to guarantee proper operation.
Bypass with 0.01 mF cap to GND
6,7
QA2, QA2
Output
Bank A differential output pair Q2. Configurable as LVPECL / LVDS / HCSL.
9,10
QA3, QA3
Output
Bank A differential output pair Q3. Configurable as LVPECL / LVDS / HCSL
11,12
QA4, QA4
Output
Bank A differential output pair Q4. Configurable as LVPECL / LVDS / HCSL
13, 18,
24, 37,
43, 48
GND
Power
Ground Supply. All GND pins must be externally connected to power supply
to guarantee proper operation.
14, 47
SMODEA0 /
SMODEA1
Input
Pulldown
Output driver selectors for BANK A. See Table 6 for function.
LVCMOS/LVTTL levels.
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NB3M8T3910G
Table 1. PIN DESCRIPTION
Default
(Internal
Resistors)
Number
Name
Type
15, 42
VDD
Power
VDD Positive Supply pin for core logic. VDD pins must all be externally
connected to a power supply to guarantee proper operation. Bypass with
0.01 mF cap to GND.
Description
16, 17
XTAL_IN,
XTAL_OUT
Input
Crystal input / output. XTAL_IN can also be driven by X0, TCX0 or other
external single−ended clock.
19, 22
SEL0
SEL1
Input
Pulldown
Input clock selectors. See Table 3 for function. LVCMOS/LVTTL interface
levels.
20
CLK0
Input
Pulldown
Non−inverting clock input 0. LVPECL, LVDS, SSTL, HCSL levels.
21
CLK0
Input
Pullup /
Pulldown
Inverting differential clock input 0. LVPECL, LVDS, SSTL, HCSL, LVCMOS
levels. Internal bias to VDD B 2.
23,
39
SMODEB0 /
SMODEB1
Input
Pulldown
Output driver selects for BANK B. See Table 6 for function. LVCMOS/LVTTL
levels.
25,26
QB4, QB4
Output
Bank B differential output pair Q4. Configurable as LVPECL / LVDS / HCSL
27,28
QB3, QB3
Output
Bank B differential output pair Q3. Configurable as LVPECL / LVDS / HCSL.
30,31
QB2, QB2
Output
Bank B differential output pair Q2. Configurable as LVPECL / LVDS / HCSL.
33,34
QB1, QB1
Output
Bank B differential output pair Q1. Configurable as LVPECL / LVDS / HCSL.
35,36
QB0, QB0
Output
Bank B differential output pair Q0. Configurable as LVPECL / LVDS / HCSL.
38
IREF
Output
Connect a fixed 475 W precision resistor from this pin to ground to provide
the output reference current. Required for HCSL, not used for LVPECL or
LVDS.
40
CLK1
Input
Pullup /
Pulldown
Inverting differential clock input 1. LVPECL, LVDS, SSTL, HCSL levels
internal bias to VDD/2. Internal bias to VDD B 2.
41
CLK1
Input
Pulldown
Non−inverting differential clock input 1. LVPECL, LVDS, SSTL, HCSL,
LVCMOS levels.
44
REFOUT
Output
46
OE_SE
Input
EP
EXPOSED
PAD
Thermal
Reference output, LVCMOS.
Pulldown
Synchronous Enable Control for REFOUT. LVCMOS/LVTTL levels.
The Exposed Pad (EP) on the QFN−48 package bottom is thermally
connected to the die for improved heat transfer out of package. The
exposed pad must be attached to a heat−sinking conduit. The pad is
electrically connected to the die, and must be electrically connected to
GND.
Table 2. PIN CHARACTERISTICS
Symbol
CIN
RPU/RPD
Parameter
Min
Typ
Max
Unit
Input Capacitance
4
pF
Input Pullup/Pulldown Resistor
50
kW
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NB3M8T3910G
FUNCTION TABLES
Table 3. SELx INPUT SELECT TABLE
Table 5. DIFF CLK INPUT / OUTPUT TABLE (Diff or
S.E. stimulus)
SEL[1:0] Inputs
Selected Input
00
CLK0/CLK0
Input State
Output State
01
CLK1/CLK1
CLKx = LOW, CLKx = HIGH
Qx = LOW, Qx = HIGH
10
XTAL
CLKx = HIGH, CLKx = LOW
Qx = HIGH, Qx = LOW
11
XTAL
CLKx = Open; CLKx = Open
Qx = LOW, Qx = HIGH
CLKx = LOW; CLKx = LOW
Qx = LOW, Qx = HIGH
CLKx = HIGH; CLKx = HIGH
Qx = LOW, Qx = HIGH
Table 4. OE_SE OUTPUT CONTROL TABLE FOR
REFOUT
Table 6. OUTPUT MODE CONFIGURATION TABLE
OE_SE Input Level
REFOUT Status
Low
High Impedance
SMODEA/B[1:0] Inputs
Output Mode
High
Enabled
00
LVPECL output.
01
LVDS output.
10
HCSL output.
11
High Impedance.
Table 7. ATTRIBUTES
Characteristic
ESD Protection
Value
Human Body Model
Machine Model
Moisture Sensitivity (Note 1)
Flammability Rating
>2 kV
200 V
QFN48
Oxygen Index: 28 to 34
Level 1
UL 94 V−0 @ 0.125 in
Transistor Count
1318 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 8. MAXIMUM RATINGS (Note 2)
Symbol
VDD
Parameter
Positive Power Supply
Unit
4.6
V
V
V
HCSL; LVCMOS
−0.5 v VO ≤ VDDO + 0.5
V
LVPECL Output Current
Continuous Current
Surge Current
50
100
mA
LVDS Output Current
Continuous Current
Surge Current
10
15
mA
−0.5 to VDDO + 0.5
V
−40 to 85
°C
XTAL_IN Input Voltage
CLKx/CLKx; SELx; SMODExx; OS_SE
Vo
Output Voltage
Io
Io
GND = 0 V
Rating
0 ≤ VI ≤ VDD
−0.5 ≤ VI ≤ VDDO + 0.5
VI
VOHCSL
Condition
Output Voltage (HCSL)
TA
Operating Temperature Range, Industrial
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
30.5
24.9
°C/W
qJC
Thermal Resistance (Junction−to−Case)
(Note 2)
12 − 17
°C/W
Tsol
Soldering Temperature
+260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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NB3M8T3910G
DC ELECTRICAL CHARACTERISTICS
Table 9. DC ELECTRICAL CHARACTERISTICS POWER SUPPLY DC CHARACTERISTICS,
GND = 0.0 V; TA = −40°C to 85°C
Symbol
VDD
VDDOx
IDD
IDDO
Max
Unit
Core Supply Voltage
Parameter
2.375
3.465
V
Output Supply Voltage
2.375
3.465
V
Core Supply Current
Output Supply Current
Test Conditions
Min
Typ
LVPECL Outputs
LVDS Outputs
HCSL Outputs
85
155
90
120
185
120
mA
All LVPECL Outputs Unloaded
ALL LVDS Outputs Loaded
All HCSL Output Unloaded
50
60
45
70
80
60
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
Table 10. LVCMOS/LVTTL DC, VDD/VDDO = 2.5 V/2.5 V, 3.3 V/3.3 V or 3.3 V/2.5 V ±5%; GND = 0.0 V; TA = −40°C to 85°C
Symbol
Test Conditions
Min
Input High Voltage
(SEL0/1, SMODEA0/1, SMODEB0/1
OE_SE)
VDD = 3.3 V
2
VDD = 2.5 V
1.7
Input Low Voltage
(SEL0/1, SMODEA0/1, SMODEB0/1
OE_SE)
VDD = 3.3 V
VDD = 2.5 V
IIH
Input High Current
(SEL0/1, SMODEA0/1, SMODEB0/1
OE_SE)
VDD = VIN = 3.465 V
IIL
Input Low Current
(SEL0/1, SMODEA0/1, SMODEB0/1
OE_SE)
VDD = 3.465V, VIN = 0 V
−150
mA
2.3
1.5
V
VIH
VIL
Parameter
VOH
Output High Voltage (Note 3) REFOUT
VDDO = 3.3 V ±5%
VDDO = 2.5 V ±5%
VOL
Output LOW Voltage (Note 3) REFOUT
VDDO = 3.3 V ±5%
VDDO = 2.5 V ±5%
Typ
Max
Unit
VDD + 0.3
VDD + 0.3
V
−0.3
0.8
V
−0.3
0.7
150
0.5
0.4
mA
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. Outputs terminated with 50 W to VDDO/2. See Parameter Measurement Information.
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NB3M8T3910G
Table 11. DIFFERENTIAL INPUT DC CHARACTERISTICS, VDD/VDDO = 2.5 V/2.5 V, 3.3 V/3.3 V or 3.3 V/2.5 V ±5%;
GND = 0.0 V; TA = −40°C to 85°C
Symbol
Parameter
Test Conditions
Min
Typ
Unit
150
mA
IIH
Input High Current
CLK0, CLK1, CLK0,
CLK1
IIL
Input Low Current
CLK0, CLK1
CLK0, CLK1
VID
Input Voltage Swing (Note 4)
0.15
1.3
V
Common Mode Input Voltage; (Notes 4 and 5)
GND
+ 0.5
VDD −
0.85
V
VCMR
VDD = VIN = 3.465 V
Max
VDD = 3.465 V, VIN = 0 V
mA
−150
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
4. VIL should not be less than −0.3 V.
5. Common mode input voltage is defined as VIH.
Table 12. LVPECL DC OUTPUT CHARACTERISTICS, VDD/VDDO = 2.5 V/2.5 V, 3.3 V/3.3 V or 3.3 V/2.5 V ±5%;
GND = 0.0 V; TA = −40°C to 85°C (Note 6)
Symbol
Parameter
Min
Typ
Max
Unit
VOH
Output High voltage
VDDO −
1.4
VDDO −
0.9
V
VOL
Output Low voltage
VDDO −
2.1
VDDO −
1.7
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
6. Output pairs are terminated with 50 W to VDDO − 2 V.
Table 13. LVDS DC OUTPUT CHARACTERISTICS, VDD/VDDO = 2.5 V/2.5 V, 3.3 V/3.3 V or 3.3 V/2.5 V ±5%; GND = 0.0 V;
TA = −40°C to 85°C. (Note 7)
Parameter
Symbol
VOH
Output High Voltage
VOL
Output Low Voltage
VOD
Differential Output Voltage
DVOD
VOS
DVOS
RO
Min
Typ
Max
1.433
V
1.064
V
250
mV
VOD Magnitude Change
Offset Voltage
1.125
VOS Magnitude Change
Output Impedance
85
Unit
1.25
25
mV
1.375
V
25
mV
140
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
7. Output pairs are terminated with 100 W line to line at receiver.
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NB3M8T3910G
Table 14. HCSL DC OUTPUT CHARACTERISTICS, VDD/VDDO = 2.5 V/2.5 V, 3.3 V/3.3 V or 3.3 V/2.5 V ±5%; GND = 0.0 V;
TA = −40°C to 85°C. (Note 8)
Parameter
Symbol
Min
Typ
Max
Unit
VOH
HCSL Output HIGH Voltage
520
920
mV
VOL
HCSL Output LOW Voltage
0
150
mV
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
8. Output pairs are terminated with 50 W to GND.
Table 15. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Min
Mode of Oscillation
Typ
Max
Unit
50
MHz
70
W
Fundamental
Frequency
10
Equivalent Series Resistance (ESR)
Shunt Capacitance
Load Capacitance
10
Crystal Drive Level
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7
7
pF
18
pF
100
mW
NB3M8T3910G
AC ELECTRICAL CHARACTERISTICS
Table 16. AC ELECTRICAL CHARACTERISTICS, VDD/VDDO = 2.5 V/2.5 V, 3.3 V/3.3 V or 3.3 V/2.5 V ±5%; GND = 0.0 V;
TA = −40°C to 85°C (Note 9)
Symbol
Parameter
Test Conditions
Min
Typ
fOSC
Input Frequency
External Crystal Input
fOUT
Output Frequency
Diff CLKx/CLKx Inputs
OUTPUTS: LVPECL
OUTPUTS: LVDS
OUTPUTS: HCSL
OUTPUTS: REFOUT
1400
1200
250
250
Single−ended Inputs
XTAL_IN, CLKx, or CLKx
250
Buffer Additive RMS Phase Jitter
(Integrated 12 kHz − 20 MHz)
Diff CLKx/CLKx Inputs
0.03
Single ended XTAL_IN
0.03
Propagation Delay;
CLKx/CLKx to any Qx/Qx
Output Mode LVPECL
Output Mode LVDS
Output Mode HCSL
Output REFOUT, CL = 10 pF
tJITTERΦ
tPD
tsk(o)
Output−to−Output Skew
tsk(pp)
Part−to−Part Skew;
10
Max
Unit
50
MHz
MHz
ps
ps
700
850
950
1600
900
1100
1300
2000
1200
1400
1650
2600
Any Two Clock Outputs with the
Same Buffer Type and Same Load
25
50
Output Mode LVPECL
Output Mode LVDS
Output Mode HCSL
45
30
30
ps
ps
TOD
Valid to High Z Delay, Output
Disable
CLKx/CLKx
200
ns
TOE
High Z to Valid Delay, Output
Enable
CLKx/CLKx
200
ns
VRB
Ringback Voltage Margin
(Notes 10, 11)
HCSL Output
−100
100
mV
VMAX
Voltage High (Notes 12, 13)
HCSL Output
520
920
mV
VMIN
Voltage Low (Notes 12, 14)
HCSL Output
−150
150
mV
VCROSS
Absolute Crossing Voltage
(Notes 12, 15, 16)
HCSL Output
160
460
mV
Total Variation of VCROSS over all
edges; (Notes 12, 15 and 17)
HCSL Output
140
mV
DVCROSS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed
circuit board with maintained transverse airflow greater than 500 lfpm.
9. OUTPUT MODE LVPECL: Output pairs are terminated with 50 W to VDDO − 2 V.
OUTPUT MODE LVDS: Output pairs are terminated with 100 W line to line at receiver.
OUTPUT MODE HCSL: Output pairs are terminated with 50 W to GND
REFOUT Output terminated with 50 W to VDDO/2.
10. Measurement taken from differential waveform.
11. TSTABLE is the time the differential clock must maintain a minimum ± 150 mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100 mV differential range.
12. Measurement taken from single−ended waveform.
13. Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
14. Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
15. Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of Qx.
16. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement.
17. Defined as the total variation of all crossing voltages of rising Qx and falling nQx, This is the maximum allowed variance in Vcross for any
particular system.
18. Measured from −150 mV to +150 mV on the differential waveform (Qx minus nQx). The signal must be monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.
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NB3M8T3910G
Table 16. AC ELECTRICAL CHARACTERISTICS, VDD/VDDO = 2.5 V/2.5 V, 3.3 V/3.3 V or 3.3 V/2.5 V ±5%; GND = 0.0 V;
TA = −40°C to 85°C (Note 9)
Symbol
DtR / DtF
tR / tF
tR / tF
tR / tF
tR / tF
odc
VPP
MUX_ISOLATION
Parameter
Test Conditions
Min
Rise/Fall Edge Rate (Notes 12,
and 18)
HCSL Outputs; Measured between
150 mV to +150 mV
Output Rise/Fall Time
Output Rise/ Fall Time
Output Rise/ Fall Time
Typ
Max
Unit
0.6
4.0
V/ns
HCSL Outputs 20% to 80% at
50 MHz
VDDO = 3.3 V
VDDO = 2.5 V
250
250
550
750
LVDS Outputs (20% to 80% at
50 MHz)
VDDO = 3.3 V
VDDO = 2.5 V
150
150
500
550
LVPECL Outputs (20% to 80% at
50 MHz)
VDDO = 3.3 V
VDDO = 2.5 V
125
125
325
375
ps
ps
ps
Output Rise/ Fall Time
REFOUT (20% to 80% at 50 MHz)
CL = 10 pF
550
Output Duty Cycle
f ≤ 350 MHz
f ≤ 250 MHz
f ≤ 350 MHz
LVPECL
HCSL
LVDS
48
48
47
52
52
53
%
f = 50 MHz
CL = 10 pF
REFOUT
45
55
%
1000
mV
Output Swing Single−Ended
LVPECL Outputs
LVDS Outputs
HCSL Outputs
400
250
520
MUX Isolation
156.25 MHz
55
ps
dB
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed
circuit board with maintained transverse airflow greater than 500 lfpm.
9. OUTPUT MODE LVPECL: Output pairs are terminated with 50 W to VDDO − 2 V.
OUTPUT MODE LVDS: Output pairs are terminated with 100 W line to line at receiver.
OUTPUT MODE HCSL: Output pairs are terminated with 50 W to GND
REFOUT Output terminated with 50 W to VDDO/2.
10. Measurement taken from differential waveform.
11. TSTABLE is the time the differential clock must maintain a minimum ± 150 mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100 mV differential range.
12. Measurement taken from single−ended waveform.
13. Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
14. Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
15. Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of Qx.
16. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement.
17. Defined as the total variation of all crossing voltages of rising Qx and falling nQx, This is the maximum allowed variance in Vcross for any
particular system.
18. Measured from −150 mV to +150 mV on the differential waveform (Qx minus nQx). The signal must be monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.
www.onsemi.com
9
NB3M8T3910G
TYPICAL PERFORMANCE CHARACTERISTICS
350
0.9
280
0.8
210
OUTPUT SWING (V)
1.0
0.7
0.6
0.5
0.4
0.3
0.2
140
70
0
−70
−140
−210
0.1
−280
0
0
1
2
3
4
5
6
7
8
9
−350
10
0
1
2
3
4
5
6
7
8
9
TIME (1 ns/div)
TIME (1 ns/div)
Figure 3. LVPECL Output Swing @
156.25 MHz
Figure 4. LVDS Output Swing @ 156.25 MHz
0.8
OUTPUT SWING (V)
OUTPUT SWING (V)
VDD = 3.3 V, VDDO = 3.3 V, TA = +25°C
0.6
0.4
0.2
0
0
1
2
3
4
5
6
TIME (1 ns/div)
7
8
9
Figure 5. HCSL Output Swing @ 156.25 MHz
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10
10
10
NB3M8T3910G
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 3.3 V, VDDO = 3.3 V, TA = +25°C
LVPECL Output
CLK Source
Figure 6. LVPECL Phase Noise @ 156.25 MHz
LVDS Output
CLK Source
Figure 7. LVDS Phase Noise @ 156.25 MHz
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11
NB3M8T3910G
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 3.3 V, VDDO = 3.3 V, TA = +25°C
HCSL Output
CLK Source
Figure 8. HCSL Phase Noise @ 156.25 MHz
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12
NB3M8T3910G
PARAMETER MEASUREMENT INFORMATION
Qx
VDD
Qx
CLK
VPP
Qv
Xpoint
VCMR
CLK
Qv
GND
tsk(o)
Figure 10. Within Device Output Skew
x=Bank A or Bank B
Figure 9. Differential Input Level
CLKx
Qx
Part 1
CLKx
Qx
Qv
Qv
Part 2
Qv
Qv
tPD
tsk(pp)
Figure 11. Device to Device Output Skew
x = Bank A or Bank B
Figure 12. Propagation Delay
Spectrum of O utput Signal Qx
MU X selects
active input clock
signal
Amplitude (dB)
A0
MU X_ISOL = A0 − A1
MU X selects
static input
A1
fc
(Fundamental)
Figure 13. MUX Isolation
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13
Frequ ency
NB3M8T3910G
PARAMETER MEASUREMENT INFORMATION
Qx
80%
80%
VPP
20%
20%
Qx
tR
tF
Figure 14. Output Rise/Fall Time
VDD
Qx
Qx
DC
Levels
Qx
Zo = 50 W
50 W
LVDS
Zo = 50 W
Qx
tPW
tPERIOD
odc = (tPW / tPERIOD) x 100%
50 W
VOS/
DVOS
GND
Figure 15. Output Duty Cycle / Pulse Width /
Period
Figure 16. LVDS Offset Voltage Setup
VDD
Qx
DC
Levels
Zo = 50 W
100 W
LVDS
Zo = 50 W
VOS/
DVOS
Qx
GND
Figure 17. LVDS Differential Output
Voltage Setup
TSTABLE
+150 mV
+100 mV
0.0 V
Qx − Qx
VRB
0.0 V
Diff Pos Duty Cycle Diff Pos Duty Cycle
−100 mV
Diff Period
+150 mV
Odc(diff) = (tDIFFPOSPW / tDIFFPERIOD)
VRB
Qx − Qx
Figure 18. Differential Measurement
Points for Duty Cycle / Pulse Width /
Period
TSTABLE
Figure 19. HCSL Differential
Measurement Points for Ringback
VMAX = 920 mV
Qx
Qx
VCROSS_MAX = 460 mV
VCROSS_MIN = 160 mV
Qx
VCROSS
Qx
VMIN = −150 mV
Figure 20. Single−Ended Measurement Points for HCSL
Absolute Crossing Voltage
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14
Figure 21. Single−Ended Measurement
Points for HCSL DVCROSS
NB3M8T3910G
APPLICATION INFORMATION
Recommendations for Unused Input and Output Pins
differential output pair should either be left floating or
terminated.
Inputs:
LVDS Outputs
CLK/CLK Inputs
All unused LVDS output pairs can be either left floating
or terminated with 100 W across. If they are left floating, we
recommend that there is no trace attached.
For applications not requiring the use of the differential
input, both CLK and CLK can be left floating. Though not
required, but for additional protection, a 1 kW resistor can be
tied from CLK to ground.
Differential Input with Single−Ended Interconnect
Refer to Figure 22 to interconnect a single ended signal to
a Differential Pair of inputs. The reference bias voltage
VREF = VDD/2 is generated by the resistor divider of R1 and
R2. Bypass capacitor (C1) can filter noise on the DC bias.
This bias circuit should be located as close to the input pin
as possible. Adjust R1 and R2 to common mode voltage of
the signal input swing to preserve duty cycle.
This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs)
equals the transmission line impedance. In addition,
matched termination by R3 and R4 will attenuate the signal
amplitude in half. This can be done in one of two ways. First,
R3 and R4 in parallel should equal the transmission line
impedance. For most 50 W applications, R3 and R4 can be
100 W. The differential input can handle full rail LVCMOS
signaling, but it is recommended that the amplitude be
reduced. The datasheet specifies differential amplitude
which needs to be doubled for a single ended equivalent
stimulus. VILmin cannot be less than −0.3 V and VIH max
cannot be more than VDD + 0.3 V. The datasheet
specifications are characterized and guaranteed by using a
differential signal.
Crystal Inputs
For applications not requiring the use of the crystal
oscillator input, both XTAL_IN and XTAL_OUT can be left
floating. Though not required, but for additional protection,
a 1 kW resistor can be tied from XTAL_IN to ground.
LVCMOS Control Pins
All control pins have internal pulldowns; additional
resistance is not required but can be added for additional
protection. A 1 kW resistor can be used.
Outputs:
LVCMOS Outputs
The unused LVCMOS output can be left floating and
recommend that there is no trace attached.
Differential Outputs
All unused differential outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
LVPECL Outputs
All unused LVPECL output pairs can be left floating. We
recommend that there is no trace attached. Both sides of the
Figure 22. Differential Input with Single−Ended Interconnect
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15
NB3M8T3910G
Crystal Input Interface
CLOCK Overdriving the XTAL Interface
The device has been characterized with 18 pF parallel
resonant crystals. The capacitor values, C1 and C2, shown
in Figure 23 below were determined using an 18 pF parallel
resonant crystal and were chosen to minimize the ppm error.
The C1 and C2 load caps are in parallel and must be reduced
by any input and stray capacitance. Typical value would be
36 pF minus all input and stray capacitance, or about 25 to
30 pF. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
The XTAL_IN input can accept a single−ended LVCMOS
signal through an AC coupling capacitor. A general
LVCMOS interface diagram is shown in Figure 24 and a
general LVPECL interface in Figure 25. The XTAL_OUT
pin must be left floating. The maximum amplitude of the
input signal should not exceed 2 V and the input edge rate
can be as slow as 10 ns. This configuration requires that the
output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In
addition, matched termination at the crystal input will
attenuate the signal in half. This can be done in one of two
ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50 W applications,
R1 and R2 can be 100 W. This can also be accomplished by
removing R1 and making R2 50 W. By overdriving the
crystal oscillator, the device will be functional, but note, the
device performance is guaranteed by using a quartz crystal.
Figure 23. Crystal Input Interface
VDD
RO
R1
100 W
Rs
XTAL_IN
Zo = 50 W
LVCMOS
R2
100 W
Z0 = RO + Rs
C1
0.1 mF
XTAL_OUT
NB3M8T3910G
GND
Figure 24. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_IN
Zo = 50 W
LVPECL
C1
0.1 mF
Zo = 50 W
NB3M8T3910G
XTAL_OUT
R2
50 W
R1
50 W
GND
Figure 25. General Diagram for LVPECL Driver to XTAL Input Interface
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16
NB3M8T3910G
HCSL RECOMMENDED TERMINATION
0.5” Max
Length 1
Zo = 50 W
0.2” Max
Length 2
1−14” Max
Length 4
0.5−3.5” Max
Length 5
Zo = 50 W
Zo = 50 W
Zo = 50 W
Zo = 50 W
Zo = 50 W
Zo = 50 W
22−33 W
0.2” Max
Length 3
50 W
PCI Express
Add in Card
PCI Express
Connector
Zo = 50 W
Zo = 50 W
Zo = 50 W
PCI Express
Clock Driver
22−33 W
50 W
GND = 0.0
Figure 26. HCSL Recommended Interconnect and Termination Board to Board
Figure 26 is the recommended termination for
applications which require the receiver and driver to be on
a separate PCB. All traces should be 50 W impedance.
18” Max
Length 1
PCI Express
Clock
Driver
0.2” Max
Length 2
Zo = 50 W
Zo = 50 W
Zo = 50 W
Zo = 50 W
50 W
50 W
GND = 0.0
Figure 27. Recommended Termination Interconnect and Termination within a Board
be used with either type of output structure. In addition,
since these outputs are LVDS compatible, the amplitude and
common mode input range of the input receivers should be
verified for compatibility with the output.
Figure 27 is the recommended termination for
applications which require a point to point connection and
contain the driver and receiver on the same PCB. All traces
should all be 50 W impedance.
LVDS Driver Termination
CLKx
Qx
A general LVDS interface is shown in Figure 28. Standard
termination for LVDS type output structure requires both a
100 W parallel resistor at the receiver and a 100 W
differential transmission line environment. In order to avoid
any transmission line reflection issues, the 100 W resistor
must be placed as close to the receiver as possible. The
standard termination schematic as shown in Figure 28 can
Zo = 50 W
100 W
LVDS
LVDS
Zo = 50 W
Qx
CLKx
Figure 28. Typical LVDS Driver Termination
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17
NB3M8T3910G
Termination for 3.3 V LVPECL Outputs
sources must be used for functionality. These outputs are
designed to drive 50 W transmission lines. Matched
impedance techniques should be used to maximize
operating frequency and minimize signal distortion.
Figures 29 and 30 show two different layouts which are
recommended only as guidelines. Consult AND8020/D for
further termination information
The clock layout topology shown below is a typical
termination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines. The
differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore,
terminating resistors (DC current path to ground) or current
VDD = +3.3 V
VDD = +3.3 V
VDD = +3.3 V
125 W
Qx
125 W
CLKx
Zo = 50 W
Differential
In
CLKx
Zo = 50 W
84 W
CLKx
Qx
LVPECL
Qx
VDD = +3.3 V
VDD = +3.3 V
Zo = 50 W
CLKx
Zo = 50 W
Qx
84 W
GND = 0.0
GND = 0.0
Differential
In
LVPECL
50 W
GND = 0.0
50 W
GND = 0.0
50 W
GND = 0.0
GND = 0.0
Figure 29. CLK / CLK Input Driven by 3.3 V LVPECL
Driver (Thevenin Parallel Termination)
Figure 30. CLK / CLK Input Driven by 3.3 V
LVPECL Driver (“Y” Parallel Termination)
Termination for 2.5 V LVPECL Outputs
− 2 V is very close to ground level. The R3 in Figure 32 can
be eliminated and the termination is shown in Figure 33.
Consult AND8020 for further termination information
Figures 31 and 32 show examples of termination for
2.5 V LVPECL driver. These terminations are equivalent to
terminating 50 W to VDD − 2 V. For VDDO = 2.5 V, the VDDO
VDD = +2.5 V
250 W
Qx
250 W
CLKx
Zo = 50 W
LVPECL
CLKx
Zo = 50 W
Qx
VDD = +2.5 V
VDD = +2.5 V
VDD = +2.5 V
GND = 0.0
CLKx
Qx
Zo = 50 W
LVPECL
Differential
In
Qx
R1
50 W
R2
50 W
GND = 0.0
GND = 0.0
Differential
In
CLKx
Zo = 50 W
62/5 W
62.5 W
VDD = +2.5 V
GND = 0.0
R3
18 W
GND = 0.0
GND
Figure 31. CLK / CLK Input Driven by 2.5 V
LVPECL Driver (Thevenin Parallel Termination)
Figure 32. CLK / CLK Input Driven by 2.5 V
LVPECL Driver (“Y” Parallel Termination)
VDD = +2.5 V
VDD = +2.5 V
Qx
CLKx
Zo = 50 W
LVPECL
CLKx
Zo = 50 W
Qx
62.5 W
Differential
In
62/5 W
GND = 0.0
GND = 0.0
GND = 0.0
Figure 33. CLK / CLK Input Driven by 2.5 V LVPECL Driver (Modified “Y” Parallel Termination)
www.onsemi.com
18
NB3M8T3910G
QFN EPAD Thermal Release Path
to ground through these vias. The vias act as thermal
conduits. The number of vias may be application specific
and dependent upon the package power dissipation as well
as electrical conductivity requirements. Thus, thermal and
electrical analysis and/or testing are recommended to
determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias
is incorporated in the land pattern. It is recommended to use
as many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13 mils
(0.30 to 0.33 mm) with 1 oz copper via barrel plating. This
is desirable to avoid any solder wicking inside the via during
the soldering process which may result in voids in solder
between the exposed pad/slug and the thermal land.
Precautions should be taken to eliminate any solder voids
between the exposed heat slug and the land pattern. Note:
These recommendations are to be used as a guideline only.
In order to maximize both the removal of heat from the
package and the electrical performance, a land pattern must
be incorporated on the Printed Circuit Board (PCB) within
the footprint of the package corresponding to the exposed
metal pad or exposed heat slug on the package, as shown in
Figure 34. The solderable area on the PCB, as defined by the
solder mask, should be at least the same size/shape as the
exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should
be designed on the PCB between the outer edges of the land
pattern and the inner edges of pad pattern for the leads to
avoid any shorts. While the land pattern on the PCB provides
a means of heat transfer and electrical grounding from the
package to the board through a solder joint, thermal vias are
necessary to effectively conduct from the surface of the PCB
to the ground plane(s). The land pattern must be connected
Figure 34. P.C. Assembly for Exposed Pad Thermal Release Path − Side View (drawing not to scale)
ORDERING INFORMATION
Device
NB3M8T3910GMNR2G
Package
Shipping†
QFN48
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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19
NB3M8T3910G
PACKAGE DIMENSIONS
QFN48 7x7, 0.5P
CASE 485AJ
ISSUE O
ÈÈÈ
ÈÈÈ
ÈÈÈ
PIN 1
LOCATION
D
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO THE PLATED
TERMINAL AND IS MEASURED ABETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A B
E
2X
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L
0.15 C
DETAIL A
OPTIONAL CONSTRUCTION
2X SCALE
2X
0.15 C
TOP VIEW
(A3)
0.05 C
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
7.00 BSC
5.00
5.20
7.00 BSC
5.00
5.20
0.50 BSC
0.20
−−−
0.30
0.50
A
0.08 C
SOLDERING FOOTPRINT*
A1
NOTE 4
2X
C
SIDE VIEW
SEATING
PLANE
D2
DETAIL A
1
K
13
5.20
25
12
2X
7.30
48X
0.63
E2
48X
1
48
48X
L
0.30
36
37
e
e/2
0.50 PITCH
DIMENSIONS: MILLIMETERS
48X
BOTTOM VIEW
b
0.10 C A B
0.05 C
NOTE 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NB3M8T3910/D