AD ADS1013 ADS1014 ADS1015 S101 5 ADS 1015 www.ti.com SBAS473C – MAY 2009 – REVISED OCTOBER 2009 Ultra-Small, Low-Power, 12-Bit Analog-to-Digital Converter with Internal Reference Check for Samples: ADS1013 ADS1014 ADS1015 FEATURES DESCRIPTION • The ADS1013, ADS1014, and ADS1015 are precision analog-to-digital converters (ADCs) with 12 bits of resolution offered in an ultra-small, leadless QFN-10 package or an MSOP-10 package. The ADS1013/4/5 are designed with precision, power, and ease of implementation in mind. The ADS1013/4/5 feature an onboard reference and oscillator. Data are transferred via an I2C-compatible serial interface; four I2C slave addresses can be selected. The ADS1013/4/5 operate from a single power supply ranging from 2.0V to 5.5V. 1 23 • • • • • • • • • ULTRA-SMALL QFN PACKAGE: 2mm × 1,5mm × 0,4mm WIDE SUPPLY RANGE: 2.0V to 5.5V LOW CURRENT CONSUMPTION: Continuous Mode: Only 150μA Single-Shot Mode: Auto Shut-Down PROGRAMMABLE DATA RATE: 128SPS to 3.3kSPS INTERNAL LOW-DRIFT VOLTAGE REFERENCE INTERNAL OSCILLATOR INTERNAL PGA I2C™ INTERFACE: Pin-Selectable Addresses FOUR SINGLE-ENDED OR TWO DIFFERENTIAL INPUTS (ADS1015) PROGRAMMABLE COMPARATOR (ADS1014 and ADS1015) The ADS1013/4/5 operate either in continuous conversion mode or a single-shot mode that automatically powers down after a conversion and greatly reduces current consumption during idle periods. The ADS1013/4/5 are specified from –40°C to +125°C. APPLICATIONS • • • • • The ADS1013/4/5 can perform conversions at rates up to 3300 samples per second (SPS). An onboard PGA is available on the ADS1014 and ADS1015 that offers input ranges from the supply to as low as ±256mV, allowing both large and small signals to be measured with high resolution. The ADS1015 also features an input multiplexer (MUX) that provides two differential or four single-ended inputs. PORTABLE INSTRUMENTATION CONSUMER GOODS BATTERY MONITORING TEMPERATURE MEASUREMENT FACTORY AUTOMATION AND PROCESS CONTROLS VDD VDD Voltage Reference ADS1015 ADS1014 ADS1013 Comparator Voltage Reference ALERT/RDY AIN0 AIN0 AIN1 ADDR 12-Bit DS ADC 2 IC Interface SCL AIN1 AIN3 SDA ADDR AIN2 MUX PGA 12-Bit DS ADC ADS1015 Only 2 IC Interface SCL SDA Oscillator Oscillator GND GND 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a trademark of NXP Semiconductors. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated ADS1013 ADS1014 ADS1015 SBAS473C – MAY 2009 – REVISED OCTOBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) ADS1013, ADS1014, ADS1015 VDD to GND Analog input current Analog input current Analog input voltage to GND SDA, SCL, ADDR, ALERT/RDY voltage to GND Maximum junction temperature Storage temperature range (1) UNIT –0.3 to +5.5 V 100, momentary mA 10, continuous mA –0.3 to VDD + 0.3 V –0.5 to +5.5 V +150 °C –60 to +150 °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PRODUCT FAMILY 2 DEVICE PACKAGE DESIGNATOR MSOP/QFN RESOLUTION (Bits) MAXIMUM SAMPLE RATE (SPS) ADS1113 BROI/N6J 16 860 ADS1114 BRNI/N5J 16 860 ADS1115 BOGI/N4J 16 860 Yes ADS1013 BRMI/N9J 12 3300 ADS1014 BRQI/N8J 12 3300 ADS1015 BRPI/N7J 12 3300 Yes Submit Documentation Feedback PGA INPUT CHANNELS (Differential/ Single-Ended) No No 1/1 Yes Yes 1/1 Yes 2/4 No No 1/1 Yes Yes 1/1 Yes 2/4 COMPARATOR Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C – MAY 2009 – REVISED OCTOBER 2009 ELECTRICAL CHARACTERISTICS All specifications at –40°C to +125°C, VDD = 3.3V, and Full-Scale (FS) = ±2.048V, unless otherwise noted. Typical values are at +25°C. ADS1013, ADS1014, ADS1015 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input voltage (1) VIN = (AINP) – (AINN) Analog input voltage AINP or AINN to GND ±4.096/PGA GND Differential input impedance V VDD V See Table 2 FS = ±6.144V (1) 10 MΩ FS = ±4.096V , ±2.048V 6 MΩ FS = ±1.024V 3 MΩ FS = ±0.512V, ±0.256V 100 MΩ (1) Common-mode input impedance SYSTEM PERFORMANCE Resolution No missing codes 12 Data rate (DR) Data rate variation All data rates Output noise Integral nonlinearity Bits 128, 250, 490, 920, 1600, 2400, 3300 –10 SPS 10 % See Typical Characteristics DR = 128SPS, FS = ±2.048V, best fit (2) FS = ±2.048V, differential inputs Offset error Offset drift Gain error (3) Gain drift (3) 0 0.5 LSB ±0.5 LSB FS = ±2.048V, single-ended inputs ±0.25 LSB FS = ±2.048V 0.005 LSB/°C FS = ±2.048V at 25°C 0.05 FS = ±0.256V 7 0.25 FS = ±2.048V 5 FS = ±6.144V (1) 5 Match between any two PGA gains 0.02 0.1 Gain match Match between any two inputs 0.05 0.1 Offset match Match between any two inputs 0.25 PGA gain match (3) % ppm/°C 40 ppm/°C ppm/°C % % LSB DIGITAL INPUT/OUTPUT Logic level VIH 0.7VDD 5.5 V VIL GND – 0.5 0.3VDD V 0.4 V 10 μA VOL IOL = 3mA GND 0.15 Input leakage (1) (2) (3) IH VIH = 5.5V IL VIL = GND 10 μA This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD + 0.3V be applied to this device. 99% of full-scale. Includes all errors from onboard PGA and reference. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 Submit Documentation Feedback 3 ADS1013 ADS1014 ADS1015 SBAS473C – MAY 2009 – REVISED OCTOBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at –40°C to +125°C, VDD = 3.3V, and Full-Scale (FS) = ±2.048V, unless otherwise noted. Typical values are at +25°C. ADS1013, ADS1014, ADS1015 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5.5 V 2 μA 5 μA 200 μA POWER-SUPPLY REQUIREMENTS Power-supply voltage 2 Power-down current at 25°C 0.5 Power-down current up to 125°C Supply current Operating current at 25°C 150 Operating current up to 125°C Power dissipation μA 300 VDD = 5.0V 0.9 mW VDD = 3.3V 0.5 mW VDD = 2.0V 0.3 mW TEMPERATURE Storage temperature –60 +150 °C Specified temperature –40 +125 °C PIN CONFIGURATIONS RUG PACKAGE QFN-10 (TOP VIEW) DGS PACKAGE MSOP-10 (TOP VIEW) SCL 10 ADDR ALERT/RDY (ADS1014/5 Only) 1 2 GND 3 AIN0 4 9 ADS1013 ADS1014 ADS1015 8 ADDR 1 ALERT/RDY (ADS1014/5 Only) 2 GND 3 AIN0 AIN1 10 SCL SDA 9 SDA 8 VDD 4 7 AIN3 (ADS1015 Only) 5 6 AIN2 (ADS1015 Only) VDD 7 AIN3 (ADS1015 Only) 6 AIN2 (ADS1015 Only) 5 ADS1013 ADS1014 ADS1015 AIN1 PIN DESCRIPTIONS DEVICE PIN # ADS1013 ADS1014 ADS1015 FUNCTION 1 ADDR ADDR ADDR Digital input 2 NC (1) 3 GND GND GND Supply 4 AIN0 AIN0 AIN0 Analog input Differential channel 1: Positive input or single-ended channel 1 input 5 AIN1 AIN1 AIN1 Analog input Differential channel 1: Negative input or single-ended channel 2 input 6 NC NC AIN2 Analog input Differential channel 2: Positive input or single-ended channel 3 input (NC for ADS1013/4) 7 NC NC AIN3 Analog input Differential channel 2: Negative input or single-ended channel 4 input (NC for ADS1013/4) 8 VDD VDD VDD Supply 9 SDA SDA SDA Digital I/O 10 SCL SCL SCL Digital input (1) 4 ALERT/RDY ALERT/RDY Digital output DESCRIPTION I2C slave address select Digital comparator output or conversion ready (NC for ADS1013) Ground Power supply: 2.0V to 5.5V Serial data: Transmits and receives data Serial clock input: Clocks data on SDA NC pins may be left floating or tied to ground. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C – MAY 2009 – REVISED OCTOBER 2009 TIMING REQUIREMENTS tLOW tF tR tHDSTA SCL tHDSTA tHIGH tHDDAT tSUSTO tSUSTA tSUDAT SDA tBUF P S S P Figure 1. I2C Timing Diagram Table 1. I2C Timing Definitions FAST MODE PARAMETER HIGH-SPEED MODE MIN MAX MIN MAX UNIT 0.4 0.01 3.4 MHz SCL operating frequency fSCL 0.01 Bus free time between START and STOP condition tBUF 600 160 ns tHDSTA 600 160 ns Repeated START condition setup time tSUSTA 600 160 ns Stop condition setup time tSUSTO 600 160 ns Data hold time tHDDAT 0 0 ns Data setup time tSUDAT 100 10 ns SCL clock low period tLOW 1300 160 ns SCL clock high period tHIGH 600 Hold time after repeated START condition. After this period, the first clock is generated. 60 ns Clock/data fall time tF 300 160 ns Clock/data rise time tR 300 160 ns Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 Submit Documentation Feedback 5 ADS1013 ADS1014 ADS1015 SBAS473C – MAY 2009 – REVISED OCTOBER 2009 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C and VDD = 3.3V, unless otherwise noted. OPERATING CURRENT vs TEMPERATURE SHUTDOWN CURRENT vs TEMPERATURE 5.0 300 4.5 Shutdown Current (mA) Operating Current (mA) 250 VDD = 5V 200 150 VDD = 3.3V VDD = 2V 100 4.0 3.5 VDD = 2V 3.0 2.5 2.0 VDD = 3.3V 1.5 1.0 50 0.5 0 -40 -20 0 20 40 60 80 100 120 VDD = 5V 0 -40 140 0 -20 20 Temperature (°C) Figure 2. FS = ±4.096V FS = ±2.048V (1) FS = ±1.024V FS = ±0.512V 50 VDD = 2V 40 Offset Voltage (mV) Offset Error (mV) 120 140 VDD = 5V 50 0 -50 -100 -150 -200 VDD = 5V 30 VDD = 4V 20 VDD = 3V 10 0 VDD = 2V -10 -250 -20 -300 -40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 Figure 4. GAIN ERROR vs TEMPERATURE 80 100 120 140 NOISE PLOT 4 DR = 3300SPS FS = ±2.048V 14k Samples FS = ±0.256V Output Code (LSBs) 3 FS = ±0.512V 0.02 0.01 FS = ±1.024V, ±2.048V, (1) (1) ±4.096V , and ±6.144V 0 60 Figure 5. 0.05 0.04 40 Temperature (°C) Temperature (°C) Gain Error (%) 100 60 100 -0.01 -0.02 2 1 0 -1 -2 -3 -0.03 -4 -0.04 -40 -20 0 20 40 60 80 100 120 140 0 2000 4000 6000 8000 10000 12000 14000 Reading Number Temperature (°C) Figure 6. 6 80 DIFFERENTIAL OFFSET vs TEMPERATURE 150 (1) 60 Figure 3. SINGLE-ENDED OFFSET ERROR vs TEMPERATURE (1) 0.03 40 Temperature (°C) Figure 7. This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD + 0.3V be applied to this device. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C – MAY 2009 – REVISED OCTOBER 2009 OVERVIEW The ADS1013/4/5 are very small, low-power, 12-bit, delta-sigma (ΔΣ) analog-to-digital converters (ADCs). The ADS1013/4/5 are extremely easy to configure and design into a wide variety of applications, and allow precise measurements to be obtained with very little effort. Both experienced and novice users of data converters find designing with the ADS1013/4/5 family to be intuitive and problem-free. The ADS1013/4/5 consist of a ΔΣ analog-to-digital (A/D) core with adjustable gain (excludes the ADS1013), an internal voltage reference, a clock oscillator, and an I2C interface. An additional feature available on the ADS1014/5 is a programmable digital comparator that provides an alert on a dedicated pin. All of these features are intended to reduce required external circuitry and improve performance. Figure 8 shows the ADS1015 functional block diagram. The ADS1013/4/5 A/D core measures a differential signal, VIN, that is the difference of AINP and AINN. A MUX is available on the ADS1015. This architecture results in a very strong attenuation of any common-mode signals. The converter core consists of a differential, switched-capacitor ΔΣ modulator followed by a digital filter. Input signals are compared to the internal voltage reference. The digital filter receives a high-speed bitstream from the modulator and outputs a code proportional to the input voltage. The ADS1013/4/5 have two available conversion modes: single-shot mode and continuous conversion mode. In single-shot mode, the ADC performs one conversion of the input signal upon request and stores the value to an internal result register. The device then enters a low-power shutdown mode. This mode is intended to provide significant power savings in systems that only require periodic conversions or when there are long idle periods between conversions. In continuous conversion mode, the ADC automatically begins a conversion of the input signal as soon as the previous conversion is completed. The rate of continuous conversion is equal to the programmed data rate. Data can be read at any time and always reflect the most recent completed conversion. VDD ADS1015 Comparator Voltage Reference MUX ALERT/RDY Gain = 2/3, 1, 2, 4, 8, or 16 AIN0 ADDR PGA AIN1 12-Bit DS ADC 2 IC Interface SCL SDA AIN2 Oscillator AIN3 GND Figure 8. ADS1015 Functional Block Diagram Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 Submit Documentation Feedback 7 ADS1013 ADS1014 ADS1015 SBAS473C – MAY 2009 – REVISED OCTOBER 2009 www.ti.com QUICKSTART GUIDE For example, to write to the configuration register to set the ADS1013/4/5 to continuous conversion mode and then read the conversion result, send the following bytes in this order: This section provides a brief example of ADS1013/4/5 communications. Refer to subsequent sections of this data sheet for more detailed explanations. Hardware for this design includes: one ADS1013/4/5 configured with an I2C address of 1001000; a microcontroller with an I2C interface (TI recommends the MSP430 product line); discrete components such as resistors, capacitors, and serial connectors; and a 2V to 5V power supply. Figure 9 shows the basic hardware configuration. Write to Config register: First byte: 0b10010000 (first 7-bit I2C address followed by a low read/write bit) Second byte: 0b00000001 (points to Config register) Third byte: 0b00000100 (MSB of the Config register to be written) The ADS1013/4/5 communicate with the master (microcontroller) through an I2C interface. The master provides a clock signal on the SCL pin and data are transferred via the SDA pin. The ADS1013/4/5 never drive the SCL pin. For information on programming and debugging the microcontroller being used, refer to the device-specific product data sheet. Fourth byte: 0b10000011 (LSB of the Config register to be written) Write to Pointer register: First byte: 0b10010000 (first 7-bit I2C address followed by a low read/write bit) Second byte: 0b00000000 (points to Conversion register) The first byte sent by the master should be the ADS1013/4/5 address followed by a bit that instructs the ADS1013/4/5 to listen for a subsequent byte. The second byte is the register pointer. Refer to Table 6 for a register map. The third and fourth bytes sent from the master are written to the register indicated in the second byte. Refer to Figure 16 and Figure 17 for read and write operation timing diagrams, respectively. All read and write transactions with the ADS1013/4/5 must be preceded by a start condition and followed by a stop condition. Read Conversion register: First byte: 0b10010001 (first 7-bit I2C address followed by a high read/write bit) Second byte: the ADS1013/4/5 response with the MSB of the Conversion register Third byte: the ADS1013/4/5 response with the LSB of the Conversion register +3.3V VDD GND 100nF +3.3V 2 I C-Capable Master (MSP430) AIN0 AIN1 AIN2 (ADS1015 Only) AIN3 (ADS1015 Only) ADDR 10kW +3.3V 10kW ADS1013/4/5 VDD SCL SDA SCL SDA ALERT (ADS1014/5 Only) 100nF GND Serial/UART JTAG Figure 9. Basic Hardware Configuration 8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C – MAY 2009 – REVISED OCTOBER 2009 MULTIPLEXER The ADS1015 contains an input multiplexer, as shown in Figure 10. Either four single-ended or two differential signals can be measured. Additionally, AIN0 and AIN1 may be measured differentially to AIN3. The multiplexer is configured by three bits in the Config register. When single-ended signals are measured, the negative input of the ADC is internally connected to GND by a switch within the multiplexer. VDD ADS1015 AIN0 VDD GND AINP VDD AINN AIN1 GND AIN2 VDD GND AIN3 GND GND Figure 10. ADS1015 MUX The ADS1013 and ADS1014 do not have a multiplexer. Either one differential or one single-ended signal may be measured with these devices. For single-ended measurements, connect the AIN1 pin to GND. Note that in subsequent sections of this data sheet, AINP refers to AIN0 and AINN refers to AIN1 for the ADS1013 and ADS1014. When measuring single-ended inputs it is important to note that the negative range of the output codes are not used. These codes are for measuring negative differential signals such as (AINP – AINN) < 0. ESD diodes to VDD and GND protect the inputs on all three devices (ADS1013, ADS1014, and ADS1015). To prevent the ESD diodes from turning on, the absolute voltage on any input must stay within the following range: If it is possible that the voltages on the input pins may violate these conditions, external Schottky clamp diodes and/or series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings table). Also, overdriving one unused input on the ADS1015 may affect conversions taking place on other input pins. If overdrive on unused inputs is possible, again it is recommended to clamp the signal with external Schottky diodes. ANALOG INPUTS The ADS1013/4/5 use a switched-capacitor input stage where capacitors are continuously charged and then discharged to measure the voltage between AINP and AINN. The capacitors used are small, and to external circuitry the average loading appears resistive. This structure is shown in Figure 12. The resistance is set by the capacitor values and the rate at which they are switched. Figure 11 shows the on/off setting of the switches illustrated in Figure 12. During the sampling phase, S1 switches are closed. This event charges CA1 to AINP, CA2 to AINN, and CB to (AINP – AINN). During the discharge phase, S1 is first opened and then S2 is closed. Both CA1 and CA2 then discharge to approximately 0.7V and CB discharges to 0V. This charging draws a very small transient current from the source driving the ADS1013/4/5 analog inputs. The average value of this current can be used to calculate the effective impedance (Reff) where Reff = VIN/IAVERAGE. tSAMPLE ON S1 OFF ON S2 OFF Figure 11. S1 and S2 Switch Timing for Figure 12 GND – 0.3V < AINx < VDD + 0.3V Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 Submit Documentation Feedback 9 ADS1013 ADS1014 ADS1015 SBAS473C – MAY 2009 – REVISED OCTOBER 2009 www.ti.com 0.7V CA1 AINP S1 ZCM S2 0.7V Equivalent Circuit AINP CB S1 ZDIFF S2 AINN AINN 0.7V CA2 ZCM fCLK = 250kHz 0.7V Figure 12. Simplified Analog Input Circuit The common-mode input impedance is measured by applying a common-mode signal to shorted AINP and AINN inputs and measuring the average current consumed by each pin. The common-mode input impedance changes depending on the PGA gain setting, but is approximately 6MΩ for the default PGA gain setting. In Figure 12, the common-mode input impedance is ZCM. The typical value of the input impedance cannot be neglected. Unless the input source has a low impedance, the ADS1013/4/5 input impedance may affect the measurement accuracy. For sources with high output impedance, buffering may be necessary. Active buffers introduce noise, and also introduce offset and gain errors. All of these factors should be considered in high-accuracy applications. The differential input impedance is measured by applying a differential signal to AINP and AINN inputs where one input is held at 0.7V. The current that flows through the pin connected to 0.7V is the differential current and scales with the PGA gain setting. In Figure 12, the differential input impedance is ZDIFF. Table 2 describes the typical differential input impedance. Because the clock oscillator frequency drifts slightly with temperature, the input impedances also drift. For many applications, this input impedance drift can be ignored, and the values given in Table 2 for typical input impedance are valid. Table 2. Differential Input Impedance FS (V) DIFFERENTIAL INPUT IMPEDANCE (1) ±6.144V 22MΩ ±4.096V(1) 15MΩ ±2.048V 4.9MΩ ±1.024V 2.4MΩ ±0.512V 710kΩ ±0.256V 710kΩ 1. This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD + 0.3V be applied to this device. FULL-SCALE INPUT A programmable gain amplifier (PGA) is implemented before the ΔΣ core of the ADS1014/5. The PGA can be set to gains of 2/3, 1, 2, 4, 8, and 16. Table 3 shows the corresponding full-scale (FS) ranges. The PGA is configured by three bits in the Config register. The ADS1013 has a fixed full-scale input range of ±2.048V. The PGA = 2/3 setting allows input measurement to extend up to the supply voltage when VDD is larger than 4V. Note though that in this case (as well as for PGA = 1 and VDD < 4V), it is not possible to reach a full-scale output code on the ADC. Analog input voltages may never exceed the analog input voltage limits given in the Electrical Characteristics table. Table 3. PGA Gain Full-Scale Range PGA SETTING FS (V) 2/3 ±6.144V(1) 1 ±4.096V(1) 2 ±2.048V 4 ±1.024V 8 ±0.512V 16 ±0.256V 1. This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD + 0.3V be applied to this device. 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C – MAY 2009 – REVISED OCTOBER 2009 DATA FORMAT The ADS1013/4/5 provide 12 bits of data in binary twos complement format. The positive full-scale input produces an output code of 7FF0h and the negative full-scale input produces an output code of 8000h. The output clips at these codes for signals that exceed full-scale. Table 4 summarizes the ideal output codes for different input signals. Figure 13 shows code transitions versus input voltage. Table 4. Input Signal versus Ideal Output Code INPUT SIGNAL, VIN (AINP – AINN) IDEAL OUTPUT CODE(1) ≥ FS (211 – 1)/211 7FF0h +FS/211 0010h 0 0 11 –FS/2 FFF0h ≤ –FS 8000h 1. Excludes the effects of noise, INL, offset, and gain errors. 0x7FF0 When designing an input filter circuit, be sure to take into account the interaction between the filter network and the input impedance of the ADS1013/4/5. OPERATING MODES The ADS1013/4/5 operate in one of two modes: continuous conversion or single-shot. In continuous conversion mode, the ADS1013/4/5 continuously perform conversions. Once a conversion has been completed, the ADS1013/4/5 place the result in the Conversion register and immediately begins another conversion. In single-shot mode, the ADS1013/4/5 wait until the OS bit is set high. Once asserted, the bit is set to '0', indicating that a conversion is currently in progress. Once conversion data are ready, the OS bit reasserts and the device powers down. Writing a '1' to the OS bit during a conversion has no effect. RESET AND POWER-UP ¼ 0x7FE0 When the ADS1013/4/5 powers up, a reset is performed. As part of the reset process, the ADS1013/4/5 set all of the bits in the Config register to the respective default settings. 0x0001 0x0000 0xFFF0 ¼ Output Code The ADS1013/4/5 digital filter provides some attenuation of high-frequency noise, but the digital Sinc filter frequency response cannot completely replace an anti-aliasing filter. For a few applications, some external filtering may be needed; in such instances, a simple RC filter is adequate. The ADS1013/4/5 respond to the I2C general call reset command. When the ADS1013/4/5 receive a general call reset, an internal reset is performed as if the device had been powered on. 0x8010 0x8000 ¼ -FS 2 11 0 -1 DUTY CYCLING FOR LOW POWER 2 11 FS -FS 2 FS ¼ Input Voltage (AINP - AINN) 11 2 -1 11 Figure 13. ADS1013/4/5 Code Transition Diagram ALIASING As with any data converter, if the input signal contains frequencies greater than half the data rate, aliasing occurs. To prevent aliasing, the input signal must be bandlimited. Some signals are inherently bandlimited. For example, the output of a thermocouple, which has a limited rate of change. Nevertheless, they can contain noise and interference components. These components can fold back into the sampling band in the same way as with any other signal. For many applications, the improved performance at low data rates may not be required. For these applications, the ADS1013/4/5 support duty cycling that can yield significant power savings by periodically requesting high data rate readings at an effectively lower data rate. For example, an ADS1013/4/5 in power-down mode with a data rate set to 3300SPS could be operated by a microcontroller that instructs a single-shot conversion every 7.8ms (128SPS). Because a conversion at 3300SPS only requires about 0.3ms, the ADS1013/4/5 enter power-down mode for the remaining 7.5ms. In this configuration, the ADS1013/4/5 consume about 1/25th the power of the ADS1013/4/5 operated in continuous conversion mode. The rate of duty cycling is completely arbitrary and is defined by the master controller. The ADS1013/4/5 offer lower data rates that do not implement duty cycling and offer improved noise performance if it is needed. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 Submit Documentation Feedback 11 ADS1013 ADS1014 ADS1015 SBAS473C – MAY 2009 – REVISED OCTOBER 2009 www.ti.com COMPARATOR (ADS1014/15 ONLY) The ADS1014/5 are each equipped with a customizable comparator that can issue an alert on the ALERT/RDY pin. This feature can significantly reduce external circuitry for many applications. The comparator can be implemented as either a traditional comparator or a window comparator via the COMP_MODE bit in the Config register. When implemented as a traditional comparator, the ALERT/RDY pin asserts (active low by default) when conversion data exceed the limit set in the high threshold register. The comparator then deasserts when the input signal falls below the low threshold register value. In window comparator mode, the ALERT/RDY pin asserts if conversion data exceed the high threshold register or fall below the low threshold register. In either window or traditional comparator mode, the comparator can be configured to latch once asserted by the COMP_LAT bit in the Config register. This setting causes the assertion to remain even if the input signal is not beyond the bounds of the threshold registers. This latched assertion can be cleared by issuing an SMBus alert response or by reading the Conversion register. The COMP_POL bit in the Config register configures the ALERT/RDY pin as active high or active low. Operational diagrams for the comparator modes are shown in Figure 14 and Figure 15. The comparator can be configured to activate the ALERT/RDY pin after a set number of successive readings exceed the threshold. The comparator can be configured to wait for one, two, or four readings beyond the threshold before activating the ALERT/RDY pin by changing the COMP_QUE bits in the Config register. The COMP_QUE bits can also disable the comparator function. TH_H Input Signal TH_L Time Successful SMBus Alert Response Latching Comparator Output Time Non-Latching Comparator Output Time Figure 14. Alert Pin Timing Diagram When Configured as a Traditional Comparator TH_H Input Signal TH_L Time CONVERSION READY PIN (ADS1014/5 ONLY) The ALERT/RDY pin can also be configured as a conversion ready pin. This mode of operation can be realized if the MSB of the high threshold register is set to '1' and the MSB of the low threshold register is set to '0'. The COMP_POL bit continues to function and the COMP_QUE bits can disable the pin; however, the COMP_MODE and COMP_LAT bits no longer control any function. When configured as a conversion ready pin, ALERT/RDY continues to require a pull-up resistor. When in continuous conversion mode, the ADS1013/4/5 provide a brief (~8µs) pulse on the ALERT/RDY pin at the end of each conversion. When in single-shot shutdown mode, the ALERT/RDY pin asserts low at the end of a conversion if the COMP_POL bit is set to '0'. Latching Comparator Output Successful SMBus Alert Response Successful SMBus Alert Response Time Non-Latching Comparator Output Time Figure 15. Alert Pin Timing Diagram When Configured as a Window Comparator 12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C – MAY 2009 – REVISED OCTOBER 2009 SMBus ALERT RESPONSE When configured in latching mode (COMP_LAT = '1' in the Config register), the ALERT/RDY pin can be implemented with an SMBus alert. The pin asserts if the comparator detects a conversion that exceeds an upper or lower threshold. This interrupt is latched and can be cleared only by reading conversion data, or by issuing a successful SMBus alert response and reading the asserting device I2C address. If conversion data exceed the upper or lower thresholds after being cleared, the pin reasserts. This assertion does not affect conversions that are already in progress. The ALERT/RDY pin, as with the SDA pin, is an open-drain pin. This architecture allows several devices to share the same interface bus. When disabled, the pin holds a high state so that it does not interfere with other devices on the same bus line. When the master senses that the ALERT/RDY pin has latched, it issues an SMBus alert command (00011001) to the I2C bus. Any ADS1014/5 data converters on the I2C bus with the ALERT/RDY pins asserted respond to the command with the slave address. This sequence is illustrated in Figure 18. In the event that two or more ADS1014/5 data converters present on the bus assert the latched ALERT/RDY pin, arbitration during the address response portion of the SMBus alert decides which device clears its assertion. The device with the lowest I2C address always wins arbitration. If a device loses arbitration, it does not clear the comparator output pin assertion. The master then repeats the SMBus alert response until all devices have had the respective assertions cleared. In window comparator mode, the SMBus alert status bit indicates a '1' if signals exceed the high threshold and a '0' if signals exceed the low threshold. I2C INTERFACE The ADS1013/4/5 communicate through an I2C interface. I2C is a two-wire open-drain interface that supports multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines low by connecting them to ground; they never drive the bus lines high. Instead, the bus wires are pulled high by pull-up resistors, so the bus wires are high when no device is driving them low. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention. Communication on the I2C bus always takes place between two devices, one acting as the master and the other as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the master. Some I2C devices can act as masters or slaves, but the ADS1013/4/5 can only act as slave devices. An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data are transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the appropriate level while SCL is low (a low on SDA indicates the bit is zero; a high indicates the bit is one). Once the SDA line settles, the SCL line is brought high, then low. This pulse on SCL clocks the SDA bit into the receiver shift register. If the I2C bus is held idle for more than 25ms, the bus times out. The I2C bus is bidirectional: the SDA line is used for both transmitting and receiving data. When the master reads from a slave, the slave drives the data line; when the master sends to a slave, the master drives the data line. The master always drives the clock line. The ADS1013/4/5 never drive SCL, because they cannot act as a master. On the ADS1013/4/5, SCL is an input only. Most of the time the bus is idle; no communication occurs, and both lines are high. When communication is taking place, the bus is active. Only master devices can start a communication and initiate a START condition on the bus. Normally, the data line is only allowed to change state while the clock line is low. If the data line changes state while the clock line is high, it is either a START condition or a STOP condition. A START condition occurs when the clock line is high and the data line goes from high to low. A STOP condition occurs when the clock line is high and the data line goes from low to high. After the master issues a START condition, it sends a byte that indicates which slave device it wants to communicate with. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to which it responds. The master sends an address in the address byte, together with a bit that indicates whether it wishes to read from or write to the slave device. Every byte transmitted on the I2C bus, whether it is address or data, is acknowledged with an acknowledge bit. When the master has finished sending a byte (eight data bits) to a slave, it stops driving SDA and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA low. The master then sends a clock pulse to clock the acknowledge bit. Similarly, when the master has finished reading a byte, it pulls SDA low to acknowledge this to the slave. It then sends a clock pulse to clock the bit. (The master always drives the clock line.) A not-acknowledge is performed by simply leaving SDA high during an acknowledge cycle. If a device is not present on the bus, and the master attempts to address it, it receives a not-acknowledge because no device is present at that address to pull the line low. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 Submit Documentation Feedback 13 ADS1013 ADS1014 ADS1015 SBAS473C – MAY 2009 – REVISED OCTOBER 2009 www.ti.com When the master has finished communicating with a slave, it may issue a STOP condition. When a STOP condition is issued, the bus becomes idle again. The master may also issue another START condition. When a START condition is issued while the bus is active, it is called a repeated START condition. See the Timing Requirements section for a timing diagram showing the ADS1013/4/5 I2C transaction. For more information on high-speed mode, consult the I2C specification. SLAVE MODE OPERATIONS I2C ADDRESS SELECTION The ADS1013/4/5 have one address pin, ADDR, that sets the I2C address. This pin can be connected to ground, VDD, SDA, or SCL, allowing four addresses to be selected with one pin as shown in Table 5. The state of the address pin ADDR is sampled continuously. Table 5. ADDR Pin Connection and Corresponding Slave Address ADDR PIN SLAVE ADDRESS Ground 1001000 VDD 1001001 SDA 1001010 SCL 1001011 I2C GENERAL CALL The ADS1013/4/5 respond to the I C general call address (0000000) if the eighth bit is '0'. The devices acknowledge the general call address and respond to commands in the second byte. If the second byte is 00000110 (06h), the ADS1013/4/5 reset the internal registers and enter power-down mode. I2C SPEED MODES The I2C bus operates at one of three speeds. Standard mode allows a clock frequency of up to 100kHz; fast mode permits a clock frequency of up to 400kHz; and high-speed mode (also called Hs mode) allows a clock frequency of up to 3.4MHz. The ADS1013/4/5 are fully compatible with all three modes. No special action is required to use the ADS1013/4/5 in standard or fast mode, but high-speed mode must be activated. To activate high-speed mode, send a special address byte of 00001xxx following the START condition, where xxx are bits unique to the Hs-capable master. This byte is called the Hs master code. (Note that this is different from normal address bytes; the eighth bit does not indicate read/write status.) The ADS1013/4/5 do not acknowledge this Submit Documentation Feedback The ADS1013/4/5 can act as either slave receivers or slave transmitters. As a slave device, the ADS1013/4/5 cannot drive the SCL line. Receive Mode: In slave receive mode the first byte transmitted from the master to the slave is the address with the R/W bit low. This byte allows the slave to be written to. The next byte transmitted by the master is the register pointer byte. The ADS1013/4/5 then acknowledge receipt of the register pointer byte. The next two bytes are written to the address given by the register pointer. The ADS1013/4/5 acknowledge each byte sent. Register bytes are sent with the most significant byte first, followed by the least significant byte. Transmit Mode: 2 14 byte; the I2C specification prohibits acknowledgment of the Hs master code. Upon receiving a master code, the ADS1013/4/5 switch on Hs mode filters, and communicate at up to 3.4MHz. The ADS1013/4/5 switch out of Hs mode with the next STOP condition. In slave transmit mode, the first byte transmitted by the master is the 7-bit slave address followed by the high R/W bit. This byte places the slave into transmit mode and indicates that the ADS1013/4/5 are being read from. The next byte transmitted by the slave is the most significant byte of the register that is indicated by the register pointer. This byte is followed by an acknowledgment from the master. The remaining least significant byte is then sent by the slave and is followed by an acknowledgment from the master. The master may terminate transmission after any byte by not acknowledging or issuing a START or STOP condition. WRITING/READING THE REGISTERS To access a specific register from the ADS1013/4/5, the master must first write an appropriate value to the Pointer register. The Pointer register is written directly after the slave address byte, low R/W bit, and a successful slave acknowledgment. After the Pointer register is written, the slave acknowledges and the master issues a STOP or a repeated START condition. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C – MAY 2009 – REVISED OCTOBER 2009 POINTER REGISTER When reading from the ADS1013/4/5, the previous value written to the Pointer register determines the register that is read from. To change which register is read, a new value must be written to the Pointer register. To write a new value to the Pointer register, the master issues a slave address byte with the R/W bit low, followed by the Pointer register byte. No additional data need to be transmitted, and a STOP condition can be issued by the master. The master may now issue a START condition and send the slave address byte with the R/W bit high to begin the read. Figure 16 details this sequence. If repeated reads from the same register are desired, there is no need to continually send Pointer register bytes, because the ADS1013/4/5 store the value of the Pointer register until it is modified by a write operation. However, every write operation requires the Pointer register to be written. The four registers are accessed by writing to the Pointer register byte; see Figure 16. Table 6 and Table 7 indicate the Pointer register byte map. Table 6. Register Address BIT 1 BIT 0 REGISTER 0 0 Conversion register 0 1 Config register 1 0 Lo_thresh register 1 1 Hi_thresh register CONVERSION REGISTER The 16-bit register contains the result of the last conversion in binary twos complement format. Following reset or power-up, the Conversion register is cleared to '0', and remains '0' until the first conversion is completed. REGISTERS The ADS1013/4/5 have four registers that are accessible via the I2C port. The Conversion register contains the result of the last conversion. The Config register allows the user to change the ADS1013/4/5 operating modes and query the status of the devices. Two registers, Lo_thresh and Hi_thresh, set the threshold values used for the comparator function. The register format is shown in Table 8. CONFIG REGISTER The 16-bit register can be used to control the ADS1013/4/5 operating mode, input selection, data rate, PGA settings, and comparator modes. The register format is shown in Table 9. Table 7. Pointer Register Byte (Write-Only) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 0 0 0 0 0 0 BIT 1 BIT 0 Register address Table 8. Conversion Register (Read-Only) BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 Table 9. Config Register (Read/Write) BIT 15 14 13 12 11 10 9 8 NAME OS MUX2 MUX1 MUX0 PGA2 PGA1 PGA0 MODE 3 2 blank BIT 7 6 5 4 NAME DR2 DR1 DR0 COMP_MODE COMP_POL COMP_LAT 1 0 COMP_QUE1 COMP_QUE0 Default = 8583h. Bit [15] OS: Operational status/single-shot conversion start This bit determines the operational status of the device. This bit can only be written when in power-down mode. For a write status: 0 : No effect 1 : Begin a single conversion (when in power-down mode) For a read status: 0 : Device is currently performing a conversion 1 : Device is not currently performing a conversion Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 Submit Documentation Feedback 15 ADS1013 ADS1014 ADS1015 SBAS473C – MAY 2009 – REVISED OCTOBER 2009 Bits [14:12] www.ti.com MUX[2:0]: Input multiplexer configuration (ADS1015 only) These bits configure the input multiplexer. They serve no function on the ADS1013/4. 000 : AINP = AIN0 and AINN = AIN1 (default) 001 : AINP = AIN0 and AINN = AIN3 010 : AINP = AIN1 and AINN = AIN3 011 : AINP = AIN2 and AINN = AIN3 Bits [11:9] 100 : AINP = AIN0 and AINN = GND 101 : AINP = AIN1 and AINN = GND 110 : AINP = AIN2 and AINN = GND 111 : AINP = AIN3 and AINN = GND PGA[2:0]: Programmable gain amplifier configuration (ADS1014 and ADS1015 only) These bits configure the programmable gain amplifier. They serve no function on the ADS1013. 000 : FS = ±6.144V (1) 001 : FS = ±4.096V (1) 010 : FS = ±2.048V (default) 011 : FS = ±1.024V Bit [8] 100 : FS = ±0.512V 101 : FS = ±0.256V 110 : FS = ±0.256V 111 : FS = ±0.256V MODE: Device operating mode This bit controls the current operational mode of the ADS1013/4/5. 0 : Continuous conversion mode 1 : Power-down single-shot mode (default) Bits [7:5] DR[2:0]: Data rate These bits control the data rate setting. 000 : 128SPS 001 : 250SPS 010 : 490SPS 011 : 920SPS Bit [4] 100 : 1600SPS (default) 101 : 2400SPS 110 : 3300SPS 111 : 3300SPS COMP_MODE: Comparator mode (ADS1014 and ADS1015 only) This bit controls the comparator mode of operation. It changes whether the comparator is implemented as a traditional comparator (COMP_MODE = '0') or as a window comparator (COMP_MODE = '1'). It serves no function on the ADS1013. 0 : Traditional comparator with hysteresis (default) 1 : Window comparator Bit [3] COMP_POL: Comparator polarity (ADS1014 and ADS1015 only) This bit controls the polarity of the ALERT/RDY pin. When COMP_POL = '0' the comparator output is active low. When COMP_POL='1' the ALERT/RDY pin is active high. It serves no function on the ADS1013. 0 : Active low (default) 1 : Active high Bit [2] COMP_LAT: Latching comparator (ADS1014 and ADS1015 only) This bit controls whether the ALERT/RDY pin latches once asserted or clears once conversions are within the margin of the upper and lower threshold values. When COMP_LAT = '0', the ALERT/RDY pin does not latch when asserted. When COMP_LAT = '1', the asserted ALERT/RDY pin remains latched until conversion data are read by the master or an appropriate SMBus alert response is sent by the master, the device responds with its address, and it is the lowest address currently asserting the ALERT/RDY bus line. This bit serves no function on the ADS1013. 0 : Non-latching comparator (default) 1 : Latching comparator Bits [1:0] COMP_QUE: Comparator queue and disable (ADS1014 and ADS1015 only) These bits perform two functions. When set to '11', they disable the comparator function and put the ALERT/RDY pin into a high state. When set to any other value, they control the number of successive conversions exceeding the upper or lower thresholds required before asserting the ALERT/RDY pin. They serve no function on the ADS1013. 00 : Assert after one conversion 01 : Assert after two conversions 10 : Assert after four conversions 11 : Disable comparator (default) (1) 16 This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD + 0.3V be applied to this device. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C – MAY 2009 – REVISED OCTOBER 2009 Lo_thresh AND Hi_thresh REGISTERS register MSB to ‘0’. However, in all other cases, the Hi_thresh register must be larger than the Lo_thresh register. The threshold register formats are shown in Table 10. When set to RDY mode, the ALERT/RDY pin outputs the state of the OS bit when in single-shot mode and pulses when in continuous conversion mode. Bits [3:0] in both the Lo_thresh and Hi_thresh registers have no effect on the comparator level thresholds. These bits should be considered as don't care bits. The upper and lower threshold values used by the comparator are stored in two 16-bit registers. These registers store values in the same format that the output register displays values; that is, they are stored in twos complement format. Because it is implemented as a digital comparator, special attention should be taken to readjust values whenever PGA settings are changed. A secondary conversion ready function of the comparator output pin can be realized by setting the Hi_thresh register MSB to '1' and the Lo_thresh Table 10. Lo_thresh and Hi_thresh Registers REGISTER Lo_thresh (Read/Write) BIT 15 14 13 12 11 10 9 8 NAME Lo_thresh11 Lo_thresh10 Lo_thresh9 Lo_thresh8 Lo_thresh7 Lo_thresh6 Lo_thresh5 Lo_thresh4 BIT 7 6 5 4 3 2 1 0 NAME Lo_thresh3 Lo_thresh2 Lo_thresh1 Lo_thresh0 0 0 0 0 BIT 15 14 13 12 11 10 9 8 NAME Hi_thresh11 Hi_thresh10 Hi_thresh9 Hi_thresh8 Hi_thresh7 Hi_thresh6 Hi_thresh5 Hi_thresh4 BIT 7 6 5 4 3 2 1 0 NAME Hi_thresh3 Hi_thresh2 Hi_thresh1 Hi_thresh0 1 1 1 1 blank REGISTER Hi_thresh (Read/Write) blank Lo_thresh default = 8000h. Hi_thresh default = 7FFFh. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 Submit Documentation Feedback 17 ADS1013 ADS1014 ADS1015 SBAS473C – MAY 2009 – REVISED OCTOBER 2009 www.ti.com 1 9 1 9 SCL ¼ SDA 1 0 0 1 0 A1 (1) A0 (1) R/W Start By Master 0 0 0 0 0 0 P1 P0 ACK By ADS1013/4/5 ACK By ADS1013/4/5 Frame 1 Two-Wire Slave Address Byte Stop By Master Frame 2 Pointer Register Byte 1 9 1 9 SCL (Continued) ¼ SDA (Continued) 1 0 0 1 0 A1 (1) A0 (1) D15 R/W Start By Master D14 D13 D12 D11 1 D9 D8 From ADS1013/4/5 ACK By ADS1013/4/5 Frame 3 Two-Wire Slave Address Byte D10 ¼ ACK By Master (2) Frame 4 Data Byte 1 Read Register 9 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 From ADS1013/4/5 ACK By Master (3) Stop By Master Frame 5 Data Byte 2 Read Register (1) The values of A0 and A1 are determined by the ADDR pin. (2) Master can leave SDA high to terminate a single-byte read operation. (3) Master can leave SDA high to terminate a two-byte read operation. Figure 16. Two-Wire Timing Diagram for Read Word Format 18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C – MAY 2009 – REVISED OCTOBER 2009 1 9 1 9 SCL ¼ 1 SDA 0 0 1 A1(1) 0 A0(1) 0 R/W Start By Master 0 0 0 0 0 P1 P0 ACK By ADS1013/4/5 ¼ ACK By ADS1013/4/5 Frame 2 Pointer Register Byte Frame 1 Two-Wire Slave Address Byte 1 9 1 9 SCL (Continued) SDA (Continued) D15 D14 D13 D12 D11 D10 D9 D7 D8 D6 D5 D4 D3 D2 D1 D0 ACK By ADS1013/4/5 ACK By ADS1013/4/5 Stop By Master Frame 4 Data Byte 2 Frame 3 Data Byte 1 (1) The values of A0 and A1 are determined by the ADDR pin. Figure 17. Two-Wire Timing Diagram for Write Word Format ALERT 1 9 1 9 SCL SDA 0 0 0 1 1 0 0 R/W Start By Master 1 0 0 1 ACK By ADS1013/4/5 Frame 1 SMBus ALERT Response Address Byte A1 A0 From ADS1013/4/5 Status NACK By Master Stop By Master Frame 2 Slave Address From ADS1015 (1) The values of A0 and A1 are determined by the ADDR pin. Figure 18. Timing Diagram for SMBus ALERT Response Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 Submit Documentation Feedback 19 ADS1013 ADS1014 ADS1015 SBAS473C – MAY 2009 – REVISED OCTOBER 2009 www.ti.com APPLICATION INFORMATION The following sections give example circuits and suggestions for using the ADS1013/4/5 in various situations. The ADS1013/4/5 interface directly to standard mode, fast mode, and high-speed mode I2C controllers. Any microcontroller I2C peripheral, including master-only and non-multiple-master I2C peripherals, can operate with the ADS1013/4/5. The ADS1013/4/5 do not perform clock-stretching (that is, they never pull the clock line low), so it is not necessary to provide for this function unless other clock-stretching devices are on the same I2C bus. BASIC CONNECTIONS For many applications, connecting the ADS1013/4/5 is simple. A basic connection diagram for the ADS1015 is shown in Figure 19. The fully differential voltage input of the ADS1013/4/5 is ideal for connection to differential sources with moderately low source impedance, such as thermocouples and thermistors. Although the ADS1013/4/5 can read bipolar differential signals, they cannot accept negative voltages on either input. It may be helpful to think of the ADS1013/4/5 positive voltage input as noninverting, and of the negative input as inverting. Pull-up resistors are required on both the SDA and SCL lines because I2C bus drivers are open-drain. The size of these resistors depends on the bus operating speed and capacitance of the bus lines. Higher-value resistors consume less power, but increase the transition times on the bus, limiting the bus speed. Lower-value resistors allow higher speed at the expense of higher power consumption. Long bus lines have higher capacitance and require smaller pull-up resistors to compensate. The resistors should not be too small; if they are, the bus drivers may not be able to pull the bus lines low. When the ADS1013/4/5 are converting data, they draw current in short spikes. The 0.1μF bypass capacitor supplies the momentary bursts of extra current needed from the supply. ADS1015 10 VDD SCL VDD Pull-Up Resistors 1kW to 10kW (typ) Microcontroller or Microprocessor 1 ADDR SDA 9 2 ALERT/RDY VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 0.1mF (typ) AIN1 2 with I C Port 5 SCL SDA GPIO Inputs Selected from Configuration Register Figure 19. Typical Connections of the ADS1015 20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C – MAY 2009 – REVISED OCTOBER 2009 CONNECTING MULTIPLE DEVICES Connecting multiple ADS1013/4/5s to a single bus is simple. Using the address pin, the ADS1013/4/5 can be set to one of four different I2C addresses. An example showing four ADS1013/4/5 devices is given in Figure 21. Up to four ADS1013/4/5s (using different address pin configurations) can be connected to a single bus. Note that only one set of pull-up resistors is needed per bus. The pull-up resistor values may need to be lowered slightly to compensate for the additional bus capacitance presented by multiple devices and increased line length. The TMP421 and DAC8574 devices detect the respective I2C bus addresses based on the states of pins. In Figure 22, the TMP421 has the address 0101010, and the DAC8574 has the address 1001100. Consult the DAC8574 and TMP421 data sheets, available at www.ti.com, for further details. USING GPIO PORTS FOR COMMUNICATION Most microcontrollers have programmable input/output (I/O) pins that can be set in software to act as inputs or outputs. If an I2C controller is not available, the ADS1013/4/5 can be connected to GPIO pins and the I2C bus protocol simulated, or bit-banged, in software. An example of this configuration for a single ADS1013/4/5 is shown in Figure 20. states. To drive the line low, the pin is set to output '0'; to let the line go high, the pin is set to input. When the pin is set to input, the state of the pin can be read; if another device is pulling the line low, this configuration reads as a '0' in the port input register. Note that no pull-up resistor is shown on the SCL line. In this simple case, the resistor is not needed; the microcontroller can simply leave the line on output, and set it to '1' or '0' as appropriate. This action is possible because the ADS1013/4/5 never drive the clock line low. This technique can also be used with multiple devices, and has the advantage of lower current consumption as a result of the absence of a resistive pull-up. If there are any devices on the bus that may drive the clock lines low, this method should not be used; the SCL line should be high-Z or '0' and a pull-up resistor provided as usual. Some microcontrollers have selectable strong pull-up circuits built in to the GPIO ports. In some cases, these circuits can be switched on and used in place of an external pull-up resistor. Weak pull-ups are also provided on some microcontrollers, but usually these are too weak for I2C communication. If there is any doubt about the matter, test the circuit before committing it to production. Bit-banging I2C with GPIO pins can be done by setting the GPIO line to '0' and toggling it between input and output modes to apply the proper bus ADS1015 VDD Microcontroller or Microprocessor with GPIO Ports GPIO_1 GPIO_0 10 SCL 1 ADDR SDA 9 2 ALERT/RDY VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 AIN1 5 NOTE: ADS1013/4/5 power and input connections omitted for clarity. Figure 20. Using GPIO with a Single ADS1015 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 Submit Documentation Feedback 21 ADS1013 ADS1014 ADS1015 SBAS473C – MAY 2009 – REVISED OCTOBER 2009 www.ti.com GND VDD GND ADS1015 10 SCL 2 I C Pull-Up Resistors 1kW to 10kW (typ.) VDD 1 ADDR 2 3 4 10 ADS1015 SDA 9 ALERT/RDY VDD 8 1 ADDR SDA 9 GND AIN3 7 2 ALERT/RDY VDD 8 AIN0 AIN2 6 3 GND AIN3 7 4 AIN0 AIN2 6 Microcontroller or Microprocessor AIN1 2 SCL 2 I C Pull-Up Resistors 1kW to 10kW (typ.) VDD AIN1 5 with I C Port VDD 5 Microcontroller or Microprocessor SCL 2 with I C Port SDA SCL SDA ADS1015 10 10 ADS1015 SCL 1 ADDR 2 ALERT/RDY 3 4 SCL SDA 9 1 ADDR SDA 9 VDD 8 2 ALERT/RDY VDD 8 GND AIN3 7 3 GND AIN3 7 AIN0 AIN2 6 4 AIN0 AIN2 6 AIN1 AIN1 5 5 TMP421 ADS1015 10 1 DXP V+ 8 2 DXN SCL 7 3 A1 SDA 6 4 A0 GND 5 1 VOUTA A3 16 2 VOUTB A2 15 3 VREFH A1 14 10 4 VDD A0 13 SCL 5 VREFL IOVDD 12 6 GND SDA 11 7 VOUTC SCL 10 8 VOUTD LDAC 9 SCL 1 2 ADDR SDA ALERT/RDY 3 GND 4 AIN0 VDD 9 Leave Floating 8 AIN3 7 AIN2 6 DAC8574 AIN1 5 ADS1015 1 ADDR SDA 9 2 ALERT/RDY VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 AIN1 5 NOTE: ADS1013/4/5 power and input connections omitted for clarity. ADDR, A3, A2, A1, and A0 select the I2C addresses. NOTE: ADS1013/4/5 power and input connections omitted for clarity. The ADDR pin selects the I2C address. Figure 22. Connecting Multiple Device Types Figure 21. Connecting Multiple ADS1013/4/5s 22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C – MAY 2009 – REVISED OCTOBER 2009 SINGLE-ENDED INPUTS The ADS1015 input range is bipolar differential with respect to the reference. The single-ended circuit shown in Figure 23 covers only half the ADS1015 input scale because it does not produce differentially negative inputs; therefore, one bit of resolution is lost. Although the ADS1015 has two differential inputs, the device can easily measure four single-ended signals. Figure 23 shows a single-ended connection scheme. The ADS1015 is configured for single-ended measurement by configuring the MUX to measure each channel with respect to ground. Data are then read out of one input based on the selection on the configuration register. The single-ended signal can range from 0V to supply. The ADS1015 loses no linearity anywhere within the input range. Negative voltages cannot be applied to this circuit because the ADS1015 can only accept positive voltages. VDD ADS1015 Output Codes 0-32767 10 SCL 1 ADDR SDA 9 2 ALERT/RDY VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 0.1mF (typ) AIN1 5 Inputs Selected from Configuration Register NOTE: Digital and address pin connections omitted for clarity. Figure 23. Measuring Single-Ended Inputs Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 Submit Documentation Feedback 23 ADS1013 ADS1014 ADS1015 SBAS473C – MAY 2009 – REVISED OCTOBER 2009 www.ti.com LOW-SIDE CURRENT MONITOR Figure 24 shows a circuit for a low-side shunt-type current monitor. The circuit monitors the voltage across a shunt resistor, which is sized as small as possible while giving a measurable output voltage. This voltage is amplified by an OPA335 low-drift op amp, and the result is read by the ADS1014/5. It is suggested that the ADS1014/5 be operated at a gain of 16. The gain of the OPA335 can then be set lower. For a gain of 16, the op amp should be set up to give a maximum output voltage no greater than 0.256V. If the shunt resistor is sized to provide a maximum voltage drop of 50mV at full-scale current, the full-scale input to the ADS1014/5 is 0.2V. 2.0V to 5V 3kW V 0.1mF Typ 5V FS = 0.2V Load OPA335 (1) RS (2) R3 49.9kW 2 ADS1014 IC 1kW G=4 The ADS1013/4/5 are fabricated in a small-geometry, low-voltage process. The analog inputs feature protection diodes to the supply rails. However, the current-handling ability of these diodes is limited, and the ADS1013/4/5 can be permanently damaged by analog input voltages that remain more than approximately 300mV beyond the rails for extended periods. One way to protect against overvoltage is to place current-limiting resistors on the input lines. The ADS1013/4/5 analog inputs can withstand momentary currents as large as 100mA. If the ADS1013/4/5 are driven by an op amp with high-voltage supplies, such as ±12V, protection should be provided, even if the op amp is configured so that it does not output out-of-range voltages. Many op amps drift to one of the supply rails immediately when power is applied, usually before the input has stabilized; this momentary spike can damage the ADS1013/4/5. This incremental damage results in slow, long-term failure, which can be disastrous for permanently installed, low-maintenance systems. If an op amp or other front-end circuitry is used with an ADS1013/4/5, performance characteristics must be taken into account when designing the application. -5V (PGA Gain = 16) 256mV FS (1) Pull-down resistor to allow accurate swing to 0V. (2) RS is sized for a 50mV drop at full-scale current. Figure 24. Low-Side Current Measurement 24 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C – MAY 2009 – REVISED OCTOBER 2009 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (September 2009) to Revision C Page • Deleted operating temperature bullet from Features section ............................................................................................... 1 • Deleted operating temperature range parameter from Absolute Maximum Ratings table ................................................... 2 • Deleted Operating temperature parameter from Temperature section of Electrical Characteristics table ........................... 4 • Changed Figure 2 to reflect maximum operating temperature ............................................................................................. 6 • Changed Figure 3 to reflect maximum operating temperature ............................................................................................. 6 • Changed Figure 4 to reflect maximum operating temperature ............................................................................................. 6 • Changed Figure 5 to reflect maximum operating temperature ............................................................................................. 6 • Changed Figure 6 to reflect maximum operating temperature ............................................................................................. 6 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1013 ADS1014 ADS1015 Submit Documentation Feedback 25 PACKAGE OPTION ADDENDUM www.ti.com 19-Nov-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Samples (3) (Requires Login) ADS1013IDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1013IDGST ACTIVE VSSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1013IRUGR ACTIVE X2QFN RUG 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ADS1013IRUGT ACTIVE X2QFN RUG 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ADS1014IDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1014IDGST ACTIVE VSSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1014IRUGR ACTIVE X2QFN RUG 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ADS1014IRUGT ACTIVE X2QFN RUG 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ADS1015IDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1015IDGST ACTIVE VSSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1015IRUGR ACTIVE X2QFN RUG 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ADS1015IRUGT ACTIVE X2QFN RUG 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 19-Nov-2012 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ADS1015 : • Automotive: ADS1015-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS1013IDGSR VSSOP DGS 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 5.3 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.3 1.3 8.0 12.0 Q1 ADS1013IDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 ADS1013IRUGR X2QFN RUG 10 3000 179.0 8.4 1.75 2.25 0.65 4.0 8.0 Q1 ADS1013IRUGT X2QFN RUG 10 250 179.0 8.4 1.75 2.25 0.65 4.0 8.0 Q1 ADS1014IDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 ADS1014IDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 ADS1014IRUGR X2QFN RUG 10 3000 179.0 8.4 1.75 2.25 0.65 4.0 8.0 Q1 ADS1014IRUGT X2QFN RUG 10 250 179.0 8.4 1.75 2.25 0.65 4.0 8.0 Q1 ADS1015IDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 ADS1015IDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 ADS1015IRUGR X2QFN RUG 10 3000 179.0 8.4 1.75 2.25 0.65 4.0 8.0 Q1 ADS1015IRUGT X2QFN RUG 10 250 179.0 8.4 1.75 2.25 0.65 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1013IDGSR VSSOP DGS 10 2500 370.0 355.0 55.0 ADS1013IDGST VSSOP DGS 10 250 195.0 200.0 45.0 ADS1013IRUGR X2QFN RUG 10 3000 203.0 203.0 35.0 ADS1013IRUGT X2QFN RUG 10 250 203.0 203.0 35.0 ADS1014IDGSR VSSOP DGS 10 2500 370.0 355.0 55.0 ADS1014IDGST VSSOP DGS 10 250 195.0 200.0 45.0 ADS1014IRUGR X2QFN RUG 10 3000 203.0 203.0 35.0 ADS1014IRUGT X2QFN RUG 10 250 203.0 203.0 35.0 ADS1015IDGSR VSSOP DGS 10 2500 370.0 355.0 55.0 ADS1015IDGST VSSOP DGS 10 250 195.0 200.0 45.0 ADS1015IRUGR X2QFN RUG 10 3000 203.0 203.0 35.0 ADS1015IRUGT X2QFN RUG 10 250 203.0 203.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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