a FEATURES 4 ns Propagation Delay at 5 V Single Supply Operation: 3 V to 5 V 100 MHz Input Latch Function APPLICATIONS High-Speed Timing Clock Recovery and Clock Distribution Line Receivers Digital Communications Phase Detectors High-Speed Sampling Read Channel Detection PCMCIA Cards Zero Crossing Detector High-Speed A/D Converter Upgrade for LT1394 and LT1016 Designs Ultrafast 4 ns Single Supply Comparators AD8611/AD8612 PIN CONFIGURATIONS 8-Lead Narrow Body SO (SO-8) OUT OUT GND LATCH Vⴙ ⴙIN ⴚIN Vⴚ AD8611 8-Lead MSOP (RM-8) 1 Vⴙ ⴙIN ⴚIN Vⴚ 8 OUT OUT GND LATCH AD8611 4 5 GENERAL DESCRIPTION The AD8611/AD8612 are single and dual 4 ns comparators with latch function and complementary output. Fast 4 ns propagation delay makes the AD8611/AD8612 a good choice for timing circuits and line receivers. Propagation delays for rising and falling signals are closely matched and track over temperature. This matched delay makes the AD8611/AD8612 a good choice for clock recovery, since the duty cycle of the output will match the duty cycle of the input. The AD8611 has the same pinout as the LT1016 and LT1394, with lower supply current and a wider common-mode input range, which includes the negative supply rail. 14-Lead TSSOP (RU-14) QA 1 14 QB QA 2 13 QB GND 3 12 GND AD8612 LE A 4 TOP VIEW 11 LE B (Not to Scale) 10 V+ Vⴚ 5 IN Aⴚ 6 9 IN Bⴚ IN A+ 7 8 IN B+ The AD8611/AD8612 is specified over the industrial (–40°C to +85°C) temperature range. The AD8611 is available in both 8-lead MSOP and narrow SO-8 surface mount packages. The AD8612 is available in 14-lead TSSOP surface-mount package. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD8611/AD8612–SPECIFICATIONS ELECTRICAL SPECIFICATIONS (@ V+ = 5.0 V, V– = VGND = 0 V, TA = 25ⴗC unless otherwise noted) Parameter Symbol INPUT CHARACTERISTICS Offset Voltage VOS Offset Voltage Drift Input Bias Current Input Offset Current Input Common-Mode Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Input Capacitance LATCH ENABLE INPUT Logic “1” Voltage Threshold Logic “0” Voltage Threshold Logic “1” Current Logic “0” Current Latch Enable Pulsewidth Setup Time Hold Time ∆VOS/∆T IB IB IOS VCM CMRR AVO CIN VIH VIL IIH IIL Conditions Min Typ Max Unit 1 7 8 mV mV µV/°C µA µA µA V dB V/V pF –40°C ≤ TA ≤ +85°C VCM = 0 V –40°C ≤ TA ≤ +85°C VCM = 0 V 0 V ≤ VCM ≤ 3.0 V RL = 10 kΩ –6 –7 0.0 55 2.0 VLH = 3.0 V VLL = 0.3 V –1.0 –5 tPW(E) tS tH 4 –4 –4.5 ±4 3.0 85 3,000 3.0 1.65 1.60 –0.3 –2.7 ns ns ns 3.35 3.4 0.25 V V V VOH VOH VOL IOH = 50 µA, ∆VIN > 250 mV IOH = 3.2 mA, ∆VIN > 250 mV IOL = 3.2 mA, ∆VIN > 250 mV DYNAMIC PERFORMANCE Input Frequency Propagation Delay fMAX tP 400 mV p-p sine wave 200 mV Step with 100 mV Overdrive1 –40°C ≤ TA ≤ +85°C 100 mV Step with 5 mV Overdrive 100 4.0 5 5 ∆tP 100 mV Step with 100 mV Overdrive1 20% to 80% 80% to 20% 0.5 2.5 1.1 PSRR I+ 4.5 V ≤ V+ ≤ 5.5 V Propagation Delay Differential Propagation Delay (Rising Propagation Delay vs. Falling Propagation Delay) Rise Time Fall Time POWER SUPPLY Power Supply Rejection Ratio V+ Supply Current2 tP Ground Supply Current2 IGND V– Supply Current2 I– –40°C ≤ TA ≤ +85°C VO = 0 V, RL = ∞ –40°C ≤ TA ≤ +85°C 55 73 5.7 3.5 2.2 –40°C ≤ TA ≤ +85°C V V µA µA 3 0.5 0.5 DIGITAL OUTPUTS Logic “1” Voltage Logic “1” Voltage Logic “0” Voltage 3.0 2.4 0.8 0.4 5.5 2.0 10 10 7 7 4 5 MHz ns ns ns ns ns ns dB mA mA mA mA mA mA NOTES 1 Guaranteed by design. 2 Per comparator. Specifications subject to change without notice. –2– REV. 0 AD8611/AD8612 ELECTRICAL SPECIFICATIONS Parameter (@ V+ = 3.0 V, V– = VGND = 0 V, TA = 25ⴗC unless otherwise noted) Symbol INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output High Voltage Output Low Voltage POWER SUPPLY Power Supply Rejection Ratio Supply Currents V+ Supply Current2 VOS IB IB VCM CMRR Conditions Min VCM = 0 V –40°C ≤ TA ≤ +85°C –6 –7 0 55 0 V ≤ VCM ≤ 1.0 V VOH VOL IOH = –3.2 mA, VIN > 250 mV IOL = +3.2 mA, VIN > 250 mV PSRR 2.7 V ≤ V+ ≤ 6 V VO = 0 V, RL = ∞ Typ Max Unit 1 –4.0 –4.5 7 mV µA µA V dB 1.0 1.21 0.3 46 I+ dB 4.5 –40°C ≤ TA ≤ +85°C Ground Supply Current2 IGND V– Supply Current2 2.5 –40°C ≤ TA ≤ +85°C I– 2 –40°C ≤ TA ≤ +85°C DYNAMIC PERFORMANCE Propagation Delay tP 100 mV Step with 20 mV Overdrive3 V V 4.5 6.5 10 3.5 5.5 3.5 4.8 mA mA mA mA mA mA 6.5 ns NOTES 1 Output high voltage without pull-up resistor. It may be useful to have a pull-up resistor to V+ for 3 V operation. 2 Per comparator. 3 Guaranteed by design. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS Total Analog Supply Voltage . . . . . . . . . . . . . . . . . . . . . 7.0 V Digital Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 4 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 5 V Output Short-Circuit Duration to GND . . . . . . . . . Indefinite Storage Temperature Range R, RU, RM Packages . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Junction Temperature Range R, RU, RM Packages . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering, 10 sec) . . . . . . . 300°C Package Type JA2 JC Unit 8-Lead SO (R) 8-Lead MSOP (RM) 14-Lead TSSOP (RU) 158 240 240 43 43 43 °C/W °C/W °C/W NOTES 1 The analog input voltage is equal to ± 4 V or the analog supply voltage, whichever is less. 2 θJA is specified for the worst-case conditions, i.e., θJA is specified for device in socket for P-DIP and θJA is specified for device soldered in circuit board for SOIC and TSSOP packages. ORDERING GUIDE Model Temperature Range Package Description Package Option Branding Information AD8611ARM AD8611AR AD8612ARU –40°C to +85°C –40°C to +85°C –40°C to +85°C 8-Lead Micro SOIC 8-Lead Small Outline IC 14-Lead Thin Shrink Small Outline RM-8 SO-8 RU-14 G1A CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8611/AD8612 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE AD8611/AD8612 8 18 V+ = 5V OVERDRIVE > 10mV 6 5 PDⴚ 4 V+ = 5V TA = 25ⴗC OVERDRIVE = 5mV 14 PROPAGATION DELAY – ns PROPAGATION DELAY – ns 7 PD+ 3 2 PDⴚ 12 PD+ 8 6 2 1 0 ⴚ50 0 ⴚ25 0 25 50 TEMPERATURE – ⴗC 75 100 V+ = 5V TA = 25ⴗC PDⴚ 7 14 12 PROPAGATION DELAY – ns PROPAGATION DELAY – ns 16 PD+ 10 8 6 4 2.0 2.5 TA = 25ⴗC STEP = 100 mV OVERDRIVE > 10 mV PD+ 6 5 PDⴚ 4 3 2 1 2 0 0 10 15 OVERDRIVE – mV 5 20 25 2 3 4 SUPPLY VOLTAGE – V 6 5 Figure 5. Propagation Delay vs. Supply Voltage Figure 2. Propagation Delay vs. Overdrive 35 8 PDⴚ TA = 25ⴗC STEP = 100 mV OVERDRIVE = 50 mV 30 PROPAGATION DELAY – ns V+ = 5V TA = 25ⴗC OVERDRIVE > 10mV 7 PROPAGATION DELAY – ns 1.0 1.5 SOURCE RESISTANCE – k⍀ 8 18 6 PD+ 5 4 3 2 25 PD+ 20 15 10 5 1 0 0.5 Figure 4. Propagation Delay vs. Source Resistance Figure 1. Propagation Delay Over Temperature 0 0 PDⴚ 0 0 20 40 CAPACITANCE – pF 60 80 2 3 4 5 COMMON-MODE VOLTAGE – V 6 Figure 6. Propagation Delay vs. Common-Mode Voltage Figure 3. Propagation Delay vs. Load Capacitance –4– REV. 0 AD8611/AD8612 1.2 0.40 VS = 3V +25ⴗC 0.35 1.0 +85ⴗC ⴚ40ⴗC LOAD CURRENT – V 0.30 0.8 VOS – mV VS = 5V 0.6 0.4 ⴚ40ⴗC 0.25 0.20 +85ⴗC 0.15 +25ⴗC 0.10 0.2 0.05 0 ⴚ60 ⴚ40 ⴚ20 0 20 40 60 80 0 100 0 2 4 6 8 SINK CURRENT – mA TEMPERATURE – ⴗC Figure 7. Offset Voltage vs. Temperature 4.0 V+ = 5V TA = 25ⴗC 3.8 OUTPUT HIGH VOLTAGE – V 35 30 25 ISY+ – mA 12 Figure 10. Output Low Voltage vs. Load Current (Sinking) Over Temperature 40 20 15 10 +85ⴗC 3.6 3.4 +25ⴗC 3.2 ⴚ40ⴗC 3.0 2.8 2.6 5 0 10 1 10 INPUT FREQUENCY – MHz 2.4 100 Figure 8. Supply Current vs. Input Frequency 0 2 4 6 8 LOAD CURRENT – mA 10 12 Figure 11. Output High Voltage vs. Load Current (Sourcing) Over Temperature 2.0 8 V+ = 5V 1.8 7 1.6 6 VS = 5V 5 1.2 ISY – mA TIMING – ns 1.4 1.0 0.8 SETUP TIME 4 VS = 3V 3 0.6 2 0.4 HOLD TIME 1 0.2 0 ⴚ50 ⴚ25 0 25 50 TEMPERATURE – ⴗC 75 0 ⴚ60 100 Figure 9. Latch Setup and Hold Time Over Temperature REV. 0 ⴚ40 ⴚ20 0 20 40 TEMPERATURE – ⴗC 60 80 100 Figure 12. Supply Current vs. Temperature –5– AD8611/AD8612 0 V+ = 5V TA = 25ⴗC ⴚ0.5 ⴚ1.0 VIN ⴚ2.0 VOLTAGE IGND – mA ⴚ1.5 VS = 3V ⴚ2.5 0V VOUT ⴚ3.0 VS = 5V ⴚ3.5 VIN TRACE – 10mV/DIV VOUT TRACE – 1V/DIV ⴚ4.0 ⴚ4.5 ⴚ50 100 50 0 TEMPERATURE – ⴗC TIME – 2ns/DIV Figure 13. IGND vs. Temperature Figure 16. Falling Edge Response 0 V+ = 5V TA = 25ⴗC ⴚ0.5 VOUT VOLTAGE ISY – mA ⴚ1.0 VS = 3V ⴚ1.5 ⴚ2.0 VIN VS = 5V ⴚ2.5 ⴚ3.0 ⴚ60 VIN TRACE – 10mV/DIV VOUT TRACE – 1V/DIV ⴚ40 ⴚ20 0 20 40 60 80 100 TIME – 4ns/DIV TEMPERATURE – ⴗC Figure 14. ISY– vs. Temperature V+ = 5V TA = 25ⴗC VOLTAGE 0V Figure 17. Response to a 50 MHz 100 mV Input Sine Wave VOUT 0V VIN VIN TRACE – 10mV/DIV VOUT TRACE – 1V/DIV TIME – 2ns/DIV Figure 15. Rising Edge Response –6– REV. 0 AD8611/AD8612 common-mode voltage range to the comparator. Note that signals much greater than 3.0 V will result in increased input currents and may cause the comparator to operate more slowly. Optimizing High-Speed Performance As with any high-speed comparator or amplifier, proper design and layout should be used to ensure optimal performance from the AD8611/AD8612. Excess stray capacitance or improper grounding can limit the maximum performance of high-speed circuitry. Minimizing resistance from the source to the comparator’s input is necessary to minimize the propagation delay of the circuit. Source resistance, in combination with the equivalent input capacitance of the AD8611/AD8612 creates an R-C filter that could cause a lagged voltage rise at the input to the comparator. The input capacitance of the AD8611/AD8612 in combination with stray capacitance from an input pin to ground results in several picofarads of equivalent capacitance. Using a surface-mount package and a minimum of input trace length, this capacitance is typically around 3 pF to 5 pF. A combination of 3 kΩ source resistance and 3 pF of input capacitance yields a time constant of 9 ns, which is slower than the 4 ns propagation delay of the AD8611/AD8612. Source impedances should be less than 1 kΩ for best performance. Another important consideration is the proper use of power supply bypass capacitors around the comparator. A 1 µF bypass capacitor should be placed within 0.5 inches of the device between each power supply pin and ground. Another 10 nF ceramic capacitor should be placed as close as possible to the device in parallel with the 1 µF bypass capacitor. The 1 µF capacitor will reduce any potential voltage ripples from the power supply, and the 10 nF capacitor acts as a charge reservoir for the comparator during high-frequency switching. The AD8611 is able to swing within 200 mV of ground and within 1.5 V of positive supply voltage. This is slightly more output voltage swing than the LT1016. The AD8611 also uses less current than the LT1016, 5 mA as compared to 25 mA of typical supply current. The AD8611 has a typical propagation delay of 4 ns, compared to the LT1394 and LT1016, whose propagation delays are typically 7 ns and 10 ns, respectively. Maximum Input Frequency and Overdrive The AD8611 can accurately compare input signals up to 100 MHz with less than 10 mV of overdrive. The level of overdrive required increases with ambient temperature, with up to 50 mV of overdrive recommended for a 100 MHz input signal and an ambient temperature of +85°C. It is not recommend to use an input signals with a fundamental frequency above 100 MHz as the AD8611 could draw up to 20 mA of supply current and the outputs may not settle to a definite state. The device will return to its specified performance once the fundamental input frequency returns to below 100 MHz. A continuous ground plane on the PC board is also recommended to maximize circuit performance. A ground plane can be created by using a continuous conductive plane over the surface of the circuit board, only allowing breaks in the plane for necessary traces and vias. The ground plane provides a low inductive current return path for the power supply, thus eliminating any potential differences at different ground points throughout the circuit board caused from “ground bounce.” A proper ground plane will also minimize the effects of stray capacitance on the circuit board. Output Loading Considerations The AD8611 can deliver up to 10 mA of output current without increasing its propagation delay. The outputs of the device should not be connected to more than 40 TTL input logic gates or drive less than 400 Ω of load resistance. The AD8611 output has a typical output swing between ground and 1 V below the positive supply voltage. Decreasing the output load resistance to ground will lower the maximum output voltage due to the increase in output current. Table I shows the typical output high voltage versus load resistance to ground. Upgrading the LT1394 and LT1016 The AD8611 single comparator is pin-for-pin compatible with the LT1394 and LT1016 and offers an improvement in propagation delay over both comparators. These devices can easily be replaced with the higher performance AD8611, but there are differences and it is useful to check that these ensure proper operation. Table I. Maximum Output Voltage vs. Resistive Load The five major differences between the AD8611 and the LT1016 include input voltage range, input bias currents, propagation delay, output voltage swing, and power consumption. Input commonmode voltage is found by taking the average of the two voltages at the inputs to the comparator. The LT1016 has an input voltage range from 1.25 V above the negative supply to 1.5 V below the positive supply. The AD8611 input voltage range extends down to the negative supply voltage to within 2 V of V+. If the input common-mode voltage could be exceeded, input signals should be shifted or attenuated to bring them into range, keeping in mind the note about source resistance in Optimizing High-Speed Performance. Output Load to Ground V+ ⴚ VOUT, HI (typ) 300 Ω 500 Ω 1 kΩ 10 kΩ > 20 kΩ 1.5 V 1.3 V 1.2 V 1.1 V 1.0 V Connecting a 500 Ω–2 kΩ pull-up resistor to V+ on the output will help increase the output voltage closer to the positive rail; in this configuration, however, the output voltage will not reach its maximum until at least 20 ns to 50 ns after the output voltage switches. This is due to the R-C time constant between the pull-up resistor and the output and load capacitances. The output pull-up resistor will not improve propagation delay. Example: An AD8611 power from a 5 V single supply has its noninverting input connected to 1 V peak-to-peak high-frequency signal centered around 2.3 V and its inverting input connected to a fixed 2.5 V reference voltage. The worst-case input common-mode voltage to the AD8611 is 2.65 V. This is well below the 3.0 V input REV. 0 The input bias current to the AD8611 is 7 µA maximum over temperature (–40°C to +85°C). This is identical to the maximum input bias current for the LT1394, and half of the maximum IB for the LT1016. Input bias currents to the AD8611 and LT1394 flow out from the comparator’s inputs, as opposed to the LT1016 whose input bias current flows into its inputs. Using low value resistors around the comparator and low impedance sources will minimize any potential voltage shifts due to bias currents. –7– AD8611/AD8612 The AD8611 is stable with all values of capacitive load; however, loading an output with greater than 30 pF will increase the propagation delay of that channel. Capacitive loads greater than 500 pF will also create some ringing on the output wave. Table II shows propagation delay versus several values of load capacitance. The loading on one output of the AD8611 does not affect the propagation delay of the other output. SIGNAL VREF PD Rising PD Falling < 10 pF 33 pF 100 pF 390 pF 680 pF 3.5 ns 5 ns 8 ns 14.5 ns 26 ns 3.5 ns 5 ns 7 ns 10 ns 15 ns R2 CF Figure 18. Configuring the AD8611/AD8612 with Hysteresis Table II. Propagation Delay vs. Capacitive Load CL R1 COMPARATOR Here, the input signal is connected directly to the inverting input of the comparator. The output is fed back to the noninverting input through R1 and R2. The ratio of R1 to R1 + R2 establishes the width of the hysteresis window with VREF setting the center of the window, or the average switching voltage. The Q output will switch low when the input voltage is greater than VHI, and will not switch high again until the input voltage is less than VLO as given in Equation 1: VHI = ( V+ − 1.5 − VREF ) Using the Latch to Maintain a Constant Output The latch input to the AD8611/AD8612 can be used to retain data at the output of the comparator. When the latch voltage goes high, the output voltage will remain in its previous state, independent of changes in the input voltage. VLO = VREF × R1 + VREF R1 + R2 (1) R2 R1 + R2 Where V+ is the positive supply voltage. The setup time for the AD8611/AD8612 is 0.5 ns and the hold time is 0.5 ns. Setup time is defined as the minimum amount of time the input voltage must remain in a valid state before the latch is activated for the latch to function properly. Hold time is defined as the amount of time the input must remain constant after the latch voltage goes high for the output to remain latched its voltage. The capacitor CF is optional and can be added to introduce a pole into the feedback network. This has the effect of increasing the amount of hysteresis at high frequencies, which is useful when comparing relatively slow signals in high-frequency noise environments. At frequencies greater than fP, the hysteresis window approaches VHI = V+ – 1.5 V and VLO = 0 V. For frequencies less than ƒP, the threshold voltages remain as in Equation 1. The latch input is TTL and CMOS compatible, so a logic high is a minimum of 2.0 V and a logic low is a maximum of 0.8 V. The latch circuitry in the AD8611/AD8612 has no built-in hysteresis. Clock Timing Recovery Comparators are often used in digital systems to recover clock timing signals. High-speed square waves transmitted over a distance, even tens of centimeters, can become distorted due to stray capacitance and inductance. Poor layout or improper termination can also cause reflections on the transmission line, further distorting the signal waveform. A high-speed comparator can be used to recover the distorted waveform while maintaining a minimum of delay. Input Stage and Bias Currents The AD8611 and AD8612 use a bipolar PNP differential input stage. This enables the input common-mode voltage range to extend from within 2.0 V of the positive supply voltage to 200 mV below the negative supply voltage. Therefore, using a single 5 V supply, the input common-mode voltage range is –200 mV to +3.0 V. Input common-mode voltage is the average of the voltages at the two inputs. For proper operation, the input common-mode voltage should be kept within the common-mode voltage range. Figure 19 shows the AD8611 used to recover a 65 MHz, 100 mV peak-to-peak distorted clock signal into a 4 V peak-to-peak square wave. The lower trace is the input to the AD8611 and the upper trace is the Q output from the comparator. The AD8611 is powered from a 5 V single supply. The input bias current for the AD8611/AD8612 is 4 µA, which is the amount of current that flows from each input of the comparator. This bias current will go to zero on an input that is high and will double on an input that is low, which is a characteristic common to any bipolar comparator. Care should be taken in choosing resistances to be connected around the comparator as large resistors could cause significant voltage drops due to the input bias current. VOUT 2V/DIV The input capacitance for the AD8611/AD8612 is typically 3 pF. This is measured by inserting a 5 kΩ source resistance in series with the input and measuring the change in propagation delay. 20mV/DIV VIN Using Hysteresis Hysteresis can easily be added to a comparator through the addition of positive feedback. Adding hysteresis to a comparator offers an advantage in noisy environments where it is not desirable for the output to toggle between states when the input signal is close to the switching threshold. Figure 18 shows a simple method for configuring the AD8611 or AD8612 with hysteresis. TIME – 10ns/DIV Figure 19. Using the AD8611 to Recover a Noisy Clock Signal –8– REV. 0 AD8611/AD8612 A 5 V High-Speed Window Comparator 5V 5V A window comparator circuit is used to detect when a signal is between two fixed voltages. The AD8612 can be used to create a high-speed window comparator, as shown in Figure 20. Here, the reference window voltages are set as: VHI R2 = R1 + R2 VLO 6 3 VIN < VLO VLO < VIN < VHI VIN > VHI 1k⍀ Q1 AD612 Q1, Q2 = 2N3960 5V AD612 9 R3 R4 Q2 500⍀ VIN VLO A2 8 5 11 14 12 1k⍀ 500⍀ PINS 2 AND 13 ARE NO CONNECTS Figure 20. A High-Speed Window Comparator Table III. Window Comparator Output States = 200 mV +5V = 200 mV 1 A1 4 To ensure a minimum of switching delay, high-speed transistors are recommended for Q1 and Q2. Using the AD8612 with 2N3960 transistors provides a total propagation delay from VIN to VOUT of less than 10 ns. Input Voltage VOUT 10 7 R2 The output of the A1 comparator will go high when the input signal exceeds VHI, and the output of A2 will go high only when VIN drops below VLO. When the input voltage is between VHI and VLO, both comparator outputs will be low, turning off both Q1 and Q2, thus driving VOUT to a high state. If the input signal goes outside of the reference voltage window, then VOUT will go low. REV. 0 VHI R4 = R 3 + R4 VOUT 1k⍀ 5V R1 –9– AD8611/AD8612 SPICE Model * AD8611 SPICE Macro-Model Typical Values * 1/2000, Ver. 1.0 * TAM / ADSC * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | Latch * | | | | | DGND * | | | | | | Q * | | | | | | | QNOT * | | | | | | | | .SUBCKT AD8611 1 2 99 50 80 51 45 65 * * INPUT STAGE * * Q1 4 3 5 PIX Q2 6 2 5 PIX IBIAS 99 5 800E-6 RC1 4 50 1E3 RC2 6 50 1E3 CL1 4 6 3E-13 CIN 1 2 3E-12 VCM1 99 7 DC 1.9 D1 5 7 DX EOS 3 1 POLY(1) (31,98) 1E-3 1 * * Reference Voltages * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 RREF 98 0 100E3 * * CMRR=66dB, ZERO AT 1kHz * ECM1 30 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 RCM1 30 31 10E3 RCM2 31 98 5 CCM1 30 31 15.9E-9 * * Latch Section * –10– REV. 0 AD8611/AD8612 RX 80 51 100E3 RB4 60 62 2000 E1 10 98 (4,6) 1 CB3 99 61 0.5E-12 S1 10 11 (80,51) SLATCH1 CB4 62 51 1E-12 R2 11 12 1 RO3 66 64 1 C3 12 98 5.4E-12 D5 E2 13 98 (12,98) 1 RO4 67 65 500 R3 12 13 500 EO3 63 51 (20,51) 1 * EO4 97 60 (20,51) 1 * Power Supply Section * * * MODELS GSY1 99 52 POLY(1) (99,50) 4E-3 -2.6E-4 * GSY2 52 50 POLY(1) (99,50) 3.7E-3 -.6E-3 .MODEL PIX PNP(BF=100,IS=1E-16) RSY .MODEL NOX NPN(BF=100,VAF=130,IS=1E-14) 52 51 10 64 65 DX * .MODEL DX D(IS=1E-14) * Gain Stage Av=250 fp=100MHz .MODEL SLATCH1 VSWITCH(ROFF=1E6,RON=500, * +VOFF=2.1,VON=1.4) G2 98 20 (12,98) 0.25 .ENDS AD8611 R1 20 98 1000 C1 20 98 10E-13 E3 97 0 (99,0) 1 E4 52 0 (51,0) 1 V1 97 21 DC 0.8 V2 22 52 DC 0.8 D2 20 21 DX D3 22 20 DX * * Q Output * Q3 99 41 46 NOX Q4 47 42 51 NOX RB1 43 41 2000 RB2 40 42 2000 CB1 99 41 0.5E-12 CB2 42 51 1E-12 RO1 46 44 1 D4 44 45 DX RO2 47 45 500 EO1 97 43 (20,51) 1 EO2 40 51 (20,51) 1 * * Q NOT Output * Q5 99 61 66 NOX Q6 67 62 51 NOX RB3 63 61 2000 REV. 0 –11– AD8611/AD8612 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead micro SO (RM-8) 0.1968 (5.00) 0.1890 (4.80) 0.122 (3.10) 0.114 (2.90) 8 8 5 0.1574 (4.00) 0.1497 (3.80) 1 0.199 (5.05) 0.187 (4.75) 0.122 (3.10) 0.114 (2.90) 1 5 4 0.2440 (6.20) 0.2284 (5.80) 4 PIN 1 0.0098 (0.25) 0.0040 (0.10) PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.011 (0.28) 0.003 (0.08) 33ⴗ 27ⴗ 0.0500 0.0192 (0.49) SEATING (1.27) 0.0098 (0.25) PLANE BSC 0.0138 (0.35) 0.0075 (0.19) 0.0196 (0.50) x 45° 0.0099 (0.25) 8° 0° 0.0500 (1.27) 0.0160 (0.41) 0.028 (0.71) 0.016 (0.41) 14-Lead Thin Shrink Small Outline (RU-14) 0.201 (5.10) 0.193 (4.90) 14 8 1 7 0.256 (6.50) 0.246 (6.25) PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 8ⴗ 0ⴗ 0.028 (0.70) 0.020 (0.50) PRINTED IN U.S.A. 0.018 (0.46) SEATING 0.008 (0.20) PLANE 0.043 (1.09) 0.037 (0.94) 0.177 (4.50) 0.169 (4.30) 0.006 (0.15) 0.002 (0.05) 0.120 (3.05) 0.112 (2.84) 0.0688 (1.75) 0.0532 (1.35) C3862–2.5–4/00 (rev. 0) 01541 8-Lead Small Outline IC (SO-8) –12– REV. 0