FEDL610Q101-03 Issue Date: Aug. 4, 2015 ML610Q101/ML610Q102 8-bit Microcontroller GENERAL DESCRIPTION This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as timers, PWM, UART, voltage level supervisor (VLS) function, and 10-bit successive approximation type A/D converter, are incorporated around 8-bit CPU nX-U8/100. The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by pipe line architecture parallel processing. The on-chip debug function that is installed enables program debugging and programming. FEATURES • CPU − 8-bit RISC CPU (CPU name: nX-U8/100) − Instruction system: 16-bit instructions − Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on − On-Chip debug function − Minimum instruction execution time 30.5µs (@32.768kHz system clock) 0.122µs (@8.192MHz system clock) • Internal memory − ML610Q101 : Internal 4Kbyte Flash ROM (2K×16 bits) (including unusable 32 byte test data area) − ML610Q102 : Internal 6Kbyte Flash ROM (3K×16 bits) (including unusable 32 byte test data area) − Internal 256byte data RAM (256×8 bits) • Interrupt controller − 1 non-maskable interrupt source (Internal source: 1) − 21 maskable interrupt sources (Internal sources: 16, External sources: 5) • Time base counter (TBC) − Low-speed time base counter ×1 channel − High-speed time base counter ×1 channel • Watchdog timer (WDT) − Non-maskable interrupt and reset − Free running − Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) • Timer − 8 bits × 6 channels (16-bit configuration available) − Support Continuos timer mode/one shot timer mode − Timer start/stop function by software or external trigger input 1/23 FEDL610Q101-03 ML610Q101/ML610Q102 • PWM − Resolution 16 bits × 1 channel − Support Continuos timer mode/one shot timer mode − PWM start/stop function by software or external trigger input • UART − Half-duplex − TXD/RXD × 1 channels − Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits − Positive logic/negative logic selectable − Built-in baud rate generator • Successive approximation type A/D converter (SA-ADC) − 10-bit A/D converter − Input × 6 channels • Analog Comparator − Operating voltage: VDD = 2.7V to 5.5V − Input voltage by common mode: VDD = 0.1V to VDD - 1.5V − Hysteresis (Comparator0 only): 20mV(Typ.) − Allows selection of interrupt disabled mode,falling-edge interrupt mode,rising-edge interrupt mode, or both-edge interrupt mode. • General-purpose ports (GPIO) − Input/output port × 11 channels (including secondary functions) • Reset − Reset by the RESET_N pin − Reset by power-on detection − Reset by the watchdog timer (WDT) overflow − Reset by voltage level supervisor(VLS) • Voltage level supervisor(VLS) − Judgment accuracy: ±3.0% (Typ.) − It can be used for low level detection reset. • Clock − Low-speed clock: Built-in RC oscillation (32.768 kHz) − High-speed clock: Built-in PLL oscillation (16.384 MHz), external clock The clock of the CPU is 8.192MHz(Max) − Selection of high-speed clock mode by software: Built-in PLL oscillation, external clock • Power management − HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states). − STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are stopped.) − Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) − Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals. 2/23 FEDL610Q101-03 ML610Q101/ML610Q102 • Shipment − 16-pin plastic SSOP ML610Q101-xxxMB (Blank product: ML610Q101-NNNMB) ML610Q102-xxxMB (Blank product: ML610Q102-NNNMB) − 16-pin plastic WQFN ML610Q101-xxxGD (Blank product: ML610Q101-NNNGD) ML610Q102-xxxGD (Blank product: ML610Q102-NNNGD) • Guaranteed operating range − Operating temperature: −40°C to 85°C − Operating voltage: VDD = 2.7V to 5.5V 3/23 FEDL610Q101-03 ML610Q101/ML610Q102 BLOCK DIAGRAM ML610Q101 Block Diagram Figure 1 show the block diagram of the ML610Q101. "*" indicates secondary function, tertiary function or quaternary function of each port. CPU (nX-U8/100) EPSW1～3 GREG 0～15 PSW Timing Controller ALU TEST RESET & TEST EA PC Instruction Register Program Memory (Flash) 4kbyte BUS Controller INT 1 UART RXD0 TXD0* PWM PWMC* Interrupt Controller INT 1 Power INT 1 INT 4 WDT INT 6 Analog Comparator ×2 INT 1 TBC 10bit-ADC INT 2 CMP0P* CMP0M* 1 CMP0POUT* CMP0NOUT* DSR/CSR RAM 256byte OSC AIN0* to AIN5* LR Data-bus VDD VSS RESET_N ECSR1～3 SP Instruction Decoder On-Chip ICE ELR1～3 8bit Timer ×6 INT 5 PA0 to PA2 GPIO PB0 to PB7 INT 1 VLS CMP1P* CMP1OUT* Figure 1 ML610Q101 Block Diagram 4/23 FEDL610Q101-03 ML610Q101/ML610Q102 ML610Q102 Block Diagram Figure 2 show the block diagram of the ML610Q102. "*" indicates secondary function, tertiary function or quaternary function of each port. CPU (nX-U8/100) EPSW1～3 GREG 0～15 PSW Timing Controller On-Chip ICE TEST Instruction Decoder DSR/CSR EA PC Instruction Register INT 1 RAM 256byte RESET & TEST UART RXD0 TXD0* PWM PWMC* Interrupt Controller Power INT 1 INT 4 WDT INT 6 INT 2 INT 1 TBC 10bit-ADC Analog Comparator ×2 Program Memory (Flash) 6kbyte BUS Controller Data-bus INT 1 CMP0P* CMP0M* CMP0OUT* CMP0POUT* CMP0NOUT* LR SP OSC AIN0* to AIN5* ECSR1～3 ALU VDD VSS RESET_N ELR1～3 8bit Timer ×6 INT 5 GPIO PA0 to PA2 PB0 to PB7 INT 1 VLS CMP1P* CMP1OUT* Figure 2 ML610Q102 Block Diagram 5/23 FEDL610Q101-03 ML610Q101/ML610Q102 PIN CONFIGURATION ML610Q101/ML610Q102 SSOP16 Pin Layout Figure 3 show the SSOP16 pin layout of the ML610Q101/ML610Q102. RESET_N TEST PB0 / PWMC / OUTCLK / CMP1OUT PB1 / TXD0 PB2 / CMP0POUT PB3 / CMP0MOUT PA2 / CLKIN / CMP0OUT VPP 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PA0 / PWMC / OUTCLK / TM9OUT PB7 / LSCLK / PWMC VDD VSS PB6 / CLKIN PB5 / PB4 / TXD0 PA1 / LSCLK / TMFOUT Figure 3 ML610Q101/ML610Q102 SSOP16 Pin Configuration 6/23 FEDL610Q101-03 ML610Q101/ML610Q102 ML610Q101/ML610Q102 WQFN16 Pin Layout VDD VSS PB6 / CLKIN PB5 / RXD0 / CMP0M 12 11 10 9 Figure 4 show the WQFN16 pin layout of the ML610Q101/ML610Q102. PA0 / PWMC / OUTCLK / TM9OUT 13 8 PA1 / LSCLK / TMFOUT PB7 / LSCLK / PWMC 14 7 PB4 / TXD0 TEST 15 6 PA2 / CLKIN / CMP0OUT RESET_N 16 PB3 / CMP0MOUT 4 PB2 / CMP0POUT 3 PB1 / TXD0 2 PB0 / PWMC / OUTCLK / CMP1OUT 1 5 VPP Figure 4 ML610Q101/ML610Q102 WQFN16 Pin Configuration 7/23 FEDL610Q101-03 ML610Q101/ML610Q102 LIST OF PINS PIN No. (SSOP) PIN No. (WQFN) 1 16 2 Primary function Pin name I/O RESET_N Secondary function Function Pin name I/O I Reset input pin Input/output pin for testing Tertiary function Function Pin name I/O O PWMC output TXD0 Quaternary function Function Pin name I/O Function Highspeed clock output CMP1 OUT O CMP1 output O UART data output 15 TEST I/O 3 1 PB0/ EXI4/ AIN2/ RXD0 4 2 PB1/ EXI5/ AIN3 Input/output port, External PWMC interrupt 4, I/O ADC input 2, UART receive Input/output port, External I/O interrupt 5, ADC input 3 5 3 PB2 I/O Input/output port, CMP0 POUT O CMP0_N output 6 4 PB3 I/O Input/output port CMP0 NOUT O CMP0_N output 7 6 Input/output port, External interrupt2 CLKIN I clock input CMP0 OUT O CMP0 output 8 5 VPP 9 8 PA1/ EXI1/ AIN1/ CMP1P Power supply pin for Flash ROM Input/output port, External interrupt 1, I/O ADC input 1, Comparator1 non-inverting input TMF OUT O timer F output 10 7 PB4/ CMP0P I/O 11 9 PB5/ RXD0/ CMP0M Input/output port, UART data receive, I/O Comparator1inverting input 12 10 PB6/ AIN4 I/O 13 11 Vss 14 12 VDD 14 PB7/ AIN5 Input/output port, LSCLK I/O ADC input 5 13 PA0/ EXI0/ AIN0 Input/output port, External PWMC I/O interrupt 0, ADC input 0 15 16 PA2/EXI2 I/O Input/output port, Comparator0 non-inverting input LSCLK O Low speed clock output TXD0 O UART data output I clock input O Lowspeed clock output PWMC O PWMC output O PWMC output Highspeed clock output TM9OUT O timer 9 output Input/output port, CLKIN ADC input 4 Negative power supply pin Positive power supply pin OUTCLK O OUTCLK O 8/23 FEDL610Q101-03 ML610Q101/ML610Q102 PIN DESCRIPTION Pin name I/O Description Primary/ Secondary/ Tertiary/ Quaternary Logic System Reset input pin. When this pin is set to a “L” level, system reset mode is set and the internal section is initialized. When this pin is set to a “H” level subsequently, — program execution starts. A pull-up resistor is internally connected. High-speed clock output pin. This pin is used as the tertiary function of the PA2 or Secondary/ CLKIN I the secondary function of PB6 pin. Tertiary Low-speed clock output pin. This pin is used as the tertiary function of the PA1 or Secondary/ LSCLK O the secondary function of the PB7 pin. Tertiary High-speed clock output pin. This pin is used as the tertiary function of the PA0 or OUTCLK O Tertiary PB0 pin. General-purpose input/output port General-purpose input/output port. PA0 to PA2 Since these pins have secondary functions and tertiary functions and quaternary I/O Primary functions, the pins cannot be used as a port when the secondary functions and PB0 to PB7 tertiary functions and quaternary functions are used. UART UART0 data output pin. This pin is used as the tertiary function of the PB1 or PB4 O TXD0 Tertiary pin. UART0 data input pin. This pin is used as the primary function of the PB0 or PB5 I RXD0 Primary or the quaternary function of the PB7 pin. PWM PWMC output pin. This pin is used as the secondary function of the PB0 or PA0 or Secondary O PWMC Quaternary the quaternary function of the PB7 pin. External interrupt External maskable interrupt input pins. Interrupt enable and edge selection can be I performed for each bit by software. These pins are used as the primary functions of Primary EXI0 to 2 the PA0 – PA2 pins. External maskable interrupt input pins. Interrupt enable and edge selection can be I performed for each bit by software. These pins are used as the primary functions of Primary EXI4,5 the PB0, PB1 pins. Timer External clock input pin used for both Timer E and Timer F.These pins are used as I TnTG Primary the primary function of the PA0-PA2, PB0-PB7 pins. O Timer 9 output pin. This pin is used as the quaternary function of the PA0 pin. TM9OUT Quaternary O Timer F output pin. This pin is used as the quaternary function of the PA1 pin. TMFOUT Quaternary RESET_N I Negative — — — Positive Positive Positive Positive Positive/ negative Positive/ negative — Positive Positive 9/23 FEDL610Q101-03 ML610Q101/ML610Q102 Pin name I/O Description Successive approximation type A/D converter Channel 0 analog input for successive approximation type A/D converter. This pin AIN0 I is used as the primary function of the PA0 pin. Channel 1 analog input for successive approximation type A/D converter. This pin AIN1 I is used as the primary function of the PA1 pin. Channel 2 analog input for successive approximation type A/D converter. This pin AIN2 I is used as the primary function of the PB0 pin. Channel 3 analog input for successive approximation type A/D converter. This pin AIN3 I is used as the primary function of the PB1 pin. Channel 4 analog input for successive approximation type A/D converter. This pin AIN4 I is used as the primary function of the PB6 pin. Channel 5 analog input for successive approximation type A/D converter. This pin AIN5 I is used as the primary function of the PB7 pin. Conparator Non-inverting input for comparator0. This pin is used as the primary function of the CMP0P I PB4 pin. Inverting input for comparator0. This pin is used as the primary function of the PB5 CMP0M I pin. CMP0OUT O Output for comparator0. This pin is used as the quaternary function of the PA2 pin. CMP0OUT O Output for comparator0. This pin is used as the quaternary function of the PB2 pin. CMP0OUT O Output for comparator0. This pin is used as the quaternary function of the PB3 pin. Non-inverting input for comparator1. This pin is used as the primary function of the CMP1P I PA1 pin. CMP1OUT O Output for comparator1. This pin is used as the quaternary function of the PB0 pin. For testing TEST Power supply VSS VDD VPP I/O Input/output pin for testing. A pull-down resistor is internally connected. — — — Negative power supply pin. Positive power supply pin. Power supply pin for Flash ROM Primary/ Secondary/ Tertiary/ Quaternary Logic Primary — Primary — Primary — Primary — Primary — Primary — Primary — Primary — Quaternary Quaternary Quaternary — — — Primary — Quaternary — — Positive — — — — — — 10/23 FEDL610Q101-03 ML610Q101/ML610Q102 ML610Q101/ML610Q102 TERMINATION OF UNUSED PINS Table 3 shows methods of terminating the unused pins for ML610Q101/ML610Q102. Table 3 Termination of Unused Pins Pin RESET_N TEST PA0 to PA2 PB0 to PB7 VPP Recommended pin termination Open Open Open Open Open Note: It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting. 11/23 FEDL610Q101-03 ML610Q101/ML610Q102 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (VSS = 0V) Symbol Condition Rating Unit Power supply voltage 1 Parameter VDD Ta = 25°C −0.3 to +7.0 V Power supply voltage 2 VPP Ta = 25°C −0.3 to +9.5 V VIN Ta = 25°C −0.3 to VDD+0.3 V Output voltage VOUT Ta = 25°C −0.3 to VDD+0.3 V Output current 1 IOUT1 Ta = 25°C −12 to +11 mA PD Ta = 25°C 0.5 mW TSTG −55 to +150 °C Input voltage Power dissipation Storage temperature RECOMMENDED OPERATING CONDITIONS (VSS = 0V) Parameter Symbol Condition Range Unit Operating temperature TOP −40 to +85 °C Operating voltage VDD 2.7 to 5.5 V Operating frequency (CPU) fOP VDD = 2.7V to 5.5V 30k to 8.4M Hz OPERATING CONDITIONS OF FLASH MEMORY (VSS=0V) Parameter Operating temperature Operating voltage Rewrite counts 1 Data retention* Symbol Condition TOP VDD VPP CEP YDR At write/erase At write/erase At write/erase ― ― Min. 0 4.5 7.7 ― 10 Rating Typ. ― ― ― ― ― Max. +40 5.5 8.3 80 ― Unit °C V cycles years *1 : However, please keep active time of the flash memory from exceeding ten years. Vpp pin has internal pull-down resistor. 12/23 FEDL610Q101-03 ML610Q101/ML610Q102 DC CHARACTERISTICS (1/4) Parameter Symbol Low-speed RC oscillation frequency fRCL (VDD=2.7 to 5.5V, VSS=0V, Ta=−40 to +85°C, unless otherwise specified) Rating Measuring Condition Unit circuit Min. Typ. Max. Ta = 25°C Ta = 25°C 1 PLL oscillation frequency* Ta = -10 to +85°C fPLL Typ. +1% Typ. +2% 16.38 4 ― Typ. +2.5% ― 34 TRST Typ. −2.5% 100 TNRST ― ― 0.4 TPOR ― ― 10 Ta = −40 to +85°C Reset pulse width Reset noise elimination pulse width Power-on reset activation power rise time Typ. −1% Typ. -2% 32.76 8 16.38 4 16.38 4 31 kHz MHz 1 µs ms *1 : 1024 clock average. CPU clk is fPLL /2 max. RESET 0.9*VDD VDD 0.3*VDD 0.3*VDD RESET_N PRST 0.3*VDD PRST RESET_N pin reset 0.9*VDD VDD 0.1*VDD TPOR Power on reset 13/23 FEDL610Q101-03 ML610Q101/ML610Q102 DC CHARACTERISTICS (2/4) Parameter Symbol (VDD=2.7 to 5.5V, VSS=0V, Ta=−40 to +85°C, unless otherwise specified) Rating Measuring Condition Unit circuit Min. Typ. Max. Typ −3.0 % Typ. −5.0 % Typ. −3.0 % Ta=25°C , VDD=fall VVLS0F VDD=fall Ta=25°C , VDD=rise VLS Judgment voltage VVLS0R Typ. −5.0 % VDD=rise ― VDD -1.5 Ta=25°C , VDD = 5.0V 10 20 30 VDD = 5.0V 5 20 35 Comparator0 Input offset voltage Comparator Referencevoltage error*3 Supply current 1 Supply current 2 VCMOF Ta=25°C , VDD = 5.0V ― ― 7 VCMREF Ta=25°C -25 ― 25 ― -50 ― 50 ― 1 30 VLS0=1 IDD1 CPU: In STOP state. Low-speed/high-speed oscillation: stopped. IDD2 CPU: In 32.768kHz 1 operating state.* High-speed oscillation: Stopped. 3.625 3.295 3.625 V 1 +5.0 % Typ +3.0 % Typ +5.0 % 0.1 VLS0=0 ― VHYSP 2.92 Typ . ― VLS0=1 Comparator0 hysteresis 2.92 3.295 VVLS1 VCMR 2.85 Typ +3.0 % Typ. +5.0 % Typ. +3.0 % Typ −3.0 % Typ −5.0 % VLS0=0 Ta=25°C Comparator0 In-phase input voltage range 2.85 V 4 Ta=-40 to +85°C mV µA 1 Ta=-40 to +85°C ― 3.7 6 mA *1 : LTBC and WDT are operating ,and significant bits of BLKCON0 to BLKCON4 registers are all “1”. *2 : When the CPU operating rate is 100%. Minimum instruction execution time: Approx 0.122 μs (at 8.192MHz system clock) *3 :Comparator input offset voltage is included. 14/23 FEDL610Q101-03 ML610Q101/ML610Q102 DC CHARACTERISTICS (3/4) Parameter Symbol (VDD=2.7 to 5.5V, VSS=0V, Ta=−40 to +85°C, unless otherwise specified) Rating Measuring Condition Unit circuit Min. Typ. Max. VOH IOH1 = −3.0mA, VDD = 4.5V *1 VDD −0.7 ― ― VOL IOL1 = +8.5mA, VDD = 4.5V *1 ― ― 0.6 VOH = VDD (in high-impedance state) VOL = VSS (in high-impedance state) VIH1 = VDD VIL1 = VSS, VDD = 5.0V VIH1 = VDD = 5.0V VIL1 = VSS VIH2 = VDD = 5.0V (when pulled-down) VIL2 = VSS, VDD=5.0V (when pulled-up) ― ― +1 −1 ― ― ― −650 20 −1 ― −500 115 ― 1 −350 200 ― 20 115 200 −200 −100 −20 Output voltage IOOH Output leakage IOOL Input current 1 (RESET_N) Input current 1 (TEST) Input current 2 (PA0-PA2) (PB0-PB7) IIH1 IIL1 IIH1 IIL1 IIH2 IIL2 V 2 µA 3 µA 4 *1 : When the one terminal output state. DC CHARACTERISTICS (4/4) Parameter Input voltage 1 (RESET_N) (TEST) (PA0 to PA2) (PB0,to PB7) Input pin capacitance (PA0 to PA2) (PB0 to PB7) Symbol (VDD=2.7 to 5.5V, VSS=0V, Ta=−40 to +85°C, unless otherwise specified) Rating Measuring Condition Unit circuit Min. Typ. Max. VIH1 0.7 ×VDD ― VDD VIL1 0 ― 0.3 ×VDD CIN f = 10kHz Ta = 25°C ― ― 20 V 2 pF 15/23 FEDL610Q101-03 ML610Q101/ML610Q102 MEASURING CIRCUITS MEASURING CIRCUIT 1 VDD VSS A CV：1μF CV MEASURING CIRCUIT 2 (*2) VIL Input pins (*1) Output pins VIH VDD Current load V VSS *1: Input logic circuit to determine the specified measuring conditions. *2: Measured at the specified output pins. 16/23 FEDL610Q101-03 ML610Q101/ML610Q102 MEASURING CIRCUIT 3 (*2) VIL Input pins (*1) Output pins VIH VDD A VSS *1: Input logic circuit to determine the specified measuring conditions. *2: Measured at the specified output pins. MEASURING CIRCUIT 4 Input pins A Output pins (*3) VDD VSS *3: Measured at the specified output pins. 17/23 FEDL610Q101-03 ML610Q101/ML610Q102 AC CHARACTERISTICS (External Interrupt) Parameter External interrupt disable period (VDD=2.7 to 5.5V, VSS=0V, Ta=−40 to +85°C, unless otherwise specified) Rating Symbol Condition Unit Min. Typ. Max. 2.5 x Interrupt: Enabled (MIE = 1), 3.5 x TNUL CPU: NOP operation syscl ― syscl µs System clock: 32.768kHz k k PA0 to PA2, PB0 to PB1 (Rising-edge interrupt) tNUL PA0 to PA2, PB0 to PB1 (Falling-edge interrupt) tNUL PA0 to PA2, PB0 to PB1 P00 ,P01,PB0 – PB2 (Both-edge interrupt) tNUL 18/23 FEDL610Q101-03 ML610Q101/ML610Q102 Electrical Characteristics of Successive Approximation Type A/D Converter Parameter Resolution Integral non-linearity error Differential non-linearity error Zero-scale error Full-scale error Allowable signal source impedance Conversion time (VDD=2.7 to 5.5V, VSS=0V, Ta=−40 to +85°C, unless otherwise specified) Rating Symbol Condition Unit Min. Typ. Max. n ― ― 10 bit INL RI≦5kΩ, HSCLK=8.192MHz −4 ― +4 DNL RI≦5kΩ, HSCLK=8.192MHz −3 ― +3 LSB RI≦5kΩ, HSCLK=8.192MHz −4 ― +4 VOFF FSE RI≦5kΩ, HSCLK=8.192MHz −4 ― +4 RI ― ― ― 5k Ω tCONV ― 102 ― φ/CH φ: fPLL/2 VDD A − 10µF RI≤5kΩ + Analog input 0.1µF AIN0 to AIN7 VSS 19/23 FEDL610Q101-03 ML610Q101/ML610Q102 PACKAGE DIMENSIONS ML610Q101/ML610Q102 SSOP16 Package (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 20/23 FEDL610Q101-03 ML610Q101/ML610Q102 ML610Q101/ML610Q102 WQFN16 Package (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 21/23 FEDL610Q101-03 ML610Q101/ML610Q102 REVISION HISTORY Document No. FEDL610Q101-01 FEDL610Q101-02 FEDL610Q101-03 Date Jan., 2013 Aug., 2013 Aug.4, 2015 Page Previous Current Edition Edition Description – – Formal edition 1 – 3 Added “16-pin plastic WQFN” – 7 Added ML610Q101/ML610Q102 WQFN16 Pin Layout 6 8 Added PIN No. (SSOP) 6 8 Changed the following description of PA0, PA1. “Input port” to “Input/output port”. 18 19 Changed the following description. “φ: fPLL/4” to “φ: fPLL/2” 18 19 Add ML610Q101/ML610Q102 WQFN16 Package – – Change the logo and style. 19 19 Add the following items. “Allowable signal source impedance” 13 13 Add the following items. “Power-on reset activation power rise slope” 22/23 FEDL610Q101-03 ML610Q101/ML610Q102 Notes 1) The information contained herein is subject to change without notice. 2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor. 3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate the standard usage and operations of the Products.The peripheral conditions must be taken into account when designing circuits for mass production. 4) The technical information specified herein is intended only to show the typical functions of the Products and examples of application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information. 5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems, gaming/entertainment sets) as well as the applications indicated in this document. 6) The Products specified in this document are not designed to be radiation tolerant. 7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems. 8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters. 9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the recommended usage conditions and specifications contained herein. 10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document. However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such information. 11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations. 12) When providing our Products and technologies contained in this document to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act. 13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor. Copyright 2013-2015 LAPIS Semiconductor Co., Ltd. 2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan http://www.lapis-semi.com/en/ 23/23