Maxim MAX9160 Lvds or lvttl/lvcmos input to 14 lvttl/lvcmos output clock driver Datasheet

19-2392; Rev 0; 4/02
LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver
Applications
Cellular Base Stations
Digital Cross-Connects
Servers
DSLAMs
Add/Drop Multiplexers
Networking Equipment
Features
♦ LVDS or LVTTL/LVCMOS Input Selection
♦ LVDS Input Fail-Safe Sets Outputs High for Open,
Undriven Short, or Undriven Parallel Termination
♦ Two Output Banks with Separate Bank Enables
♦ Integrated Output Series Termination for 60Ω
Lines
♦ 200ps (max) Output-to-Output Skew
♦ ±100ps (max) Peak-to-Peak Added Output Jitter
♦ 42% to 58% Output Duty Cycle at 125MHz
♦ Guaranteed 125MHz Operating Frequency
♦ LVDS Input Is High Impedance with VCC = 0V
or Open (Hot Swappable)
♦ 28-Pin Exposed- and Nonexposed-Pad TSSOP
or 32-Lead QFN Packages
♦ -40°C to +85°C Operating Temperature
♦ 3.0V to 3.6V Supply Voltage
Ordering Information
Typical Application Circuit and Functional Diagram appear
at end of data sheet.
Pin Configurations
TEMP RANGE
PIN-PACKAGE
MAX9160EUI
PART
-40°C to +85°C
28 TSSOP
MAX9160AEUI
-40°C to +85°C
28 TSSOP-EP**
MAX9160EGJ*
-40°C to +85°C
32 QFN-EP
*Future product—contact factory for availability.
**Exposed pad.
TOP VIEW
OUTA5 1
28 OUTA4
OUTA6 2
27 OUTA3
ENA 3
26 GND
SEL 4
25 OUTA2
SE_IN 5
VCC 6
24 OUTA1
MAX9160
EN_
SEL
SE_IN
VID
OUT_
H
H
H
X
H
H
H
L or
open
X
L
H
L or
open
X
≥ +50mV
H
H
L or
open
X
≤ -50mV
L
H
L or
open
X
Open, undriven short, or
undriven parallel termination
H
L or
Open
X
X
X
L
23 VCC
GND 7
22 OUTA0
IN+ 8
21 OUTB6
IN- 9
20 GND
GND 10
19 OUTB5
RSET 11
18 OUTB4
ENB 12
Function Table
17 VCC
OUTB0 13
16 OUTB3
OUTB1 14
15 OUTB2
TSSOP
Pin Configurations continued at end of data sheet.
VID = VIN+ - VINH = high logic level
L = low logic level
X = don’t care
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX9160
General Description
The MAX9160 125MHz, 14-port LVTTL/LVCMOS clock
driver repeats the selected LVDS or LVTTL/LVCMOS
input on two output banks. Each bank consists of seven
LVTTL/LVCMOS series terminated outputs and a bank
enable. The LVDS input has a fail-safe function. The
MAX9160 has a propagation delay that can be adjusted
using an external resistor to set the bias current for an
internal delay cell. The LVTTL/LVCMOS outputs feature
200ps maximum output-to-output skew and ±100ps maximum added peak-to-peak jitter.
The MAX9160 is designed to operate with a 3.3V supply voltage over the extended temperature range of
-40°C to +85°C. This device is available in 28-pin
exposed- and nonexposed-pad TSSOP and 32-lead
5mm x 5mm QFN packages.
MAX9160
LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..............................................................-0.3V to +4V
IN+, IN- to GND........................................................-0.3V to +4V
SE_IN, EN_, SEL, RSET, OUT_ to GND ........-0.3V to VCC + 0.3V
Output Short-Circuit Duration (OUT_) (Note 1) ..........Continuous
Continuous Power Dissipation (TA = +70°C)
28-Pin TSSOP (derate 12.8mW/°C above +70°C) .....1024mW
28-Pin TSSOP-EP (derate 23.8mW/°C above +70°C) ..1904mW
32-Pin QFN (derate 21.2mW/°C above +70°C) .........1704mW
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
ESD Protection
Human Body Model (IN+, IN-) .......................................±16kV
Human Body Model (SE_IN) ............................................±8kV
Soldering Temperature (10s) ...........................................+300°C
Note 1: Short one output at a time. Do not exceed the absolute maximum junction temperature.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, ENA = ENB = high, RSET = 12kΩ ±1%, differential input voltage IVIDI = 0.05V to 1.2V, input common-mode voltage VCM = IVID/2 I to 2.4V - IVID/2 I, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, IVIDI = 0.2V,
VCM = 1.2V, TA = +25°C.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (SE_IN, ENA, ENB, SEL)
Input High Voltage
VIH
2.0
VCC
V
Input Low Voltage
VIL
GND
0.8
V
Input Clamp Voltage
VCL
ICL = -18mA
-1.5
-20
Input Current
IIN
VIN = high or low
SE_IN Capacitance (Note 4)
CIN
SE_IN to GND
-0.85
V
+20
µA
6.1
pF
50
mV
LVDS INPUT (IN+, IN-)
Differential Input High Threshold
VTH
Differential Input Low Threshold
VTL
Input Current
IIN+, IIN-
Power-Off Input Current
IIN+(off)
IIN-(off)
-50
mV
0.05V ≤ IVIDI ≤ 0.6V
-15
+15
0.6V < IVIDI ≤ 1.2V
-20
+20
0.05V ≤ IVIDI ≤ 0.6V, VCC = 0V or open
-15
+15
0.6V < IVIDI ≤ 1.2V, VCC = 0V or open
-20
+20
µA
µA
Input Resistor 1
RIN1
VCC = 3.6V or 0V, Figure 1
51
100
kΩ
Input Resistor 2
RIN2
VCC = 3.6V or 0 V, Figure 1
200
341
kΩ
Input Capacitance (Note 4)
CIN
IN+ or IN- to GND
6.0
pF
-30
mA
9
pF
OUTPUTS (OUT_)
Output Short-Circuit Current
(Note 1)
IOS
Output Capacitance (Note 4)
CO
SEL = high, SE_IN = high, VOUT = 0V
SEL = low, VID = 100mV, VOUT = 0V
OUT_ to GND
VCC 0.2
IOH = -100µA
Output High Voltage
Fail-Safe Output High Voltage
2
VOH
VOHFS
-115
IOH = -4mA
2.4
IOH = -8mA
IOH = -4mA
2.1
VCC 0.2
2.4
IOH = -8mA
2.1
SEL = low, inputs
open, undriven short,
or undriven parallel
terminated
IOH = -100µA
_______________________________________________________________________________________
V
V
LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver
(VCC = 3.0V to 3.6V, ENA = ENB = high, RSET = 12kΩ ±1%, differential input voltage IVIDI = 0.05V to 1.2V, input common-mode voltage VCM = IVID/2 I to 2.4V - IVID/2 I, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, IVIDI = 0.2V,
VCM = 1.2V, TA = +25°C.) (Notes 2, 3)
PARAMETER
Output Low Voltage
SYMBOL
VOL
Supply Current
ICC
Output Series Resistance
(Note 5)
RS
CONDITIONS
MIN
TYP
MAX
UNITS
IOL = 100µA
0.2
IOL = 4mA
0.4
IOL = 8mA
0.8
SEL = high, SE_IN = high or low, no load
15
µA
10
mA
SEL = low, VID = -100mV or 100mV, no load
7.0
Output switched high, VOUT = 1.65V
72
Output switched low, VOUT = 1.65V
61
V
Ω
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, CL = 20pF, ENA = ENB = high, SEL = high or low, RSET = 12kΩ ±1%, differential input voltage IVIDI = 0.15V to
1.2V, input common-mode voltage VCM = IVID/2I to 2.4V - IVID/2 I, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
VCC = 3.3V, IVIDI = 0.2V, VCM = 1.2V, TA = +25°C.) (Notes 6, 7, 8)
PARAMETER
SYMBOL
Rise Time
tR
Fall Time
tF
CONDITIONS
MIN
TYP
1.4
Figures 2 and 3
1.4
RSET = 12kΩ
5.3
RSET = open
4.9
RSET = 12kΩ
5.3
RSET = open
4.9
6.5
MAX
UNITS
2.95
ns
2.95
ns
8.0
Low-to-High Propagation Delay
IN+, IN- to OUT_
tPLH1
SEL = low
High-to-Low Propagation Delay
IN+, IN- to OUT_
tPHL1
SEL = low
Low-to-High Propagation Delay
SE_IN to OUT_
tPLH2
SEL = high
2.2
2.9
3.8
ns
High-to-Low Propagation Delay
SE_IN to OUT_
tPHL2
SEL = high
2.2
3.1
3.8
ns
100
ps
Added Peak-to-Peak Output Jitter
tJ
Output Duty Cycle
ODC
Output-to-Output Skew (Note 9)
tSKOO
Part-to-Part Skew (Note 10)
tSKPP1
Part-to-Part Skew (Note 11)
tSKPP2
Maximum Switching Frequency
(Note 12)
fMAX
100mV peak-to-peak supply noise at
200kHz, 3.3V supply
9.0
6.4
8.0
9.0
fIN = 125MHz
42
58
fIN = 35MHz
48.75
51.25
200
SE_IN to OUT_, SEL = high
0.9
IN+, IN- to OUT_, SEL = low
2.2
SE_IN to OUT_, SEL = high
1.6
IN+, IN- to OUT_, SEL = low
2.7
125
ns
ns
%
ps
ns
ns
MHz
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH, VTL, and VID.
Note 3: Parameter limits over temperature are guaranteed by design and characterization. Devices are production tested at
TA = +25°C.
_______________________________________________________________________________________
3
MAX9160
DC ELECTRICAL CHARACTERISTICS (continued)
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.0V to 3.6V, CL = 20pF, ENA = ENB = high, SEL = high or low, RSET = 12kΩ ±1%, differential input voltage IVIDI = 0.15V to
1.2V, input common-mode voltage VCM = IVID/2I to 2.4V - IVID/2 I, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
VCC = 3.3V, IVIDI = 0.2V, VCM = 1.2V, TA = +25°C.) (Notes 6, 7, 8)
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Guaranteed by design and characterization.
Total of driver output resistance and integrated series resistor.
AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma.
CL includes scope probe and test jig capacitance.
Pulse generator conditions for SE_IN input: frequency = 125MHz, 50% duty cycle, ZO = 50Ω, tR = 1.2ns, and tF = 1.2ns (20%
to 80%), VOH = VCC, VOL = 0V. Pulse generator conditions for IN+, IN- input: frequency = 125MHz, 50% duty cycle, ZO =
50Ω, t R = 1ns, and t F = 1ns (20% to 80%). V ID , V CM as specified in AC Electrical Characteristics general
conditions.
Measured between outputs with identical loads at VCC/2 for a same-edge transition.
tSKPP1 is the greatest difference in propagation delay between different parts operating under identical conditions within
rated conditions.
tSKPP2 is the greatest difference in propagation delay between different parts operating within rated conditions.
All AC specifications met at fMAX.
Typical Operating Characteristics
(MAX9160 with RSET = 12kΩ ±1%, VCC = 3.3V, CL = 20pF, ENA = ENB = high, IVIDI = 0.2, VCM = 1.2V, fIN = 125MHz, TA = +25°C,
unless otherwise noted.)
6.2
tPHL
5.7
5.2
4.7
4.2
4
3.5
tPHL
3.0
2.5
tPLH
2.0
8.2
MAX9160 toc03
tPLH
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
MAX9160 toc02
6.7
4.0
SINGLE-ENDED PROPAGATION DELAY (ns)
MAX9160 toc01
7.2
SINGLE-ENDED PROPAGATION DELAY
vs. TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY (ns)
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
DIFFERENTIAL PROPAGATION DEALY (ns)
MAX9160
LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver
7.7
7.2
tPLH
6.7
6.2
tPHL
5.7
5.2
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
TEMPERATURE (°C)
3.0
3.1
3.2
3.3
3.4
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
3.5
3.6
LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver
tPLH
2.0
1.5
1.0
0.5
0
7.2
3.1
3.2
3.3
3.4
3.5
6.2
tPHL
5.7
5.2
3.15
3.10
3.05
4.7
3.6
3.00
0.1
0.6
1.1
1.6
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
2.1
SUPPLY VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
TEMPERATURE (°C)
OUTPUT VOLTAGE LOW
vs. TEMPERATURE
OUTPUT VOLTAGE HIGH
vs. SUPPLY VOLTAGE
OUTPUT VOLTAGE LOW
vs. SUPPLY VOLTAGE
0.15
0.10
ILOAD = -4mA
3.5
OUTPUT VOLTAGE LOW (V)
0.20
0.25
MAX9160 toc08
0.25
4.0
OUTPUT VOLTAGE HIGH (V)
MAX9160 toc07
0.30
3.0
2.5
2.0
1.5
1.0
0.24
0.23
0.22
0.21
0.05
0.5
ILOAD = 4mA
3.0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
3.2
3.3
3.4
3.5
3.6
3.1
3.2
3.3
3.4
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. FREQUENCY
DIFFERENTIAL PROPAGATION DELAY
vs. OUTPUT CAPACITANCE
TRANSITION TIME
vs. TEMPERATURE
100
80
60
40
20
10
tPLH
8
tPHL
6
4
15
30
45
60
75
FREQUENCY (MHz)
90
105 120
2.5
2.0
tR
tF
1.5
2
0
0
3.6
MAX9160 toc12
MAX9160 toc11
12
3.5
3.0
TRANSITION TIME (ns)
120
14
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9160 toc10
140
0
3.0
SUPPLY VOLTAGE (V)
ALL CHANNELS SWITCHING
CL = 18pF
SINGLE-ENDED INPUT
160
3.1
0.20
TEMPERATURE (°C)
200
180
ILOAD = 4mA
0
0
SUPPLY CURRENT (mA)
tPLH
6.7
ILOAD = -4mA
4.2
3.0
OUTPUT VOLTAGE LOW (V)
7.7
MAX9160 toc09
2.5
3.20
OUTPUT VOLTAGE HIGH (V)
3.0
OUTPUT VOLTAGE HIGH
vs. TEMPERATURE
MAX9160 toc05
tPHL
8.2
DIFFERENTIAL PROPAGATION DELAY (ns)
3.5
MAX9160 toc04
SINGLE-ENDED PROPAGATION DELAY (ns)
4.0
DIFFERENTIAL PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
MAX9160 toc06
SINGLE-ENDED PROPAGATION DELAY
vs. SUPPLY VOLTAGE
1.0
15
30
45
60
75
OUTPUT CAPACITANCE (pF)
90
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
_______________________________________________________________________________________
5
MAX9160
Typical Operating Characteristics (continued)
(MAX9160 with RSET = 12kΩ ±1%, VCC = 3.3V, CL = 20pF, ENA = ENB = high, IVIDI = 0.2, VCM = 1.2V, fIN = 125MHz, TA = +25°C,
unless otherwise noted.)
Typical Operating Characteristics (continued)
(MAX9160 with RSET = 12kΩ ±1%, VCC = 3.3V, CL = 20pF, ENA = ENB = high, IVIDI = 0.2, VCM = 1.2V, fIN = 125MHz, TA = +25°C,
unless otherwise noted.)
2.0
tF
1.5
1.0
8
7
tPLH
6
5
tPHL
4
3
2
3.2
3.3
3.4
3.5
3.6
MAX9160 toc15
MAX9160 toc14
9
250
DIFFERENTIAL INPUT
200
150
100
50
1
0
0
3.1
3.0
300
OUTPUT JITTER (psP-P)
tR
2.5
10
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9160 toc13
3.0
OUTPUT JITTER vs. 200kHz
SUPPLY NOISE AMPLITUDE
DIFFERENTIAL PROPAGATION DELAY
vs. RSET
TRANSITION TIME vs. SUPPLY VOLTAGE
TRANSITION TIME (ns)
MAX9160
LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver
5
SUPPLY VOLTAGE (V)
10
15
0
20
50
100
150
200
250
300
SUPPLY NOISE AMPLITUDE (mVP-P)
RSET (kΩ)
Pin Description
PIN
NAME
6
FUNCTION
QFN
TSSOP
1
4
SEL
LVCMOS/LVTTL Level Logic Input. SEL = high selects SE_IN. SEL = low or
open selects IN+, IN-. SEL is pulled to GND by an internal resistor.
2
5
SE_IN
LVCMOS/LVTTL Level Input. SE_IN is pulled to GND by an internal resistor.
3, 12, 16,
22, 29
6, 17, 23
VCC
Positive Supply Voltage. Bypass with 0.1µF and 0.001µF capacitors to ground.
4, 7, 13,
19, 25, 28
7, 10, 20, 26
GND
Ground
5
8
IN+
Noninverting Input of Differential Input
6
9
IN-
Inverting Input of Differential Input
8
11
RSET
Connect a 12kΩ ±1% resistor to ground to decrease the minimum to maximum
IN+, IN- to OUT_ propagation delay.
9
12
ENB
LVCMOS/LVTTL Level Logic Input. When ENB = high, outputs OUTB_ are
enabled and follow the selected input. When ENB = low or open, outputs
OUTB_ are driven low. ENB is pulled to GND by an internal resistor.
10, 11, 14, 15,
17, 18, 20
13–16, 18,
19, 21
OUTB_
Bank B LVCMOS/LVTTL Outputs
_______________________________________________________________________________________
LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver
PIN
NAME
QFN
TSSOP
21, 23, 24, 26,
27, 30, 31
1, 2, 22, 24, 25,
27, 28
OUTA_
32
3
ENA
Exposed
Pad
EP*
FUNCTION
Bank A LVCMOS/LVTTL Outputs
LVCMOS/LVTTL Level Logic Input. When ENA = high, outputs OUTA_ are
enabled and follow the selected input. When ENA = low or open, outputs
OUTA_ are driven low. ENA is pulled to GND by an internal resistor.
Solder to PC board
*MAX9160EGJ and MAX9160AEUI.
VCC
OUT_
CL
RIN2
FAIL-SAFE
COMPARATOR
TO INPUT
MUX
VCC - 0.3V
IN+
Figure 2. Output Load
-40°C to +85°C. This device is available in 28-pin
exposed and nonexposed pad TSSOP and 32-lead
5mm x 5mm QFN packages.
Fail-Safe
RIN1
A fail-safe circuit on the MAX9160 sets enabled outputs
high when the LVDS input is:
RIN1
IN-
Figure 1. Fail-Safe Input Circuit
Detailed Description
The MAX9160 125MHz, 14-port LVTTL/LVCMOS clock
driver repeats the selected LVDS or LVTTL/LVCMOS
input on two output banks. Each bank consists of seven
LVTTL/LVCMOS series terminated outputs and a bank
enable. The LVDS input has a fail-safe function. The
MAX9160 has a propagation delay that can be adjusted
using an external resistor to set the bias current for an
internal delay cell. The LVTTL/LVCMOS outputs feature
200ps maximum output-to-output skew and ±100ps
maximum added peak-to-peak jitter.
The MAX9160 is designed to operate with a 3.3V supply voltage over the extended temperature range of
• Open
• Undriven and shorted
• Undriven and terminated
Without a fail-safe circuit, when the LVDS input is
selected and undriven, noise may cause the enabled
outputs to switch. Open or undriven terminated input
conditions can occur when a cable is disconnected or
cut, or when a driver output is in high impedance. A
shorted input can occur because of a cable failure.
When the MAX9160 LVDS input is driven with a differential signal with a common-mode voltage between
IVID/2I and 2.4V - IVID/2I, the fail-safe circuit is not activated. If the input is open, undriven and shorted, or
undriven and parallel terminated, an internal resistor in
the fail-safe circuit pulls both of the LVDS inputs above
VCC - 0.3V, activating the fail-safe circuit and forcing
the output high (Figure 1).
_______________________________________________________________________________________
7
MAX9160
Pin Description (continued)
MAX9160
LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver
VCC
VCC/2
VCC/2
0V
SE_IN
IN0V DIFFERENTIAL
0V DIFFERENTIAL
IN+
tPHL
tPLH
VOH
80% VCC
80% VCC
50% VCC
50% VCC
OUT_
20% VCC
20% VCC
VOL
tR
tF
Figure 3. Transition Time and Propagation Delay Timing Diagram
Propagation Delay and RSET
Supply Bypassing
The MAX9160 delay can be adjusted by connecting a
resistor from RSET to ground. See Typical Operating
Characteristics for a graph of delay vs. RSET.
Bypass each supply pin with high-frequency surfacemount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller
value capacitor closest to the device.
Output Enables
Each bank of seven LVTTL/LVCMOS drivers is controlled by an output enable. Outputs follow the selected
input when EN_ is high. Outputs are low (not high
impedance) when EN_ = low.
Power Dissipation and Package Type
Power dissipation at high switching frequencies may
exceed the power dissipation capacity of the standard
TSSOP package (see the Supply Current vs. Frequency
graph in the Typical Operating Characteristics). An EP
version of the TSSOP package is available that dissipates higher power. Also, a space-saving QFN package with EP is available. The EP must be soldered to
the PC board.
8
Board Layout
A four-layer PC board that provides separate power,
ground, input, and output signals is recommended.
Keep input and output signals separated to prevent
coupling.
Chip Information
TRANSISTOR COUNT: 756
PROCESS: CMOS
_______________________________________________________________________________________
LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver
ENA
VCC
OUTA[0:6]
SEL
RSET
IN+
IN-
DELAY
MUX
VCC
SE_IN
OUTB[0:6]
ENB
_______________________________________________________________________________________
9
MAX9160
Functional Diagram
LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver
MAX9160
Typical Application Circuit
CARD 2
CARD 1
ASIC 1
ASIC 14
1
14
FPGA 1
FPGA 14
1
14
MAX9160
MAX9160
LVDS SYSTEM CLOCK
BACKPLANE
RT
TEST CLOCK
RT
SINGLE ENDED
ENA
OUTA6
OUTA5
VCC
GND
OUTA4
OUTA3
GND
31
30
29
28
27
26
25
TOP VIEW
32
Pin Configurations (continued)
SEL
1
24
SE_IN
2
23
OUTA1
VCC
3
22
VCC
GND
4
21
OUTA0
20
OUTB6
IN+
5
MAX9160
OUTA2
13
14
15
16
GND
OUTB2
OUTB3
VCC
OUTB4
12
17
11
8
VCC
RSET
OUTB1
OUTB5
10
GND
18
OUTB0
19
7
9
6
ENB
INGND
QFN
10
______________________________________________________________________________________
LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver
______________________________________________________________________________________
11
MAX9160
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX9160
LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
12
______________________________________________________________________________________
LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver
TSSOP, 4.0,EXP PADS.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX9160
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)