Holtek HA0004E A/d type 8-bit otp mcu Datasheet

HT46R14
A/D Type 8-Bit OTP MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0004E HT48 & HT46 MCU UART Software Implementation Method
- HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series
- HA0011E HT48 & HT46 Keyboard Scan Program
- HA0013E HT48 & HT46 LCM Interface Design
- HA0102E Using the HT46R14 in a CCFL Lamp Inverter
Features
· Operating voltage:
· Supports PFD for sound generation
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· HALT function and wake-up feature reduce power
consumption
· 20 bidirectional I/O lines
· Up to 0.5ms instruction cycle with 8MHz system clock
· Two interrupt input shared with an I/O line
at VDD=5V
· Two 8-bit programmable timer/event counter with
· 8-level subroutine nesting
overflow interrupt and 7-stage prescaler
· 8 channels 9-bit resolution A/D converter
· Two 8-bit programmable pulse generator (PPG) out-
· Two comparators with interrupt function
put channels, with prescaler and 8-bit programmable
timer counter, and supports active low or active high
output
· Bit manipulation instruction
· 15-bit table read instruction
· 63 powerful instructions
· On-chip crystal and RC oscillator
· All instructions in one or two machine cycles
· Watchdog Timer
· Low voltage reset function
· 4096´15 program memory
· 28-pin SKDIP/SOP package
· 192´8 data memory RAM
General Description
The device are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for
A/D applications that interface directly to analog signals,
such as those from sensors.
and wake-up functions, enhance the versatility of these
devices to suit a wide range of A/D application possibilities such as sensor signal processing, etc.
The device provides two comparators and programmable pulse generator (PPG). It is particularly suitable for
use in products such as induction cooker and home appliances.
The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions,
oscillator options, multi-channel A/D Converter, HALT
Rev. 1.00
1
November 1, 2005
HT46R14
Block Diagram
M
T M R 0 C
T M R 0
P F D 0
S ta c k
P ro g ra m
R O M
IN T C
P ro g ra m
C o u n te r
In s tr u c tio n
R e g is te r
M
M P
U
X
P P G 0 C
P P G T 0
P P G 0
D a ta
M e m o ry
P P G 1 C
P P G T 1
P P G 1
P C
S T A T U S
A L U
P o rt C
P C C
S h ifte r
T im in g
G e n e ra to r
U
P r e s c a le r
X
fS
Y S
T M R 0
T M R 1
U
M
W D T
M U X
In s tr u c tio n
D e c o d e r
M
T M R 1 C
T M R 1
P F D 1
In te rru p t
C ir c u it
U
X
fS
X
fS
Y S
Y S
/4
/4
W D T O S C
P r e s c a le r
fS
Y S
P r e s c a le r
fS
Y S
P C
P C
P C
P C
0 /C
1 /C
2 /C
3 /C
0 V
0 V
0 O
1 O
IN
IN
U
U
T
+
T
8 -C h a n n e l
A /D C o n v e rte r
O S C 2
O S
R E
V D
V S
S
S
C 1
H A L T
A C C
D
P B
E N /D IS
P o rt B
P B C
P B 0 /A N 0 ~ P B 7 /A N 7
L V R
P P G C
P A
P P G 0 C
P P G 0
P P G 0
P o rt A
P A C
P A
P A
P A
P A
P A
P A
P A
0 /P
1 ~ P
3 /P
4 /T
5 /IN
6 /IN
7 /T
P G 1
A 2
F D
M R 0
T 0
T 1
M R 1
Pin Assignment
P B 1 /A N 1
1
2 8
P B 2 /A N 2
P B 0 /A N 0
2
2 7
P B 3 /A N 3
P A 3 /P F D
3
2 6
P A 4 /T M R 0
P A 2
4
2 5
P A 5 /IN T 0
P A 1
5
2 4
P A 6 /IN T 1
P A 0 /P P G 1
6
2 3
P A 7 /T M R 1
P B 7 /A N 7
7
2 2
O S C 2
P B 6 /A N 6
8
2 1
O S C 1
P B 5 /A N 5
9
2 0
V D D
P B 4 /A N 4
1 0
1 9
R E S
V S S
1 1
1 8
P P G 0
C 1 V IN +
1 2
1 7
P C 0 /C 0 V IN -
C 1 V IN -
1 3
1 6
P C 1 /C 0 V IN +
P C 3 /C 1 O U T
1 4
1 5
P C 2 /C 0 O U T
H T 4 6 R 1 4
2 8 S K D IP -A /S O P -A
Rev. 1.00
2
November 1, 2005
HT46R14
Pin Description
Pin Name
PA0/PPG1
PA1~PA2
PA3/PFD
PA4/TMR0
PA5/INT0
PA6/INT1
PA7/TMR1
PB0/AN0~
PB7/AN7
I/O
I/O
I/O
Option
Description
Pull-high
Wake-up
PA3 or PFD
Bidirectional 8-bit input/output port. Each bit can be configured as wake-up input by options. Software instructions determine the CMOS output or Schmitt
trigger input with or without pull-high resistor (determined by pull-high option:
bit option).
The PFD, INT0 and INT1 are pin-shared with PA3, PA5 and PA6. The TMR0
is pin-shared with PA4, TMR1 is pin shared with PA7, respectively.
The PPG1 is a programmable pulse generator1 output pin, pin shared with
PA0. The PPG1 or I/O function is selected via configuration option. The PPG1
output pin is floating during power-on reset, RES pin reset or LVR reset. The
PPG1 output level (active low or active high) can be selected via configuration
option.
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high option: bit option) or A/D input.
Once a PB line is selected as an A/D input (by using software control), the I/O
function and pull-high resistor are disabled automatically.
PC0/C0VINPC1/C0VIN+
PC2/C0OUT
PC3/C1OUT
C1VIN+
C1VIN-
I/O
Pull-high
I/O or
Comparator
Bidirectional 4-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (determine by pull-high option: byte option).
C0VIN+, C0VIN- and C0OUT are pin-shared with PC1, PC0 and PC2. Once
the Comparator 0 function is used, the internal registers related to PC1, PC0
cannot be used, PC2 can be used as input only, the PC1, PC0 I/O function,
PC2 output function and pull-high resistor are disabled automatically. Software instructions determine the Comparator 0 function to be used.
C1VIN+ and C1VIN- are Comparator 1 input, C1OUT is pin-shared with PC3.
Once the Comparator 1 function is used, the internal register related to PC3
can be used as input only, the PC3 output function and pull-high resistor are
disabled automatically. Software instructions determine the Comparator 1
function to be used.
PPG0
O
¾
This is a programmable pulse generator 0 output pin, the pin is floating during
power-on reset, RES pin reset or LVR reset. The PPG0 output level (active
low or active high) can be selected via configuration option
OSC1
OSC2
I
O
Crystal
or RC
OSC1, OSC2 are connected to an RC network or a Crystal (determined by options) for the internal system clock. In the case of RC operation, OSC2 is the
output terminal for 1/4 system clock.
RES
I
¾
Schmitt trigger reset input. Active low.
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.00
3
November 1, 2005
HT46R14
D.C. Characteristics
Symbol
VDD
IDD1
Parameter
Operating Voltage
Test Conditions
5.5
V
¾
fSYS=8MHz
3.3
¾
5.5
V
3V
No load, fSYS=4MHz
ADC disable
¾
0.6
1.5
mA
¾
2
4
mA
¾
0.8
1.5
mA
¾
2.5
4
mA
¾
4
8
mA
¾
¾
5
mA
¾
¾
10
mA
¾
¾
1
mA
¾
¾
2
mA
5V
Standby Current (WDT Enabled)
5V
No load, fSYS=4MHz
ADC disable
No load, fSYS=8MHz
ADC disable
3V
No load, system HALT
5V
ISTB2
Unit
¾
3V
ISTB1
Max.
2.2
Operating Current (RC OSC)
Operating Current
(Crystal OSC, RC OSC)
Typ.
fSYS=4MHz
Operating Current (Crystal OSC)
IDD3
Min.
¾
5V
IDD2
Conditions
VDD
3V
Standby Current (WDT Disabled)
No load, system HALT
5V
VIL1
Input Low Voltage for I/O Ports,
TMR0 and TMR1
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR0 and TMR1
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾
¾
2.7
3
3.3
V
IOL
4
8
¾
mA
I/O Port Sink Current
10
20
¾
mA
-2
-4
¾
mA
-5
-10
¾
mA
3V
VOL=0.1VDD
5V
IOH
3V
I/O Port Source Current
VOH=0.9VDD
5V
RPH
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
Pull-high Resistance
VAD
A/D Input Voltage
¾
¾
0
¾
VDD
V
EAD
A/D Conversion Error
¾
¾
¾
±0.5
±1
LSB
IADC
Additional Power Consumption
if A/D Converter is Used
3V
¾
0.5
1
mA
¾
1.5
3
mA
VOS
Comparator Input Offset Voltage
¾
¾
-10
¾
10
mV
VI
Comparator Input Voltage Range
¾
¾
0.2
¾
VDD-0.8
V
¾
5V
Ta=25°C
Rev. 1.00
4
November 1, 2005
HT46R14
A.C. Characteristics
Symbol
fSYS
fTIMER
tWDTOSC
Ta=25°C
Test Conditions
Parameter
VDD
System Clock
Timer I/P Frequency
(TMR0/TMR1)
Conditions
Min.
Typ.
Max.
Unit
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
3V
5V
Watchdog Oscillator Period
0
¾
8000
kHz
¾
45
90
180
ms
¾
32
65
130
ms
¾
1
¾
¾
ms
¾
1024
¾
*tSYS
tRES
External Reset Low Pulse Width
¾
tSST
System Start-up Timer Period
¾
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD
A/D Clock Period
¾
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
76
¾
tAD
tADCS
A/D Sampling Time
¾
¾
¾
32
¾
tAD
tCOMP
Comparator Response Time
¾
¾
¾
¾
3
ms
Power-up or Wake-up
from HALT
Note: *tSYS=1/fSYS
Functional Description
Execution Flow
Program Counter - PC
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
The program counter (PC) controls the sequence in
which the instructions stored in program PROM are executed and its contents specify full range of program
memory.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the
memory word containing the next instruction code.
S y s te m
O S C 2 (R C
C lo c k
T 1
T 2
T 3
T 4
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 1
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
P C + 2
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Rev. 1.00
5
November 1, 2005
HT46R14
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt 0
0
0
0
0
0
0
0
0
0
1
0
0
External Interrupt 1
0
0
0
0
0
0
0
0
1
0
0
0
Comparator 0 interrupt
0
0
0
0
0
0
0
0
1
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
1
0
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
1
0
1
0
0
A/D Converter Interrupt
0
0
0
0
0
0
0
1
1
0
0
0
Skip
Program Counter+2
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*11~*0: Program counter bits
#11~#0: Instruction code bits
S11~S0: Stack register bits
@7~@0: PCL bits
· Location 00CH
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
Location 00CH is reserved for the Comparator 0 interrupt service program. If the Comparator 0 output pin is
activated, and if the interrupt is enable and the stack is
not full, the program begins execution at location
00CH.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations. When a control transfer takes
place, an additional dummy cycle is required.
· Location 010H
Location 010H is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 010H.
Program memory - ROM
· Location 014H
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
4096´15 bits, addressed by the program counter and table pointer.
Location 014H is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 014H.
Certain locations in the program memory are reserved
for special usage:
· Location 018H
Location 018H is reserved for the A/D converter interrupt service program. If an A/D converter interrupt results from an end of A/D conversion, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 018H.
· Location 000H
Location 000H is reserved for program initialization.
After chip reset, the program always begins execution
at location 000H.
· Table location
· Location 004H
Any location in the PROM space can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower
portion of TBLH, and the remaining 1 bit is read as ²0².
Location 004H is reserved for the external interrupt 0
service program. If the INT0 input pin is activated, the
interrupt is enabled and the stack is not full, the program begins execution at location 004H.
· Location 008H
Location 008H is reserved for the external Interrupt 1
service program. If the INT1 input pin is activated, the
interrupt is enabled and the stack is not full, the program begins execution at location 008H.
Rev. 1.00
6
November 1, 2005
HT46R14
The Table Higher-order byte register (TBLH) is read
only. The table pointer (TBLP) is a read/write register
(07H), which indicates the table location. Before accessing the table, the location must be placed in
TBLP. The TBLH is read only and cannot be restored.
If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be
changed by the table read instruction used in the ISR.
Errors can occur. In other words, using the table read
instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read
instruction has to be applied in both the main routine
and the ISR, the interrupt is supposed to be disabled
prior to the table read instruction. It will not be enabled
until the TBLH has been backed up. All table related
instructions require two cycles to complete the operation. These areas may function as normal program
memory depending upon the requirements.
0 0 0 H
E x te r n a l In te r r u p t 0 S u b r o u tin e
0 0 8 H
Data Memory - RAM
E x te r n a l In te r r u p t 1 S u b r o u tin e
0 0 C H
0 1 4 H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 8 return addresses are stored).
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
0 1 0 H
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
The data memory is designed with 221´8 bits. The
data memory is divided into two functional groups: special function registers and general purpose data memory (192´8). Most are read/write, but some are read
only.
C o m p a r a to r 0 In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e
0 1 8 H
A /D
n 0 0 H
P ro g ra m
M e m o ry
C o n v e r te r In te r r u p t S u b r o u tin e
The special function registers consist of an Indirect addressing register 0 (00H), a Memory pointer register 0
(MP0;01H), an Indirect addressing register 1 (02H), a
Memory pointer register 1 (MP1;03H), an Accumulator
(ACC;05H), a Program counter lower-order byte register (PCL;06H), a Table pointer (TBLP;07H), a Table
higher-order byte register (TBLH;08H), a Status register (STATUS;0AH), an Interrupt control register 0
(INTC0;0BH), a Timer/Event Counter 0 (TMR0;0DH), a
Timer/Event Counter 0 control register (TMR0C;0EH),
a Timer/Event Counter 1 (TMR1:10H), a Timer/Event
Counter 1 control register (TMR1C; 11H), Interrupt
control register 1 (INTC1;1EH) , the A/D result
lower-order byte register (ADRL;24H), the A/D result
higher-order byte register (ADRH;25H), the A/D control
register (ADCR;26H), the A/D clock setting register
(ACSR;27H), I/O registers (PA;12H, PB;14H, PC;16H)
and I/O control registers (PAC;13H, PBC;15H, PCC;
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
L o o k - u p T a b le ( 2 5 6 w o r d s )
F F F H
1 5 b its
N o te : n ra n g e s fro m
0 to F
Program Memory
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 8 levels and is neither part of the
Instruction
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*11~*0: Table location bits
@7~@0: Table pointer bits
Rev. 1.00
P11~P8: Current program counter bits
7
November 1, 2005
HT46R14
In d ir e c t A d d r e s s in g R e g is te r 0
17H), the programmable pulse generator0 (PPG0)
control register (PPG0C;20H), the programmable
pulse generator timer register (PPGT0;21H), the programmable pulse generator1 (PPG1) control register
(PPG1C;22H), the programmable pulse generator
timer register (PPGT1;23H).
0 0 H
0 6 H
P C L
The remaining space before the 40H is reserved for future expanded usage and reading these locations will
get ²00H². The general purpose data memory, addressed from ²40H² to ²FFH², is used for data and control information under instruction commands.
0 7 H
T B L P
0 8 H
T B L H
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
0 5 H
A C C
0 9 H
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0;01H/MP1;03H).
0 D H
T M R 0
0 E H
T M R 0 C
0 F H
1 0 H
T M R 1
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
Indirect Addressing Register
1 4 H
P B
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to
by MP0(01H) and MP1(03H) respectively. Reading location 00H or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation.
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
1 9 H
1 A H
1 B H
1 C H
The function of data movement between two indirect addressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 8-bit registers used to
access the RAM by combining corresponding indirect
addressing registers.
1 D H
1 E H
IN T C 1
1 F H
2 0 H
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
P P G 0 C
2 1 H
P P G T 0
2 2 H
P P G 1 C
2 3 H
P P G T 1
2 4 H
A D R L
2 5 H
A D R H
2 6 H
A D C R
2 7 H
A C S R
2 8 H
Arithmetic and Logic Unit - ALU
3 F H
4 0 H
This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
F F H
· Logic operations (AND, OR, XOR, CPL)
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 9 2 B y te s )
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
(TO). It also records the status information and controls
the operation sequence.
· Branch decision (SZ, SNZ, SIZ, SDZ)
The ALU not only saves the results of a data operation but
also changes the status register.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addition operations related to the status register may give
different results from those intended. The TO flag
can be affected only by system power-up, a WDT
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
Rev. 1.00
S p e c ia l P u r p o s e
D a ta M e m o ry
8
November 1, 2005
HT46R14
time-out or executing the ²CLR WDT² or ²HALT² instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or a
system power-up.
stack followed by a branch to a subroutine at the specified location in the ROM. Only the contents of the program counter is pushed onto the stack. If the contents of
the register or of the status register (STATUS) is altered
by the interrupt service program which corrupts the desired control sequence, the contents should be saved in
advance.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
External interrupts are triggered by a high to low transition of INT0 or INT1, and the related interrupt request
flag (EI0F;bit 4 of the INTC0, EI1F;bit 5 of the INTC0) is
set as well. After the interrupt is enabled, the stack is not
full, and the external interrupt is active, a subroutine call
to location 04H or 08H occurs. The interrupt request flag
(EI0F or EI1F) and EMI bits are all cleared to disable
other interrupts.
Interrupt
The devices provides two external interrupts, two internal timer/event counter 0/1 interrupts, one comparator
interrupt, and A/D converter interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register
1 (INTC1;1EH) both contain the interrupt control bits
that are used to set the enable/disable status and interrupt request flags.
The Comparator 0 output Interrupt is initialized by setting the Comparator 0 output Interrupt request flag
(C0F; bit 6 of the INTC0), which is caused by a falling
edge transition of comparator 0 output. After the interrupt is enabled, and the stack is not full, and the C0F bit
is set, a subroutine call to location 0CH occurs. The related interrupt request flag (C0F) is reset, and the EMI
bit is cleared to disable further maskable interrupts.
Once an interrupt subroutine is serviced, other interrupts are all blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may take place during this interval,
but only the interrupt request flag will be recorded. If a
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit of the
INTC0 or of INTC1 may be set in order to allow interrupt
nesting. Once the stack is full, the interrupt request will
not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service
is desired, the stack should be prevented from becoming full.
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F;bit 4 of the INTC1), which is normally
caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a
subroutine call to location 010H occurs. The related interrupt request flag (T0F) is reset, and the EMI bit is
cleared to disable further interrupts. The Timer/Event
Counter 1 is operated in the same manner, The
Timer/Event Counter 1 related interrupt request flag is
T1F (bit 5 of the INTC1) and its subroutine call location
is 014H. The related interrupt request flag (T1F) will be
reset and the EMI bit cleared to disable further interrupts.
All these interrupts can support a wake-up function. As
an interrupt is serviced, a control transfer occurs by
pushing the contents of the program counter onto the
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction, otherwise AC is cleared.
2
Z
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa, otherwise OV is cleared.
4
PDF
PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.
Status (0AH) Register
Rev. 1.00
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November 1, 2005
HT46R14
Interrupt Source
The A/D converter interrupt is initialized by setting the
A/D converter request flag (ADF; bit 6 of the INTC1), is
caused by an end of A/D conversion. When the interrupt
is enabled, the stack is not full and the ADF is set, a subroutine call to location 018H will occur. The related interrupt request flag (ADF) will be reset and the EMI bit
cleared to disable further interrupts. After the interrupt is
enabled, and a subroutine call to location 018H occurs.
During the execution of an interrupt subroutine, other interrupt acknowledgments are all held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set both to 1 (if the stack is not
full). To return from the interrupt subroutine, ²RET² or
²RETI² may be invoked. RETI sets the EMI bit and enables an interrupt service, but RET does not.
Priority Vector
External interrupt 0
1
04H
External interrupt 1
2
08H
Comparator 0 output interrupt
3
0CH
Timer/Event Counter 0 overflow
4
10H
Timer/Event Counter 1 overflow
5
14H
A/D converter interrupt
6
18H
The Comparator 0 interrupt request flag (C0F), external
interrupt 1 request flag (EI1F), External Interrupt 0 request flag (EI0F), Enable Comparator 0 output interrupt
bit (EC0I), Enable External interrupt 1 bit (EEI1), Enable
External Interrupt 0 bit (EEI0), and enable master interrupt bit (EMI) make up of the Interrupt Control register 0
(INTC0) which is located at 0BH in the RAM.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
priorities in the following table apply. These can be
masked by resetting the EMI bit.
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1=enable; 0=disable)
1
EEI0
Controls the external interrupt 0 (1=enable; 0=disable)
2
EEI1
Controls the external interrupt 1 (1=enable; 0=disable)
3
EC0I
Control the Comparator 0 interrupt (1= enable; 0= disable)
4
EI0F
External interrupt 0 request flag (1=active; 0=inactive)
5
EI1F
External interrupt 1 request flag (1=active; 0=inactive)
6
C0F
The Comparator 0 request flag (1=active; 0=inactive)
7
¾
For test mode used only.
Must be written as ²0²; otherwise may result in unpredictable operation.
INTC0 (0BH) Register
Bit No.
Label
Function
0
ET0I
Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)
1
ET1I
Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable)
2
EADI
Controls the A/D converter interrupt (1=enable; 0=disable)
3
¾
4
T0F
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
5
T1F
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
6
ADF
The A/D converter request flag (1=active; 0=inactive)
7
¾
Unused bit, read as ²0²
Unused bit, read as ²0²
INTC1 (1EH) Register
Rev. 1.00
10
November 1, 2005
HT46R14
lation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not
suitable for timing sensitive operations where an accurate oscillator frequency is desired.
The A/D converter request flag (ADF), the Timer/Event
Counter 1 interrupt request flag (T1F), the Timer/Event
Counter 0 interrupt request flag (T0F), enable A/D converter interrupt bit (EADI), enable Timer/Event Counter
1 interrupt bit (ET1I), and enable Timer/Event Counter 0
interrupt bit (ET0I), constitute the Interrupt Control register 1 (INTC1) which is located at 1EH in the RAM.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to
get a frequency reference, but two external capacitors in
OSC1 and OSC2 are required (If the oscillating frequency is less than 1MHz).
EMI, EEI0, EEI1, EC0I, ET0I, ET1I, and EADI are all
used to control the enable/disable status of interrupts.
These bits prevent the requested interrupt from being
serviced. Once the interrupt request flags (EI0F, EI1F,
C0F, T0F, T1F, ADF) are all set, they remain in the
INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a software instruction.
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works within
a period of approximately 65ms@5V. The WDT oscillator
can be disabled by options to conserve power.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged
once the ²CALL² operates in the interrupt subroutine.
Watchdog Timer - WDT
The clock source of the WDT is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock
(system clock divided by 4) determined by options. This
timer is designed to prevent a software malfunction or
sequence jumping to an unknown location with unpredictable results. The watchdog timer can be disabled by
option. If the watchdog timer is disabled, all the executions related to the WDT result in no operation.
Oscillator Configuration
There are two oscillator circuits in the microcontroller.
V
D D
O S C 1
O S C 1
fS Y S /4
N M O S O p e n D r a in
O S C 2
C r y s ta l O s c illa to r
Once an internal WDT oscillator (RC oscillator with a period of 65ms/@5V normally) is selected, it is divided by
213, 214 , 215 or 216 (by options) to get the WDT time-out
period. The minimum WDT time-out period is about
600ms. This time-out period may vary with temperature,
VDD and process variations. By selection the WDT options, longer time-out periods can be realized. If the
WDT time-out is selected to fS/216, the maximum
time-out period is about 4.7s.
O S C 2
R C
O s c illa to r
System Oscillator
Both are designed for system clocks, namely the RC oscillator and the Crystal oscillator, which are determined
by options. No matter what oscillator type is selected,
the signal provides the system clock. The HALT mode
stops the system oscillator and ignores an external signal to conserve power.
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the Halt state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. If the
device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance must
range from 24kW to 1MW. The system clock, divided by
4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the most
cost effective solution. However, the frequency of oscilS y s te m
W D T
O S C
C lo c k /4
M a s k
o p tio n
s e le c t
fs
D iv id e r
fs/2
8
W D T P r e s c a le r
M a s k O p tio n
W D T C le a r
T im e - o u t R e s e t
fs/2 1 6
fs/2 1 5
fs/2 1 4
fs/2 1 3
Watchdog Timer
Rev. 1.00
11
November 1, 2005
HT46R14
quences may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is
set to ²1² before entering the HALT mode, the wake-up
function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 tSYS (system clock
period) to resume normal operation. In other words, a
dummy period will be inserted after wake-up. If the
wake-up results from an interrupt acknowledgment, the
actual interrupt subroutine execution will be delayed by
one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately
after the dummy period is finished.
The WDT overflow under normal operation will initialize a
²chip reset² and set the status bit TO. Whereas in the Halt
mode, the overflow will initialize a ²warm reset² in which
only the program counter and stack pointer are reset to
zero. To clear the contents of the WDT, three methods are
adopted; external reset (a low level to RES), software instructions, or a HALT instruction. The software instructions
include CLR WDT and the other set - CLR WDT1 and
CLR WDT2. Of these two types of instruction, only one
can be active depending on the mask option - ²CLR WDT
times selection option². If the ²CLR WDT² is selected (i.e.
CLRWDT times equal one), any execution of the CLR
WDT instruction will clear the WDT. In case ²CLR WDT1²
and ²CLR WDT2² are chosen (i.e. CLRWDT times equal
two), these two instructions must be executed to clear the
WDT; otherwise, the WDT may reset the chip because of
time-out.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
If the WDT time-out period is selected fs/212 (by options),
the WDT time-out period ranges from fs/212~fs/213, since
the ²CLR WDT² or ²CLR WDT1² and ²CLR WDT2² instructions only clear the last two stages of the WDT.
Reset
There are three ways in which a reset can occur:
· RES reset during normal operation
· RES reset during HALT
Power Down Operation - HALT
· WDT time-out reset during normal operation
The HALT mode is initialized by the ²HALT² instruction
and results in the following:
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the program counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
· The system oscillator will be turned off but the WDT
oscillator keeps running (if the WDT oscillator is selected).
· The contents of the on chip RAM and registers remain
unchanged.
· WDT will be cleared and recounted again (if the WDT
clock is from the WDT oscillator).
· All of the I/O ports maintain their original status.
· The PD flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². After the TO and PD flags are examined, the reason for chip reset can be determined.
The PD flag is cleared by system power-up or executing
the ²CLR WDT² instruction and is set when executing
the ²HALT² instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the program counter and stack pointer; the others keep
their original status.
PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: ²u² means ²unchanged²
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by the mask option. Awakening from an I/O port
stimulus, the program will resume execution of the next
instruction. If it awakens from an interrupt, two se-
Rev. 1.00
TO
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay. The functional unit chip reset status
are shown below.
12
November 1, 2005
HT46R14
An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES reset).
Program Counter
000H
Interrupt
Disable
Prescaler, Divider
Cleared
WDT
Clear. After master reset, WDT begins counting
Timer/Event Counter
Off
PPG Timer
Off
PPG output
Floating
Input/Output Ports
Input mode
Stack Pointer
Points to the top of the stack
The registers states are summarized in the following table.
Register
Reset
(Power On)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000H
000H
000H
000H
000H
Program
Counter
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PCC
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
INTC1
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
PPG0C
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PPGT0
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
PPG1C
0000 00-0
0000 00-0
0000 00-0
0000 00-0
uuuu uu-u
PPGT1
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
x--- ----
x--- ----
x--- ----
x--- ----
u--- ----
ADRL
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
---- --00
---- --00
---- --00
---- --00
---- --uu
Note:
²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
Rev. 1.00
13
November 1, 2005
HT46R14
makes the starting value be placed in the timer/event
counter 0/1 preload register and reading TMR0/1 get the
contents of the timer/event counter 0/1. The TMR0C and
TMR1C are Timer/Event Counter control register 0/1,
which defines the operating mode, counting enable or disable and an active edge.
V D D
R E S
tS
S T
S S T T im e - o u t
C h ip
R e s e t
Reset Timing Chart
V
The T0M0/T1M0 and T0M1/T1M1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an
external (TMR0, TMR1) pin. The timer mode functions as
a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level
duration of the external signal (TMR0, TMR1), and the
counting is based on the internal selected clock source.
D D
0 .0 1 m F *
1 0 0 k W
R E S
1 0 k W
0 .1 m F *
In the event count or timer mode, the Timer/Event Counter
0/1 starts counting at the current contents in the
timer/event counter and ends at FFH. Once an overflow
occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request
flag (T0F; bit 4 of the INTC1, T1F; bit 5 of the INTC1).
Reset Circuit
Note:
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
H A L T
W a rm
In the pulse width measurement mode with the values of
the T0ON/T1ON and T0E/T1E bits equal to ²1², after the
TMR0/TMR1 has received a transient from low to high (or
high to low if the T0E/T1E bit is ²0²), it will start counting
until the TMR0/TMR1 returns to the original level and resets the T0ON/T1ON.
R e s e t
W D T
R E S
S S T
1 0 - b it R ip p le
C o u n te r
C o ld
R e s e t
The measured result remains in the timer/event counter
even if the activated transient occurs again. In other
words, only 1-cycle measurement can be made until the
T0ON/T1ON is set. The cycle measurement will
S y s te m R e s e t
re-function as long as it receives further transient pulse. In
this operation mode, the timer/event counter begins
Reset Configuration
counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter
Timer/Event Counter
is reloaded from the timer/event counter register and isTwo timer/event counters (TMR0, TMR1) are implemented sues an interrupt request, as in the other two modes, i.e.,
in the microcontroller. The Timer/Event counter 0 contains event and timer modes.
an 8-bit programmable count-up counter and the clock may
come from an external source or an internal clock source. To enable the counting operation, the Timer ON bit
An internal clock source comes from fSYS. The Timer/Event (T0ON; bit 4 of the TMR0C or T1ON; bit 4 of the TMR1C)
Counter 1 contains an 8-bit programmable count-up coun- should be set to ²1². In the pulse width measurement
ter and the clock may come from an external source or an mode, the T0ON/T1ON is automatically cleared after the
internal clock source. An internal clock source comes from measurement cycle is completed. But in the other two
system clock/4. The external clock input allows the user to modes, the T0ON/T1ON can only be reset by instructions.
count external events, measure time intervals or pulse The overflow of the Timer/Event Counter 0/1 is one of the
widths, or to generate an accurate time base.
wake-up sources and the Timer/Event Counter 0/1 can
Using the internal system clock, the timer/event counter is also be applied to a PFD (Programmable Frequency Dionly one reference time-base. The internal clock source vider) output at PA3 by options. Only one PFD (PFD0 or
comes from external events, measure time intervals or PFD1) can be applied to PA3 by options. No matter what
pulse widths, or generate an accurate time base. Using the operation mode is, writing a ²0² to ET0I or ET1I disthe internal clock allows the user to generate an accurate ables the related interrupt service. When the PFD function
time base.
is selected, executing ²SET [PA].3 instruction to enable
There are four registers related to the Timer/Event Coun- the PFD output and executing ²CLR [PA].3² instruction to
ter 0; TMR0 (0DH), TMR0C (0EH), the Timer/Event Coun- disable the PFD output.
O S C 1
ter 1; TMR1(10H), TMR1C (11H). Writing TMR0/TMR1
Rev. 1.00
14
November 1, 2005
HT46R14
fS
8 - s ta g e P r e s c a le r
Y S
f IN
8 -1 M U X
T
D a ta b u s
T 0 P S C 2 ~ T 0 P S C 0
(1 /1 ~ 1 /1 2 8 )
T 0 M 1
T 0 M 0
T M R 0
8 - b it T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T 0 E
T 0 M 1
T 0 M 0
T 0 O N
8 - b it T im e r /E v e n t
C o u n te r (T M R 0 )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
T o In te rru p t
P F D 0
Timer/Event Counter 0
fS
Y S
D a ta b u s
/4
T 1 M 1
T 1 M 0
T M R 1
8 - b it T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T 1 E
T 1 M 1
T 1 M 0
T 1 O N
8 - b it T im e r /E v e n t
C o u n te r (T M R 1 )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
T o In te rru p t
P F D 1
Timer/Event Counter 1
P F D 0
P F D 1
M
U
T
X
Q
P F D
P A 3 D a ta C T R L
P F D
S o u r c e O p tio n
PFD Source Option
lated timer/event counter, for proper operation since the
initial value of TMR0/TMR1 is unknown. Due to the
timer/event scheme, the programmer should pay special attention on the instruction to enable then disable
the timer for the first time, whenever there is a need to
use the timer/event function, to avoid unpredictable result. After this procedure, the timer/event function can
be operated normally.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the
timer/event counter is turn on, data written to the
timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs. When the
timer/event counter (reading TMR0/TMR1) is read, the
clock is blocked to avoid errors, as this may results in a
counting error. Blocking of the clock should be taken into
account by the programmer.
The bit0~bit2 of the TMR0C can be used to define the
pre-scaling stages of the internal clock sources of
timer/event counter. The definitions are as shown. The
overflow signal of timer/event counter can be used to
generate the PFD signal.
It is strongly recommended to load a desired value into
the TMR0/TMR1 register first, before turning on the re-
Rev. 1.00
15
November 1, 2005
HT46R14
Bit No.
0
1
2
Label
T0PSC0
T0PSC1
T0PSC2
3
T0E
4
T0ON
5
¾
6
7
T0M0
T0M1
Function
Define the prescaler stages, T0PSC2, T0PSC1, T0PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
Defines the TMR0 active edge of the timer/event counter:
In Event Counter Mode (T0M1,T0M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T0M1,T0M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enable/disable the timer counting
(0=disable; 1=enable)
Unused bit, read as ²0²
Define the operating mode (T0M1, T0M0)
01=Event count mode (External clock)
10=Timer mode (Internal clock)
11=Pulse Width measurement mode (External clock)
00=Unused
TMR0C (0EH) Register
Bit No.
Label
0~2
¾
3
T1E
4
T1ON
5
¾
6
7
T1M0
T1M1
Function
Unused bit, read as ²0²
Defines the TMR1 active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enable/disable timer counting
(0= disable; 1= enable)
Unused bit, read as ²0²
Define the operating mode (T1M1, T1M0)
01= Event count mode (External clock)
10= Timer mode (Internal clock)
11= Pulse Width measurement mode (External clock)
00= Unused
TMR1C (11H) Register
Rev. 1.00
16
November 1, 2005
HT46R14
Programmable Pulse Generator - PPG
timer counter preload register, and generates a signal to
stop the PPG timer. The software trigger bit (PxST) will
be cleared when the PPG timer overflow occurs.
This device provides two 8-bit PPG output channels. Each
PPG has a programmable period of 256´T, where ²T² can
be 1/fSYS, 2/fSYS, 4/fSYS, 8/fSYS, 16/fSYS, 32/fSYS, 64/fSYS,
128/fSYS for an output pulse width.
There are four registers related to the PPG output function, two control registers PPG0C and PPG1C and two
timer preload register PPGT0 and PPGT1. Two control
registers PPG0C and PPG1C define the PPG0 and
PPG1 input control mode (trigger source), enable or disable the comparators, define the PPG0 or PPG1 timer
prescaler rate, range form fSYS/1, fSYS/2, fSYS/4, fSYS/8,
fSYS/16, fSYS/32, fSYS/64, fSYS/128, enable or disable stopping the PPG0/PPG1 timer using PISP/INT0 triggered
input, enable or disable the restarting of the
PPG0/PPG1 timer using C1VO/PIRS triggered input,
and control the PPG0/PPG1 software trigger bit to trigger the PPG0/PPG1 timer On or Off. The PPGT0 is the
PPG0 preload register and PPGT1 is PPG1 preload
register, these two register contents decide the output
pulse width.
The PPG detects the falling edge of a trigger input, and
outputs a single pulse, the falling edge trigger may come
from comparator, INT0, INT1 or software trigger bit, which
can be selected by software. The PPG is capable of generating signals from 0.25ms to 8.192ms pulse width when
the system frequency is operating at 4MHz. The PPG can
set the polarity control bit (PxLEV) as active low or active
high output (by mask option). A ²00H² data write to the
PPGTx register yields a pulse width 256´T output.
· PPG functional description
The PPG module consists of PPG timers, a PPG Mode
Control, two comparators. The PPG timer consists of a
prescaler, one 8-bit up-counter timer, and an 8-bit
preload data register. The programmable pulse generator (PPG) starts counting at the current contents in the
preload register and ends at ²FFH®00H². Once an
overflow occurs, the counter is reloaded from the PPG
The PPG1 output is pin-shared with the PA0, the function is selected via configuration option. If not selected,
the pin can operate as a normal I/O pin, if the pin is selected as a PPG1 output pin, the I/O function is disabled
automatically.
IN T 1
IN T 0
C 0 IN T
D a ta b u s
P r e lo a d R e g is te r
C 1 V IN +
+
C 1 V O
P P G 0 T im e r O n /O ff
-
C 1 V IN -
O v e r flo w
P P G 0 T im e r
P C 3 /C 1 O U T
P P G 0 T im e r O ff
P C 1 /C 0 V IN +
+
P C 0 /C 0 V IN -
C 0 V O
M
-
IN T 1
P IS P
U
M
P C 2 /C 0 O U T
P 0 fs
U
X
P IR S
P 0 L E V ( O p tio n )
D a ta b u s
X
P r e lo a d R e g is te r
O v e r flo w
P P G 1 T im e r
U
X
P 0 P S C 2
P 0 P S C 1
P 0 P S C 0
P 1 fs
P 1 L E V ( O p tio n )
P P G 1 O u tp u t
P P G 1
C M P 0 E N
C M P 1 E N
Y S
U
P 0 S T
fS
M
P 1 S T
X
P P G 1 T im e r O ff
P 0 fs
P r e s c a le r
M
R e lo a d
P P G 1 T im e r O n /O ff
P IE
P 1 fs
P P G 0
P P G 0 O u tp u t
P P G M o d e
C o n tro l
IN T 0
P 1 P S C 2
P 1 P S C 1
P 1 P S C 0
R e lo a d
PPG Block Diagram
Rev. 1.00
17
November 1, 2005
HT46R14
· PPG0C control register
Bit No.
PPG0C (20H)
7
6
5
4
3
2
1
0
P0ST
P0RSEN
P0SPEN
P0PSC2
P0PSC1
P0PSC0
CMP1EN
CMP0EN
0
0
0
0
0
0
0
0
POR value
CMP0EN: Enables or disables the Comparator 0 (0=disable, 1=enable)
CMP1EN: Enables or disables the Comparator 1 (0=disable, 1=enable)
P0PSC2, P0PSC1, P0PSC0: These three bits select the PPG0 timer prescaler rate.
P0SPEN: Enables or disables the stopping of the PPG0 timer using PISP trigger input (0=disable, 1=enable)
P0RSEN: Enables or disables the restarting of the PPG0 timer using C1VO trigger input. (0=disable, 1=enable)
P0ST: PPG0 software trigger bit. (0=Stop PPG0, 1=Restart PPG0)
The CMP0EN and CMP1EN bits are used as the enable or disable bits, if the CMP0EN is cleared to ²0², the
Comparator 0 is disabled, the PC0/C0VIN-, PC1/C0VIN+, PC2/C0OUT are all GPIO pins, if the CMP0EN is set to
²1², the Comparator 0 is enabled, the PC0/C0VIN-, PC1/C0VIN+ are Comparator 0 input pins, PC2/C0OUT is a
Comparator 0 output pin, PC2 output and Pull-high resistor are disabled, PC2 can still be used as input pin, the status
of C0VO can be read by reading the PC2 register. If the CMP1EN is cleared to ²0², the Comparator 1 is disabled, the
PC3/C1OUT is a GPIO pin, If the CMP1EN is set to ²1², the Comparator 1 is enabled, PC3/C1OUT is a Comparator 1
output pin, PC3 output and PC3 Pull-high resistor are disabled, PC3 can still be used as input pin, the status of C1VO
can be read by reading the PC3 register.
PPG0C: CMP0EN, CMP1EN comparators enable/disable bits
CMP0EN
Description
0
Disable the Comparator 0. PC0/C0VIN-, PC1/C0VIN+, PC2/C0OUT are all GPIO pins.
1
Enable the Comparator 0, the PC0/C0VIN-, PC1/C0VIN+ are Comparator 0 input pins, PC2/C0OUT
is a Comparator 0 output pin, PC2 output disable, PC2 Pull-high resister disable.
CMP1EN
Description
0
Disable the Comparator 1. PC3/C1OUT is a PGIO pin.
1
Enable the Comparator 1. PC3/C1OUT is a Comparator 1 output pin, PC3 output disable, PC3
Pull-high resistor disable.
The bits 4~2 of the PPG0 control register (PPG0C) can be used to define the pre-scaling stages of the PPG0 timer
counter clock.
PPG0C: PPG0 timer prescaler rate bits
P0PSC2
P0PSC1
P0PSC0
0
0
0
P0fS=fSYS
0
0
1
P0fS=fSYS/2
0
1
0
P0fS=fSYS/4
0
1
1
P0fS=fSYS/8
1
0
0
P0fS=fSYS/16
1
0
1
P0fS=fSYS/32
1
1
0
P0fS=fSYS/64
1
1
1
P0fS=fSYS/128
Rev. 1.00
Define the prescaler stages
18
November 1, 2005
HT46R14
The P0SPEN is the PPG0 stopping enable or disable bit using PISP trigger input, if this bit is enabled, the PPG0 stopping input can be triggered by PISP falling edge. The PISP signal may come from C0VO, PC2 or INT1, determined by
PIE (bit0 of PPG1C). The P0RSEN is the PPG0 restarting enable or disable bit using C1VO triggered input, if this bit
is enabled, the PPG0 timer restarting input can be triggered by C1VO or PC3 falling edge. User can read the status of
C0VO or C1VO by setting the PC2 or PC3 to be an input pin when Comparator 0 or Comparator 1 is enabled.
P0SPEN
Description
0
Disable stopping the PPG0 timer using C0VO trigger input. PPG0 module output can be stopped by
software control (P0ST) only.
1
Enable stopping the PPG0 timer using PISP trigger input. PPG0 module output can be stopped by
PISP (C0VO or INT1) falling edge trigger or software control (P0ST bit is cleared to ²0²).
P0RSEN
Description
0
Disable restarting the PPG0 timer using C1VO trigger input. PPG0 module output can be restarted by
software control (P0ST) only.
1
Enable restarting the PPG0 timer using C1VO trigger input. PPG0 module output can be restarted by
C1VO falling edge trigger or software control (P0ST is set to ²1²)
The P0ST is a software trigger bit, if this bit is set to ²1², the PPG0 timer will start counting and this bit will be cleared
when the PPG0 timer overflow occurs or the PPG0 timer stop counting, if this bit is cleared to ²0², the PPG0 timer will
stop counting, when the PPG0 timer is counting and if a falling edge is generated from C1VO, PC3 or a software control bit (P0ST) is set, the PPG0 timer counter is not affected, the trigger from C1V0, PC3 or P0ST is not useful. The
P0ST can also be used as a status bit of the PPG0 timer output.
· PPG1C control register
Bit No.
PPG1C (22H)
POR value
7
6
5
4
3
2
1
0
P1ST
P1RSEN
P1SPEN
P1PSC2
P1PSC1
P1PSC0
¾
PIE
0
0
0
0
0
0
¾
0
PIE: PPG input exchange bit (0=disable, 1=enable).
¾: Undefined, cannot be used
P1PSC2, P1PSC1, P1PSC0: These three bits select the PPG1 timer prescaler rate.
P1SPEN: Enables or disables stopping the PPG1 timer using INT0 trigger input. (0=disable, 1=enable)
P1RSEN: Enables or disables restarting the PPG1 timer using PIRS trigger input. (0=disable, 1=enable)
P1ST: PPG1 software trigger bit. (0=Stop PPG1, 1=Restart PPG1)
The PIE bit is used as C0VO and INT1 exchange bit. When PIE bit is reset to ²0², the PISP signal comes from INT1
and the PIRS signal comes from C0VO. When PIE bit is set to ²1², the PISP signal comes from C0VO and the PIRS
signal comes from INT1.
The P1SPEN and P1RSEN should be disabled before setting the PIE bit.
PPG1C - PIE; C0VO and INT1 exchange bit
PIE
Description
0
PISP signal comes from INT1 and the PIRS signal comes form C0VO
1
PISP signal comes from C0VO and the PIRS signal comes from INT1.
Rev. 1.00
19
November 1, 2005
HT46R14
The bits 4~2 of the PPG1 control register (PPG1C) can be used to define the pre-scaling stages of the PPG1 timer
counter clock.
PPG1C: PPG1 timer prescaler rate bits
P1PSC2
P1PSC1
P1PSC0
To define the prescaler stages
0
0
0
P1fS=fSYS
0
0
1
P1fS=fSYS/2
0
1
0
P1fS=fSYS/4
0
1
1
P1fS=fSYS/8
1
0
0
P1fS=fSYS/16
1
0
1
P1fS=fSYS/32
1
1
0
P1fS=fSYS/64
1
1
1
P1fS=fSYS/128
The P1SPEN is the PPG1 timer Off enable or disable bit using INT0 trigger input, if this bit is enabled, the PPG1 stopping input can be triggered by INT0 falling edge. The P1RSEN is the PPG1 restarting enable or disable bit using trigger input, if this bit is enabled, the PPG1 timer restarting input can be triggered by PIRS falling edge. The PIRS signal
may come from C0VO, PC2 or INT1, determined by PIE (bit0 of the PPG1C). User can read the status of C0VO or
C1VO by setting the PC2 or PC3 as an input pin when Comparator 0 or Comparator 1 is enabled.
P1SPEN
Description
0
Disable stopping the PPG1 timer using INT0 trigger input. PPG1 module output can be stopped by
software control (P1ST) only.
1
Enable stopping the PPG0 timer using INT0 trigger input. PPG0 module output can be stopped by
INT0 falling edge trigger or software control (P1ST bit is cleared to ²0²).
P1RSEN
Description
0
Disable restarting the PPG1 timer using PIRS trigger input. PPG1 module output can be restarted by
software control (P1ST) only
1
Enable restarting the PPG1 timer using PIRS trigger input. PPG1 module output can be restarted by
PIRS (C0VO or INT1) falling edge trigger or software control (P1ST is set to ²1²)
The P1ST is a software trigger bit, if this bit is set to ²1², the PPG1 timer will start counting and this bit will be cleared
when the PPG1 timer overflow occurs or PPG1 timer stop counting, if this bit is cleared to ²0², the PPG1 timer will
stop counting, when the PPG timer is counting and if a falling edge is generated from PIRS or a software control bit
(P1ST) is set, the PPG1 timer counter is not affected, the trigger from PIRS or P1ST is not useful. The P1ST can also
be used as a status bit of PPG1 timer output.
Rev. 1.00
20
November 1, 2005
HT46R14
Input/Output Ports
There are 20 bidirectional input/output lines in the
microcontroller, labeled as PA, PB, PC, which are mapped
to the data memory of [12H], [14H] and [16H] respectively.
All of these I/O ports can be used for input and output operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2
rising edge of instruction ²MOV A,[m]² (m=12H, 14H or
16H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten.
Some instructions first input data and then follow the output operations. For example, ²SET [m].i², ²CLR [m].i²,
²CPL [m]², ²CPLA [m]² read the entire port states into the
CPU, execute the defined operations (bit-operation), and
then write the results back to the latches or the accumulator.
Each line of port A has the capability of waking-up the device. Each I/O port has a pull-high option. Once the
pull-high option is selected, the I/O port has a pull-high resistor, otherwise, there¢s none. Take note that a
Each I/O line has its own control register (PAC, PBC, non-pull-high I/O port operating in input mode will cause a
PCC) to control the input/output configuration. With this floating state.
control register, CMOS output or Schmitt trigger input with The PA0, PA3, PA4, PA5, PA6 and PA7 are pin-shared
or without pull-high resistor structures can be reconfig- with PPG1, PFD, TMR0, INT0, INT1 and TMR1 pins reured dynamically under software control. To function as an spectively. And the PC0, PC1, PC2 and PC3 are
input, the corresponding latch of the control register must pin-shared with C0VIN1-, C0VIN+, C0OUT, C1OUT.
write ²1². The input source also depends on the control
The PA3 is pin-shared with the PFD signal. If the PFD opregister. If the control register bit is ²1², the input will read
tion is selected, the output signal in output mode of PA3
the pad state. If the control register bit is ²0², the contents
will be the PFD signal generated by the timer/event counof the latches will move to the internal bus. The latter is
ter overflow signal. The input mode always remain in its
possible in the ²read-modify-write² instruction.
original functions. Once the PFD option is selected, the
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H, 15H
and 17H.
After a chip reset, these input/output lines remain at high
levels or floating state (depending on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H or
16H) instructions.
PFD output signal is controlled by PA3 data register only.
Writing a ²1² to PA3 data register will enable the PFD output function and writing ²0² will force the PA3 to remain at
²0².
V
C o n tr o l B it
D a ta B u s
W r ite C o n tr o l R e g is te r
Q
D
C K
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P U
P A
P A
P A
P A
P A
P A
P A
P B
P C
P C
P C
P C
Q
S
C h ip R e s e t
D a ta B it
Q
D
Q
C K
S
M
(P A 0 ) P A 3
(P P G 1 ) P F D
M
R e a d D a ta R e g is te r
S y s te m
U
0 fo
1 fo
0 fo
1 fo
r P
r P
r P
r P
A 5 O
A 6 O
A 4 O
A 7 O
U
0 /P
1 , P
3 /P
4 /T
5 /IN
6 /IN
7 /T
0 /A
0 /C
1 /C
2 /C
3 /C
P G
A 2
F D
M R
T 0
T 1
M R
N 0
1 V
1 V
1 O
2 O
1
0
1
~ P
IN
IN
U
U
T
+
-
B 7 /A N 7
T
X
E N
(P F D )
X
W a k e - u p ( P A o n ly )
IN T
IN T
T M R
T M R
D D
O P 0 ~ O P 7
n ly
n ly
n ly
n ly
Input/Output Ports
Rev. 1.00
21
November 1, 2005
HT46R14
A/D converter control register, which defines the A/D
channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. If
the users want to start an A/D conversion. Define PB
configuration, select the converted analog channel, and
give START bit a raising edge and falling edge
(0®1®0). At the end of A/D conversion, the EOCB bit is
cleared and an A/D converter interrupt occurs (if the A/D
converter interrupt is enabled). The ACSR is A/D clock
setting register, which is used to select the A/D clock
source.
The I/O functions of PA3 are shown below.
I/O
I/P
Mode (Normal)
Logical
Input
PA3
Note:
O/P
(Normal)
I/P
(PFD)
O/P
(PFD)
Logical
Output
Logical
Input
PFD
(Timer on)
The PFD frequency is the timer/event counter
overflow frequency divided by 2.
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There¢s a total of eight
channels to select. The bit5~bit3 of the ADCR are used
to set the PB configurations. PB can be an analog input
or as digital I/O line determined by these 3 bits. Once a
PB line is selected as an analog input, the I/O functions
and pull-high resistor of this I/O line are disabled and the
A/D converter circuit is powered on. The EOCB bit (bit6
of the ADCR) is end of A/D conversion flag. Check this
bit to know when A/D conversion is completed. The
START bit of the ADCR is used to begin the conversion
of the A/D converter. Giving START bit a rising edge and
falling edge means that the A/D conversion has started.
In order to ensure the A/D conversion is completed, the
START should remain at ²0² until the EOCB is cleared to
²0² (end of A/D conversion).
The PFD (PFD0 or PFD1) output shares pin with PA3,
as determined by options. When the PFD (PFD0 or
PFD1) option is selected, setting PA3 ²1² (²SET PA.3²)
will enable the PFD output and setting PA3 ²0² (²CLR
PA.3²) will disable the PFD output and PA3 output at low
level.
The definitions of PFD control signal and PFD output
frequency are listed in the following table.
Timer
PA3 Data PA3 Pad
Timer Preload
Register
State
Value
PFD
Frequency
OFF
X
0
0
X
OFF
X
1
U
X
ON
N
0
0
X
ON
N
1
PFD
fTMR/[2´(M-N)]
Note:
Bit 7 of the ACSR register is used for test purposes only
and must not be used for other purposes by the application program. Bit1 and bit0 of the ACSR register are
used to select the A/D clock source.
²X² stands for unused
²U² stands for unknown
²M² is ²256² for PFD
²N² is preload value for timer/event counter
²fTMR² is input clock frequency for timer/event
counter
When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to ²1²
when the START bit is set from ²0² to ²1².
Important Note for A/D initialization:
Special care must be taken to initialize the A/D converter each time the Port B A/D channel selection bits
are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialization is implemented
by setting the START bit high and then clearing it to zero
within 10 instruction cycles of the Port B channel selection bits being modified. Note that if the Port B channel
selection bits are all cleared to zero then an A/D initialization is not required.
A/D Converter
The 8 channels and 9-bit resolution A/D (8-bit accuracy)
converter are implemented in this microcontroller. The
reference voltage is VDD. The A/D converter contains
four special registers which are; ADRL (24H), ADRH
(25H), ADCR (26H) and ACSR (27H). The ADRH and
ADRL are A/D result register higher-order byte and
lower-order byte and are read-only. After the A/D conversion is completed, the ADRH and ADRL should be
read to get the conversion result data. The ADCR is an
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HT46R14
Bit No.
Label
Function
Selects the A/D converter clock source
00=system clock/2
ADCS0
01=system clock/8
ADCS1
10=system clock/32
11=undefined
0
1
2~6
¾
Unused bit, read as ²0²
7
TEST
For test mode used only
ACSR (27H) Register
Bit No.
Label
Function
0
1
2
ACS0
ACS1
ACS2
ACS2, ACS1, ACS0: Select A/D channel
0, 0, 0: AN0
0, 0, 1: AN1
0, 1, 0: AN2
0, 1, 1: AN3
1, 0, 0: AN4
1, 0, 1: AN5
1, 1, 0: AN6
1, 1, 1: AN7
3
4
5
PCR0
PCR1
PCR2
Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is
powered off to reduce power consumption
6
EOCB
Indicates end of A/D conversion. (0 = end of A/D conversion)
Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See ²Important note for A/D initialization².
7
START Starts the A/D conversion. (0®1®0= start; 0®1= Reset A/D converter and set EOCB to ²1²)
ADCR (26H) Register
Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ADRL (24H)
D0
¾
¾
¾
¾
¾
¾
¾
ADRH (25H)
D8
D7
D6
D5
D4
D3
D2
D1
Note:
D0~D8 is A/D conversion result data bit LSB~MSB.
ADRL (24H), ADRH (25H) Register
PCR2
PCR1
PCR0
7
6
5
4
3
2
1
0
0
0
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
0
0
1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
AN0
0
1
0
PB7
PB6
PB5
PB4
PB3
PB2
AN1
AN0
0
1
1
PB7
PB6
PB5
PB4
PB3
AN2
AN1
AN0
1
0
0
PB7
PB6
PB5
PB4
AN3
AN2
AN1
AN0
1
0
1
PB7
PB6
PB5
AN4
AN3
AN2
AN1
AN0
1
1
0
PB7
PB6
AN5
AN4
AN3
AN2
AN1
AN0
1
1
1
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Port B Configuration
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HT46R14
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
a,00100000B
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov
ADCR,a
; and select AN0 to be connected to the A/D converter
:
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
START
set
START
; reset A/D
clr
START
; start A/D
Polling_EOC:
sz
EOCB
; poll the ADCR register EOCB bit to detect end of A/D conversion
jmp
polling_EOC
; continue polling
mov
a,ADRH
; read conversion result high byte value from the ADRH register
mov
adrh_buffer,a
; save result to user defined memory
mov
a,ADRL
; read conversion result low byte value from the ADRL register
mov
adrl_buffer,a
; save result to user defined memory
:
:
jmp
start_conversion
; start next A/D conversion
Example: using interrupt method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
mov
a,00100000B
ADCR,a
:
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
START
set
START
clr
START
clr
ADF
set
EADI
set
EMI
:
:
:
; ADC interrupt service routine
ADC_ISR:
mov
acc_stack,a
mov
a,STATUS
mov
status_stack,a
:
:
mov
a,ADRH
mov
adrh_buffer,a
mov
a,ADRL
mov
adrl_buffer,a
clr
START
set
START
clr
START
:
:
EXIT_INT_ISR:
mov
a,status_stack
mov
STATUS,a
mov
a,acc_stack
reti
Rev. 1.00
; reset A/D
; start A/D
; clear ADC interrupt request flag
; enable ADC interrupt
; enable global interrupt
; save ACC to user defined memory
; save STATUS to user defined memory
; read conversion result high byte value from the ADRH register
; save result to user defined register
; read conversion result low byte value from the ADRL register
; save result to user defined register
; reset A/D
; start A/D
; restore STATUS from user defined memory
; restore ACC from user defined memory
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HT46R14
M in im u m
o n e in s tr u c tio n c y c le n e e d e d , M a x im u m
te n in s tr u c tio n c y c le s a llo w e d
S T A R T
E O C B
A /D
tA
P C R 2 ~
P C R 0
s a m p lin g tim e
A /D
tA
D C S
0 0 0 B
s a m p lin g tim e
A /D
tA
D C S
1 0 0 B
1 0 0 B
s a m p lin g tim e
D C S
1 0 1 B
0 0 0 B
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~
A C S 0
0 0 0 B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e P B c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
A /D
N o te :
A /D c lo c k m u s t b e fS
tA D C S = 3 2 tA D
tA D C = 7 6 tA D
Y S
/2 , fS
tA D C
c o n v e r s io n tim e
Y S
/8 o r fS
Y S
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
d o n 't c a r e
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
/3 2
A/D Conversion Timing
Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
V D D
5 .5 V
The microcontroller provides a low voltage reset circuit
in order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally.
O P R
5 .5 V
V
L V R
3 .0 V
The LVR includes the following specifications:
2 .2 V
· The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
0 .9 V
Note: VOPR is the voltage range for proper chip
operation at 4MHz system clock.
· The LVR uses the ²OR² function with the external RES
signal to perform chip reset.
V
V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
*1
R e s e t
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay,
the device enters the reset mode.
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HT46R14
Options
The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure having
a proper functioning system.
Options
OSC type selection.
This option is to determine whether an RC or crystal oscillator is chosen as system clock.
WDT clock source selection. WDT oscillator or fsys/4.
WDT enable/disable selection. WDT can be enabled or disabled by option.
WDT time-out period selection.
There are four types of selection: fS/213, fS/214, fS/215 and fS/216
CLRWDT times selection.
This option defines how to clear the WDT by instruction. ²One time² means that the CLR WDT instruction can clear
the WDT. ²Two times² means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, then
WDT can be cleared.
Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT.
Pull-high selection. This option is to determine whether a pull-high resistance is viable or not in the input mode of the
I/O ports. PA0~PA7, can be independently selected.
Pull-high selection. This option is to determine whether a pull-high resistance is viable or not in the input mode of the
I/O ports. PB0~PB7, can be independently selected.
This option is to determine whether a pull-high resistance is viable or not in the input mode of the I/O ports. PC0~PC3
byte option.
I/O pins share with other function selections.
PA0/PPG1: PA0 can be set as I/O pins or PPG1 output.
I/O pins share with other function selections.
PA3/PFD: PA3 can be set as I/O pins or PFD output.
PFD selection:
If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as
the PFD output. PFD0, PFD1 are generated by the timer overflow signals of the Timer/Event Counter 0, Timer/Event
Counter 1 respectively.
Low voltage reset selection.
Enable or disable the LVR function.
PPG0 output level selection; P0LEV.
This option is to determine the PPG0 output level. Active Low or Active High selection. Disable this bit to ²0², the
PPG0 output will be defined as an active high output, Enable this bit to ²1², the PPG0 output will be defined as an active low output.
PPG1 output level selection; P1LEV.
This option is to determine the PPG1 output level. Active Low or Active High selection. Disable this bit to ²0², the
PPG1 output will be defined as an active high output, Enable this bit to ²1², the PPG1 output will be defined as an active low output.
PPG0 timer start counting synchronized with clock; P0TSYN.
This option is to determine whether the PPG0 timer start counting is synchronized with input clock or not.
PPG1 timer start counting synchronized with clock; P1TSYN.
This option is to determine the PPG1 timer start counting is synchronized with input clock or not.
Rev. 1.00
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HT46R14
Application Circuits
V
D D
0 .0 1 m F *
P A 0 /P P
P A 2 , P
P A 3 /P
P A 4 /T M
P A 5 /IN
P A 6 /IN
P A 7 /T M
V D D
1 0 0 k W
0 .1 m F
R E S
1 0 k W
0 .1 m F *
V S S
V
D D
4 7 0 p F
R
P B 0 /A N 0
P B 7 /A N 7
O S C
O S C 1
fS
Y S
/4
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
O S C 2
~
O S C
C ir c u it
G 1
A 3
F D
R 0
T 0
T 1
R 1
P C
P C
P C
P C
O S C 1
O S C 2
S e e R ig h t S id e
0 /C
1 /C
2 /C
3 /C
0 V
0 V
0 O
1 O
IN
IN
U
U
C 1
O S C 1
+
C 2
T
R 1
T
H T 4 6 R 1 4
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
O S C 2
O S C C ir c u it
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)
C1, C2
R1
4MHz Crystal
Crystal or Resonator
0pF
10kW
4MHz Resonator
10pF
12kW
3.58MHz Crystal
0pF
10kW
3.58MHz Resonator
25pF
10kW
2MHz Crystal & Resonator
25pF
10kW
1MHz Crystal
35pF
27kW
480kHz Resonator
300pF
9.1kW
455kHz Resonator
300pF
10kW
429kHz Resonator
300pF
10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the
MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES to high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
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HT46R14
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.00
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HT46R14
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.00
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
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HT46R14
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
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HT46R14
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
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HT46R14
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
32
November 1, 2005
HT46R14
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
33
November 1, 2005
HT46R14
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
34
November 1, 2005
HT46R14
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
35
November 1, 2005
HT46R14
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
36
November 1, 2005
HT46R14
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
37
November 1, 2005
HT46R14
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
38
November 1, 2005
HT46R14
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
39
November 1, 2005
HT46R14
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
40
November 1, 2005
HT46R14
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
41
November 1, 2005
HT46R14
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
42
November 1, 2005
HT46R14
Package Information
28-pin SKDIP (300mil) Outline Dimensions
A
B
2 8
1 5
1
1 4
H
C
D
E
Symbol
Rev. 1.00
F
a
G
I
Dimensions in mil
Min.
Nom.
Max.
A
1375
¾
1395
B
278
¾
298
C
125
¾
135
D
125
¾
145
E
16
¾
20
F
50
¾
70
G
¾
100
¾
H
295
¾
315
I
330
¾
375
a
0°
¾
15°
43
November 1, 2005
HT46R14
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
Symbol
Rev. 1.00
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
697
¾
713
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
44
November 1, 2005
HT46R14
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1.0
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
Rev. 1.00
45
November 1, 2005
HT46R14
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 28W
Symbol
W
Description
Dimensions in mm
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.85±0.1
B0
Cavity Width
18.34±0.1
K0
Cavity Depth
2.97±0.1
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
Rev. 1.00
21.3
46
November 1, 2005
HT46R14
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031
Tel: 0755-8346-5589
Fax: 0755-8346-5590
ISDN: 0755-8346-5591
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
Holmate Semiconductor, Inc. (North America Sales Office)
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2005 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
47
November 1, 2005