TI1 ADS8319 Serial interface, micropower, miniature sar analog-to-digital converter Datasheet

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ADS8319
SLAS600B – MAY 2008 – REVISED DECEMBER 2015
ADS8319 16-Bit, 500-kSPS, Serial Interface, Micropower, Miniature,
SAR Analog-to-Digital Converter
1 Features
3 Description
•
•
•
•
•
The ADS8319 is a 16-bit, 500-kSPS, analog-to-digital
converter (ADC) that operates with a 2.25-V to 5.5-V
external reference. The device includes a capacitorbased, successive-approximation register (SAR) ADC
with inherent sample and hold.
1
•
•
•
•
•
500-kHz Sample Rate
16-Bit Resolution
Zero Latency at Full Speed
Unipolar, Single-Ended Input Range: 0 V to Vref
SPI™-Compatible Serial Interface with DaisyChain Option
Excellent Performance:
– 93.6-dB SNR (Typ) at 10-kHz Input
– –106-dB THD (Typ) at 10-kHz Input
– ±1.5-LSB (Max) INL
– ±1.0-LSB (Max) DNL
Low Power Dissipation: 18 mW (Typ) at 500 kSPS
Power Scales Linearly with Speed:
3.6 mW/100 kSPS
Power Dissipation During Power-Down State:
0.25 μW (Typ)
MSOP-10 and SON-10 Packages
2 Applications
•
•
•
•
•
The device includes a 50-MHz, SPI-compatible serial
interface. The interface is designed to support daisychaining or cascading of multiple devices.
Furthermore, a Busy Indicator makes synchronizing
with the digital host easy.
The device unipolar, single-ended input
supports an input swing of 0 V to +Vref.
Device operation is optimized for very-low power
operation and the power consumption directly scales
with speed. This feature makes the device attractive
for lower speed applications. The device is available
in MSOP-10 and SON-10 packages.
Device Information(1)
PART NUMBER
ADS8319
Battery-Powered Equipment
Data Acquisition Systems
Instrumentation and Process Controls
Medical Electronics
Optical Networking
range
PACKAGE
BODY SIZE (NOM)
VSSOP (10)
3.00 mm × 3.00 mm
SON (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
+VA
SAR
O/P
Drive
COMP
I/P
Shift
Reg
IN+
CDAC
+VBD
IN-
REFIN
Conversion and I/O
Control Logic
ADS8319
GND
SDO
SDI
SCLK
CONVST
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS8319
SLAS600B – MAY 2008 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configurations and Functions .......................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
4
4
6
6
Absolute Maximum Ratings ......................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Timing Requirements ................................................
7.5 Typical Characteristics .............................................. 8
8
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Feature Description................................................. 16
8.3 Device Functional Modes........................................ 19
9
Device and Documentation Support.................. 26
9.1
9.2
9.3
9.4
Community Resources............................................
Trademarks .............................................................
Electrostatic Discharge Caution ..............................
Glossary ..................................................................
26
26
26
26
10 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2013) to Revision B
Page
•
Added Feature Description section, Device Functional Modes section, Device and Documentation Support section,
and Mechanical, Packaging, and Orderable Information section ........................................................................................... 1
•
Deleted data from the Device Comparison Table this is repeated in the POA ..................................................................... 3
•
Changed External Reference Input, Vref parameter maximum specification ......................................................................... 5
•
Changed VDD to +VA in first sentence fo the Reference section ........................................................................................ 18
•
Changed Figure 51: added +VBD to device SDI connection .............................................................................................. 20
•
Changed Figure 57: changed device number for device blocks ......................................................................................... 24
•
Changed Figure 58: changed SDO #2 trace ....................................................................................................................... 24
•
Changed Figure 59: changed device number for device blocks ......................................................................................... 25
•
Changed Figure 60: changed SDO #2 trace ....................................................................................................................... 25
Changes from Original (May 2008) to Revision A
Page
•
Changed CBC to CEN in Ordering Information...................................................................................................................... 3
•
Changed CBE to CEP in Ordering Information ...................................................................................................................... 3
2
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SLAS600B – MAY 2008 – REVISED DECEMBER 2015
5 Device Comparison Table
DEVICE
MAXIMUM INTEGRAL
LINEARITY (LSB)
MAXIMUM DIFFERENTIAL
LINEARITY (LSB)
NO MISSING CODES AT
RESOLUTION (Bits)
ADS8319I
±2.5
+1.5, –1
16
ADS8319IB
±1.5
±1.0
16
6 Pin Configurations and Functions
DGS Package
10-Pin MSOP
Top View
REFIN
+VA
IN+
INGND
1
10
2
9
3
8
4
7
5
6
DRC Package
10-Pin SON
Top View
+VBD
SDI
SCLK
SDO
CONVST
REFIN
+VA
IN+
INGND
1
10
2
9
3
8
4
7
5
6
+VBD
SDI
SCLK
SDO
CONVST
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
REFIN
2
+VA
Power
3
+IN
Analog input
Noninverting analog signal input
4
–IN
Analog input
Inverting analog signal input. Note that this input has a limited range of ±0.1 V and is
typically grounded at the input decoupling capacitor.
5
GND
Power
6
CONVST
Input
7
SDO
Output
8
SCLK
Input
Serial I/O clock input. Data (on the SDO output are synchronized with this clock.
9
SDI
Input
Serial data input. The SDI level at the start of a conversion selects the mode of operation
(such as CS or daisy-chain mode). This pin also serves as the CS input in 4-wire interface
mode. See the Description and Timing Requirements sections for more details.
10
+VBD
Power
Analog input
Reference (positive) input. Decouple to GND with a 0.1-μF bypass capacitor and a 10-μF
storage capacitor.
Analog power supply. Decouple to GND.
Device ground. Note that this pin is a common ground for both analog power supply (+VA)
and digital I/O supply (+VBD).
Convert input. CONVST also functions as the CS input in 3-wire interface mode. See the
Description and Timing Requirements sections for more details.
Serial data output
Digital I/O power supply. Decouple to GND.
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ADS8319
SLAS600B – MAY 2008 – REVISED DECEMBER 2015
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range, unless otherwise noted. (1)
+IN
MAX
UNIT
+VA + 0.3
V
±130
mA
–0.3
–IN
TA
MIN
–0.3
–0.3
7
V
–0.3
7
V
Digital input voltage to GND
–0.3
+VBD + 0.3
V
Digital output to GND
–0.3
+VBD + 0.3
V
Operating free-air temperature range
–40
+85
°C
+150
°C
Power dissipation
(TJ max – TA) / θJA
θJA thermal impedance
Maximum MSOP reflow temperature (2)
Power dissipation
SON package
θJA thermal impedance
Storage temperature
°C
+180
°C/W
+260
°C
(TJ max – TA) / θJA
Maximum SON reflow temperature (2)
(2)
mA
+VBD to BDGND
MSOP package
(1)
V
±130
+VA to AGND
Junction temperature (TJ max)
Tstg
0.3
–65
°C
+70
°C/W
+260
°C
+150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The device is rated to MSL2 260°C, as per the JSTD-020 specification.
7.2 Electrical Characteristics
TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V to 2.375 V, Vref = 4 V, and fSAMPLE = 500 kHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input span (1)
Operating input range
+IN – (–IN)
0
Vref
+IN
–0.1
Vref + 0.1
–IN
–0.1
0.1
Input capacitance
Input leakage current
During acquisition
V
V
59
pF
1000
pA
16
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
16
Bits
ADS8319I
–2.5
±1.2
2.5
ADS8319IB
–1.5
±1
1.5
–1
±0.65
1.5
–1
±0.5
1
INL
Integral linearity (2)
DNL
Differential linearity
EO
Offset error (4)
EG
Gain error
CMRR
Common-mode rejection ratio
With common-mode input signal = 200 mVPP at
500 kHz
78
dB
PSRR
Power-supply rejection ratio
At FFF0h output code
80
dB
0.5
LSB
ADS8319I
ADS8319IB
At 16-bit level
Transition noise
(1)
(2)
(3)
(4)
4
LSB (3)
LSB
–1.5
±0.3
1.5
mV
–0.03
±0.0045
0.03
%FSR
Ideal input span, does not include gain or offset error.
This parameter is endpoint INL, not best fit.
LSB means least significant bit.
Measured relative to actual measured reference.
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Electrical Characteristics (continued)
TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V to 2.375 V, Vref = 4 V, and fSAMPLE = 500 kHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SAMPLING DYNAMICS
tCONV
Conversion time
Acquisition time
+VBD = 5 V
1400
+VBD = 3 V
1400
+VBD = 5 V
600
+VBD = 3 V
600
ns
Maximum throughput rate with or
without latency
0.5
Aperture delay
Aperture jitter, RMS
Step response
Settling to 16-bit accuracy
Overvoltage recovery
ns
MHz
2.5
ns
6
ps
600
ns
600
ns
DYNAMIC CHARACTERISTICS
Total harmonic distortion (5)
THD
ADS8319IB
SNR
Signal-to-noise ratio
SINAD
SFDR
Signal-to-noise + distortion
Spurious-free dynamic range
VIN 0.4 dB below FS at 1 kHz, Vref = 5 V
–111
VIN 0.4 dB below FS at 10 kHz, Vref = 5 V
–106
VIN 0.4 dB below FS at 100 kHz, Vref = 5 V
–89
VIN 0.4 dB below FS at 1 kHz, Vref = 5 V
dB
92
VIN 0.4 dB below FS at 1 kHz, Vref = 5 V
93.9
VIN 0.4 dB below FS at 10 kHz, Vref = 5 V
93.6
VIN 0.4 dB below FS at 100 kHz, Vref = 5 V
92.2
VIN 0.4 dB below FS at 1 kHz, Vref = 5 V
93.8
VIN 0.4 dB below FS at 10 kHz, Vref = 5 V
93.4
VIN 0.4 dB below FS at 100 kHz, Vref = 5 V
87.4
VIN 0.4 dB below FS at 1 kHz, Vref = 5 V
113
VIN 0.4 dB below FS at 10 kHz, Vref = 5 V
107
VIN 0.4 dB below FS at 100 kHz, Vref = 5 V
90
–3-dB small-signal bandwidth
dB
dB
dB
15
MHz
EXTERNAL REFERENCE INPUT
Vref
Input range
2.25
Reference input current (6)
During conversion
4.096
+VA + 0.1
V
μA
250
POWER SUPPLY REQUIREMENTS
Power-supply
voltage
+VBD
Supply current
+VA
+VA
2.375
3.3
5.5
4.5
5
5.5
V
500-kHz sample rate
3.6
4.5
mA
PVA
Power dissipation
+VA = 5 V, 500-kHz sample rate
18
22.5
mW
IVApd
Device power-down current (7)
+VA = 5 V
50
300
nA
LOGIC FAMILY CMOS
VIH
IIH = 5 μA
+(0.7 × VBD)
+VBD + 0.3
VIL
IIL = 5 μA
–0.3
+(0.3 × VBD)
IOH = 2 TTL loads
+VBD – 0.3
+VBD
IOL = 2 TTL loads
0
0.4
–40
+85
VOH
Logic level
VOL
V
TEMPERATURE RANGE
TA
(5)
(6)
(7)
Operating free-air temperature
°C
Calculated on the first nine harmonics of the input frequency.
Can vary by ±20%.
The device automatically enters a power-down state at the end of every conversion and remains in a power-down state during the
acquisition phase.
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SLAS600B – MAY 2008 – REVISED DECEMBER 2015
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7.3 Timing Requirements
All specifications are typical at –40°C to 85°C, +VA = 5 V, and +VBD ≥ 4.5 V, unless otherwise noted.
REF FIGURE
MIN
TYP
MAX
UNIT
SAMPLING AND CONVERSION RELATED
tacq
Acquisition time
tcnv
Conversion time
tcyc
Time between conversions
t1
Pulse duration, CONVST high
t6
Pulse duration, CONVST low
600
ns
Figure 50, Figure 52, Figure 53,
Figure 55
1400
ns
2000
ns
Figure 50, Figure 52
10
ns
Figure 53, Figure 55, Figure 58
20
ns
20
ns
9
ns
9
ns
I/O RELATED
tclk
SCLK period
tclkl
SCLK low time
tclkh
SCLK high time
t2
SCLK falling edge to data remains valid
t3
SCLK falling edge to next data valid delay
ten
Enable time, CONVST or SDI low to MSB valid
tdis
Disable time, CONVST or SDI high or last SCLK falling edge
to SDO 3-state (CS mode)
t4
Setup time, SDI valid to CONVST rising edge
t5
Hold time, SDI valid from CONVST rising edge
t7
Setup time, SCLK valid to CONVST rising edge
t8
Hold time, SCLK valid from CONVST rising edge
Figure 50, Figure 52, Figure 53,
Figure 55, Figure 58, Figure 60
5
ns
16
ns
Figure 50, Figure 53
15
ns
Figure 50, Figure 52, Figure 53,
Figure 55
12
ns
Figure 53, Figure 55
Figure 58
5
ns
5
ns
5
ns
5
ns
7.4 Timing Requirements
All specifications are typical at –40°C to 85°C, +VA = 5 V, and +4.5 V > +VBD ≥ 2.375 V, unless otherwise noted.
REF FIGURE
MIN
TYP
MAX
UNIT
SAMPLING AND CONVERSION RELATED
tacq
Acquisition time
tcnv
Conversion time
600
tcyc
Time between conversions
2000
ns
t1
Pulse width CONVST high
Figure 50, Figure 52
10
ns
t6
Pulse width CONVST low
Figure 53, Figure 55, Figure 58
20
ns
Figure 50, Figure 52, Figure 53,
Figure 55
ns
1400
ns
I/O RELATED
tclk
SCLK period
30
ns
tclkl
SCLK low time
13
ns
tclkh
SCLK high time
13
ns
t2
SCLK falling edge to data remains valid
t3
SCLK falling edge to next data valid delay
ten
CONVST or SDI low to MSB valid
tdis
CONVST or SDI high or last SCLK falling edge to SDO 3state (CS mode)
t4
SDI valid setup time to CONVST rising edge
t5
SDI valid hold time from CONVST rising edge
t7
SCLK valid setup time to CONVST rising edge
t8
SCLK valid hold time from CONVST rising edge
6
Figure 50, Figure 52, Figure 53,
Figure 55, Figure 58, Figure 60
5
ns
24
ns
Figure 50, Figure 53
22
ns
Figure 50, Figure 52, Figure 53,
Figure 55
15
ns
Figure 53, Figure 55
Figure 58
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5
ns
5
ns
5
ns
5
ns
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SLAS600B – MAY 2008 – REVISED DECEMBER 2015
500µA
I ol
From
SDO
1.4V
20pF
500µA
I oh
Figure 1. Load Circuit For Digital Interface Timing
0.7 VBD
0.3 VBD
t DELAY
tDELAY
2V
2V
0.8V
0.8V
Figure 2. Voltage Levels For Timing
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SLAS600B – MAY 2008 – REVISED DECEMBER 2015
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7.5 Typical Characteristics
0.005
-0.2
0.0045
-0.25
0.004
Gain Error - %FSR
Offset Error - mV
-0.3
-0.35
-0.4
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
TA = 30°C
-0.45
-0.5
4.5
4.75
5
5.25
0.0035
0.003
0.0025
0.002
0.0015
0.0005
0
4.5
5.5
4.75
5.5
0.0045
0
+VBD = 2.7 V,
+VA = 5 V,
fs = 500 KSPS,
TA = 30°C
-0.1
0.004
0.0035
Gain Error - %FSR
-0.05
-0.15
-0.2
-0.25
0.003
0.0025
0.002
0.0015
+VBD = 2.7 V,
+VA = 5 V,
fs = 500 KSPS,
TA = 30°C
0.001
-0.3
0.0005
0
-0.35
2
2.5
3
3.5
4
4.5
Vref - Reference Voltage - V
2
5
0
-0.1
-0.2
5
0.01
+VA = 5 V,
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS
0.009
0.008
Gain Error - %FSR
-0.3
-0.4
-0.5
-0.6
-0.7
0.007
0.005
0.004
0.003
0.002
-0.9
0.001
-25 -10
5
20
35
50
65
0
-40 -25 -10 5
20
35 50 65
TA - Free-Air Temperature - °C
80
TA - Free-Air Temperature - °C
Figure 7. Offset Error vs Free-Air Temperature
+VA = 5 V,
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS
0.006
-0.8
-1
-40
2.5
3
3.5
4
4.5
Vref - Reference Voltage - V
Figure 6. Gain Error vs Reference Voltage
Figure 5. Offset Error vs Reference Voltage
Offset Error - mV
5.25
Figure 4. Gain Error vs Supply Voltage
Figure 3. Offset Error vs Supply Voltage
8
5
+VA - Supply Voltage - V
+VA - Supply Voltage - V
Offset Error - mV
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
TA = 30°C
0.001
80
Figure 8. Gain Error vs Free-Air Temperature
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Typical Characteristics (continued)
25
14
+VA = 5 V,
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS
10
8
6
4
3
3
20
15
10
5
5
5
1
2
0
0
0
0
0
1
0
0
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
TA = 30°C
0.6
0
0
0
0
0
Figure 10. Offset Error Drift Histogram
1.5
INL - Integral Nonlinearity LSBs
1
0
-0.5 -0.4 -0.3-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
ppm/°C
Figure 9. Gain Error Drift Histogram
0.8
0
0
-0.5 -0.4-0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
ppm/°C
DNL - Differential Nonlinearity - LSBs
+VA = 5 V
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS
20
Number of Devices
Number of Devices
12
12 12
DNLMAX
0.4
0.2
0
-0.2
DNLMIN
-0.4
-0.6
INLMAX
1
0.5
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
TA = 30°C
0
-0.5
INLMIN
-1
-0.8
-1
4.5
4.75
5
5.25
+VA - Supply Voltage - V
-1.5
4.5
5.5
5
5.25
5.5
+VA - Supply Voltage - V
Figure 11. Differential Nonlinearity vs Supply Voltage
Figure 12. Integral Nonlinearity vs Supply Voltage
1.5
1
0.8
INL - Integral Nonlinearity LSBs
DNL - Differential Nonlinearity LSBs
4.75
DNLMAX
0.6
0.4
+VA = 5 V,
+VBD = 2.7 V,
fs = 500 KSPS,
TA = 30°C
0.2
0
-0.2
DNLMIN
-0.4
-0.6
INLMAX
1
0.5
+VA = 5 V,
+VBD = 2.7 V,
fs = 500 KSPS,
TA = 30°C
0
-0.5
INLMIN
-1
-0.8
-1.5
-1
2
2.5
3
3.5
4
4.5
Vref - Reference Voltage - V
2
5
Figure 13. Differential Nonlinearity vs Reference Voltage
2.5
3
3.5
4
4.5
Vref - Reference Voltage - V
5
Figure 14. Integral Nonlinearity vs Reference Voltage
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1
1
0.8
0.8
0.6
INL - Integral Nonlinearity - LSBs
INL - Integral Nonlinearity LSBs
Typical Characteristics (continued)
DNLMAX
0.4
0.2
0
-0.2
DNLMIN
-0.4
+VA = 5 V
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS
-0.6
-0.8
-1
-40
-25 -10 5
20 35 50 65
TA - Free-Air Temperature - °C
80
15.6
15.5
15.4
15.3
15.2
15.1
4.75
5
5.25
+VA - Supply Voltage - V
INLMIN
-25
-10
5
20 35
50 65
TA - Free-Air Temperature - °C
80
+VA = 5 V,
+VBD = 2.7 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
15.8
15.6
15.4
15.2
15
14.8
14.6
14.4
14.2
15.6
15.5
15.4
15.3
15.2
15.1
-10
5
20 35
50 65
TA - Free-Air Temperature - °C
2
2.5
3
3.5
4
4.5
5
Figure 18. Effective Number of Bits vs Reference Voltage
SFDR - Spurious Free Dynamic Range - dB
ENOB - Effective Number Of Bits - LSBs
+VA = 5 V,
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS,
fi = 1.9 kHz
15
-40 -25
80
Figure 19. Effective Number of Bits vs Free-Air Temperature
10
-0.8
Vref - Reference Voltage - V
16
15.7
-0.6
5.5
Figure 17. Effective Number of Bits vs Supply Voltage
15.8
-0.4
14
15
4.5
15.9
0
-0.2
16
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
ENOB - Effective Number Of Bits - LSBs
ENOB - Effective Number Of Bits - LSBs
15.7
+VA = 5 V
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS
0.2
Figure 16. Integral Nonlinearity vs Free-Air Temperature
16
15.8
0.6
0.4
-1
-40
Figure 15. Differential Nonlinearity vs Free-Air Temperature
15.9
INLMAX
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
119
117
115
113
111
109
107
105
4.5
4.75
5
5.25
+VA - Supply Voltage - V
5.5
Figure 20. Spurious-Free Dynamic Range vs Supply Voltage
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Typical Characteristics (continued)
94.5
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
94
SNR - Signal-to-Noise Ratio - dB
SINAD - Signal-to-Noise and Distortion - dB
94.5
93.5
93
92.5
92
4.5
4.75
5
5.25
+VA - Supply Voltage - V
115
113
111
109
107
105
4.5
4.75
5
5.25
+VA - Supply Voltage - V
92
4.5
117
113
111
109
107
105
2
95
SNR - Signal-to-Noise Ratio - dB
93
92.5
92
91.5
91
2.5
3
3.5
4
4.5
Vref - Reference Voltage - V
5
Figure 24. Spurious-Free Dynamic Range vs Reference
Voltage
94.5
93.5
5.5
+VA = 5 V,
+VBD = 2.7 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
115
95
+VA = 5 V,
+VBD = 2.7 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
4.75
5
5.25
+VA - Supply Voltage - V
Figure 22. Signal-to-Noise Ratio vs Supply Voltage
94.5
94
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
92.5
5.5
Figure 23. Total Harmonic Distortion vs Supply Voltage
SINAD - Signal-to-Noise + Distortion - dB
93
SFDR - Spurious Free Dynamic Range - dB
THD - Total Harmonic Distortion - dB
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
117
93.5
5.5
Figure 21. Signal-to-Noise + Distortion vs Supply Voltage
119
94
94
93.5
93
+VA = 5 V,
+VBD = 2.7 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
92.5
92
91.5
91
90.5
90.5
90
2
2.5
3
3.5
4
4.5
90
2
5
2.5
3
3.5
4
4.5
Vref - Reference Voltage - V
5
Vref - Reference Voltage - V
Figure 25. Signal-to-Noise + Distortion vs Reference Voltage
Figure 26. Signal-to-Noise Ratio vs Reference Voltage
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THD - Total Harmonic Distortion - dB
117
115
113
SFDR - Spurious Free Dynamic Range - dB
Typical Characteristics (continued)
+VA = 5 V,
+VBD = 2.7 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
111
109
107
105
2
2.5
3
3.5
4
4.5
Vref - Reference Voltage - V
5
Figure 27. Total Harmonic Distortion vs Reference Voltage
SNR - Signal-to-Noise Ratio - dB
SINAD - Signal-to-noise + Distortion - dB
113
SFDR
111
109
107
105
103
-40
SINAD
93
+VA = 5 V,
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS,
fi = 1.9 kHz
92
91
-25
-10
5
20
35
50
65
94
93
92
91
SINAD - Signal-To-Noise + Distortion - dB
THD - Total Harmonic Distortion
-10
5
20 35 50 65
TA - Free-Air Temperature - °C
80
95
+VA = 5 V,
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS,
fi = 1.9 kHz
111
THD
109
107
105
-25
-10
5
20 35 50 65
TA - Free-Air Temperature - °C
80
Figure 31. Total Harmonic Distortion vs Free-Air
Temperature
12
-25
Figure 30. Signal-to-Noise Ratio vs Free-Air Temperature
117
103
-40
+VA = 5 V,
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS,
fi = 1.9 kHz
90
-40
80
Figure 29. Signal-to-Noise + Distortion vs Free-Air
Temperature
113
80
SNR
95
TA - Free-Air Temperature - °C
115
-25 -10
5
20 35 50 65
TA - Free-Air Temperature - °C
96
94
90
-40
+VA = 5 V,
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS,
fi = 1.9 kHz
115
Figure 28. Spurious-Free Dynamic Range vs Free-Air
Temperature
96
95
117
94
SINAD @ -10 dB
93
92
91
SINAD @ -0.5 dB
90
89
88
87
1
+VA = 5 V
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS,
TA = 30°C
10
fi - Signal Input Frequency - kHz
100
Figure 32. Signal-to-Noise + Distortion vs Signal Input
Frequency
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Typical Characteristics (continued)
300000
+VA = 5 V,
+VBD = 2.7 V,
250000 Vref = 5 V,
fs = 500 KSPS,
T = 30°C
200000 A
+VA = 5 V
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS,
TA = 30°C
125
115
Hits
THD - Total Harmonic Distortion - dB
135
THD @ -0.5 dB
105
150000
100000
95
THD @ -10 dB
85
50000
75
0
1
10
fi - Signal Input Frequency - kHz
100
Figure 33. Total Harmonic Distortion vs Signal Input
Frequency
101
32765
0
32766
Codes
32767
Figure 34. Dc Histogram of ADC Close to Center Code
3.85
114
0 pF
3.8
112
110
Iavdd - Supply Current - mA
THD - Total Harmonic Distortion - dB
262043
680 pF
100 pF
108
+VA = 5V, +VBD = 2.7 V,
Vref = 5 V, fi = 1.9 kHz,
fs = 500 KSPS, TA = 30°C
106
104
3.75
3.7
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
TA = 30°C
3.65
3.6
3.55
3.5
3.45
102
3.4
100
0
100
200
300
400
500
3.35
4.5
600
Source Resistance - W
4.75
5
5.25
+VA - Supply Voltage - V
Figure 35. Total Harmonic Distortion vs Source Resistance
Figure 36. Supply Current vs Supply Voltage
3.9
3.7
4000
3500
+VA = 5 V
+VBD = 2.7 V,
fs = 500 KSPS
Iavdd - Supply Current - mA
Iavdd - Supply Current - mA
3.8
3.6
3.5
3.4
3.3
3.2
3000
+VA = 5 V,
+VBD = 2.7 V,
TA = 30°C
2500
2000
1500
1000
500
3.1
3.0
-40
5.5
-25 -10 5
20 35 50 65
TA - Free-Air Temperature - °C
0
0
80
Figure 37. Supply Current vs Free-Air Temperature
100
200
300
400
fs - sampling frequency - kSPS
500
Figure 38. Supply Current vs Sampling Frequency
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Typical Characteristics (continued)
200
+VA = 5 V,
+VBD = 2.7 V,
Vref = 5 V,
TA = 30°C
18
16
Iavdd-pd - Powerdown Current - nA
Iavdd*VA - Power Dissipation - mW
20
14
12
10
8
6
4
2
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 0.0 KSPS,
TA = 30°C
180
160
140
120
100
80
60
40
20
0
4.5
0
0
100
200
300
400
fs - sampling frequency - kSPS
500
Figure 39. Power Dissipation vs Sampling Frequency
5
+VA - Supply Voltage - V
5.5
Figure 40. Power-Down Current vs Supply Voltage
500
Iavdd-PD - Powerdown Current - nA
450
400
350
+VA = 5 V
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 0.0 KSPS
300
250
200
150
100
50
0
-40
-25
-10 5
20 35
50 65
TA - Free-Air Temperature - °C
80
Figure 41. Power-Down Current vs Free-Air Temperature
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Typical Characteristics (continued)
INL
+VA = 5 V, +VBD = 2.7 V,
Vref = 5 V, fs = 500 KSPS,
TA = 30°C
INL - LSB
DNL - LSB
DNL
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
10000
20000
30000
Codes
40000
50000
1
0.8
0.6
0.4
0.2
+VA = 5 V, +VBD = 2.7 V,
Vref = 5 V, fs = 500 KSPS,
TA = 30°C
0
-0.2
-0.4
-0.6
-0.8
-1
0
60000
10000
20000
30000
40000
50000
60000
Codes
Figure 42. DNL
Figure 43. INL
Amplitude - dB
FFT
0
-20
-40
-60
-80
+VA = 5 V, +VBD = 2.7 V,
Vref = 5 V, fi = 1.9 kHz,
fs = 500 KSPS, TA = 30°C
-100
-120
-140
-160
-180
-200
0
50000
100000
150000
200000
250000
f - Frequency - Hz
Figure 44. FFT
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8 Detailed Description
8.1 Overview
The ADS8319 is a high-speed, low power, successive approximation register (SAR) analog-to-digital converter
(ADC) that uses an external reference. The architecture is based on charge redistribution, which inherently
includes a sample/hold function.
The ADS8319 is a single channel device. The analog input is provided to two input pins: +IN and -IN where -IN is
a pseudo differential input and it has a limited range of ±0.1 V. When a conversion is initiated, the differential
input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both +IN and IN inputs are disconnected from any internal function.
The ADS8319 has an internal clock that is used to run the conversion, and hence the conversion requires a fixed
amount of time. After a conversion is completed, the device reconnects the sampling capacitors to the +IN and
–IN pins, and the device is in the acquisition phase. During this phase the device is powered down and
conversion data can be read.
The device digital output is available in SPI compatible format. It easily interfaces with microprocessors, DSPs, or
FPGAs.
This is a low pin count device; however, it offers six different options for the interface. They can be grossly
classified as CS mode (3- or 4-wire interface) and daisy chain mode. In both modes it can either be with or
without a busy indicator, where the busy indicator is a bit preceeding the 16-bit serial data.
The 3-wire interface CS mode is useful for applications which need galvanic isolation on-board, where as 4-wire
interface CS mode makes it easy to control an individual device while having multiple devices on-board. The
daisy chain mode is provided to hook multiple devices in a chain like a shift register and is useful to reduce
component count and the number of signal traces on the board.
8.2 Feature Description
8.2.1 Analog Input
When the converter samples the input, the voltage difference between the +IN and -IN inputs is captured on the
internal capacitor array. The voltage on the +IN is limited between GND –0.1 V and Vref + 0.1 V and on -IN is
limited between GND-0.1 to GND+0.1V; where as the differential signal range is [(+IN) – (–IN)]. This allows the
input to reject small signals which are common to both the +IN and –IN inputs.
Device in Hold Mode
218 W
+IN
55 pF
4 pF
+VA
4 pF
AGND
218 W
-IN
55 pF
Figure 45. Input Equivalent Circuit
The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input
voltage, and source impedance. The current into the ADS8319 charges the internal capacitor array during the
sample period. After this capacitance has been fully charged, there is no further input current. The source of the
analog input voltage must be able to charge the input capacitance (59 pF) to a 18-bit settling level within the
minimum acquisition time. When the converter goes into hold mode, the input impedance is greater than 1 GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN
and -IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, converter
linearity may not meet specifications.
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Feature Description (continued)
Care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are
matched. If this is not observed, the two inputs could have different settling times. This may result in an offset
error, gain error, and linearity error which change with temperature and input voltage. Typically the -IN input is
grounded at the input decoupling capacitor.
8.2.2 Driver Amplifier Choice
The analog input to the converter needs to be driven with a low noise, op-amp like the THS4031, OPA211. An
RC filter is recommended at the input pins to low-pass filter the noise from the source. A resistor of 5Ω and a
capacitor of 1nF is recommended. The input to the converter is a unipolar input voltage in the range 0 V to Vref.
The minimum –3dB bandwidth of the driving operational amplifier can be calculated as:
f3db = (ln(2) × (n+2))/(2π × tACQ)
where n is equal to 16, the resolution of the ADC (in the case of the ADS8319). When tACQ = 600 ns (minimum
acquisition time), the minimum bandwidth of the driving circuit is ~3 MHz (including RC following the driver OPA).
The bandwidth can be relaxed if the acquisition time is increased by the application.
Typically a low noise OPA with ten times or higher bandwidth is selected. The driving circuit bandwidth is
adjusted (to the required value) with a RC following the OPA. The OPA211 or THS4031 from Texas Instruments
is recommended for driving high-resolution high-speed ADCs.
8.2.3 Driver Amplifier Configurations
It is better to use a unity gain, noninverting buffer configuration. As explained before a RC following the OPA
limits the input circuit bandwidth just enough for 16-bit settling. Note higher bandwidth reduces the settling time
(beyond what is needed) but increases the noise in the ADC sampled signal, and hence the ADC output.
0-Vref
+VA
+
THS4031
or OPA211
ADS8319
5W
+IN
1nF
50 W
-IN
5W
Figure 46. Input Drive Configuration
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Feature Description (continued)
8.2.4 Reference
The ADS8319 can operate with an external reference with a range from 2.25 V to +VA + 0.1 V. A clean, low
noise, well-decoupled reference voltage on this pin is required to ensure good performance of the converter. A
low noise band-gap reference like the REF5040, REF5050 can be used to drive this pin. A ceramic decoupling
capacitor is required between the REF+ and GND pins of the converter, as shown in Figure 47. The capacitor
should be placed as close as possible to the pins of the device.
50 W
REF5050
+
OUT
+
-
47 mF,
1.5 W ESR
(High ESR)
10 mF
OPA365
REFIN
TRIM
+
-
IN +
4.7 mF,
Low ESR
ADS8319
IN -
Figure 47. External Reference Driving Circuit
REF5050
OUT
+
-
22 mF
47 mF,
1.5 W ESR
(High ESR)
REFIN
TRIM
+
-
4.7 mF,
Low ESR
IN +
ADS8319
IN -
Figure 48. Direct External Reference Driving Circuit
8.2.5 Power Saving
The ADS8319 has an auto power-down feature. The device powers down at the end of every conversion. The
input signal is acquired on sampling capacitors while the device is in the power-down state, and at the same time
the conversion results are available for reading. The device powers up by itself on the start of the conversion. As
discussed before, the conversion runs on an internal clock and takes a fixed time. As a result, device power
consumption is directly proportional to the speed of operation.
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Feature Description (continued)
8.2.6 Digital Output
As discussed in the Description and Timing Requirements sections, the device digital output is SPI compatible.
Table 1 lists the output codes corresponding to various analog input voltages.
Table 1. Output Codes
DESCRIPTION
ANALOG VALUE (V)
DIGITAL OUTPUT STRAIGHT BINARY
Full-scale range
Vref
Least significant bit (LSB)
Vref/65536
Positive full scale
+Vref – 1 LSB
1111 1111 1111 1111
FFFF
Midscale
Vref/2
1000 0000 0000 0000
8000
Midscale – 1 LSB
Vref/2– 1 LSB
0111 1111 1111 1111
7FFF
Zero
0
0000 0000 0000 0000
0000
BINARY CODE
HEX CODE
8.2.7 SCLK Input
The device uses SCLK for serial data output. Data is read after the conversion is over and the device is in the
acquisition phase. It is possible to use a free running SCLK for the device, but it is recommended to stop the
clock during a conversion, as the clock edges can couple with the internal analog circuit and can affect
conversion results.
8.3 Device Functional Modes
8.3.1
CS Mode
CS Mode is selected if SDI is high at the rising edge of CONVST. As indicated before there are four different
interface options available in this mode, namely 3-wire CS mode without busy indicator, 3-wire CS mode with
busy indicator, 4-wire CS mode without busy indicator, 4-wire CS mode with busy indicator. The following section
discusses these interface options in detail.
8.3.1.1 3-Wire CS Mode Without Busy Indicator
The three wire interface option in CS mode is selected if SDI is tied to +VBD, as shown in Figure 49. In the three
wire interface option, CONVST acts like CS. The device samples the input signal and enters the conversion
phase on the rising edge of CONVST, at the same time SDO goes to 3-state; see Figure 50. Conversion is done
with the internal clock and it continues irrespective of the state of CONVST. As a result it is possible to bring
CONVST (acting as CS) low after the start of the conversion to select other devices on the board. But it is
absolutely necessary that CONVST is high again before the minimum conversion time (tcnv in timing
requirements table) is elapsed. A high level on CONVST at the end of the conversion ensures the device does
not generate a busy indicator.
Digital Host
ADS8319
+VBD
SDI
CONVST
CNV
SCLK
CLK
SDO
SDI
Figure 49. Connection Diagram, 3-Wire CS Mode Without Busy Indicator (SDI = 1)
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Device Functional Modes (continued)
tcyc
t1
CONVST
tacq
tcnv
ACQUISITION
CONVERSION
ACQUISITION
tclkl
t2
SCLK
1
2
ten
t3
SDO
D15
16
15
tclkh
tdis
tclk
D14
D1
D0
Figure 50. Interface Timing Diagram, 3-Wire CS Mode Without Busy Indicator (SDI = 1)
When the conversion is over, the device enters the acquisition phase and powers down. On the falling edge of
CONVST, SDO comes out of three state, and the device outputs the MSB of the data. After this, the device
outputs the next lower data bits on every falling edge of SCLK. SDO goes to 3-state after the 16th falling edge of
SCLK or CONVST high, whichever occurs first. It is necessary that the device sees a minimum of 15 falling
edges of SCLK during the low period of CONVST.
8.3.1.2 3-Wire CS Mode With Busy Indicator
The three wire interface option in CS mode is selected if SDI is tied to +VBD, as shown in Figure 51. In the three
wire interface option, CONVST acts like CS. The device samples the input signal and enters the conversion
phase on the rising edge of CONVST, at the same time SDO goes to 3 state; see Figure 52. Conversion is done
with the internal clock and it continues irrespective of the state of CONVST. As a result it is possible to toggle
CONVST (acting as CS) after the start of the conversion to select other devices on the board. But it is absolutely
necessary that CONVST is low again before the minimum conversion time (tcnv in timing requirements table) is
elapsed and continues to stay low until the end of maximum conversion time. A low level on the CONVST input
at the end of a conversion ensures the device generates a busy indicator.
Digital Host
Device
CNV
CONVST
+VBD
SDI
SCLK
+VBD
SDO
CLK
SDI
IRQ
Figure 51. Connection Diagram, 3-Wire CS Mode With Busy Indicator
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Device Functional Modes (continued)
tcyc
t1
CONVST
tacq
tcnv
ACQUISITION
CONVERSION
ACQUISITION
tclkl
t2
1
SCLK
2
3
16
t3
SDO
D15
tclk
D14
D1
17
tclkh
tdis
D0
Figure 52. Interface Timing Diagram, 3-Wire CS Mode With Busy Indicator (SDI = 1)
When the conversion is over, the device enters the acquisition phase and powers down, and the device forces
SDO out of three state and outputs a busy indicator bit (low level). The device outputs the MSB of data on the
first falling edge of SCLK after the conversion is over and continues to output the next lower data bits on every
subsequent falling edge of SCLK. SDO goes to three state after the 17th falling edge of SCLK or CONVST high,
whichever occurs first. It is necessary that the device sees a minimum of 16 falling edges of SCLK during the low
period of CONVST.
8.3.1.3 4-Wire CS Mode Without Busy Indicator
As mentioned before for selecting CS mode it is necessary that SDI is high at the time of the CONVST rising
edge. Unlike in three wire interface option, SDI is controlled by digital host and acts like CS. As shown in
Figure 53, SDI goes to a high level before the rising edge of CONVST. The rising edge of CONVST while SDI is
high selects CS mode, forces SDO to three state, samples the input signal, and the device enters the conversion
phase. In the 4 wire interface option CONVST needs to be at a high level from the start of the conversion until all
of the data bits are read. Conversion is done with the internal clock and it continues irrespective of the state of
SDI. As a result it is possible to bring SDI (acting as CS) low to select other devices on the board. But it is
absolutely necessary that SDI is high again before the minimum conversion time (tcnv in timing requirements
table) is elapsed.
CONVST
t6
SDI (CS) #1
t4
t5
SDI (CS) #2
tcnv
ACQUISITION
tacq
CONVERSION
ten
ACQUISITION
tclkl
t2
SCLK
1
ten
2
t3
SDO
D15#1
17
16
15
tclkh
tclk
D14#1
D1#1
18
31
D0#1
D15#2 D14#2
32
tdis
tdis
D1#2
D0#2
Figure 53. Interface Timing Diagram, 4-Wire CS Mode Without Busy Indicator
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Device Functional Modes (continued)
When the conversion is over, the device enters the acquisition phase and powers down. SDI falling edge can
occur after the maximum conversion time (tcnv in timing requirements table). Note that it is necessary that SDI is
high at the end of the conversion, so that the device does not generate a busy indicator. The falling edge of SDI
brings SDO out of 3-state and the device outputs the MSB of the data. Subsequent to this the device outputs the
next lower data bits on every falling edge of SCLK. SDO goes to three state after the 16th falling edge of SCLK or
SDI (CS) high, whichever occurs first. As shown in Figure 54, it is possible to hook multiple devices on the same
data bus. In this case the second device SDI (acting as CS) can go low after the first device data is read and
device 1 SDO is in three state.
CS1
CS2
CNV
CONVST
SDI
CONVST
SDO
SDI
SDO
SCLK
SDI
SCLK
CLK
ADS8319#2
ADS8319#1
Digital Host
Figure 54. Connection Diagram, 4-Wire CS Mode Without Busy Indicator
Care needs to be taken so that CONVST and SDI are not low together at any time during the cycle.
8.3.1.4 4-Wire CS Mode With Busy Indicator
As mentioned before for selecting CS mode it is necessary that SDI is high at the time of the CONVST rising
edge. Unlike in the three wire interface option, SDI is controlled by the digital host and acts like CS. SDI goes to
a high level before the rising edge of CONVST; see Figure 55. The rising edge of CONVST while SDI is high
selects CS mode, forces SDO to three state, samples the input signal, and the device enters the conversion
phase. In the 4 wire interface option CONVST needs to be at a high level from the start of the conversion until all
of the data bits are read. Conversion is done with the internal clock and it continues irrespective of the state of
SDI. As a result it is possible to toggle SDI (acting as CS) to select other devices on the board. But it is
absolutely necessary that SDI is low before the minimum conversion time (tcnv in timing requirements table) is
elapsed and continues to stay low until the end of the maximum conversion time. A low level on the SDI input at
the end of a conversion ensures the device generates a busy indicator.
22
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Device Functional Modes (continued)
tcyc
t6
CNVST
t5
SDI (CS) t
4
tacq
tcnv
ACQUISITION
CONVERSION
ACQUISITION
tclkh
t2
1
SCLK
2
3
t3
SDO
D15
17
16
tclkl
tdis
tclk
D14
D1
D0
Figure 55. Interface Timing Diagram, 4-Wire CS Mode With Busy Indicator
CS
SDI
CNV
CONVST
+ VBD
SDO
ADS8319
CLK
SDI
IRQ
Digital Host
Figure 56. Connection Diagram, 4-Wire CS Mode With Busy Indicator
When the conversion is over, the device enters the acquisition phase and powers down, forces SDO out of three
state, and outputs a busy indicator bit (low level). The device outputs the MSB of the data on the first falling edge
of SCLK after the conversion is over and continues to output the next lower data bits on every falling edge of
SCLK. SDO goes to three state after the 17th falling edge of SCLK or SDI (CS) high, whichever occurs first.
Care needs to be taken so that CONVST and SDI are not low together at any time during the cycle.
8.3.2 Daisy-Chain Mode
Daisy chain mode is selected if SDI is low at the time of CONVST rising edge. This mode is useful to reduce
wiring and hardware like digital isolators in the applications where multiple (ADC) devices are used. In this mode
all of the devices are connected in a chain (SDO of one device connected to the SDI of the next device) and data
transfer is analogous to a shift register.
Like CS mode even this mode offers operation with or without a busy indicator. The following section discusses
these interface options in detail.
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Device Functional Modes (continued)
8.3.2.1 Daisy-Chain Mode Without Busy Indicator
Figure 57 shows the connection diagram. SDI for device 1 is tied to ground and SDO of device 1 goes to SDI of
device 2 and so on. SDO of the last device in the chain goes to the digital host. CONVST for all of the devices in
the chain are tied together. In this mode there is no CS signal. The device SDO is driven low when SDI low
selects daisy chain mode and the device samples the analog input and enters the conversion phase. It is
necessary that SCLK is low at the rising edge of CONVST so that the device does not generate a busy indicator
at the end of the conversion. In this mode CONVST continues to be high from the start of the conversion until all
of the data bits are read. Once started, conversion continues irrespective of the state of SCLK.
CNV
CONVST
SDI
CONVST
SDO
SDI
SDO
SCLK
SCLK
Device 1
Device 2
SDI
CLK
Digital Host
Figure 57. Connection Diagram, Daisy-Chain Mode Without Busy Indicator (SDI = 0)
tcyc
t6
CONVST
tacq
tcnv
ACQUISITION
ACQUISITION
CONVERSION
t7
tclkl
t2
SCLK
1
2
SDO #1, SDI #2
16
15
t8
tclk
#1-D15
#1-D14
17
18
#1-D15
#1-D14
31
32
tclkh
#1-D1
#1-D0
#2-D1
#2-D0
t3
SDO #2
#2-D15
#2-D14
#1-D1
#1-D0
Figure 58. Interface Timing Diagram, Daisy-Chain Mode Without Busy Indicator
At the end of the conversion, every device in the chain initiates output of its conversion data starting with the
MSB bit. Further the next lower data bit is output on every falling edge of SCLK. While every device outputs its
data on the SDO pin, it also receives previous device data on the SDI pin (other than device #1) and stores it in
the shift register. The device latches incoming data on every falling edge of SCLK. SDO of the first device in the
chain goes low after the 16th falling edge of SCLK. All subsequent devices in the chain output the stored data
from the previous device in MSB first format immediately following their own data word.
It needs 16 × N clocks to read data for N devices in the chain.
24
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Device Functional Modes (continued)
8.3.2.2 Daisy-Chain Mode With Busy Indicator
Figure 59 shows the connection diagram. SDI for device 1 is wired to it's CONVST and CONVST for all the
devices in the chain are wired together. SDO of device 1 goes to SDI of device 2 and so on. SDO of the last
device in the chain goes to the digital host. In this mode there is no CS signal. On the rising edge of CONVST,
all of the device in the chain sample the analog input and enter the conversion phase. For the first device, SDI
and CONVST are wired together, and the setup time of SDI to rising edge of CONVST is adjusted so that the
device still enters chain mode even though SDI and CONVST rise together. It is necessary that SCLK is high at
the rising edge of CONVST so that the device generates a busy indicator at the end of the conversion. In this
mode, CONVST continues to be high from the start of the conversion until all of the data bits are read. Once
started, conversion continues irrespective of the state of SCLK.
CNV
CONVST
SDI
CONVST
SDO
SDI
IRQ
SDO
SCLK
SCLK
Device 1
Device 2
SDI
CLK
Digital Host
Figure 59. Connection Diagram, Daisy-Mode With Busy Indicator (SDI = 0)
tcyc
t6
CONVST
tacq
tcnv
ACQUISITION
ACQUISITION
CONVERSION
t7
tclkl
t2
1
SCLK
2
3
16
SDO #1, SDI #2
17
18
19
32
33
#1-D15
#1-D14
#1-D1
#1-D0
tclk
t8
tclkh
#1-D15
#1-D14
#1-D1
#1-D0
#2-D1
#2-D0
t3
SDO #2
#2-D15
#2-D14
Figure 60. Interface Timing Diagram, Daisy-Chain Mode With Busy Indicator
At the end of the conversion, all the devices in the chain generate busy indicators. On the first falling edge of
SCLK following the busy indicator bit, all of the devices in the chain output their conversion data starting with the
MSB bit. After this the next lower data bit is output on every falling edge of SCLK. While every device outputs its
data on the SDO pin, it also receives the previous device data on the SDI pin (except for device #1) and stores it
in the shift register. Each device latches incoming data on every falling edge of SCLK. SDO of the first device in
the chain goes high after the 17th falling edge of SCLK. All subsequent devices in the chain output the stored
data from the pervious device in MSB first format immediately following their own data word. It needs 16 × N + 1
clock pulses to read data for N devices in the chain.
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9 Device and Documentation Support
9.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
9.2 Trademarks
E2E is a trademark of Texas Instruments.
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
9.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
9.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS8319IBDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CEN
ADS8319IBDGST
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CEN
ADS8319IBDRCR
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CEP
ADS8319IBDRCT
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CEP
ADS8319IDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CEN
ADS8319IDGST
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CEN
ADS8319IDRCT
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CEP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2015
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ADS8319IBDGSR
VSSOP
DGS
10
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS8319IBDGST
VSSOP
DGS
10
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS8319IBDRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ADS8319IBDRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ADS8319IDGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS8319IDGST
VSSOP
DGS
10
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS8319IDRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Feb-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS8319IBDGSR
VSSOP
DGS
10
2500
367.0
367.0
38.0
ADS8319IBDGST
VSSOP
DGS
10
250
210.0
185.0
35.0
ADS8319IBDRCR
VSON
DRC
10
3000
338.1
338.1
20.6
ADS8319IBDRCT
VSON
DRC
10
250
210.0
185.0
35.0
ADS8319IDGSR
VSSOP
DGS
10
2500
367.0
367.0
38.0
ADS8319IDGST
VSSOP
DGS
10
250
210.0
185.0
35.0
ADS8319IDRCT
VSON
DRC
10
250
210.0
185.0
35.0
Pack Materials-Page 2
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