Cypress CY8C27243-24SIT Psoc programmable system-on-chip Datasheet

CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
PSoC® Programmable System-on-Chip™
Features
■
■
■
■
■
Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 3.0 to 5.25V Operating Voltage
❐ Operating Voltages Down to 1.0V Using On-Chip Switch
Mode Pump (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
■
Additional System Resources
❐ I2C Slave, Master, and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■
Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Trace Memory
Advanced Peripherals (PSoC® Blocks)
❐ 12 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ 8 Digital PSoC Blocks Provide:
• 8- to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Up to 2 Full-Duplex UARTs
• Multiple SPI™ Masters or Slaves
• Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
Logic Block Diagram
Port 5
Port 2
Port 1
Port 0
PSoC
CORE
Analog
Drivers
System Bus
Global Digital Interconnect
Precision, Programmable Clocking
❐ Internal 2.5% 24/48 MHz Oscillator
❐ 24/48 MHz with Optional 32 kHz Crystal
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
SRAM
256 Bytes
Global Analog Interconnect
SROM
Flash 16K
CPUCore (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
Flexible On-Chip Memory
❐ 16K Flash Program Storage 50,000 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
Programmable Pin Configurations
a. 25 mA Sink on all GPIO
b. Pull up, Pull down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
c. Up to 12 Analog Inputs on GPIO
d. Four 30 mA Analog Outputs on GPIO
e. Configurable Interrupt on all GPIO
Port 4 Port 3
DIGITAL SYSTEM
ANALOG SYSTEM
Digital
Block
Array
Digital
Clocks
Multiply
Accum.
Analog
Ref.
Analog
Block
Array
Analog
Input
Muxing
POR and LVD
Decimator
I 2C
System Resets
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 38-12012 Rev. *M
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 17, 2009
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PSoC Functional Overview
The PSoC® family consists of many Programmable
System-on-Chip Controller devices. These devices are designed
to replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture allows
the user to create customized peripheral configurations that
match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of convenient pinouts and packages.
Digital System
The Digital System is composed of 8 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references.
Figure 1. Digital System Block Diagram
Port 5
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C27x43 family can have up to five IO
ports that connect to the global digital and analog interconnects,
providing access to 8 digital blocks and 12 analog blocks.
To System Bus
ToAnalog
System
Row Input
Configuration
DBB00
DBB01
DCB02
4
DCB03
4
Row Output
Configuration
Row 0
8
8
Row 1
DBB10
DBB11
DCB12
4
DCB13
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
8
Row Output
Configuration
Row Input
Configuration
8
The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 17 vectors,
to simplify programming of real time embedded events. Program
execution is timed and protected using the included Sleep and
Watch Dog Timers (WDT).
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system
interrupt on high level, low level, and change from last read.
Digital Clocks
FromCore
Port 0
Digital PSoC Block Array
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose IO).
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to
2.5% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
Port 1
Port 2
DIGITAL SYSTEM
PSoC Core
Memory encompasses 16K of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2K of EEPROM
emulated using the Flash. Program Flash utilizes four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
Port 3
Port 4
GOE[7:0]
GOO[7:0]
Digital peripheral configurations include those listed below.
■
PWMs (8 to 32 bit)
■
PWMs with Dead band (8 to 32 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity (up to 2)
■
SPI slave and master (up to 2)
■
I2C slave and multi-master (1 available as a System Resource)
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA (up to 2)
■
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device Characteristics” on page 4.
Document Number: 38-12012 Rev. *M
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The Analog System is composed of 12 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are listed below.
■
■
Analog-to-digital converters (up to 4, with 6- to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
Figure 2. Analog System Block Diagram
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
AGNDIn RefIn
Analog System
P2[3]
Filters (2, 4, 6, and 8 pole band-pass, low-pass, and notch)
■
Amplifiers (up to 4, with selectable gain to 48x)
■
Instrumentation amplifiers (up to 2, with selectable gain to 93x)
■
Comparators (up to 4, with 16 selectable thresholds)
■
DACs (up to 4, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 4, with 6- to 9-bit resolution)
■
High current output drivers (four with 30 mA drive as a Core
Resource)
■
1.3V reference (as a System Resource)
■
DTMF Dialer
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
P2[1]
P2[6]
P2[4]
P2[2]
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
Block Array
ACB00
ACB01
ACB02
ACB03
ASC10
ASD11
ASC12
ASD13
ASD20
ASC21
ASD22
ASC23
Analog blocks are provided in columns of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in the figure below.
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 38-12012 Rev. *M
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Getting Started
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Statements
describing the merits of each system resource are below.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
Multiply accumulate (MAC) provides fast 8-bit multiplier with
32-bit accumulate, to assist in general math and digital filters.
■
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■
Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
■
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources available
for specific PSoC device groups.The PSoC device covered by
this data sheet is highlighted below.
Table 1. PSoC Device Characteristics
For in depth information, along with detailed programming information, see the PSoC® Programmable System-on-Chip™
Technical Reference Manual for CY8C28xxx PSoC devices.
For up to date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at www.cypress.com/psoc.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Digital
IO
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
Solutions Library
CY8C29x66
up to
64
4
16
12
4
4
12
2K
32K
CY8C27x43
up to
44
2
8
12
4
4
12
256
Bytes
16K
CY8C24x94
49
1
4
48
2
2
6
1K
16K
CY8C24x23
up to
24
1
4
12
2
2
6
256
Bytes
4K
CY8C24x23A
up to
24
1
4
12
2
2
6
256
Bytes
4K
CY8C21x34
up to
28
1
4
28
0
2
4[1]
512
Bytes
8K
CY8C21x23
16
1
4
8
0
2
4[2]
256
Bytes
4K
CY8C20x34
up to
28
0
0
28
0
0
3[2]
512
Bytes
8K
PSoC Part
Number
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various
application designs that include firmware and hardware design
files that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
Notes
1. Limited analog functionality.
2. Two analog blocks and one CapSense.
Document Number: 38-12012 Rev. *M
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Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built in support for third party
assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication
interfaces. You define when and how an output device changes
state based upon any or all other system devices. Based upon
the design, PSoC Designer automatically selects one or more
PSoC Programmable System-on-Chip Controllers that match
your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.4. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
Document Number: 38-12012 Rev. *M
Code Generation Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write IO registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select Components
2. Configure Components
3. Organize and Connect
4. Generate, Verify, and Debug
Organize and Connect
You can build signal chains at the chip level by interconnecting
user modules to each other and the IO pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
Select Components
Generate, Verify, and Debug
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
(I2C-bus, for example), and the logic to control how they interact
with one another (called valuators).
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and programmable
system-on-chip varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Document Number: 38-12012 Rev. *M
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the ICE where it runs at full speed.
Debugger capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the Debugger provides a large trace
buffer and allows you define complex breakpoint events that
include monitoring address and data bus values, memory
locations and external signals.
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Document Conventions
Units of Measure
Acronyms Used
This table lists the acronyms used in this data sheet.
A units of measure table is located in the section
Electrical Specifications on page 19. Table 13 on page 19 lists all
the abbreviations used to measure the PSoC devices.
Table 2. Acronyms
Numeric Naming
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
EEPROM
electrically erasable programmable read-only
memory
FSR
full scale range
GPIO
general purpose IO
ICE
in-circuit emulator
IDE
integrated development environment
IO
input/output
ISSP
in-system serial programming
IPOR
imprecise power on reset
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
PC
program counter
PGA
programmable gain amplifier
POR
power on reset
PPOR
precision power on reset
PSoC®
Programmable System-on-Chip™
PWM
pulse width modulator
ROM
read only memory
SC
switched capacitor
SMP
switch mode pump
SRAM
static random access memory
Document Number: 38-12012 Rev. *M
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
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Pinouts
The CY8C27x43 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
8-Pin Part Pinout
Table 3. Pin Definitions - 8-Pin PDIP
Type
Pin
No.
Digital
Analog
Pin
Name
1
IO
IO
P0[5]
Analog column mux input and column output.
2
IO
IO
P0[3]
Analog column mux input and column output.
3
IO
P1[1]
Crystal Input (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
4
Power
5
IO
6
IO
7
IO
8
Vss
Description
A, IO, P0[5]
A, IO, P0[3]
I2CSCL,XTALin, P1[1]
Vss
1
8
2PDIP 7
3
6
4
5
Vdd
P0[4], A, IO
P0[2], A, IO
P1[0],XTALout,I2CSDA
Ground connection.
P1[0]
Crystal Output (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
IO
P0[2]
Analog column mux input and column output.
IO
P0[4]
Analog column mux input and column output.
Vdd
Supply voltage.
Power
Figure 3. CY8C27143 8-Pin PSoC Device
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference
Manual for details.
20-Pin Part Pinout
Table 4. Pin Definitions - 20-Pin SSOP, SOIC
Type
Pin
No.
Digital
Analog
Pin
Name
1
IO
I
P0[7]
Analog column mux input.
2
IO
IO
P0[5]
Analog column mux input and column output.
3
IO
IO
P0[3]
Analog column mux input and column output.
4
IO
I
P0[1]
Analog column mux input.
SMP
Switch Mode Pump (SMP) connection to external
components required.
5
Power
Description
6
IO
P1[7]
I2C Serial Clock (SCL).
7
IO
P1[5]
I2C Serial Data (SDA).
8
IO
P1[3]
9
IO
P1[1]
10
Power
Vss
11
IO
P1[0]
12
IO
P1[2]
13
IO
P1[4]
14
IO
P1[6]
15
1
2
3
4
5
6
7
8
9
10
SSOP
SOIC
20
19
18
17
16
15
14
13
12
11
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
XRES
P1[6]
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA
Ground connection.
Crystal Output (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
Optional External Clock Input (EXTCLK).
XRES
Active high external reset with internal pull down.
IO
I
P0[0]
Analog column mux input.
17
IO
IO
P0[2]
Analog column mux input and column output.
18
IO
IO
P0[4]
Analog column mux input and column output.
19
IO
I
P0[6]
Analog column mux input.
Vdd
Supply voltage.
Power
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
SMP
I2CSCL,P1[7]
I2CSDA, P1[5]
P1[3]
I2CSCL,XTALin, P1[1]
Vss
Crystal Input (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
16
20
Input
Figure 4. CY8C27243 20-Pin PSoC Device
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12012 Rev. *M
Page 8 of 53
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CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
28-Pin Part Pinout
Table 5. Pin Definitions - 28-Pin PDIP, SSOP, SOIC
Type
Digital
Analog
Pin
Name
1
IO
I
P0[7]
Analog column mux input.
2
IO
IO
P0[5]
Analog column mux input and column output.
3
IO
IO
P0[3]
Analog column mux input and column output.
4
IO
I
P0[1]
Analog column mux input.
5
IO
6
IO
7
IO
I
P2[3]
8
IO
I
P2[1]
Direct switched capacitor block input.
SMP
Switch Mode Pump (SMP) connection to external
components required.
Pin No.
9
Description
P2[7]
P2[5]
Power
Direct switched capacitor block input.
10
IO
P1[7]
I2C Serial Clock (SCL).
11
IO
P1[5]
I2C Serial Data (SDA).
12
IO
P1[3]
13
IO
P1[1]
14
Power
Vss
15
IO
P1[0]
16
IO
P1[2]
17
IO
P1[4]
18
IO
19
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I, P2[3]
A, I, P2[1]
SMP
I2CSCL,P1[7]
I2CSDA, P1[5]
P1[3]
I2CSCL,XTALin, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PDIP
SSOP
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6],ExternalVRef
P2[4],ExternalAGND
P2[2], A, I
P2[0], A, I
XRES
P1[6]
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA
Crystal Input (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
Ground connection.
Crystal Output (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
Optional External Clock Input (EXTCLK).
P1[6]
Input
XRES
Active high external reset with internal pull down.
20
IO
I
P2[0]
Direct switched capacitor block input.
21
IO
I
P2[2]
Direct switched capacitor block input.
22
IO
P2[4]
External Analog Ground (AGND).
23
IO
P2[6]
External Voltage Reference (VRef).
24
IO
I
P0[0]
Analog column mux input.
25
IO
IO
P0[2]
Analog column mux input and column output.
26
IO
IO
P0[4]
Analog column mux input and column output.
27
IO
I
P0[6]
Analog column mux input.
Vdd
Supply voltage.
28
Figure 5. CY8C27443 28-Pin PSoC Device
Power
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12012 Rev. *M
Page 9 of 53
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CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
44-Pin Part Pinout
Table 6. Pin Definitions - 44-Pin TQFP
IO
IO
IO
IO
IO
IO
IO
IO
17
18
IO
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Power
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
P1[3]
P1[1]
Power
Vss
P1[0]
IO
IO
IO
IO
IO
IO
IO
Input
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
I
I
IO
IO
I
Power
IO
IO
IO
IO
IO
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
I
IO
IO
I
P1[2]
P1[4]
P1[6]
P3[0]
P3[2]
P3[4]
P3[6]
XRES
P4[0]
P4[2]
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
Figure 6. CY8C27543 44-Pin PSoC Device
Direct switched capacitor block input.
Direct switched capacitor block input.
Switch Mode Pump (SMP) connection to external
components required.
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
Crystal Input (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
Ground connection.
Crystal Output (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
P2[5]
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6],ExternalVRef
9
10
11
12
13
14
15
16
I
I
Description
P2[7]
P0[1], A, I
P0[3], A, IO
P0[5], A, IO
P0[7], A, I
Vdd
IO
IO
IO
IO
IO
IO
IO
Pin Name
44
43
42
41
40
39
38
37
36
35
34
1
2
3
4
5
6
7
8
Analog
1
2
3
4
5
6
7
8
9
10
11
TQFP
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
Type
Digital
P2[4], External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[1]
I2CSCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2CSCL,XTALin,P1[1]
Vss
I2CSDA,XTALout,P1[0]
P1[2]
EXTCLK,P1[4]
P1[6]
P3[0]
Pin
No.
Optional External Clock Input (EXTCLK).
Active high external reset with internal pull down.
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND).
External Voltage Reference (VRef).
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12012 Rev. *M
Page 10 of 53
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CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
48-Pin Part Pinout
Table 7. 48-Pin Part Pinout (SSOP)
Pin
No.
Type
Figure 7. CY8C27643 48-Pin PSoC Device
Pin
Name
Description
Digital
Analog
1
IO
I
P0[7]
Analog column mux input.
2
IO
IO
P0[5]
Analog column mux input and column
output.
3
IO
IO
P0[3]
Analog column mux input and column
output.
4
IO
I
P0[1]
Analog column mux input.
5
IO
6
IO
7
IO
I
P2[3]
Direct switched capacitor block input.
8
IO
I
P2[1]
Direct switched capacitor block input.
9
IO
P4[7]
10
IO
P4[5]
11
IO
P4[3]
12
IO
13
P2[7]
P2[5]
P4[1]
Power
SMP
Switch Mode Pump (SMP) connection
to external components required.
14
IO
P3[7]
15
IO
P3[5]
16
IO
P3[3]
17
IO
P3[1]
18
IO
P5[3]
19
IO
P5[1]
20
IO
P1[7]
I2C Serial Clock (SCL).
21
IO
P1[5]
I2C Serial Data (SDA).
22
IO
P1[3]
23
IO
P1[1]
Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*.
24
Vss
Ground connection.
25
IO
Power
P1[0]
Crystal Output (XTALout), I2C Serial
Data (SDA), ISSP-SDATA.*
26
IO
P1[2]
27
IO
P1[4]
28
IO
P1[6]
29
IO
P5[0]
30
IO
P5[2]
31
IO
P3[0]
32
IO
P3[2]
33
IO
P3[4]
34
IO
35
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
I2CSCL, P1[7]
I2CSDA, P1[5]
P1[3]
I2CSCL,XTALin,P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6],External VRef
P2[4],External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P5[2]
P5[0]
P1[6]
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA
Optional External Clock Input
(EXTCLK).
P3[6]
Input
XRES
Active high external reset with internal
pull down.
36
IO
P4[0]
37
IO
P4[2]
38
IO
P4[4]
39
IO
40
IO
I
P2[0]
41
IO
I
P2[2]
Direct switched capacitor block input.
42
IO
P2[4]
External Analog Ground (AGND).
P4[6]
Direct switched capacitor block input.
Document Number: 38-12012 Rev. *M
Page 11 of 53
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CY8C27443, CY8C27543, CY8C27643
Table 7. 48-Pin Part Pinout (SSOP)
43
IO
44
IO
I
45
IO
IO
P2[6]
P0[0]
P0[2]
46
IO
IO
P0[4]
47
IO
I
P0[6]
Vdd
Power
48
External Voltage Reference (VRef).
Analog column mux input.
Analog column mux input and
column output.
Analog column mux input and
column output.
Analog column mux input.
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
Table 8. 48-Pin Part Pinout (QFN)*
Figure 8. CY8C27643 48-Pin PSoC Device
Pi
Type
n
No Digital Analog
.
Pin
Name
1
IO
I
P2[3]
Direct switched capacitor block input.
2
IO
I
P2[1]
Direct switched capacitor block input.
3
IO
P4[7]
4
IO
P4[5]
5
IO
P4[3]
6
IO
P4[1]
SMP
Switch Mode Pump (SMP) connection to
external components required.
8
IO
P3[7]
9
IO
P3[5]
10
IO
P3[3]
11
IO
P3[1]
12
IO
P5[3]
13
IO
P5[1]
14
IO
P1[7]
I2C Serial Clock (SCL).
15
IO
P1[5]
I2C Serial Data (SDA).
16
IO
P1[3]
17
IO
P1[1]
Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK**.
18
Vss
Ground connection.
19
IO
Power
P1[0]
Crystal Output (XTALout), I2C Serial
Data (SDA), ISSP-SDATA**.
20
IO
P1[2]
21
IO
P1[4]
22
IO
P1[6]
23
IO
P5[0]
24
IO
P5[2]
25
IO
P3[0]
26
IO
P3[2]
27
IO
P3[4]
28
IO
29
Vdd
P0[6], A,I
P0[4], A,IO
P0[2], A,IO
P0[0], A,I
P2[6],ExternalVRef
P2[5]
P2[7]
P0[1], A,I
P0[3], A,IO
P0[5], A,IO
P0[7], A,I
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
QFN
(Top View )
36
35
34
33
32
31
30
29
28
27
26
25
13
14
I2CSDA,P1[5] 15
P1[3] 16
I2CSCL,XTALin,P1[1] 17
Vss 18
I2CSDA,XTALout,P1[0] 19
P1[2] 20
EXTCLK,P1[4] 21
P1[6] 22
P5[0] 23
P5[2] 24
Power
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P2[4],External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P5[1]
I2CSCL,P1[7]
7
Description
Optional External Clock Input (EXTCLK).
P3[6]
Input
XRES
30
IO
P4[0]
31
IO
P4[2]
32
IO
P4[4]
33
IO
P4[6]
Active high external reset with internal
pull down.
Document Number: 38-12012 Rev. *M
Page 12 of 53
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CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
Table 8. 48-Pin Part Pinout (QFN)*
34
IO
I
P2[0]
35
IO
I
P2[2]
Direct switched capacitor block input.
36
IO
P2[4]
External Analog Ground (AGND).
37
IO
P2[6]
External Voltage Reference (VRef).
38
IO
I
P0[0]
Analog column mux input.
39
IO
IO
P0[2]
Analog column mux input and column
output.
40
IO
IO
P0[4]
Analog column mux input and column
output.
41
IO
42
I
Power
Direct switched capacitor block input.
P0[6]
Analog column mux input.
Vdd
Supply voltage.
43
IO
I
P0[7]
Analog column mux input.
44
IO
IO
P0[5]
Analog column mux input and column
output.
45
IO
IO
P0[3]
Analog column mux input and column
output.
46
IO
I
P0[1]
Analog column mux input.
47
IO
P2[7]
48
IO
P2[5]
LEGEND: A = Analog, I = Input, and O = Output.
* The QFN package has a center pad that must be connected to ground (Vss).
** These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
Document Number: 38-12012 Rev. *M
Page 13 of 53
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CY8C27443, CY8C27543, CY8C27643
56-Pin Part Pinout
The 56-pin SSOP part is for the CY8C27002 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Table 9. 56-Pin Part Pinout (SSOP)
Pin
No.
Type
Digital
Analog
1
Figure 9. CY8C27002 56-Pin PSoC Device
Pin
Name
NC
Description
No connection.
2
IO
I
P0[7]
Analog column mux input.
3
IO
I
P0[5]
Analog column mux input and column
output.
4
IO
I
P0[3]
Analog column mux input and column
output.
5
IO
I
P0[1]
Analog column mux input.
6
IO
7
IO
8
IO
I
9
IO
I
10
IO
11
IO
12
IO
I
P4[3]
13
IO
I
P4[1]
14
OCD
15
OCD
16
P2[7]
P2[5]
P2[3]
Direct switched capacitor block input.
P2[1]
Direct switched capacitor block input.
P4[7]
P4[5]
Power
OCDE OCD even data IO.
OCDO OCD odd data output.
SMP
Switch Mode Pump (SMP) connection to
required external components.
17
IO
P3[7]
18
IO
P3[5]
19
IO
P3[3]
20
IO
P3[1]
21
IO
P5[3]
22
IO
P5[1]
23
IO
P1[7]
I2C Serial Clock (SCL).
24
IO
P1[5]
I2C Serial Data (SDA).
NC
No connection.
25
IO
P1[3]
27
IO
P1[1]
Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*.
Power
Vdd
Supply voltage.
29
NC
No connection.
30
NC
No connection..
Crystal Output (XTALout), I2C Serial
Data (SDA), ISSP-SDATA*.
31
IO
P1[0]
32
IO
P1[2]
33
IO
P1[4]
34
IO
P1[6]
35
IO
P5[0]
36
IO
P5[2]
37
IO
P3[0]
38
IO
P3[2]
39
IO
P3[4]
40
IO
P3[6]
P2[5]
AI, P2[3]
AI, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
56
55
54
53
1
2
3
4
5
6
7
8
9
10
52
51
11
12
13
OCDE
OCDO
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
I2C SCL, P1[7]
14
15
16
17
I2C SDA, P1[5]
NC
P1[3]
SCLK, I2C SCL, XTALIn, P1[1]
Vss
24
25
26
27
28
18
19
20
21
22
23
SSOP
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Vdd
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
P2[6], External VRef
P2[4], External AGND
P2[2], AI
P2[0], AI
P4[6]
P4[4]
P4[2]
P4[0]
CCLK
HCLK
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P5[2]
P5[0]
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALOut, I2C SDA, SDATA
NC
NC
Not for Production
26
28
NC
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
Optional External Clock Input (EXTCLK).
Document Number: 38-12012 Rev. *M
Page 14 of 53
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Table 9. 56-Pin Part Pinout (SSOP)
41
Input
XRES
Active high external reset with internal
pull down.
42
OCD
HCLK
OCD high-speed clock output.
43
OCD
CCLK
OCD CPU clock output.
44
IO
P4[0]
45
IO
P4[2]
46
IO
P4[4]
47
IO
48
IO
I
P2[0]
Direct switched capacitor block input.
49
IO
I
P2[2]
Direct switched capacitor block input.
50
IO
P2[4]
External Analog Ground (AGND).
51
IO
P2[6]
External Voltage Reference (VRef).
52
IO
I
P0[0]
Analog column mux input.
53
IO
I
P0[2]
Analog column mux input and column
output.
54
IO
I
P0[4]
Analog column mux input and column
output.
55
IO
P0[6]
Analog column mux input.
Vdd
Supply voltage.
56
P4[6]
I
Power
LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
Document Number: 38-12012 Rev. *M
Page 15 of 53
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Register Reference
Register Mapping Tables
This chapter lists the registers of the CY8C27x43 PSoC device.
For detailed register information, reference the
PSoC Programmable System-on-Chip Technical Reference
Manual.
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.
Register Conventions
Note In the following register mapping tables, blank fields are
reserved and must not be accessed.
The register conventions specific to this section are listed in the
following table.
Table 10. Register Conventions
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Table 11. Register Map Bank 0 Table: User Space
INT_CLR3
INT_MSK3
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
Access
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
Addr
(0,Hex)
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RW
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
# Access is bit specific.
Access
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC12CR0
ASC12CR1
ASC12CR2
ASC12CR3
ASD13CR0
ASD13CR1
ASD13CR2
ASD13CR3
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
ASD22CR0
ASD22CR1
ASD22CR2
ASD22CR3
ASC23CR0
ASC23CR1
ASC23CR2
ASC23CR3
Addr
(0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
Name
Document Number: 38-12012 Rev. *M
Access
00
RW
01
RW
02
RW
03
RW
04
RW
05
RW
06
RW
07
RW
08
RW
09
RW
0A
RW
0B
RW
0C
RW
0D
RW
0E
RW
0F
RW
10
RW
11
RW
12
RW
13
RW
14
RW
15
RW
16
RW
17
RW
18
19
1A
1B
1C
1D
1E
1F
DBB00DR0
20
#
AMX_IN
DBB00DR1
21
W
DBB00DR2
22
RW
DBB00CR0
23
#
ARF_CR
DBB01DR0
24
#
CMP_CR0
DBB01DR1
25
W
ASY_CR
Blank fields are Reserved and must not be accessed.
Addr
(0,Hex)
Name
Access
Addr
(0,Hex)
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
PRT5GS
PRT5DM2
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
Page 16 of 53
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Table 11. Register Map Bank 0 Table: User Space (continued)
RW
RW
RW
RW
RW
RW
RW
CPU_F
RW
RW
RW
RW
RW
RW
RW
CPU_SCR1
CPU_SCR0
Access
DEC_CR0
DEC_CR1
MUL_X
MUL_Y
MUL_DH
MUL_DL
ACC_DR1
ACC_DR0
ACC_DR3
ACC_DR2
Addr
(0,Hex)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
RDI1RI
B8
RDI1SYN
B9
RDI1IS
BA
RDI1LT0
BB
RDI1LT1
BC
RDI1RO0
BD
RDI1RO1
BE
BF
# Access is bit specific.
Access
RW
Addr
(0,Hex)
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Name
Access
Addr
(0,Hex)
Name
Access
Addr
(0,Hex)
Name
DBB01DR2
26
RW
CMP_CR1
DBB01CR0
27
#
DCB02DR0
28
#
DCB02DR1
29
W
DCB02DR2
2A
RW
DCB02CR0
2B
#
DCB03DR0
2C
#
DCB03DR1
2D
W
DCB03DR2
2E
RW
DCB03CR0
2F
#
DBB10DR0
30
#
ACB00CR3
DBB10DR1
31
W
ACB00CR0
DBB10DR2
32
RW
ACB00CR1
DBB10CR0
33
#
ACB00CR2
DBB11DR0
34
#
ACB01CR3
DBB11DR1
35
W
ACB01CR0
DBB11DR2
36
RW
ACB01CR1
DBB11CR0
37
#
ACB01CR2
DCB12DR0
38
#
ACB02CR3
DCB12DR1
39
W
ACB02CR0
DCB12DR2
3A
RW
ACB02CR1
DCB12CR0
3B
#
ACB02CR2
DCB13DR0
3C
#
ACB03CR3
DCB13DR1
3D
W
ACB03CR0
DCB13DR2
3E
RW
ACB03CR1
DCB13CR0
3F
#
ACB03CR2
Blank fields are Reserved and must not be accessed.
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
#
#
Table 12. Register Map Bank 1 Table: Configuration Space
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
Access
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
Addr
(1,Hex)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0
80
ASC10CR1
81
ASC10CR2
82
ASC10CR3
83
ASD11CR0
84
ASD11CR1
85
ASD11CR2
86
ASD11CR3
87
ASC12CR0
88
ASC12CR1
89
ASC12CR2
8A
ASC12CR3
8B
ASD13CR0
8C
ASD13CR1
8D
ASD13CR2
8E
ASD13CR3
8F
ASD20CR0
90
ASD20CR1
91
ASD20CR2
92
ASD20CR3
93
ASC21CR0
94
ASC21CR1
95
ASC21CR2
96
ASC21CR3
97
ASD22CR0
98
ASD22CR1
99
ASD22CR2
9A
ASD22CR3
9B
# Access is bit specific.
Access
Addr
(1,Hex)
Name
Document Number: 38-12012 Rev. *M
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
Access
00
RW
01
RW
02
RW
03
RW
04
RW
05
RW
06
RW
07
RW
08
RW
09
RW
0A
RW
0B
RW
0C
RW
0D
RW
0E
RW
0F
RW
10
RW
11
RW
12
RW
13
RW
14
RW
15
RW
16
RW
17
RW
18
19
1A
1B
Blank fields are Reserved and must not be accessed.
Addr
(1,Hex)
Name
Access
Addr
(1,Hex)
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
PRT5DM1
PRT5IC0
PRT5IC1
RW
RW
RW
RW
Page 17 of 53
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Table 12. Register Map Bank 1 Table: Configuration Space (continued)
IMO_TR
ILO_TR
BDG_TR
ECO_TR
RW
RW
RW
RW
RW
RW
RW
CPU_F
RW
RW
RW
RW
RW
RW
RW
CPU_SCR1
CPU_SCR0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
Addr
(1,Hex)
RW
RW
RW
RW
RW
RW
RW
RW
Name
RW
RW
RW
RW
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
RDI1RI
B8
RDI1SYN
B9
RDI1IS
BA
RDI1LT0
BB
RDI1LT1
BC
RDI1RO0
BD
RDI1RO1
BE
BF
# Access is bit specific.
Access
ASC23CR0
ASC23CR1
ASC23CR2
ASC23CR3
Addr
(1,Hex)
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Name
Access
Document Number: 38-12012 Rev. *M
Addr
(1,Hex)
Name
Access
Addr
(1,Hex)
Name
1C
1D
1E
1F
DBB00FN
20
RW
CLK_CR0
DBB00IN
21
RW
CLK_CR1
DBB00OU
22
RW
ABF_CR0
23
AMD_CR0
DBB01FN
24
RW
DBB01IN
25
RW
DBB01OU
26
RW
AMD_CR1
27
ALT_CR0
DCB02FN
28
RW
ALT_CR1
DCB02IN
29
RW
CLK_CR2
DCB02OU
2A
RW
2B
DCB03FN
2C
RW
DCB03IN
2D
RW
DCB03OU
2E
RW
2F
DBB10FN
30
RW
ACB00CR3
DBB10IN
31
RW
ACB00CR0
DBB10OU
32
RW
ACB00CR1
33
ACB00CR2
DBB11FN
34
RW
ACB01CR3
DBB11IN
35
RW
ACB01CR0
DBB11OU
36
RW
ACB01CR1
37
ACB01CR2
DCB12FN
38
RW
ACB02CR3
DCB12IN
39
RW
ACB02CR0
DCB12OU
3A
RW
ACB02CR1
3B
ACB02CR2
DCB13FN
3C
RW
ACB03CR3
DCB13IN
3D
RW
ACB03CR0
DCB13OU
3E
RW
ACB03CR1
3F
ACB03CR2
Blank fields are Reserved and must not be accessed.
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
RW
RW
RW
RW
RW
R
W
W
RW
W
RL
#
#
Page 18 of 53
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Electrical Specifications
This chapter presents the DC and AC electrical specifications of the CY8C27x43 PSoC device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
Specifications are valid for -40°C ≤ TA ≤ 85°C and TJ ≤ 100°C, except where noted. Specifications for devices running at greater than
12 MHz are valid for -40°C ≤ TA ≤ 70°C and TJ ≤ 82°C.
Figure 10. Voltage versus CPU Frequency
5.25
Vdd Voltage
l id g
Va atin
n
r
pe gio
Re
O
4.75
3.00
93 kHz
CPU Fre que ncy
12 MHz
24 MHz
The following table lists the units of measure that are used in this chapter.
Table 13. Units of Measure
Symbol
Unit of Measure
Symbol
Unit of Measure
oC
degree Celsius
μW
microwatts
dB
decibels
mA
milli-ampere
fF
femto farad
ms
milli-second
Hz
hertz
mV
milli-volts
KB
1024 bytes
nA
nanoampere
Kbit
1024 bits
ns
nanosecond
kHz
kilohertz
nV
nanovolts
kΩ
kilohm
W
ohm
MHz
megahertz
pA
picoampere
MΩ
megaohm
pF
picofarad
μA
microampere
pp
peak-to-peak
μF
microfarad
μH
microhenry
ps
picosecond
μs
microsecond
sps
samples per second
μV
microvolts
s
sigma: one standard deviation
microvolts root-mean-square
V
volts
μVrms
Document Number: 38-12012 Rev. *M
ppm
parts per million
Page 19 of 53
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Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 14. Absolute Maximum Ratings
Min
Typ
Max
Unit
Notes
TSTG
Symbol
Storage Temperature
Description
-55
25
+100
oC
Higher storage temperatures reduce
data retention time. Recommended
storage temperature is +25°C ±
25°C. Extended duration storage
temperatures above 65oC degrade
reliability.
TA
Ambient Temperature with Power Applied
-40
–
+85
oC
Vdd
Supply Voltage on Vdd Relative to Vss
VIO
DC Input Voltage
VIOZ
DC Voltage Applied to Tri-state
IMIO
IMAIO
ESD
Electro Static Discharge Voltage
LU
Latch up Current
-0.5
–
+6.0
V
Vss- 0.5
–
Vdd + 0.5
V
Vss 0.5
–
Vdd + 0.5
V
Maximum Current into any Port Pin
-25
–
+50
mA
Maximum Current into any Port Pin Configured
as Analog Driver
-50
–
+50
mA
2000
–
–
V
–
–
200
mA
Min
-40
-40
Typ
–
–
Max
+85
+100
Unit
oC
oC
Human Body Model ESD.
Operating Temperature
Table 15. Operating Temperature
Symbol
Description
TA
Ambient Temperature
TJ
Junction Temperature
Document Number: 38-12012 Rev. *M
Notes
The temperature rise from ambient
to junction is package specific. See
“Thermal Impedances” on page 46.
The user must limit the power
consumption to comply with this
requirement.
Page 20 of 53
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DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 16. DC Chip-Level Specifications
Symbol
Description
Vdd
Supply Voltage
IDD
Supply Current
Min
3.00
–
Typ
–
5
Max
5.25
8
Unit
V
mA
IDD3
Supply Current
–
3.3
6.0
mA
ISB
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT.[3]
–
3
6.5
μA
ISBH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT at high temperature.[3]
–
4
25
μA
ISBXTL
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal.[3]
–
4
7.5
μA
ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal at high
temperature.[3]
VREF
Reference Voltage (Bandgap) for Silicon A [4]
VREF
Reference Voltage (Bandgap) for Silicon B [4]
–
5
26
μA
1.275
1.280
1.300
1.300
1.325
1.320
V
V
Notes
Conditions are Vdd = 5.0V, TA = 25 oC,
CPU = 3 MHz, SYSCLK doubler
disabled. VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75 kHz.
Conditions are Vdd = 3.3V, TA = 25 oC,
CPU = 3 MHz, SYSCLK doubler
disabled. VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75 kHz.
Conditions are with internal slow
speed oscillator, Vdd = 3.3V,
-40 oC ≤ TA ≤ 55 oC.
Conditions are with internal slow
speed oscillator, Vdd = 3.3V,
55 oC < TA ≤ 85 oC.
Conditions are with properly loaded, 1
μW max, 32.768 kHz crystal.
Vdd = 3.3V, -40 oC ≤ TA ≤ 55 oC.
Conditions are with properly loaded, 1
μW max, 32.768 kHz crystal.
Vdd = 3.3V, 55 oC < TA ≤ 85 oC.
Trimmed for appropriate Vdd.
Trimmed for appropriate Vdd.
Notes
3. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar
functions enabled.
4. Refer to the “Ordering Information” on page 50.
Document Number: 38-12012 Rev. *M
Page 21 of 53
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DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 17. DC GPIO Specifications
Symbol
Description
Pull up Resistor
RPU
Pull down Resistor
RPD
VOH
High Output Level
VOL
Low Output Level
VIL
VIH
VH
IIL
CIN
Input Low Level
Input High Level
Input Hysterisis
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
COUT
Capacitive Load on Pins as Output
Min
4
4
Vdd 1.0
Typ
5.6
5.6
–
Max
8
8
–
Unit
kΩ
kΩ
V
–
–
0.75
V
–
2.1
–
–
–
–
–
60
1
3.5
0.8
–
–
10
V
V
mV
nA
pF
–
3.5
10
pF
Notes
IOH = 10 mA, Vdd = 4.75 to 5.25V
(8 total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])).
IOL = 25 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])).
Vdd = 3.0 to 5.25
Vdd = 3.0 to 5.25
Gross tested to 1 μA.
Package and pin dependent.
Temp = 25oC.
Package and pin dependent.
Temp = 25oC.
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at
25°C and are for design guidance only.
Table 18. 5V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
TCVOSOA Average Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog Pins)
IEBOA
Input Capacitance (Port 0 Analog Pins)
CINOA
VCMOA
Common Mode Voltage Range
Common Mode Voltage Range (high power or
high opamp bias)
Document Number: 38-12012 Rev. *M
Min
Typ
Max
Unit
–
–
–
–
–
–
1.6
1.3
1.2
10
8
7.5
mV
mV
mV
7.0
20
4.5
35.0
–
9.5
0.0
0.5
–
–
Vdd
Vdd - 0.5
Notes
μV/oC
pA
Gross tested to 1 μA.
pF
Package and pin dependent.
Temp = 25oC.
V
The common-mode input
voltage range is measured
through an analog output
buffer. The specification
includes the limitations
imposed by the characteristics
of the analog output buffer.
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Table 18. 5V DC Operational Amplifier Specifications (continued)
Symbol
CMRROA
Description
Common Mode Rejection Ratio
Power = Low
Power = Medium
Power = High
GOLOA
Open Loop Gain
Power = Low
Power = Medium
Power = High
Typ
–
Max
–
Unit
dB
–
–
dB
Vdd - 0.2
Vdd - 0.2
Vdd - 0.5
–
–
–
–
–
–
V
V
V
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
μA
μA
μA
μA
μA
μA
60
–
–
dB
Min
Typ
Max
Unit
–
–
1.65
1.32
10
8
mV
mV
TCVOSOA Average Input Offset Voltage Drift
–
7.0
35.0
μV/oC
VOHIGHOA High Output Voltage Swing (internal signals)
Power = Low
Power = Medium
Power = High
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low
Power = Medium
Power = High
ISOA
Supply Current (including associated AGND
buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
PSRROA Supply Voltage Rejection Ratio
Min
60
60
60
60
60
80
Notes
Specification is applicable at
high power. For all other bias
modes (except high power,
high opamp bias), minimum is
60 dB.
Specification is applicable at
high power. For all other bias
modes (except high power,
high opamp bias), minimum is
60 dB.
Vss ≤ VIN ≤ (Vdd - 2.25) or
(Vdd - 1.25V) ≤ VIN ≤ Vdd.
Table 19. 3.3V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
High Power is 5 Volts Only
Notes
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
20
–
pA
Gross tested to 1 μA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25oC.
VCMOA
Common Mode Voltage Range
0.2
–
Vdd - 0.2
V
The common-mode input
voltage range is measured
through an analog output
buffer. The specification
includes the limitations
imposed by the characteristics
of the analog output buffer.
CMRROA
Common Mode Rejection Ratio
Power = Low
Power = Medium
Power = High
50
50
50
–
–
dB
Specification is applicable at
high power. For all other bias
modes (except high power,
high opamp bias), minimum is
60 dB.
Document Number: 38-12012 Rev. *M
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Table 19. 3.3V DC Operational Amplifier Specifications (continued)
Symbol
GOLOA
Description
Open Loop Gain
Power = Low
Power = Medium
Power = High
Min
60
60
80
Typ
Max
Unit
Notes
–
–
dB
Specification is applicable at
high power. For all other bias
modes (except high power,
high opamp bias), minimum is
60 dB.
VOHIGHOA High Output Voltage Swing (internal signals)
Power = Low
Power = Medium
Power = High is 5V only
Vdd - 0.2
Vdd - 0.2
Vdd - 0.2
–
–
–
–
–
–
V
V
V
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low
Power = Medium
Power = High
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
ISOA
Supply Current (including associated AGND
buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
μA
μA
μA
μA
μA
μA
PSRROA
Supply Voltage Rejection Ratio
50
80
–
dB
Vss ≤ VIN ≤ (Vdd - 2.25) or
(Vdd - 1.25V) ≤ VIN ≤ Vdd.
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 20. DC Low Power Comparator Specifications
Symbol
VREFLPC
ISLPC
VOSLPC
Description
Low power comparator (LPC) reference
voltage range
LPC supply current
LPC voltage offset
Document Number: 38-12012 Rev. *M
Min
0.2
Typ
–
Max
Vdd - 1
Unit
V
–
–
10
2.5
40
30
μA
mV
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DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 21. 5V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
VOHIGHOB
VOLOWOB
ISOB
PSRROB
Description
Min
Input Offset Voltage (Absolute Value)
–
Average Input Offset Voltage Drift
–
Common-Mode Input Voltage Range
0.5
Output Resistance
Power = Low
–
Power = High
–
High Output Voltage Swing (Load = 32 ohms
to Vdd/2)
0.5 x Vdd + 1.3
Power = Low
0.5 x Vdd + 1.3
Power = High
Low Output Voltage Swing (Load = 32 ohms
–
to Vdd/2)
–
Power = Low
Power = High
Supply Current Including Bias Cell (No Load)
Power = Low
–
Power = High
–
Supply Voltage Rejection Ratio
60
Typ
3
+6
–
Max
12
–
Vdd - 1.0
Unit
mV
μV/°C
V
1
1
–
–
W
W
–
–
–
–
V
V
–
–
0.5 x Vdd - 1.3
0.5 x Vdd - 1.3
V
V
1.1
2.6
64
5.1
8.8
–
mA
mA
dB
Typ
3
+6
-
Max
12
–
Vdd - 1.0
Units
mV
μV/°C
V
1
1
–
–
W
W
–
–
–
–
V
V
–
–
0.5 x Vdd - 1.0
0.5 x Vdd - 1.0
V
V
0.8
2.0
64
2.0
4.3
–
mA
mA
dB
Table 22. 3.3V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
VOHIGHOB
VOLOWOB
ISOB
PSRROB
Description
Min
Input Offset Voltage (Absolute Value)
–
Average Input Offset Voltage Drift
–
Common-Mode Input Voltage Range
0.5
Output Resistance
Power = Low
–
Power = High
–
High Output Voltage Swing (Load = 1k ohms
to Vdd/2)
0.5 x Vdd + 1.0
Power = Low
0.5 x Vdd + 1.0
Power = High
Low Output Voltage Swing (Load = 1k ohms
to Vdd/2)
–
Power = Low
–
Power = High
Supply Current Including Bias Cell (No Load)
Power = Low
–
Power = High
Supply Voltage Rejection Ratio
60
Document Number: 38-12012 Rev. *M
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DC Switch Mode Pump Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 23. DC Switch Mode Pump (SMP) Specifications
Symbol
Description
Min
Typ
Max
Unit
Notes
VPUMP 5V
5V Output Voltage
4.75
5.0
5.25
V
Configuration of footnote.[5] Average,
neglecting ripple. SMP trip voltage is
set to 5.0V.
VPUMP 3V
3V Output Voltage
3.00
3.25
3.60
V
Configuration of footnote.[5] Average,
neglecting ripple. SMP trip voltage is
set to 3.25V.
IPUMP
Available Output Current
VBAT = 1.5V, VPUMP = 3.25V
VBAT = 1.8V, VPUMP = 5.0V
8
5
–
–
–
–
mA
mA
VBAT5V
Input Voltage Range from Battery
1.8
–
5.0
V
Configuration of footnote.[5] SMP trip
voltage is set to 5.0V.
VBAT3V
Input Voltage Range from Battery
1.0
–
3.3
V
Configuration of footnote.[5] SMP trip
voltage is set to 3.25V.
VBATSTART
Minimum Input Voltage from Battery to
Start Pump
1.1
–
–
V
Configuration of footnote.[5]
ΔVPUMP_Line
Line Regulation (over VBAT range)
–
5
–
%VO
Configuration of footnote.[5] VO is the
“Vdd Value for PUMP Trip” specified
by the VM[2:0] setting in the DC POR
and LVD Specification, Table 29 on
page 30.
ΔVPUMP_Load
Load Regulation
–
5
–
%VO
Configuration of footnote.[5] VO is the
“Vdd Value for PUMP Trip” specified
by the VM[2:0] setting in the DC POR
and LVD Specification, Table 29 on
page 30.
ΔVPUMP_Ripple Output Voltage Ripple (depends on
capacitor/load)
–
100
–
mVpp Configuration of footnote.[5] Load is 5
mA.
E3
Efficiency
35
50
–
%
FPUMP
Switching Frequency
–
1.3
–
MHz
DCPUMP
Switching Duty Cycle
–
50
–
%
Configuration of footnote.[5]
SMP trip voltage is set to 3.25V.
SMP trip voltage is set to 5.0V.
Configuration of footnote.[5] Load is 5
mA. SMP trip voltage is set to 3.25V.
Note
5. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 11.
Document Number: 38-12012 Rev. *M
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Figure 11. Basic Switch Mode Pump Circuit
D1
Vdd
L1
V BAT
+
V PUMP
C1
SMP
Battery
PSoC TM
Vss
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling
of the digital signal may appear on the AGND.
Table 24. Silicon Revision A – 5V DC Analog Reference Specifications
Symbol
BG
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Description
Bandgap Voltage Reference
AGND = Vdd/2[6]
AGND = 2 x BandGap[6]
AGND = P2[4] (P2[4] = Vdd/2)[6]
AGND = BandGap[6]
AGND = 1.6 x BandGap[6]
AGND Block to Block Variation
(AGND = Vdd/2)[6]
RefHi = Vdd/2 + BandGap
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6]
(P2[6] = 1.3V)
RefHi = P2[4] + BandGap
(P2[4] = Vdd/2)
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,
P2[6] = 1.3V)
RefHi = 3.2 x BandGap
RefLo = Vdd/2 – BandGap
RefLo = BandGap
RefLo = 2 x BandGap - P2[6]
(P2[6] = 1.3V)
RefLo = P2[4] – BandGap
(P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2,
P2[6] = 1.3V)
Min
1.274
Vdd/2 - 0.030
2 x BG - 0.043
P2[4] - 0.013
BG - 0.009
1.6 x BG - 0.018
-0.034
Typ
1.30
Vdd/2 - 0.004
2 x BG - 0.010
P2[4]
BG
1.6 x BG
0.000
Max
1.326
Vdd/2 + 0.003
2 x BG + 0.024
P2[4] + 0.014
BG + 0.009
1.6 x BG + 0.018
0.034
Unit
V
V
V
V
V
V
V
Vdd/2 + BG - 0.140
3 x BG - 0.112
2 x BG + P2[6] - 0.113
Vdd/2 + BG - 0.018
3 x BG - 0.018
2 x BG + P2[6] - 0.018
Vdd/2 + BG + 0.103
3 x BG + 0.076
2 x BG + P2[6] + 0.077
V
V
V
P2[4] + BG - 0.130
P2[4] + BG - 0.016
P2[4] + BG + 0.098
V
P2[4] + P2[6] - 0.133
P2[4] + P2[6] - 0.016
P2[4] + P2[6] + 0.100
V
3.2 x BG - 0.112
Vdd/2 - BG - 0.051
BG - 0.082
2 x BG - P2[6] - 0.084
3.2 x BG
Vdd/2 - BG + 0.024
BG + 0.023
2 x BG - P2[6] + 0.025
3.2 x BG + 0.076
Vdd/2 - BG + 0.098
BG + 0.129
2 x BG - P2[6] + 0.134
V
V
V
V
P2[4] - BG - 0.056
P2[4] - BG + 0.026
P2[4] - BG + 0.107
V
P2[4] - P2[6] - 0.057
P2[4] - P2[6] + 0.026
P2[4] - P2[6] + 0.110
V
Note
6. AGND tolerance includes the offsets of the local buffer in the PSoC block.
Document Number: 38-12012 Rev. *M
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Table 25. Silicon Revision B – 5V DC Analog Reference Specifications
Symbol
BG
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Description
Bandgap Voltage Reference
AGND = Vdd/2[7]
AGND = 2 x BandGap[7]
AGND = P2[4] (P2[4] = Vdd/2)[7]
AGND = BandGap[7]
AGND = 1.6 x BandGap[7]
AGND Block to Block Variation
(AGND = Vdd/2)[7]
RefHi = Vdd/2 + BandGap
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6]
(P2[6] = 1.3V)
RefHi = P2[4] + BandGap
(P2[4] = Vdd/2)
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,
P2[6] = 1.3V)
RefHi = 3.2 x BandGap
RefLo = Vdd/2 – BandGap
RefLo = BandGap
RefLo = 2 x BandGap - P2[6]
(P2[6] = 1.3V)
RefLo = P2[4] – BandGap
(P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2,
P2[6] = 1.3V)
Min
Typ
Max
Unit
V
V
V
V
V
V
V
1.28
Vdd/2 - 0.030
2 x BG - 0.043
P2[4] - 0.011
BG - 0.009
1.6 x BG - 0.018
-0.034
1.30
Vdd/2
2 x BG
P2[4]
BG
1.6 x BG
0.000
1.32
Vdd/2 + 0.007
2 x BG + 0.024
P2[4] + 0.011
BG + 0.009
1.6 x BG + 0.018
0.034
Vdd/2 + BG - 0.1
3 x BG - 0.06
2 x BG + P2[6] - 0.06
Vdd/2 + BG - 0.01
3 x BG - 0.01
2 x BG + P2[6] - 0.01
Vdd/2 + BG + 0.1
3 x BG + 0.06
2 x BG + P2[6] + 0.06
V
V
V
P2[4] + BG - 0.06
P2[4] + BG - 0.01
P2[4] + BG + 0.06
V
P2[4] + P2[6] - 0.06
P2[4] + P2[6] - 0.01
P2[4] + P2[6] + 0.06
V
3.2 x BG - 0.06
Vdd/2 - BG - 0.051
BG - 0.06
2 x BG - P2[6] - 0.04
3.2 x BG - 0.01
Vdd/2 - BG + 0.01
BG + 0.01
2 x BG - P2[6] + 0.01
3.2 x BG + 0.06
Vdd/2 - BG + 0.06
BG + 0.06
2 x BG - P2[6] + 0.04
V
V
V
V
P2[4] - BG - 0.056
P2[4] - BG + 0.01
P2[4] - BG + 0.056
V
P2[4] - P2[6] - 0.056
P2[4] - P2[6] + 0.01
P2[4] - P2[6] + 0.056
V
Table 26. Silicon Revision A – 3.3V DC Analog Reference Specifications
Symbol
BG
–
–
–
–
–
–
–
–
–
–
–
–
–
Description
Bandgap Voltage Reference
AGND = Vdd/2[8]
AGND = 2 x BandGap[8]
AGND = P2[4] (P2[4] = Vdd/2)
AGND = BandGap[8]
AGND = 1.6 x BandGap[8]
AGND Block to Block Variation
(AGND = Vdd/2)[8]
RefHi = Vdd/2 + BandGap
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6]
(P2[6] = 0.5V)
RefHi = P2[4] + BandGap
(P2[4] = Vdd/2)
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,
P2[6] = 0.5V)
RefHi = 3.2 x BandGap
RefLo = Vdd/2 - BandGap
Min
1.274
Vdd/2 - 0.027
Not Allowed
P2[4] - 0.008
BG - 0.009
1.6 x BG - 0.018
-0.034
Typ
1.30
Vdd/2 - 0.003
Max
1.326
Vdd/2 + 0.002
Unit
V
V
P2[4] + 0.001
BG
1.6 x BG
0.000
P2[4] + 0.009
BG + 0.009
1.6 x BG + 0.018
0.034
V
V
V
V
P2[4] + P2[6] - 0.009
P2[4] + P2[6] + 0.057
V
Not Allowed
Not Allowed
Not Allowed
Not Allowed
P2[4] + P2[6] - 0.075
Not Allowed
Not Allowed
Note
7. AGND tolerance includes the offsets of the local buffer in the PSoC block.
Document Number: 38-12012 Rev. *M
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Table 26. Silicon Revision A – 3.3V DC Analog Reference Specifications (continued)
Symbol
Description
–
RefLo = BandGap
–
RefLo = 2 x BandGap - P2[6]
(P2[6] = 0.5V)
–
RefLo = P2[4] – BandGap
(P2[4] = Vdd/2)
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2,
P2[6] = 0.5V)
Min
Not Allowed
Not Allowed
Typ
Max
Unit
P2[4] - P2[6] + 0.092
V
Not Allowed
P2[4] - P2[6] - 0.048
P2[4] - P2[6] + 0.022
Table 27. Silicon Revision B – 3.3V DC Analog Reference Specifications
Symbol
BG
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Description
Bandgap Voltage Reference
AGND = Vdd/2[8]
AGND = 2 x BandGap[8]
AGND = P2[4] (P2[4] = Vdd/2)
AGND = BandGap[8]
AGND = 1.6 x BandGap[8]
AGND Block to Block Variation
(AGND = Vdd/2)[8]
RefHi = Vdd/2 + BandGap
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6]
(P2[6] = 0.5V)
RefHi = P2[4] + BandGap
(P2[4] = Vdd/2)
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,
P2[6] = 0.5V)
RefHi = 3.2 x BandGap
RefLo = Vdd/2 - BandGap
RefLo = BandGap
RefLo = 2 x BandGap - P2[6]
(P2[6] = 0.5V)
RefLo = P2[4] – BandGap
(P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2,
P2[6] = 0.5V)
Min
1.28
Vdd/2 - 0.027
Not Allowed
P2[4] - 0.008
BG - 0.009
1.6 x BG - 0.018
-0.034
1.30
Vdd/2
Typ
Max
1.32
Vdd/2 + 0.005
Unit
V
V
P2[4]
BG
1.6 x BG
0.000
P2[4] + 0.009
BG + 0.009
1.6 x BG + 0.018
0.034
V
V
V
mV
P2[4] + P2[6] - 0.01
P2[4] + P2[6] + 0.057
V
P2[4] - P2[6] + 0.01
P2[4] - P2[6] + 0.048
V
Not Allowed
Not Allowed
Not Allowed
Not Allowed
P2[4] + P2[6] - 0.06
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
P2[4] - P2[6] - 0.048
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 28. DC Analog PSoC Block Specifications
Symbol
RCT
CSC
Description
Resistor Unit Value (Continuous Time)
Capacitor Unit Value (Switch Cap)
Min
–
–
Typ
12.2
80
Max
–
–
Unit
kΩ
fF
Note
8. AGND tolerance includes the offsets of the local buffer in the PSoC block.
See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.
Document Number: 38-12012 Rev. *M
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DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Programmable System-on-Chip
Technical Reference Manual for more information on the VLT_CR register.
Table 29. DC POR and LVD Specifications
Symbol
Description
VPPOR0R
VPPOR1R
VPPOR2R
Vdd Value for PPOR Trip (positive ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VPPOR0
VPPOR1
VPPOR2
Vdd Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VPH0
VPH1
VPH2
PPOR Hysteresis
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VPUMP0
VPUMP1
VPUMP2
VPUMP3
VPUMP4
VPUMP5
VPUMP6
VPUMP7
Min
Typ
Max
Unit
Notes
Vdd must be greater than or equal
to 2.5V during startup, reset from
the XRES pin, or reset from
Watchdog.
–
2.91
4.39
4.55
–
V
V
V
–
2.82
4.39
4.55
–
V
V
V
–
–
–
92
0
0
–
–
–
mV
mV
mV
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.86
2.96
3.07
3.92
4.39
4.55
4.63
4.72
2.92
3.02
3.13
4.00
4.48
4.64
4.73
4.81
2.98[9]
3.08
3.20
4.08
4.57
4.74[10]
4.82
4.91
V
V
V
V
V
V
V
V
V
Vdd Value for PUMP Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.96
3.03
3.18
4.11
4.55
4.63
4.72
4.90
3.02
3.10
3.25
4.19
4.64
4.73
4.82
5.00
3.08
3.16
3.32
4.28
4.74
4.82
4.91
5.10
V
V
V
V
V
V
V
V
V
Notes
9. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
10. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
Document Number: 38-12012 Rev. *M
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DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 30. DC Programming Specifications
Symbol
IDDP
VILP
Description
Min
Supply Current During Programming or Verify
–
Input Low Voltage During Programming or
–
Verify
VIHP
Input High Voltage During Programming or
2.2
Verify
IILP
Input Current when Applying Vilp to P1[0] or
–
P1[1] During Programming or Verify
IIHP
Input Current when Applying Vihp to P1[0] or
–
P1[1] During Programming or Verify
VOLV
Output Low Voltage During Programming or
–
Verify
VOHV
Output High Voltage During Programming or Vdd - 1.0
Verify
FlashENP Flash Endurance (per block)
50,000
Typ
5
–
Max
25
0.8
Unit
mA
V
Notes
–
–
V
–
0.2
mA
–
1.5
mA
–
V
–
Vss +
0.75
Vdd
–
–
–
Erase/write cycles per block.
–
–
–
Erase/write cycles.
–
–
Years
Driving internal pull-down
resistor.
Driving internal pull-down
resistor.
V
B
FlashENT Flash Endurance (total)[11]
FlashDR
Flash Data Retention
1,800,0
00
10
Note
11. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block
ever sees more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information
Document Number: 38-12012 Rev. *M
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AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 31. AC Chip-Level Specifications
Symbol
FIMO
Description
Internal Main Oscillator Frequency
Min
23.4
Typ
24
Max
24.6[12]
Unit
MHz
FCPU1
CPU Frequency (5V Nominal)
0.93
24
24.6[12,13]
MHz
FCPU2
CPU Frequency (3.3V Nominal)
0.93
12
12.3[13,14]
MHz
F48M
Digital PSoC Block Frequency
0
48
49.2[12,13, 15]
MHz
F24M
F32K1
F32K2
Digital PSoC Block Frequency
Internal Low Speed Oscillator Frequency
External Crystal Oscillator
0
15
–
24
32
32.768
24.6[13, 15]
64
–
MHz
kHz
kHz
FPLL
PLL Frequency
–
23.986
–
MHz
–
0.5
0.5
–
–
–
600
10
50
ps
ms
ms
–
–
1700
2800
2620
3800
ms
ms
–
10
40
–
46.8
100
–
50
50
48.0
–
60
–
49.2[12,14]
ns
μs
%
kHz
MHz
–
–
600
–
12.3
ps
MHz
0
–
–
μs
Jitter24M2 24 MHz Period Jitter (PLL)
TPLLSLEW PLL Lock Time
TPLLSLEWS PLL Lock Time for Low Gain Setting
Notes
Trimmed. Utilizing factory trim
values.
Trimmed. Utilizing factory trim
values.
Trimmed. Utilizing factory trim
values.
Refer to the AC Digital Block
Specifications below.
Accuracy is capacitor and crystal
dependent. 50% duty cycle.
Multiple (x732) of crystal
frequency.
LOW
TOS
TOSACC
External Crystal Oscillator Startup to 1%
External Crystal Oscillator Startup to 100
ppm
Jitter32k
TXRST
DC24M
Step24M
Fout48M
32 kHz Period Jitter
External Reset Pulse Width
24 MHz Duty Cycle
24 MHz Trim Step Size
48 MHz Output Frequency
Jitter24M1
FMAX
24 MHz Period Jitter (IMO)
Maximum frequency of signal on row
input or row output.
Supply Ramp Time
TRAMP
The crystal oscillator frequency is
within 100 ppm of its final value
by the end of the Tosacc period.
Correct operation assumes a
properly loaded 1 µW maximum
drive level 32.768 kHz crystal.
3.0V ≤ Vdd ≤ 5.5V,
-40°C ≤ TA ≤ 85°C.
Trimmed. Utilizing factory trim
values.
Notes
12. 4.75V < Vdd < 5.25V.
13. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
14. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3V.
15. See the individual user module data sheets for information on maximum frequencies for user modules.
Document Number: 38-12012 Rev. *M
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Figure 12. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 13. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 14. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Figure 15. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F 24M
Figure 16. 32 kHz Period Jitter (ECO) Timing Diagram
Jitter32k
F 32K2
Document Number: 38-12012 Rev. *M
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AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 32. AC GPIO Specifications
Symbol
FGPIO
TRiseF
TFallF
TRiseS
TFallS
Description
GPIO Operating Frequency
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
Min
0
3
2
10
10
Typ
–
–
–
27
22
Max
12
18
18
–
–
Unit
MHz
ns
ns
ns
ns
Notes
Normal Strong Mode
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Figure 17. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 33. 5V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
Description
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Document Number: 38-12012 Rev. *M
Min
Typ
Max
Unit
–
–
–
–
–
–
3.9
0.72
0.62
μs
μs
μs
–
–
–
–
–
–
5.9
0.92
0.72
μs
μs
μs
0.15
1.7
6.5
–
–
–
–
–
–
V/μs
V/μs
V/μs
0.01
0.5
4.0
–
–
–
–
–
–
V/μs
V/μs
V/μs
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Table 33. 5V AC Operational Amplifier Specifications (continued)
Symbol
BWOA
ENOA
Description
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
Min
Typ
Max
Unit
0.75
3.1
5.4
–
–
–
–
100
–
–
–
–
MHz
MHz
MHz
nV/rt-Hz
Min
Typ
Max
Units
–
–
–
–
3.92
0.72
μs
μs
–
–
–
–
5.41
0.72
μs
μs
0.31
2.7
–
–
–
–
V/μs
V/μs
0.24
1.8
–
–
–
–
V/μs
V/μs
0.67
2.8
–
–
–
100
–
–
–
MHz
MHz
nV/rt-Hz
Table 34. 3.3V AC Operational Amplifier Specifications
Symbol
Description
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain)
TROA
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
TSOA
SRROA
SRFOA
BWOA
ENOA
Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 18. Typical AGND Noise with P2[4] Bypass
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Document Number: 38-12012 Rev. *M
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Figure 19. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
0.01
0.1
1
Freq (kHz)
10
100
AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 35. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Unit
μs
Notes
≥ 50 mV overdrive comparator
reference set within VREFLPC.
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 36. AC Digital Block Specifications
Function
Description
Min
Typ
All
Maximum Block Clocking Frequency (> 4.75V)
Functions Maximum Block Clocking Frequency (< 4.75V)
Timer
Capture Pulse Width
Maximum Frequency, No Capture
Maximum Frequency, With Capture
Counter
Max
Unit
49.2
4.75V < Vdd < 5.25V
24.6
3.0V < Vdd < 4.75V
50[16]
–
–
ns
–
–
49.2
MHz
–
–
24.6
MHz
50[16]
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.2
MHz
Maximum Frequency, Enable Input
–
–
24.6
MHz
Enable Pulse Width
Notes
4.75V < Vdd < 5.25V
4.75V < Vdd < 5.25V
Notes
16. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
17. Refer to Table 47 on page 50
Document Number: 38-12012 Rev. *M
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Table 36. AC Digital Block Specifications (continued)
Function
Dead
Band
Description
Min
Typ
Max
Unit
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50[16]
–
–
ns
Disable Mode
50[16]
–
–
ns
Notes
Kill Pulse Width:
Maximum Frequency
–
–
49.2
MHz
4.75V < Vdd < 5.25V
CRCPRS Maximum Input Clock Frequency
(PRS
Mode)
–
–
49.2
MHz
4.75V < Vdd < 5.25V
CRCPRS Maximum Input Clock Frequency
(CRC
Mode)
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
SPIS
Maximum Input Clock Frequency
–
–
4.1
MHz
50[16]
–
–
MHz
Maximum Input Clock Frequency [16]
Silicon A
–
–
16.4
MHz
Silicon B
–
–
24.6
MHz
Silicon B Maximum Input Clock Frequency with
Vdd ≥ 4.75V, 2 Stop Bits
–
–
49.2
MHz
Maximum Input Clock Frequency [17]
Silicon A
–
–
16.4
MHz
Silicon B
–
–
24.6
MHz
Silicon B Maximum Input Clock Frequency with
Vdd ≥ 4.75V, 2 Stop Bits
–
–
49.2
MHz
Width of SS_ Negated Between Transmissions
Transmitter
Receiver
Document Number: 38-12012 Rev. *M
Maximum data rate at 4.1 MHz due
to 2 x over clocking.
Maximum data rate at 2.05 MHz
due to 8 x over clocking.
Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Maximum data rate at 6.15 MHz
due to 8 x over clocking.
Maximum data rate at 2.05 MHz
due to 8 x over clocking.
Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Maximum data rate at 6.15 MHz
due to 8 x over clocking.
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AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 37. 5V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High
Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load
Power = Low
Power = High
Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load
Power = Low
Power = High
Min
Typ
Max
Unit
–
–
–
–
2.5
2.5
μs
μs
–
–
–
–
2.2
2.2
μs
μs
0.65
0.65
–
–
–
–
V/μs
V/μs
0.65
0.65
–
–
–
–
V/μs
V/μs
0.8
0.8
–
–
–
–
MHz
MHz
300
300
–
–
–
–
kHz
kHz
Min
Typ
Max
Unit
–
–
–
–
3.8
3.8
μs
μs
–
–
–
–
2.6
2.6
μs
μs
0.5
0.5
–
–
–
–
V/μs
V/μs
0.5
0.5
–
–
–
–
V/μs
V/μs
0.7
0.7
–
–
–
–
MHz
MHz
200
200
–
–
–
–
kHz
kHz
Table 38. 3.3V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High
Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load
Power = Low
Power = High
Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load
Power = Low
Power = High
Document Number: 38-12012 Rev. *M
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AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 39. 5V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Unit
FOSCEXT
Frequency
0.093
–
24.6
MHz
–
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Table 40. 3.3V AC External Clock Specifications
Min
Typ
Max
Unit
FOSCEXT
Symbol
Frequency with CPU Clock divide by 1[18]
Description
0.093
–
12.3
MHz
FOSCEXT
Frequency with CPU Clock divide by 2 or greater[19]
0.186
–
24.6
MHz
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 41. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
TERASEB
TWRITE
TDSCLK
TDSCLK3
Description
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Min
1
1
40
40
0
–
–
–
–
Typ
–
–
–
–
–
10
10
–
–
Max
20
20
–
–
8
–
–
45
50
Unit
ns
ns
ns
ns
MHz
ms
ms
ns
ns
Notes
Vdd > 3.6
3.0 ≤ Vdd ≤ 3.6
Notes
18. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle
requirements.
19. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the
fifty percent duty cycle requirement is met.
Document Number: 38-12012 Rev. *M
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AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 42. AC Characteristics of the I2C SDA and SCL Pins
Symbol
FSCLI2C
THDSTAI2C
TLOWI2C
THIGHI2C
TSUSTAI2C
THDDATI2C
TSUDATI2C
TSUSTOI2C
TBUFI2C
TSPI2C
Description
SCL Clock Frequency
Hold Time (repeated) START Condition. After this period, the first
clock pulse is generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Set-up Time for a Repeated START Condition
Data Hold Time
Data Set-up Time
Set-up Time for STOP Condition
Bus Free Time Between a STOP and START Condition
Pulse Width of spikes are suppressed by the input filter.
Standard Mode
Min
Max
0
100
4.0
–
4.7
4.0
4.7
0
250
4.0
4.7
–
Fast Mode
Min
Max
0
400
0.6
–
–
–
–
–
–
–
–
–
1.3
0.6
0.6
0
100[20]
0.6
1.3
0
–
–
–
–
–
–
–
50
Unit
kHz
μs
μs
μs
μs
μs
ns
μs
μs
ns
Figure 20. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Note
20. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This is automatically the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 38-12012 Rev. *M
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Packaging Information
This section illustrates the packaging specifications for the CY8C27x43 PSoC device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Packaging Dimensions
Figure 21. 8-Pin (300-Mil) PDIP
51-85075 *A
Document Number: 38-12012 Rev. *M
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Figure 22. 20-Pin (210-Mil) SSOP
51-85077 *C
Figure 23. 20-Pin (300-Mil) Molded SOIC
51-85024 *C
Document Number: 38-12012 Rev. *M
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Figure 24. 28-Pin (300-Mil) Molded DIP
51-85014 *D
Figure 25. 28-Pin (210-Mil) SSOP
51-85079 *C
Document Number: 38-12012 Rev. *M
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Figure 26. 28-Pin (300-Mil) Molded SOIC
51-85026 *D
Figure 27. 44-Pin TQFP
51-85064 *C
Document Number: 38-12012 Rev. *M
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Figure 28. 48-Pin (300-Mil) SSOP
51-85061
*C
51-85061-C
Figure 29. 48-Pin QFN 7X7X 0.90 MM (Sawn Type)
001-13191 *C
Document Number: 38-12012 Rev. *M
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Figure 30. 48-Pin (7x7 mm) QFN
51-85152 *C
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Thermal Impedances
Capacitance on Crystal Pins
Table 43. Thermal Impedances per Package
Table 44. Typical Package Capacitance on Crystal Pins
Package
Typical θJA *
Package
Package Capacitance
8 PDIP
120 oC/W
8 PDIP
2.8 pF
20 SSOP
116
oC/W
20 SSOP
2.6 pF
20 SOIC
79 oC/W
20 SOIC
2.5 pF
28 PDIP
67
oC/W
28 PDIP
3.5 pF
28 SSOP
95 oC/W
28 SSOP
2.8 pF
28 SOIC
68
oC/W
28 SOIC
2.7 pF
44 TQFP
61 oC/W
44 TQFP
2.6 pF
48 SSOP
oC/W
48 SSOP
3.3 pF
48 QFN
2.3 pF
48 QFN
69
18 oC/W
* TJ = TA + POWER x θJA
Document Number: 38-12012 Rev. *M
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Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 45. Solder Reflow Peak Temperature
Silicon A*
Silicon B*
Package
Minimum Peak
Temperature**
Maximum Peak
Temperature
Minimum Peak
Temperature*
Maximum Peak
Temperature
8 PDIP
220oC
240oC
240oC
260oC
20 SSOP
220oC
240oC
240oC
260oC
20 SOIC
220oC
240oC
220oC
260oC
28 PDIP
220oC
240oC
240oC
260oC
28 SSOP
220oC
240oC
240oC
260oC
28 SOIC
220oC
240oC
220oC
260oC
44 TQFP
220oC
240oC
220oC
260oC
48 SSOP
220oC
240oC
220oC
260oC
48 QFN
220oC
240oC
240oC
260oC
*Refer to Table 47 on page 50.
**Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC
with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
Document Number: 38-12012 Rev. *M
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Development Tool Selection
■
iMAGEcraft C Compiler (Registration Required)
■
ISSP Cable
■
USB 2.0 Cable and Blue Cat-5 Cable
Software
■
2 CY8C29466-24PXI 28-PDIP Chip Samples
PSoC Designer™
CY3210-ExpressDK PSoC Express Development Kit
At the core of the PSoC development software suite is PSoC
Designer. Utilized by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for half a decade.
PSoC Designer is available free of charge at
http://www.cypress.com under DESIGN RESOURCES >>
Software and Drivers.
The CY3210-ExpressDK is for advanced prototyping and development with PSoC Express (may be used with ICE-Cube
In-Circuit Emulator). It provides access to I2C buses, voltage
reference, switches, upgradeable modules and more. The kit
includes:
This chapter presents the development tools available for all
current PSoC device families including the CY8C27x43 family.
■
PSoC Express Software CD
■
Express Development Board
■
4 Fan Modules
■
2 Proto Modules
■
MiniProg In-System Serial Programmer
■
MiniEval PCB Evaluation Board
■
Jumper Wire Kit
CY3202-C iMAGEcraft C Compiler
■
USB 2.0 Cable
CY3202 is the optional upgrade to PSoC Designer that enables
the iMAGEcraft C compiler. It can be purchased from the
Cypress Online Store. At http://www.cypress.com, click the
Online Store shopping cart icon at the bottom of the web page,
and click PSoC (Programmable System-on-Chip) to view a
current list of available items.
■
Serial Cable (DB9)
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
2 CY8C24423A-24PXI 28-PDIP Chip Samples
■
2 CY8C27443-24PXI 28-PDIP Chip Samples
■
2 CY8C29466-24PXI 28-PDIP Chip Samples
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer or PSoC Express. PSoC
Programmer software is compatible with both PSoC ICE-Cube
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free ofcharge at http://www.cypress.com/psocprogrammer.
Development Kits
All development kits can be purchased from the Cypress Online
Store.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface allows users to run, halt, and single step the processor
and view the content of specific memory locations. Advance
emulation features also supported through PSoC Designer. The
kit includes:
■
PSoC Designer Software CD
■
ICE-Cube In-Circuit Emulator
■
ICE Flex-Pod for CY8C29x66 Family
■
Cat-5 Adapter
■
Mini-Eval Programming Board
■
110 ~ 240V Power Supply, Euro-Plug Adapter
Document Number: 38-12012 Rev. *M
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online
Store.
CY3210-MiniProg1
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
MiniProg Programming Unit
■
MiniEval Socket Programming and Evaluation Board
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
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CY3210-PSoCEval1
Device Programmers
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
All device programmers can be purchased from the Cypress
Online Store.
CY3216 Modular Programmer
■
Evaluation Board with LCD Module
■
MiniProg Programming Unit
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
Modular Programmer Base
■
PSoC Designer Software CD
■
3 Programming Module Cards
■
Getting Started Guide
■
MiniProg Programming Unit
■
USB 2.0 Cable
■
PSoC Designer Software CD
CY3214-PSoCEvalUSB
■
Getting Started Guide
The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special
features of the board include both USB and capacitive sensing
development and debugging support. This evaluation board also
includes an LCD module, potentiometer, LEDs, an enunciator
and plenty of bread boarding space to meet all of your evaluation
needs. The kit includes:
■
USB 2.0 Cable
CY3207ISSP In-System Serial Programmer (ISSP)
■
PSoCEvalUSB Board
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note: CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
■
LCD Module
■
CY3207 Programmer Unit
■
MIniProg Programming Unit
■
PSoC ISSP Software CD
■
Mini USB Cable
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
PSoC Designer and Example Projects CD
■
USB 2.0 Cable
■
Getting Started Guide
■
Wire Pack
Accessories (Emulation and Programming)
Table 46. Emulation and Programming Accessories
Part #
Pin Package
Flex-Pod Kit[21]
Foot Kit[22]
CY8C27143-24PXI
8 PDIP
CY3250-27XXX
CY3250-8PDIP-FK
CY8C27243-24PVXI
20 SSOP
CY3250-27XXX
CY3250-20SSOP-FK
CY8C27243-24SXI
20 SOIC
CY3250-27XXX
CY3250-20SOIC-FK
CY8C27443-24PXI
28 PDIP
CY3250-27XXX
CY3250-28PDIP-FK
CY8C27443-24PVXI
28 SSOP
CY3250-27XXX
CY3250-28SSOP-FK
CY8C27443-24SXI
28 SOIC
CY3250-27XXX
CY3250-28SOIC-FK
CY8C27543-24AXI
44 TQFP
CY3250-27XXX
CY3250-44TQFP-FK
CY8C27643-24PVXI
48 SSOP
CY3250-27XXX
CY3250-48SSOP-FK
CY8C27643-24LFXI
48 QFN
CY3250-27XXXQFN
CY3250-48QFN-FK
Adapter[23]
Adapters can be found at
http://www.emulation.com.
Notes
21. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
22. Foot kit includes surface mount feet that can be soldered to the target PCB.
23. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com.
Document Number: 38-12012 Rev. *M
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3rd-Party Tools
Build a PSoC Emulator into Your Board
Several tools have been specially designed by the following
3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools
can be found at http://www.cypress.com under DESIGN
RESOURCES >> Evaluation Boards.
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, see Application Note “Debugging - Build a PSoC
Emulator
into
Your
Board
AN2323”
at
http://www.cypress.com/an2323.
Ordering Information
The following table lists the CY8C27x43 PSoC device’s key package features and ordering codes.
XRES Pin
Analog
Outputs
Analog
Inputs
Digital IO
Pins
Analog Blocks
(Columns of 3)
Digital Blocks
(Rows of 4)
Temperature
Range
Switch Mode
Pump
RAM
(Bytes)
Flash
(Bytes)
Package
Ordering
Code
Table 47. CY8C27x43 PSoC Device Key Features and Ordering Information
CY8C27x43 Silicon B – These parts are lead free and offer the following improvements. The DEC_CR1 register selections are enhanced to allow any digital block to be
the decimator clock source, the ECO EX and ECO EXW bits in the CPU_SCR1 register are readable, and the accuracy of the analog reference is enhanced (see the
Electrical Specifications chapter). All silicon A errata are fixed in silicon B.
8 Pin (300 Mil) DIP
CY8C27143-24PXI
16K
256
No
-40C to +85C
8
12
6
4
4
No
20 Pin (210 Mil) SSOP
CY8C27243-24PVXI
16K
256
Yes
-40C to +85C
8
12
16
8
4
Yes
20 Pin (210 Mil) SSOP
(Tape and Reel)
CY8C27243-24PVXIT
16K
256
Yes
-40C to +85C
8
12
16
8
4
Yes
20 Pin (300 Mil) SOIC
CY8C27243-24SXI
16K
256
Yes
-40C to +85C
8
12
16
8
4
Yes
20 Pin 300 Mil) SOIC
(Tape and Reel)
CY8C27243-24SXIT
16K
256
Yes
-40C to +85C
8
12
16
8
4
Yes
28 Pin (300 Mil) DIP
CY8C27443-24PXI
16K
256
Yes
-40C to +85C
8
12
24
12
4
Yes
28 Pin (210 Mil) SSOP
CY8C27443-24PVXI
16K
256
Yes
-40C to +85C
8
12
24
12
4
Yes
28 Pin (210 Mil) SSOP
(Tape and Reel)
CY8C27443-24PVXIT
16K
256
Yes
-40C to +85C
8
12
24
12
4
Yes
28 Pin (300 Mil) SOIC
CY8C27443-24SXI
16K
256
Yes
-40C to +85C
8
12
24
12
4
Yes
28 Pin (300 Mil) SOIC
(Tape and Reel)
CY8C27443-24SXIT
16K
256
Yes
-40C to +85C
8
12
24
12
4
Yes
44 Pin TQFP
CY8C27543-24AXI
16K
256
Yes
-40C to +85C
8
12
40
12
4
Yes
44 Pin TQFP
(Tape and Reel)
CY8C27543-24AXIT
16K
256
Yes
-40C to +85C
8
12
40
12
4
Yes
48 Pin (300 Mil) SSOP
CY8C27643-24PVXI
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
48 Pin (300 Mil) SSOP
(Tape and Reel)
CY8C27643-24PVXIT
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
48 Pin (7x7) QFN
CY8C27643-24LFXI
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
48 Pin (7x7) QFN
(Tape and Reel)
CY8C27643-24LFXIT
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
56 Pin OCD SSOP
CY8C27002-24PVXI[24]
16K
256
Yes
-40C to +85C
8
12
44
14
4
Yes
CY8C27x43 Silicon A – Silicon A is not recommended for new designs.
8 Pin (300 Mil) DIP
CY8C27143-24PI
16K
256
No
-40C to +85C
8
12
6
4
4
No
20 Pin (210 Mil) SSOP
CY8C27243-24PVI
16K
256
Yes
-40C to +85C
8
12
16
8
4
Yes
20 Pin (210 Mil) SSOP
(Tape and Reel)
CY8C27243-24PVIT
16K
256
Yes
-40C to +85C
8
12
16
8
4
Yes
20 Pin (300 Mil) SOIC
CY8C27243-24SI
16K
256
Yes
-40C to +85C
8
12
16
8
4
Yes
20 Pin 300 Mil) SOIC
(Tape and Reel)
CY8C27243-24SIT
16K
256
Yes
-40C to +85C
8
12
16
8
4
Yes
28 Pin (300 Mil) DIP
CY8C27443-24PI
16K
256
Yes
-40C to +85C
8
12
24
12
4
Yes
28 Pin (210 Mil) SSOP
CY8C27443-24PVI
16K
256
Yes
-40C to +85C
8
12
24
12
4
Yes
28 Pin (210 Mil) SSOP
(Tape and Reel)
CY8C27443-24PVIT
16K
256
Yes
-40C to +85C
8
12
24
12
4
Yes
Note
24. This part may be used for in-circuit debugging. It is NOT available for production.
Document Number: 38-12012 Rev. *M
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CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
RAM
(Bytes)
Switch Mode
Pump
Temperature
Range
Digital Blocks
(Rows of 4)
Analog Blocks
(Columns of 3)
Digital IO
Pins
Analog
Inputs
Analog
Outputs
XRES Pin
28 Pin (300 Mil) SOIC
CY8C27443-24SI
16K
256
Yes
-40C to +85C
8
12
24
12
4
Yes
28 Pin (300 Mil) SOIC
(Tape and Reel)
CY8C27443-24SIT
16K
256
Yes
-40C to +85C
8
12
24
12
4
Yes
44 Pin TQFP
CY8C27543-24AI
16K
256
Yes
-40C to +85C
8
12
40
12
4
Yes
44 Pin TQFP
(Tape and Reel)
CY8C27543-24AIT
16K
256
Yes
-40C to +85C
8
12
40
12
4
Yes
48 Pin (300 Mil) SSOP
CY8C27643-24PVI
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
48 Pin (300 Mil) SSOP
(Tape and Reel)
CY8C27643-24PVIT
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
48 Pin (7x7) MLF
CY8C27643-24LFI
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
48 Pin (7x7) MLF
(Tape and Reel)
CY8C27643-24LFIT
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
48 Pin (7X7X 0.90 MM) QFN (Sawn)
CY8C27643-24LTXI
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
48 Pin (7X7X 0.90 MM) QFN (Sawn)
CY8C27643-24LTXIT
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
Package
Ordering
Code
Flash
(Bytes)
Table 47. CY8C27x43 PSoC Device Key Features and Ordering Information (continued)
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Ordering Code Definitions
CY 8 C 27 xxx-SPxx
Package Type:
PX = PDIP Pb-Free
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
LFX/LKX = QFN Pb-Free
AX = TQFP Pb-Free
Thermal Rating:
C = Commercial
I = Industrial
E = Extended
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 38-12012 Rev. *M
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CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
Document History Page
Document Title: CY8C27143, CY8C27243, CY8C27443, CY8C27543, CY8C27643 PSoC® Programmable System-on-Chip™
Document Number: 38-12012
Revision ECN No. Submission
Date
Origin of
Change
Description of Change
**
127087
7/01/2003
New Silicon.
*A
128780
7/29/2003
Engineering and New electrical spec additions, fix of Core Architecture links, corrections to
NWJ.
some text, tables, drawings, and format.
*B
128992
8/14/2003
NWJ
Interrupt controller table fixed, refinements to Electrical Spec section and
Register chapter.
*C
129283
8/28/2003
NWJ
Significant changes to the Electrical Specifications section.
*D
129442
9/09/2003
NWJ
Changes made to Electrical Spec section. Added 20/28-Lead SOIC
packages and pinouts.
*E
130129
10/13/2003
NWJ
Revised document for Silicon Revision A.
*F
130651
10/28/2003
NWJ
Refinements to Electrical Specification section and I2C chapter.
*G
131298
11/18/2003
NWJ
Revisions to GDI, RDI, and Digital Block chapters. Revisions to AC Digital
Block Spec and miscellaneous register changes.
*H
229416
See ECN
SFV
New data sheet format and organization. Reference the PSoC Programmable System-on-Chip Technical Reference Manual for additional information. Title change.
*I
247529
See ECN
SFV
Added Silicon B information to this data sheet.
*J
355555
See ECN
HMT
Add DS standards, update device table, swap 48-pin SSOP 45 and 46, add
Reflow Peak Temp. table. Add new color and logo. Re-add pinout ISSP
notation. Add URL to preferred dimensions for mounting MLF packages.
Update Transmitter and Receiver AC Digital Block Electrical Specifications.
*K
523233
See ECN
HMT
Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add new
Dev. Tool section. Add CY8C20x34 to PSoC Device Characteristics table.
Add OCD pinout and package diagram. Add ISSP note to pinout tables.
Update package diagram revisions. Update typical and recommended
Storage Temperature per industrial specs. Update CY branding and QFN
convention. Update copyright and trademarks.
*L
2545030
07/29/08
YARA
Added note to DC Analog Reference Specification table and Ordering Information.
*M
2696188
04/22/2009
DPT/PYRS
Changed title from “ CY8C27143, CY8C27243, CY8C27443, CY8C27543,
and CY8C27643 PSoC Mixed Signal Array Final Data Sheet” to
“CY8C27143, CY8C27243, CY8C27443, CY8C27543, CY8C27643
PSoC® Programmable System-on-Chip™”. Updated data sheet template.
Added 48-Pin QFN (Sawn) package outline diagram and Ordering information details for CY8C27643-24LTXI and CY8C27643-24LTXIT parts
Document Number: 38-12012 Rev. *M
New document (Revision **).
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CY8C27443, CY8C27543, CY8C27643
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
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clocks.cypress.com
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psoc.cypress.com/solutions
psoc.cypress.com/low-power
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wireless.cypress.com
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memory.cypress.com
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image.cypress.com
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© Cypress Semiconductor Corporation, 2003-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-12012 Rev. *M
Revised April 17, 2009
Page 53 of 53
PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced
herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights
to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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