DS90LV804 4-Channel 800 Mbps LVDS Buffer/Repeater General Description Features The DS90LV804 is a four channel 800 Mbps LVDS buffer/ repeater. In many large systems, signals are distributed across cables and signal integrity is highly dependent on the data rate, cable type, length, and the termination scheme. In order to maximize signal integrity, the DS90LV804 features both an internal input and output (source) termination to eliminate these extra components from the board, and to also place the terminations as close as possible to receiver inputs and driver output. This is especially significant when driving longer cables. The DS90LV804, available in the LLP (Leadless Leadframe Package) package, minimizes the footprint, and improves system performance. An output enable pin is provided, which allows the user to place the LVDS outputs and internal biasing generators in a TRI-STATE, low power mode. The differential inputs interface to LVDS, and Bus LVDS signals such as those on National's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The differential inputs are internally terminated with a 100Ω resistor to improve performance and minimize board space. This function function is especially useful for boosting signals over lossy cables or point-to-point backplane configurations. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 800 Mbps data rate per channel Low output skew and jitter Hot plug protection LVDS/CML/LVPECL compatible input, LVDS output On-chip 100Ω input and output termination 15 kV ESD protection on LVDS Inputs and Outputs Single 3.3V supply Very low power consumption Industrial -40 to +85°C temperature range Small LLP Package Footprint Typical Application 20156720 © 2007 National Semiconductor Corporation 201567 www.national.com DS90LV804 4-Channel 800 Mbps LVDS Buffer/Repeater May 2007 DS90LV804 Block and Connection Diagrams 20156702 20156701 DS90LV804 LLP Pinout (Top View) DS90LV804 Block Diagram Pin Descriptions Pin Name LLP Pin Number I/O, Type Description DIFFERENTIAL INPUTS IN0+ IN0− 9 10 I, LVDS Channel 0 inverting and non-inverting differential inputs. IN1+ IN1− 11 12 I, LVDS Channel 1 inverting and non-inverting differential inputs. IN2+ IN2− 13 14 I, LVDS Channel 2 inverting and non-inverting differential inputs. IN3+ IN3− 15 16 I, LVDS Channel 3 inverting and non-inverting differential inputs. DIFFERENTIAL OUTPUTS OUT0+ OUT0− 32 31 O, LVDS Channel 0 inverting and non-inverting differential outputs. (Note 2) OUT1+ OUT1− 30 29 O, LVDS Channel 1 inverting and non-inverting differential outputs. (Note 2) OUT2+ OUT2− 28 27 O, LVDS Channel 2 inverting and non-inverting differential outputs. (Note 2) OUT3+ OUT3- 26 25 O, LVDS Channel 3 inverting and non-inverting differential outputs. (Note 2) DIGITAL CONTROL INTERFACE EN 8 I, LVTTL Enable pin. When EN is LOW, the driver is disabled and the LVDS outputs are in TRISTATE. When EN is HIGH, the driver is enabled. LVCMOS/LVTTL level input. POWER VDD 3, 4, 6, 7, 19, 20, 21, 22 GND 1, 2, 5, 17, 18 (Note 1) N/C 23, 24 I, Power VDD = 3.3V, ±5% I, Power Ground reference for LVDS and CMOS circuitry. For the LLP package, the DAP is used as the primary GND connection to the device. The DAP is the exposed metal contact at the bottom of the LLP-32 package. It should be connected to the ground plane with at least 4 vias for optimal AC and thermal performance. The pin numbers listed should also be tied to ground for proper biasing. No Connect Note 1: Note that for the LLP package the GND is connected thru the DAP on the back side of the LLP package in addition to grounding actual pins on the package as listed. Note 2: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS90LV804 device have been optimized for point-to-point backplane and cable applications. www.national.com 2 Supply Voltage (VDD) CMOS Input Voltage (EN) LVDS Receiver Input Voltage (Note 4) LVDS Driver Output Voltage LVDS Output Short Circuit Current Junction Temperature Storage Temperature Lead Temperature (Solder, 4sec) Max Pkg Power Capacity @ 25°C Thermal Resistance EIAJ, 0Ω, 200pF Charged Device Model −0.3V to +4.0V −0.3V to (VDD+0.3V) Recommended Operating Conditions −0.3V to (VDD+0.3V) −0.3V to (VDD+0.3V) +90 mA +150°C −65°C to +150°C 260°C 4.16W θJA Supply Voltage (VCC) Input Voltage (VI) (Note 4) Output Voltage (VO) Operating Temperature (TA) Industrial 3.15V to 3.45V 0V to VDD 0V to VDD −40°C to +85°C Note 3: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of products outside of recommended operation conditions. 29.5°C/W θJC Package Derating above +25°C ESD Last Passing Voltage HBM, 1.5kΩ, 100pF 250V 1000V 3.5°C/W 33.3mW/°C Note 4: VID max < 2.4V 15 kV Electrical Characteristics Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (Note 5) Max Units VDD V LVTTL DC SPECIFICATIONS (EN) VIH High Level Input Voltage VIL Low Level Input Voltage GND 0.8 V IIH High Level Input Current VIN = VDD = VDDMAX −10 +10 µA IIL Low Level Input Current VIN = VSS, VDD = VDDMAX −10 +10 µA CIN1 Input Capacitance Any Digital Input Pin to VSS VCL Input Clamp Voltage ICL = −18 mA 2.0 −1.5 3.5 pF −0.8 V LVDS INPUT DC SPECIFICATIONS (INn±) VTH Differential Input High Threshold VCM = 0.8V to 3.4V, (Note 6) VDD = 3.45V VTL Differential Input Low Threshold VCM = 0.8V to 3.4V, (Note 6) VDD = 3.45V −100 VID Differential Input Voltage VCM = 0.8V to 3.4V, VDD = 3.45V 100 VCMR Common Mode Voltage Range VID = 150 mV, VDD = 3.45V 0.05 CIN2 Input Capacitance IN+ or IN− to VSS IIN Input Current VIN = 3.45V, VDD = VDDMAX −10 +10 µA VIN = 0V, VDD = VDDMAX −10 +10 µA 0 100 0 mV 2400 3.40 3.5 3 mV mV V pF www.national.com DS90LV804 Absolute Maximum Ratings (Note 3) DS90LV804 Symbol Parameter Conditions Min Typ (Note 5) Max Units 250 500 600 mV 35 mV 1.475 V 35 mV −90 mA LVDS OUTPUT DC SPECIFICATIONS (OUTn±) VOD ΔVOD Differential Output Voltage (Note RL = 100Ω external resistor between OUT+ and 6) OUT− Change in VOD between Complementary States −35 VOS Offset Voltage (Note 7) 1.05 ΔVOS Change in VOS between Complementary States −35 IOS Output Short Circuit Current OUT+ or OUT− Short to GND −60 COUT2 Output Capacitance OUT+ or OUT− to GND when TRI-STATE 5.5 All inputs and outputs enabled and active, terminated with external differential load of 100Ω between OUT+ and OUT-. 117 140 mA EN = 0V 2.7 6 mA 210 300 ps 210 300 ps 2.0 3.2 ns 2.0 3.2 ns 25 80 ps 50 125 ps 1.1 ns 1.18 pF SUPPLY CURRENT (Static) ICC ICCZ Total Supply Current TRI-STATE Supply Current SWITCHING CHARACTERISTICS—LVDS OUTPUTS tLHT Differential Low to High Transition Time Use an alternating 1 and 0 pattern at 200 Mbps, measure between 20% and 80% of VOD. (Note 12) tHLT Differential High to Low Transition Time tPLHD Differential Low to High Propagation Delay tPHLD Differential High to Low Propagation Delay tSKD1 Pulse Skew tSKCC Output Channel to Channel Skew Difference in propagation delay (tPLHD or tPHLD) among all output channels. (Note 12) tSKP Part to Part Skew Common edge, parts at same temp and VCC(Note 12) tJIT Jitter (Note 8) RJ - Alternating 1 and 0 at 400 MHz (Note 9) 1.1 1.5 psrms DJ - K28.5 Pattern, 800 Mbps (Note 10) 15 35 psp-p TJ - PRBS 223-1 Pattern, 800 Mbps (Note 11) 30 55 psp-p Use an alternating 1 and 0 pattern at 200 Mbps, measure at 50% VOD between input to output. |tPLHD–tPHLD| (Note 12) tON LVDS Output Enable Time Time from EN to OUT± change from TRI-STATE to active. 300 ns tOFF LVDS Output Disable Time Time from EN to OUT± change from active to TRISTATE. 12 ns Note 5: Typical parameters are measured at VDD = 3.3V, TA = 25°C. They are for reference purposes, and are not production-tested. Note 6: Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−). Note 7: Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states. Note 8: Jitter is not production tested, but guaranteed through characterization on a sample basis. Note 9: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50% duty cycle at 400 MHz, tr = tf = 50ps (20% to 80%). Note 10: Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = VID = 500mV, K28.5 pattern at 800 Mbps, tr = tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101). Note 11: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been subtracted. The input voltage = VID = 500mV, 223-1 PRBS pattern at 800 Mbps, tr = tf = 50ps (20% to 80%). Note 12: Not production tested. Guaranteed by statistical analysis on a sample basis at the time of characterization. www.national.com 4 INTERNAL TERMINATIONS The DS90LV804 has integrated termination resistors on both the input and outputs. The inputs have a 100Ω resistor across the differential pair, placing the receiver termination as close as possible to the input stage of the device. The LVDS outputs also contain an integrated 100Ω ohm termination resistor, this resistor is used to reduce the effects of Near End Crosstalk (NEXT) and does not take the place of the 100 ohm termination at the inputs to the receiving device. The integrated terminations improve signal integrity and decrease the external component count resulting in space savings. INPUT FAILSAFE BIASING External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point ideally should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry. Please refer to application note AN-1194 “Failsafe Biasing of LVDS Interfaces” for more information. OUTPUT CHARACTERISTICS The output characteristics of the DS90LV804 have been optimized for point-to-point backplane and cable applications, and are not intended for multipoint or multidrop signaling. TRI-STATE MODE The EN input activates a hardware TRI-STATE mode. When the TRI-STATE mode is active (EN=L), all input and output 5 www.national.com DS90LV804 buffers and internal bias circuitry are powered off and disabled. Outputs are tri-stated in TRI-STATE mode. When exiting TRI-STATE mode, there is a delay associated with turning on bandgap references and input/output buffer circuits as indicated in the LVDS Output Switching Characteristics Feature Descriptions DS90LV804 INPUT INTERFACING The DS90LV804 accepts differential signals and allow simple AC or DC coupling. With a wide common mode range, the DS90LV804 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the DS90LV804 inputs are internally terminated with a 100Ω resistor. 20156731 Typical LVDS Driver DC-Coupled Interface to DS90LV804 Input 20156732 Typical CML Driver DC-Coupled Interface to DS90LV804 Input 20156733 Typical LVPECL Driver DC-Coupled Interface to DS90LV804 Input www.national.com 6 The DS90LV804 outputs signals that are compliant to the LVDS standard. Their outputs can be DC-coupled to most common differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a common mode input range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to implementing the suggested interface implementation. 20156734 Typical DS90LV804 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver TYPICAL PERFORMANCE CHARACTERISTICS Packaging Information The Leadless Leadframe Package (LLP) is a leadframe based chip scale package (CSP) that may enhance chip speed, reduce thermal impedance, and reduce the printed circuit board area required for mounting. The small size and very low profile make this package ideal for high density PCBs used in small-scale electronic applications such as cellular phones, pagers, and handheld PDAs. The LLP package is offered in the no Pullback configuration. In the no Pullback configuration the standard solder pads extend and terminate at the edge of the package. This feature offers a visible solder fillet after board mounting. The LLP has the following advantages: • Low thermal resistance • Reduced electrical parasitics • Improved board space efficiency • Reduced package height • Reduced package mass For more details about LLP packaging technology, refer to applications note AN-1187, "Leadless Leadframe Package" 20156741 Dynamic power supply current was measured while running a clock or PRBS 223-1 pattern with all 4 channels active. VCC = 3.3V, TA = +25°C, VID = 0.5V, VCM = 1.2V Power Supply Current vs. Bit Data Rate 7 www.national.com DS90LV804 OUTPUT INTERFACING DS90LV804 Physical Dimensions inches (millimeters) unless otherwise noted 32-LLP, Plastic, Quad Order Number DS90LV804TSQ (1000 piece Tape and Reel) DS90LV804TSQX (4500 piece Tape and Reel) NS Package Number SQA32A www.national.com 8 DS90LV804 Notes 9 www.national.com DS90LV804 4-Channel 800 Mbps LVDS Buffer/Repeater Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. Copyright© 2007 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Customer Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530-85-86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +49 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: [email protected] National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: [email protected] Tel: 81-3-5639-7560