Maxim MAX19542EGK 12-bit, 170msps adc with cmos outputs for wideband application Datasheet

19-3464; Rev 1; 10/10
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
Applications
Base-Station Power Amplifier Linearization
Cable Head-End Receivers
Wireless and Wired Broadband Communication
Communications Test Equipment
Radar and Satellite Subsystems
o SFDR = 73dBc, fIN = 100MHz at 170Msps
o ±0.7 LSB INL, ±0.25 DNL (typ)
o 907mW Power Dissipation at 170Msps
o On-Chip Selectable Divide-by-2 Clock Input
o Parallel or Demux Parallel Digital CMOS Outputs
o Reset Option for Synchronizing Multiple ADCs
o Data Clock Output
o Offset Binary or Two’s-Complement Output
o Evaluation Kit Available (MAX19542EVKIT)
Ordering Information
PART
MAX19542EGK+
TEMP RANGE
PIN-PACKAGE
-40°C to +85°C
68 QFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
+
63 62 61 60 59 58
DA6
DA5
DA8
DA9
DA10
DA11
ORA
OVCC
OGND
67 66 65 64
AVCC
AGND
68
AVCC
TOP VIEW
AVCC
Pin Configuration
AGND
The MAX19542 operates in either parallel mode where
the data outputs appear on a single parallel port at the
sampling rate, or in demux parallel mode, where the outputs appear on two separate parallel ports at one-half
the sampling rate. See the Mode of Operation section.
The MAX19542 operates on a single 1.8V supply. The
analog input is differential and can be AC- or DC-coupled. The ADC also features a selectable on-chip
divide-by-2 clock circuit that allows clock frequencies
as high as 340MHz. This helps to reduce the phase
noise of the input clock source, allowing for higher
dynamic performance. For best performance, a differential LVPECL sampling clock is recommended. The
digital outputs are CMOS compatible and the data format can be selected to be either two’s complement or
offset binary.
A pin-compatible, 12-bit, 125Msps version of the
MAX19542 is also available. Refer to the MAX19541
data sheet for more information.
The MAX19542 is available in a 68-pin QFN with
exposed pad (EP) and is specified over the extended
(-40°C to +85°C) temperature range.
o SNR = 64.3dB, fIN = 100MHz at 170Msps
ITL
At 170Msps and an input frequency of 240MHz, the
MAX19542 achieves a spurious-free dynamic range
(SFDR) of 76.4dBc. The MAX19542 features an excellent signal-to-noise ratio (SNR) of 65dB at 10MHz that
remains flat (within 3dB) for input tones up to 250MHz.
This makes the MAX19542 ideal for wideband applications such as power-amplifier predistortion in cellular
base-station transceiver systems.
o 170Msps Conversion Rate
T/B
The MAX19542 monolithic 12-bit, 170Msps analog-todigital converter (ADC) is optimized for outstanding
dynamic performance at high-IF frequencies of
300MHz and beyond. This device operates with conversion rates up to 170Msps while consuming only
907mW.
Features
57 56 55 54 53 52
AVCC
1
51 DA4
AGND
2
50 DA3
REFIO
3
49 DA2
REFADJ
4
48 DA1
AGND
5
47 DA0
AVCC
6
46 ORB
AGND
7
45 OGND
INP
8
INN
9
44 OVCC
43 DCLKP
MAX19542
AGND 10
42 DCLKN
AVCC 11
41 OVCC
AVCC 12
40 DB11
AVCC 13
39 DB10
AVCC 14
38 DB9
RESET 15
37 DB8
EP
DEMUX 16
36 DB7
CLKDIV 17
35 DB6
NOTE: EXPOSED PAD CONNECTED TO AGND.
DB5
DB4
DB3
DB2
DB1
DB0
OVCC
OVCC
OGND
AVCC
AGND
CLKP
CLKN
AGND
AVCC
AGND
AGND
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
QFN
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX19542
General Description
DA7
KIT
ATION
EVALU
E
L
B
AVAILA
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
ABSOLUTE MAXIMUM RATINGS
ESD on All Pins (Human Body Model).............................±2000V
Continuous Power Dissipation (TA = +70°C)
68-Pin QFN (derate 41.7mW/°C above +70°C) ........ 3333mW
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Soldering Temperature (reflow) ......................................+260°C
AVCC to AGND ......................................................-0.3V to +2.1V
OVCC to OGND .....................................................-0.3V to +2.1V
AVCC to OVCC .......................................................-0.3V to +2.1V
AGND to OGND ....................................................-0.3V to +0.3V
Analog Inputs (INP, INN) to AGND ..........-0.3V to (AVCC + 0.3V)
All Digital Inputs to AGND........................-0.3V to (AVCC + 0.3V)
REFIO, REFADJ to AGND ........................-0.3V to (AVCC + 0.3V)
All Digital Outputs to OGND ....................-0.3V to (OVCC + 0.3V)
Maximum Current into Any Pin ....................................... ±50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVCC = VOVCC = 1.8V, VAGND = VOGND = 0V, fSAMPLE = 170MHz, DEMUX = 0, differential LVPECL clock input drive, 0.1µF capacitor on REFIO, internal reference, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by production test, TA < +25°C
guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
12
Bits
Integral Nonlinearity
INL
fIN = 10MHz (Note 1)
-2.5
±0.7
+2.5
LSB
Differential Nonlinearity
DNL
fIN = 10MHz, no missing codes (Note 1)
-0.75
±0.25
+0.75
LSB
Transfer Curve Offset
VOS
(Note 1)
-3
Offset Temperature Drift
+3
40
mV
mV/°C
ANALOG INPUTS (INP, INN)
Full-Scale Input Voltage Range
VFS
(Note 1)
1300
Full-Scale Range Temperature
Drift
Common-Mode Input Range
VCM
Input Capacitance
CIN
Differential Input Resistance
RIN
Full-Power Analog Bandwidth
1410
1510
130
ppm/°C
1.365
±0.15
V
3
3.00
FPBW
mVP-P
4.3
pF
6.25
900
kΩ
MHz
REFERENCE (REFIO, REFADJ)
Reference Output Voltage
VREFIO
1.22
Reference Temperature Drift
REFADJ Input High Voltage
1.245
90
VREFADJ
Used to disable the internal reference
VAVCC
- 0.3
1.27
V
ppm/°C
V
SAMPLING CHARACTERISTICS
Maximum Sampling Rate
fSAMPLE
Minimum Sampling Rate
fSAMPLE
Clock Duty Cycle
tAD
Aperture Jitter
tAJ
MHz
20
Set by clock-management circuit
Aperture Delay
2
170
Figure 4
MHz
40 to 60
%
620
ps
0.2
psRMS
_______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
(VAVCC = VOVCC = 1.8V, VAGND = VOGND = 0V, fSAMPLE = 170MHz, DEMUX = 0, differential LVPECL clock input drive, 0.1µF capacitor on REFIO, internal reference, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by production test, TA < +25°C
guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
200
500
mVP-P
1.15
±0.25
V
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input
Amplitude
(Note 2)
Clock Input Common-Mode
Voltage Range
Clock Differential Input
Resistance
RCLK
11
±25%
kΩ
Clock Differential Input
Capacitance
CCLK
5
pF
DYNAMIC CHARACTERISTICS (at -2dBFS)
Signal-to-Noise Ratio
SNR
fIN = 10MHz
62.3
65
fIN = 100MHz
62.3
64.3
fIN = 180MHz
fIN = 240MHz
Signal-to-Noise and Distortion
Spurious-Free Dynamic Range
SINAD
SFDR
Worst Harmonics
(HD2 or HD3)
Two-Tone Intermodulation
Distortion
IMD100
dB
63.5
63.3
fIN = 10MHz
61.9
64.8
fIN = 100MHz
61.7
63.6
fIN = 180MHz
62.6
fIN = 240MHz
63
fIN = 10MHz
68.3
82
fIN = 100MHz
68.3
73
fIN = 180MHz
72.4
fIN = 240MHz
76.4
dB
dBc
fIN = 10MHz
-85
-69.1
fIN = 100MHz
-73
-68.7
fIN = 180MHz
-72.4
fIN = 240MHz
-76.4
fIN1 = 207.5MHz at -7dBFS,
fIN2 = 211.5MHz at -7dBFS, fSAMPLE = 170MHz
-69
dBc
dBc
CMOS DIGITAL OUTPUTS (DA0–DA11, DB0–DB11, ORA, ORB)
Logic-High Output Voltage
VOH
Logic-Low Output Voltage
VOL
VOVCC
- 0.1
V
0.1
V
0.2 x
VAVCC
V
LVCMOS DIGITAL INPUTS (CLKDIV, T/B, DEMUX, ITL)
Digital Input-Voltage Low
VIL
Digital Input-Voltage High
VIH
0.8 x
VAVCC
V
_______________________________________________________________________________________
3
MAX19542
ELECTRICAL CHARACTERISTICS (continued)
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
ELECTRICAL CHARACTERISTICS (continued)
(VAVCC = VOVCC = 1.8V, VAGND = VOGND = 0V, fSAMPLE = 170MHz, DEMUX = 0, differential LVPECL clock input drive, 0.1µF capacitor on REFIO, internal reference, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by production test, TA < +25°C
guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Resistance
RIN
46.5
kΩ
Input Capacitance
CIN
5
pF
TIMING CHARACTERISTICS
CLKP-to DA0–DA11 Propagation
Delay
tPDL
Figures 5, 6, and 7
2.5
ns
CLKP-to-DCLKP Propagation
Delay
tCPDL
Figures 5, 6, and 7
2.1
ns
DCLKP Rising Edge to
DA0–DA11
tPDL tCPDL
Figures 5, 6, and 7 (Note 2)
CMOS Output Rise Time
tRISE
20% to 80%, CL = 5pF
1
CMOS Output Fall Time
tFALL
20% to 80%, CL = 5pF
1
ns
180
400
710
ns
ns
RESET Hold
tHR
Figure 4
100
ps
RESET Setup
tSR
Figure 4
500
ps
tLATENCY
Figure 4
11
Clock
cycles
Output Data Pipeline Delay
POWER REQUIREMENTS
Analog Supply Voltage Range
AVCC
Digital Supply Voltage Range
OVCC
1.8
1.9
V
Analog Supply Current
IAVCC
fIN = 100MHz
480
520
mA
Digital Supply Current
IOVCC
fIN = 100MHz
24
31
mA
Analog Power Dissipation
PDISS
fIN = 100MHz
907
992
Offset (Note 3)
1.8
mV/V
Gain (Note 3)
1.5
%FS/V
Power-Supply Rejection Ratio
PSRR
1.7
1.7
1.8
1.9
V
mW
Note 1: Static linearity and offset parameters are computed from a straight line drawn between the end points of the code transition
transfer function. The full-scale range (FSR) is defined as 4096 x slope of the line.
Note 2: Parameter guaranteed by design and characterization; TA = TMIN to TMAX.
Note 3: PSRR is measured with both analog and digital supplies connected to the same potential.
4
_______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
-50
-60
-70
2
-80
4
3
5
-30
-50
-60
3
-70
67
-30
7
2
5
-80
4
6
-50
-60
-90
-90
-100
40
50
60
70
-40
-50
-60
20
30
40
50
60
70
0
80
10
20
30
40
50
60
70
80
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
(16,384-POINT DATA RECORD)
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 170.0043MHz, AIN = -1dBFS)
SFDR vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 170.0043MHz, AIN = -1dBFS)
2
-70
3 4
7 5
-80
SNR
67
90
MAX19542 toc06
70
85
80
75
SFDR (dBc)
-30
10
ANALOG INPUT FREQUENCY (MHz)
SNR/SINAD (dB)
-20
4
ANALOG INPUT FREQUENCY (MHz)
fIN = 241.008937MHz
fSAMPLE = 170.0043234MHz
AIN = -1.035dBFS
SNR = 64.01dB
SINAD = 63.521dB
SFDR = 74.963dBc
HD2 = -74.963dBc
HD3 = -82.606dBc
-10
0
80
MAX19542 toc04
0
30
5
6
-110
-110
20
3
2
-80
-100
10
7
-70
-90
0
64
SINAD
61
6
70
65
60
55
50
58
-90
45
-100
-110
40
55
0
10
20
30
40
50
60
70
80
0
0
25 50 75 100 125 150 175 200 225 250
25 50 75 100 125 150 175 200 225 250
ANALOG INPUT FREQUENCY (MHz)
fIN (MHz)
fIN (MHz)
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 170.0043MHz, AIN = -1dBFS)
THD vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 170.0043MHz, AIN = -1dBFS)
SNR/SINAD vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 170.0043MHz, fIN = 64.9864MHz)
-65
MAX19542 toc09
68
MAX19542 toc08
HD3
-60
MAX19542 toc07
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
SNR
62
SNR/SINAD (dB)
-70
THD (dBc)
HD2/HD3 (dBc)
-40
-100
-110
AMPLITUDE (dB)
-40
-20
MAX19542 toc03
-20
fIN = 190.186111MHz
fSAMPLE = 170.0043234MHz
AIN = -1.03dBFS
SNR = 64.664dB
SINAD = 63.513dB
SFDR = 71.34dBc
HD2 = -77.559dBc
HD3 = -71.34dBc
-10
AMPLITUDE (dB)
-40
fIN = 64.9863939MHz
fSAMPLE = 170.0043234MHz
AIN = -1.068dBFS
SNR = 65.921dB
SINAD = 65dB
SFDR = 74.007dBc
HD2 = -82.197dBc
HD3 = -79.515dBc
MAX19542 toc05
AMPLITUDE (dB)
-30
0
MAX19542 toc02
-20
0
-10
AMPLITUDE (dB)
fIN = 12.9599243MHz
fSAMPLE = 170.0043234MHz
AIN = -1.05dBFS
SNR = 65.923dB
SINAD = 65.822dB
SFDR = 88.137dBc
HD2 = -92.278dBc
HD3 = -88.96dBc
MAX19542 toc01
0
-10
-75
-80
-85
HD2
SINAD
56
50
44
-90
38
-95
-100
0
25 50 75 100 125 150 175 200 225 250
fIN (MHz)
32
0
25 50 75 100 125 150 175 200 225 250
fIN (MHz)
-30
-25
-20
-15
-10
-5
0
AIN (dBFS)
_______________________________________________________________________________________
5
MAX19542
Typical Operating Characteristics
(VAVCC = VOVCC = 1.8V, VAGND = VOGND = 0V, fSAMPLE = 170MHz, AIN = -1dBFS; see TOCs for detailed information on test conditions, differential input drive, differential LVPECL clock input drive, 0.1µF capacitor on REFIO, internal reference, digital outputs differential RL = 100Ω, TA = +25°C.)
FFT PLOT
FFT PLOT
FFT PLOT
(16,384-POINT DATA RECORD)
(16,384-POINT DATA RECORD)
(16,384-POINT DATA RECORD)
Typical Operating Characteristics (continued)
(VAVCC = VOVCC = 1.8V, VAGND = VOGND = 0V, fSAMPLE = 170MHz, AIN = -1dBFS; see TOCs for detailed information on test conditions, differential input drive, differential LVPECL clock input drive, 0.1µF capacitor on REFIO, internal reference, digital outputs differential RL = 100Ω, TA = +25°C.)
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
THD vs. ANALOG INPUT AMPLITUDE
SFDR vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 170.0043MHz, fIN = 64.9864MHz)
(fSAMPLE = 170.0043MHz, fIN = 64.9864MHz)
(fSAMPLE = 170.0043MHz, fIN = 64.9864MHz)
HD2
-60
MAX19542 toc12
80
-50
MAX19542 toc11
85
-60
HD2/HD3 (dBc)
70
65
60
55
THD (dBc)
-70
75
SFDR (dBc)
-50
MAX19542 toc10
90
-80
-90
HD3
-70
-80
-100
50
-90
-110
45
-120
-30
-25
-20
-15
-10
-5
-25
-20
-15
-5
0
-30
-15
-10
-5
SFDR vs. fSAMPLE
(fIN = 65.0165MHz, AIN = -1dBFS)
HD2/HD3 vs. fSAMPLE
(fIN = 65.0165MHz, AIN = -1dBFS)
75
SFDR (dBc)
65
64
SINAD
63
HD2/HD3 (dBc)
85
80
70
65
62
60
61
55
60
-50
-55
-60
MAX19542 toc14
MAX19542 toc13
90
60
80 100 120 140 160 180 200
HD2
-100
-105
-110
50
40
HD3
-65
-70
-75
-80
-85
-90
-95
20
40
60
20
80 100 120 140 160 180 200
40
60
80 100 120 140 160 180 200
fSAMPLE (MHz)
fSAMPLE (MHz)
fSAMPLE (MHz)
THD vs. fSAMPLE
(fIN = 65.0165MHz, AIN = -1dBFS)
TWO-TONE IMD
(16,384-POINT DATA RECORD)
INL vs. DIGITAL OUTPUT CODE
(512k-POINT DATA RECORD)
-20
AMPLITUDE (dB)
-30
-70
-75
-80
-85
-90
-40
fIN1
-50
fIN2
2fIN2 - fIN1
-60
2fIN1 - fIN2
-70
60
80 100 120 140 160 180 200
fSAMPLE (MHz)
fIN = 13.008646MHz
0.8
0.6
0.4
0.2
0
-0.2
-80
-0.4
-90
-0.6
-100
-0.8
-110
40
1.0
INL (LSB)
-65
fIN1 = 207.4936801MHz
fIN2 = 211.5611664MHz
fSAMPLE = 170.00432MHz
AIN1 = AIN2 = -7dBFS
IMD = -69dBc
-10
MAX19542 toc17
0
MAX19542 toc16
-60
0
MAX19542 toc15
SNR/SINAD vs. fSAMPLE
(fIN = 65.0165MHz, AIN = -1dBFS)
66
20
-20
AIN (dBFS)
67
20
-25
AIN (dBFS)
SNR
6
-10
AIN (dBFS)
68
SNR/SINAD (dB)
-100
-30
0
MAX19542 toc18
40
THD (dBc)
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
-1.0
0
10
20
30
40
50
60
70
ANALOG INPUT FREQUENCY (MHz)
80
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL OUTPUT CODE
_______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
0
66
0
-0.2
SNR/SINAD (dB)
GAIN (dB)
0.2
SNR
-2
-3
-4
-0.4
65
64
63
SINAD
-5
-0.6
-0.8
-6
-1.0
-7
512 1024 1536 2048 2560 3072 3584 4096
62
61
10
-40
1000
100
-15
10
35
85
60
DIGITAL OUTPUT CODE
ANALOG INPUT FREQUENCY (MHz)
TEMPERATURE (°C)
SFDR vs. TEMPERATURE
(fSAMPLE = 170MHz, AIN = -2dBFS)
TOTAL POWER DISSIPATION vs. fSAMPLE
(fIN = 65.0165MHz, AIN = -1dBFS)
FULL-SCALE ADJUSTMENT RANGE
vs. FULL-SCALE ADJUSTMENT RESISTANCE
0.975
0.950
75
PDISS (W)
74
73
72
0.925
0.900
0.875
71
0.850
70
69
0.825
68
0.800
-40
-15
10
35
60
85
1.32
1.30
1.28
RADJ BETWEEN REFADJ AND REFIO
1.26
1.24
1.22
RADJ BETWEEN REFADJ AND GND
1.20
1.18
1.16
1.14
20
TEMPERATURE (°C)
40
60
80
0
100 120 140 160 180
200
66
800
1000
1.250
MAX19542 toc26
AVCC = OVCC
SNR
600
INTERNAL REFERENCE
vs. SUPPLY VOLTAGE
MAX19542 toc25
68
400
RADJ (kΩ)
fSAMPLE (MHz)
SNR/SINAD vs. SUPPLY VOLTAGE
(fIN = 64.9864MHz, AIN = -1dBFS)
1.249
1.248
64
VREFIO (V)
SNR/SINAD (dB)
1.34
MAX19542 toc24
76
1.000
INTERNAL REFERENCE (V)
fIN = 100MHz
77
MAX19542 toc23
78
MAX19542 toc22
0
SFDR (dBc)
fIN = 100MHz
-1
0.4
DNL (LSB)
67
MAX19542 toc21
0.6
1
MAX19542 toc20
fIN = 13.008646MHz
0.8
MAX19542 toc19
1.0
SINAD
62
1.247
1.246
60
1.245
58
1.6
1.7
1.8
1.9
SUPPLY VOLTAGE (V)
2.0
2.1
1.244
1.6
1.7
1.8
1.9
2.0
2.1
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
7
MAX19542
Typical Operating Characteristics (continued)
(VAVCC = VOVCC = 1.8V, VAGND = VOGND = 0V, fSAMPLE = 170MHz, AIN = -1dBFS; see TOCs for detailed information on test conditions, differential input drive, differential LVPECL clock input drive, 0.1µF capacitor on REFIO, internal reference, digital outputs differential RL = 100Ω, TA = +25°C.)
DNL vs. DIGITAL OUTPUT CODE
SNR/SINAD vs. TEMPERATURE
GAIN BANDWIDTH PLOT
(512k-POINT DATA RECORD)
(fSAMPLE = 170MHz, AIN = -2dBFS)
(fSAMPLE = 170.0043MHz, AIN = -1dBFS)
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
Pin Description
PIN
NAME
1, 6, 11–14,
20, 25, 62,
63, 65
AVCC
Analog Supply Voltage. Bypass each AVCC pin with a 0.1µF capacitor for best decoupling results.
Additional board decoupling might be required. See the Grounding, Bypassing, and Layout
Considerations section.
2, 5, 7, 10,
18, 19, 21,
24, 64, 66
AGND
Analog Converter Ground. Connect the converter’s exposed pad (EP) to AGND.
3
REFIO
Reference Input/Output. Drive REFADJ high to allow an external reference source to be connected to
the MAX19542. Drive REFADJ low to activate the internal 1.23V bandgap reference. Connect a 0.1µF
capacitor from REFIO to AGND.
8
4
REFADJ
8
INP
9
INN
FUNCTION
Reference Adjust Input. REFADJ allows for full-scale range adjustments by placing a resistor or trim
potentiometer between REFADJ and AGND (decreases FS range) or REFADJ and REFIO (increases
FS range). If REFADJ is connected to AVCC, the internal reference can be overdriven with an external
source connected to REFIO. If REFADJ is connected to AGND, the internal reference is used to
determine the full-scale range of the data converter.
Positive Analog Input Terminal
Negative Analog Input Terminal
15
RESET
Active-High RESET Input. RESET controls the latency of the MAX19542. RESET has an internal
pulldown resistor. See the Reset Operation section.
16
DEMUX
Output-Mode-Select Input. Drive DEMUX low for the parallel output mode (full-rate CMOS outputs on
A ports only). Drive DEMUX high for the demux parallel or demux interleaved modes (half-rate outputs
on both ports A and B) depending on the state of the ITL input. See the Modes of Operation section.
17
CLKDIV
Clock-Divider Input. CLKDIV is an LVCMOS-compatible input that controls the sampling frequency
relative to the input clock frequency. CLKDIV has an internal pulldown resistor:
CLKDIV = 0: sampling frequency is 1/2 the input clock frequency.
CLKDIV = 1: sampling frequency is equal to the input clock frequency.
22
CLKN
Complementary Clock Input. CLKN ideally requires an LVPECL-compatible input level to maintain the
converter’s excellent performance.
23
CLKP
True Clock Input. CLKP ideally requires an LVPECL-compatible input level to maintain the converter’s
excellent performance.
26, 45, 61
OGND
Digital Converter Ground. Ground connection for digital circuitry and output drivers.
27, 28, 41,
44, 60
OVCC
Digital Supply Voltage. Bypass OVCC with a 0.1µF capacitor for best decoupling results. Additional board
decoupling might be required. See the Grounding, Bypassing, and Layout Considerations section.
29
DB0
Port B CMOS Digital Output Bit 0 (LSB)
30
DB1
Port B CMOS Digital Output Bit 1
31
DB2
Port B CMOS Digital Output Bit 2
32
DB3
Port B CMOS Digital Output Bit 3
33
DB4
Port B CMOS Digital Output Bit 4
34
DB5
Port B CMOS Digital Output Bit 5
35
DB6
Port B CMOS Digital Output Bit 6
36
DB7
Port B CMOS Digital Output Bit 7
37
DB8
Port B CMOS Digital Output Bit 8
_______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
PIN
NAME
38
DB9
Port B CMOS Digital Output Bit 9
FUNCTION
39
DB10
Port B CMOS Digital Output Bit 10
40
DB11
Port B CMOS Digital Output Bit 11 (MSB)
42
DCLKN
Inverted CMOS Digital Clock Output. DCLKN provides a CMOS-compatible output level and can be
used to synchronize external devices to the converter clock. When DEMUX is high, the frequency at
DCLKN is half the sampling clock’s frequency.
43
DCLKP
True CMOS Digital Clock Output. DCLKP provides a CMOS-compatible output level and can be used
to synchronize external devices to the converter clock. When DEMUX is high, the frequency at DCLKP is
half the sampling clock’s frequency.
46
ORB
Port B CMOS Digital Output Overrange
47
DA0
Port A CMOS Digital Output Bit 0 (LSB)
48
DA1
Port A CMOS Digital Output Bit 1
49
DA2
Port A CMOS Digital Output Bit 2
50
DA3
Port A CMOS Digital Output Bit 3
51
DA4
Port A CMOS Digital Output Bit 4
52
DA5
Port A CMOS Digital Output Bit 5
53
DA6
Port A CMOS Digital Output Bit 6
54
DA7
Port A CMOS Digital Output Bit 7
55
DA8
Port A CMOS Digital Output Bit 8
56
DA9
Port A CMOS Digital Output Bit 9
57
DA10
Port A CMOS Digital Output Bit 10
58
DA11
Port A CMOS Digital Output Bit 11 (MSB)
59
ORA
Port A CMOS Digital Output Overrange
67
ITL
Interleaved/Parallel-Select Input. Drive ITL low for the demux parallel mode. Drive ITL high for the demux
interleaved mode.
68
T/B
Output-Format-Select Input. T/B is an LVCMOS-compatible input that controls the digital output format
of the MAX19542. T/B has an internal pulldown resistor:
T/B = 1: binary output format.
T/B = 0: two’s-complement output format.
—
EP
Exposed Pad. Connect EP to analog ground (AGND) for optimum performance. The exposed pad is
located on the backside of the chip. EP is internally connected to the die substrate.
_______________________________________________________________________________________
9
MAX19542
Pin Description (continued)
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
Detailed Description—
Theory of Operation
The MAX19542 uses a fully differential, pipelined architecture that allows for high-speed conversion, optimized accuracy and linearity, while minimizing power
consumption. Both positive (INP) and negative/complementary analog input terminals (INN) are centered
around a 1.365V common-mode voltage, and accept a
±350mV differential analog input voltage swing each,
resulting in a 1.41V P-P typical differential full-scale
signal swing.
Inputs INP and INN are buffered prior to entering each
track-and-hold (T/H) stage and are sampled when the
differential sampling clock signal transitions high. The
CLKDIV
CLKP
RESET
CLOCKDIVIDER
CONTROL
CLKN
CLOCK
MANAGEMENT
T/H
INN
2.15kΩ
2.15kΩ
DEMUX
ITL
12 BITS
BUFFER
INP
ADC following the first T/H stage then digitizes the signal, and controls a digital-to-analog converter (DAC).
Digitized and reference signals are then subtracted,
resulting in a fractional residue signal that is amplified
before it is passed on to the next stage through another
T/H amplifier. This process is repeated until the applied
input signal has successfully passed through all stages
of the 12-bit quantizer. Finally, the digital outputs of all
stages are combined and corrected for in the digital
correction logic to generate the final output code. The
result is a 12-bit parallel digital output word in userselectable two’s complement or binary output formats
with CMOS-compatible output levels. See the functional
diagram (Figure 1) for a more detailed view of the
MAX19542’s architecture.
12-BIT PIPELINE
QUANTIZER
CORE
CMOS
DATA
PORTS
DA0–DA11, ORA
DB0–DB11, ORB
12 BITS
CM
BUFFER
REFERENCE
REFIO
CLK
GENERATOR
MAX19542
DCLKP
DCLKN
REFADJ
Figure 1. MAX19542 Functional Diagram
10
______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
REFT
AVCC
G
MAX19542
ADC FULL SCALE = REFT - REFB
REFERENCESCALING
AMPLIFIER
REFB
REFERENCE
BUFFER
INN
INP
2.15kΩ
2.15kΩ
REFIO
1V
0.1µF
MAX19542
REFADJ*
CONTROL LINE
TO DISABLE
REFERENCE BUFFER
TO COMMON-MODE
INPUT
TO COMMON-MODE
INPUT
AGND
AVCC
AVCC/2
*REFADJ CAN BE SHORTED TO AGND THROUGH A 1kΩ
RESISTOR OR POTENTIOMETER.
Figure 2. Simplified Analog Input Architecture
Figure 3. Simplified Reference Architecture
Analog Inputs (INP, INN)
Clock Inputs (CLKP, CLKN)
INP and INN are the fully differential inputs of the
MAX19542. Differential inputs usually feature good
rejection of even-order harmonics, which allows for
enhanced AC performance as the signals are progressing through the analog stages. The MAX19542
analog inputs are self-biased at a 1.365V commonmode voltage and allow a 1.41VP-P differential input
voltage swing. Both inputs are self-biased through
2.15kΩ resistors, resulting in a typical differential input
resistance of 4.3kΩ (Figure 2). It is recommended driving the analog inputs of the MAX19542 in an AC-coupled configuration to achieve the best dynamic
performance. See the Transformer-Coupled, Differential
Analog Input Drive section for a detailed discussion of
this configuration.
Drive the clock inputs of the MAX19542 differentially
with an LVPECL-compatible clock to achieve the best
dynamic performance. The clock signal source must be
high-quality, low phase noise to avoid any degradation
in the noise performance of the ADC. The clock inputs
(CLKP, CLKN) are internally biased to typically 1.15V,
accept a typical 0.5VP-P differential signal swing, and
are usually driven in an AC-coupled configuration. See
the Differential, AC-Coupled Clock Input section for
more circuit details on how to drive CLKP and CLKN
appropriately.
The MAX19542 features an internal clock-management
circuit (duty-cycle equalizer). The clock-management
circuit ensures that the clock signal applied to inputs
CLKP and CLKN is processed to provide a near 50%
duty-cycle clock signal. This desensitizes the performance of the converter to variations in the duty cycle of
the input clock source. Note that the clock duty-cycle
equalizer cannot be turned off externally.
On-Chip Reference Circuit
The MAX19542 features an internal 1.24V bandgap reference circuit (Figure 3), which, in combination with an
internal reference-scaling amplifier, determine the fullscale range of the MAX19542. Bypass REFIO with a
0.1µF capacitor to AGND. To compensate for gain errors
or increase the ADC’s full-scale range, the voltage of this
bandgap reference can be indirectly adjusted by adding
an external resistor (e.g., 100kΩ trim potentiometer)
between REFADJ and AGND or REFADJ and REFIO.
See Figure 7 and the Applications Information section for
a detailed description of this process.
Clock Outputs (DCLKP, DCLKN)
The MAX19542 features CMOS-complementary clock
outputs (DCLKP, DCLKN) to latch the digital output
data with an external latch or receiver. Additionally, the
clock outputs can be used to synchronize external
devices (e.g., FPGAs) to the ADC. There is a 2.1ns
delay time between the rising (falling) edge of CLKP
(CLKN) and the rising (falling) edge of DCLKP
(DCLKN). See Figure 4 for timing details.
______________________________________________________________________________________
11
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
Divide-by-Two Clock Control (CLKDIV)
RESET Operation
The MAX19542 offers a clock control line (CLKDIV) that
allows the reduction of clock jitter and phase noise in a
system as higher frequency oscillators usually exhibit
better phase noise and jitter characteristics. Connect
CLKDIV to OGND to enable the ADC’s internal divideby-2 clock divider, which allows the user to use an
oscillator of twice the maximum sampling frequency.
The sampling frequency now becomes 1/2 of the input
clock frequency. CLKDIV has an internal pulldown
resistor and can be left open for applications that
require this divide-by-2 mode. Connecting CLKDIV to
OVCC disables the divide-by-2 mode.
The RESET input defines the pipeline latency of the
MAX19542. Drive RESET high to place the MAX19542
in reset mode with the CMOS outputs tri-stated. During
the time when RESET is high, no sample information is
available at the outputs. For pipeline latency, the first
sample is defined at the first rising edge of CLKP after
RESET goes low. The conversion information is available at the outputs after 11 clock cycles. Synchronize
RESET with the input clock of the device by observing
the minimum RESET hold (tHR) and RESET setup (tSR)
times (Figure 4). RESET is only used to control the
latency of the device and, in applications where this is
not critical, drive RESET low or leave unconnected.
RESET has an internal pulldown resistor.
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
INN
INP
tAD
CLKN
N
N+1
N + 11
CLKP
tSR
RESET
tCH
N + 12
tCL
tHR
Figure 4. RESET Timing Diagram
12
______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
Modes of Operation
The MAX19542 features three modes of operation. In
each mode of operation, the conversion data is output
in a different format.
SAMPLING EVENT
SAMPLING EVENT
Parallel Mode
Drive DEMUX low to place the MAX19542 in the parallel
mode. In this mode, the output clock has the same frequency as the sampling frequency and conversion
data is output at full rate on parallel ports DA0–DA11.
Note that the sampling frequency may not be the same
as the input clock frequency. See the Divide-by-Two
Clock Control (CLKDIV) section. In parallel mode, samples are taken on the rising edge of CLKP. Conversion
data appears at the outputs on the rising edge of
DCLKP after the latency period of 11 clock cycles and
is stable for one clock period (Figure 5). If an overrange
condition occurs, it is reflected on the ORA port.
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
INN
INP
tAD
CLKN
N
N+1
N + 11
N + 12
CLKP
tCL
tCH
RESET
tCPDL
DCLKN
N - 11
N - 10
DCLKP
N+1
tLATENCY
tPDL
DA0–DA11, ORA
N
N - 11
N - 10
N -1
N
N+1
Figure 5. Parallel Mode Timing Diagram
______________________________________________________________________________________
13
MAX19542
System Timing Requirements
Figures 5, 6, and 7 depict the relationship between the
clock input and output, analog input, sampling event,
and data output. The MAX19542 samples on the rising
(falling) edge of CLKP (CLKN). In all these figures,
CLKDIV is assumed to be high; otherwise, the sampling
events would occur at every other rising edge of CLKP.
Output data is latched on the next rising (falling) edge
of the DCLKP (DCLKN) clock, but has an internal latency of 11 input clock cycles.
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
Demux Parallel Mode
Drive DEMUX high and ITL low to place the MAX19542
in the demux parallel mode. In this mode, the output
clock’s frequency is 1/2 the sampling frequency. The
sampling frequency may not be the same as the input
clock frequency. See the Divide-by-Two Clock Control
(CLKDIV) section. Each conversion starts with a sampling event on the rising edge of CLKP. Conversion
data now appears on both DA0–DA11 and DB0–DB11.
The first conversion result is output on the A ports on
the rising edge of DCLKP after 12 input clock cycles
from the initial sampling event. The second conversion
result is output on the B ports on the rising edge of
DCLKP after 11 input clock cycles from the initial sam-
SAMPLING EVENT
SAMPLING EVENT
pling event. Both conversion results are output simultaneously (Figure 6). The conversion results on ports A
and B remain stable for one period of DCLKP after they
become valid. Thus, the overall throughput rate is the
same as in parallel mode; however, now each data line
is allowed to be valid for a longer time (two sampling
periods, one digital clock period). Overrange conditions are reflected on the appropriate output port, ORA
or ORB, depending on which conversion they occur.
The demux interleaved mode is the recommended
demux mode of operation due to the fact that output
bus switching is more evenly distributed over sample
clock edges.
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
INN
INP
tAD
CLKN
N
N + 12
CLKP
tCPDL
tCL
tCH
RESET
DCLKP
N
N+2
DCLKN
tLATENCY
tPDL
DA0–DA11, ORA
N
N+2
DB0–DB11, ORB
N+1
N+3
DEMUX PARALLEL MODE
Figure 6. Demux Parallel Mode Timing Diagram
14
______________________________________________________________________________________
SAMPLING EVENT
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
SAMPLING EVENT
SAMPLING EVENT
after 12 input clock cycles from the initial sampling
event. The second conversion result is output on the B
ports on the rising edge of DCLKN after 12 input clock
cycles from the initial sampling event. In this way, the two
conversion results are interleaved with respect to each
other (Figure 7). The conversion results on ports A and B
remain stable for one period of DCLKP and DCLKN,
respectively, after they become valid. Overrange conditions are reflected on the appropriate output port, ORA
or ORB, depending on which conversion they occur.
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
INN
INP
tAD
CLKN
N
N + 12
CLKP
tCPDL
tCL
tCH
RESET
DCLKP
N
N+2
DCLKN
tLATENCY
tPDL
DA0–DA11, ORA
N
DB0–DB11, ORB
N+2
N+1
N+3
DEMUX INTERLEAVED MODE
Figure 7. Demux Interleaved Mode Timing Diagram
______________________________________________________________________________________
15
MAX19542
Demux Interleaved Mode
Drive DEMUX high and ITL high to place the
MAX19542 in the demux interleaved mode of operation.
In this mode, the output clock’s frequency is 1/2 the
sampling frequency. The sampling frequency may not
be the same as the input clock frequency. See the
Divide-by-Two Clock Control (CLKDIV) section. Each
conversion starts with a sampling event on the rising
edge of CLKP. Conversion data now appears on both
DA0–DA11 and DB0–DB11. The first conversion result
is output on the A ports on the rising edge of DCLKP
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
Digital Outputs
(DA0–DA11, DCLKP, DCLKN, ORA,
DB0–DB11, ORB) and Control Input T/B
Digital outputs DA0/DB0–DA11/DB11, DCLKP, DCLKN,
ORA/ORB are CMOS compatible, and data on DA0/DB
DA11/DB11 are presented in either binary or two’scomplement format (Table 1). The T/B control line is an
LVCMOS-compatible input that allows the user to select
the desired output format. Drive T/B high to select data
to be output in offset binary format and drive it low to
select data to be output in two’s complement format on
the 12-bit parallel bus. T/B has an internal pulldown
resistor and can be left unconnected in applications
using only two’s-complement output format. The CMOS
outputs are powered from a separate power supply that
can be operated between 1.7V and 1.9V.
The MAX19542 offers an additional differential output
pair (ORA, ORB) to flag overrange conditions, where
overrange is above positive or below negative full scale.
An overrange condition is identified with ORA/ORB transitioning high.
Note: Keep the capacitive load on the digital outputs as
low as possible. Use digital buffers on the digital outputs of the ADC when driving larger loads to improve
overall performance and reduce system timing constraints. Further improvements in dynamic performance
can be achieved by adding small series resistors
(100Ω) to the digital output paths, close to the ADC.
Table 1. MAX19542 Digital Output Coding
BINARY
DIGITAL OUTPUT CODE
(D_11–D_0)
TWO’S-COMPLEMENT
DIGITAL OUTPUT CODE
(D_11–D_0)
INP ANALOG INPUT
VOLTAGE LEVEL
INN ANALOG INPUT
VOLTAGE LEVEL
OVERRANGE
ORA/ORB
> VREF + 0.35V
< VREF - 0.35V
1
1111 1111 1111
(exceeds +FS, OR set)
0111 1111 1111
(exceeds +FS, OR set)
VREF + 0.35V
VREF - 0.35V
0
1111 1111 1111
(+FS)
0111 1111 1111
(+FS)
VREF
VREF
0
1000 0000 0000 or
0111 1111 1111
(FS/2)
0000 0000 0000 or
1111 1111 1111
(FS/2)
VREF - 0.35V
VREF + 0.35V
0
0000 0000 0000
(-FS)
1000 0000 0000
(-FS)
< VREF + 0.35V
> VREF - 0.35V
1
00 0000 0000
(exceeds -FS, OR set)
10 0000 0000
(exceeds -FS, OR set)
16
______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
Full-Scale Range Adjustments Using the
Internal Bandgap Reference
The MAX19542 supports a full-scale adjustment range
of ±10%. To decrease the full-scale range, an external
resistor value ranging from 13kΩ to 1MΩ can be added
between REFADJ and AGND. A similar approach can
be taken to increase the ADCs full-scale range. Add a
variable resistor, potentiometer, or predetermined resistor value between REFADJ and REFIO to increase the
full-scale range of the data converter. Figure 8 shows
the two possible configurations and their impact on the
ADC FULL SCALE = REFT - REFB
REFT
G
overall full-scale range adjustment of the MAX19542.
Do not use resistor values of less than 13kΩ to avoid
instability of the internal gain regulation loop for the
bandgap reference. Use the following formula to calculate the percentage change of the reference voltage:
VREF (%) = 1.25% x
100kΩ
RADJ
The percentage change is positive when R ADJ is
added between REFADJ and REFIO, and is negative
when RADJ is added between REFADJ and GND.
ADC FULL SCALE = REFT-REFB
REFERENCESCALING
AMPLIFIER
REFT
G
REFERENCESCALING
AMPLIFIER
REFB
REFB
REFERENCE
BUFFER
REFERENCE
BUFFER
1V
REFIO
MAX19542
REFADJ
CONTROL LINE
TO DISABLE
REFERENCE BUFFER
AVCC
1V
0.1µF
13kΩ TO
100kΩ
REFIO
0.1µF
MAX19542
REFADJ
CONTROL LINE
TO DISABLE
REFERENCE BUFFER
AVCC/2
AVCC
13kΩ TO 100kΩ
AVCC/2
Figure 8. Circuit Suggestions to Adjust the ADC’s Full-Scale Range (Simplified Schematic)
______________________________________________________________________________________
17
MAX19542
Applications Information
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
Differential, AC-Coupled, LVPECLCompatible Clock Input
The MAX19542 dynamic performance depends on a
very clean clock source. The phase noise floor of the
clock source has a negative impact on the SNR performance. Spurious signals on the clock signal source
also affect the ADC’s dynamic range. The preferred
method of clocking the MAX19542 is differentially with
LVPECL-compatible input levels. The fast data transition
rates of these logic families minimize the clock-input circuitry’s transition uncertainty, thereby improving the SNR
performance. Apply a 50Ω reverse-terminated clock
signal source with low phase noise AC-coupled into a
fast differential receiver such as the MC100LVEL16
(Figure 9). The receiver produces the necessary
LVPECL output levels to drive the clock inputs of the
data converter.
Transformer-Coupled,
Differential Analog Input Drive
The MAX19542 provides the best SFDR and THD with
fully differential input signals and it is not recommended driving the ADC inputs in single-ended configuration. In differential input mode, even-order harmonics
are usually lower since INP and INN are balanced, and
each of the ADC inputs requires only half the signal
swing compared to a single-ended configuration.
Wideband RF transformers provide an excellent solu-
tion to convert a single-ended source signal to a fully
differential signal, required by the MAX19542 for optimum dynamic performance.
A secondary-side termination of a 1:1 transformer (e.g.,
Mini-Circuit’s ADT1-1WT) into two separate 24.9Ω
±0.1% resistors (use tight resistor tolerances to minimize effects of imbalance; 0.1% would be an ideal
choice) placed between top/bottom and center tap of
the transformer is recommended to maximize the
ADC’s dynamic range. This configuration optimizes
THD and SFDR performance of the ADC by reducing
the effects of transformer parasitics. However, the
source impedance combined with the shunt capacitance provided by a PC board and the ADC’s parasitic
capacitance limit the ADC’s full-power input bandwidth
to approximately 600MHz.
To further enhance THD and SFDR performance at high
input frequencies (>100MHz), a second transformer
(Figure 10) should be placed in series with the singleended-to-differential conversion transformer. This transformer reduces the increase of even-order harmonics
at high frequencies.
For more detailed information on transformer termination methods, refer to the Application Note: SecondarySide Transformer Termination Improves Gain Flatness
in High-Speed ADCs from the Maxim website:
www.maxim-ic.com.
VCLK
0.1µF
SINGLE-ENDED
INPUT TERMINAL 0.1µF
8
0.1µF
2
7
150Ω
MC100LVEL16
0.1µF
50Ω
AVCC OVCC
6
3
510Ω
150Ω
510Ω
4
0.01µF
5
INP
CLKN CLKP
D_0–D_11, OR_
MAX19542
VGND
12
INN
AGND OGND
Figure 9. Differential, AC-Coupled, LVPECL-Compatible Clock Input Configuration
18
______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
SINGLE-ENDED
INPUT TERMINAL
10Ω
0.1µF
OVCC
INP
ADT1-1WT
ADT1-1WT
MAX19542
AVCC
D_0–D_11, OR_
25Ω
MAX19542
25Ω
0.1µF
12
INN
10Ω
AGND
OGND
Figure 10. Analog Input Configuration with Back-to-Back Transformers and Secondary-Side Termination
AVCC
SINGLE-ENDED
INPUT TERMINAL
0.1µF
OVCC
INP
D_0–D_11, OR_
50Ω
0.1µF
MAX19542
INN
12
25Ω
AGND
OGND
Figure 11. Single-Ended AC-Coupled Analog Input Configuration
Single-Ended, AC-Coupled Analog Input
Although not recommended, the MAX19542 can be
used in single-ended mode (Figure 11). Analog signals
can be AC-coupled to the positive input INP through a
0.1µF capacitor and terminated with a 49.9Ω resistor to
AGND. Terminate the negative input with a 24.9Ω resistor and AC ground it with a 0.1µF capacitor.
Grounding, Bypassing, and Board
Layout Considerations
The MAX19542 requires board layout design techniques suitable for high-speed data converters. This
ADC provides separate analog and digital power supplies. The analog and digital supply voltage inputs
AVCC and OVCC accept 1.7V to 1.9V input voltage
ranges. Although both supply types can be combined
and supplied from one source, it is recommended
using separate sources to cut down on performance
degradation caused by digital switching currents that
can couple into the analog supply network. Isolate analog and digital supplies (AVCC and OVCC) where they
enter the PC board with separate networks of ferrite
beads and capacitors to their corresponding grounds
(AGND, OGND).
To achieve optimum performance, provide each supply
with a separate network of a 47µF tantalum capacitor in
parallel with 10µF and 1µF ceramic capacitors.
Additionally, the ADC requires each supply pin to be
bypassed with separate 0.1µF ceramic capacitors
(Figure 12). Locate these capacitors directly at the
ADC supply pins or as close as possible to the
MAX19542. Choose surface-mount capacitors, whose
preferred location should be on the same side as the
converter, to save space and minimize the inductance.
If close placement on the same side is not possible,
these bypassing capacitors may be routed through
vias to the bottom side of the PC board.
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arranged to
match the physical location of analog and digital
ground on the ADC’s package. The two ground planes
should be joined at a single point so the noisy digital
ground currents do not interfere with the analog ground
plane. A major concern with this approach are the
dynamic currents that may need to travel long distances before they are recombined at a common
source ground, resulting in large and undesirable
______________________________________________________________________________________
19
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
ground loops. Ground loops can add to digital noise by
coupling back to the analog front end of the converter,
resulting in increased spur activity and a decreased
noise performance.
Alternatively, all ground pins could share the same
ground plane if the ground plane is sufficiently isolated
from any noisy, digital systems ground. To minimize the
effects of digital noise coupling, ground return vias can
be positioned throughout the layout to divert digital
switching currents away from the sensitive analog sections of the ADC. This does not require additional
ground splitting, but can be accomplished by placing
substantial ground connections between the analog
front end and the digital outputs.
The MAX19542 is packaged in a 68-pin QFN-EP package (package code: G6800-4), providing greater
design flexibility, increased thermal dissipation, and
optimized AC performance of the ADC. The EP must be
soldered down to AGND.
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed
at the package bottom surface, facing the PC board
side of the package. This allows a solid attachment of
the package to the board with standard infrared (IR)
flow-soldering techniques.
Thermal efficiency is one of the factors for the selection
of a package with an exposed pad for the MAX19542.
The exposed pad improves thermal dissipation and
ensures a solid ground connection between the ADC
and the PC board’s analog ground layer.
Take considerable care when routing the digital output
traces for a high-speed, high-resolution data converter.
It is essential to keep trace lengths at a minimum and
place minimal capacitive loading—less than 5pF—on
any digital trace to prevent coupling to sensitive analog
sections of the ADC. Route high-speed digital signal
traces away from sensitive analog traces, and remove
digital ground and power planes from underneath digital
outputs. Keep all signal lines short and free of 90° turns.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. However, the
static linearity parameters for the MAX19542 are measured using the histogram method with a 10MHz input
frequency.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. The
MAX19542’s DNL specification is measured with the
histogram method based on a 10MHz input tone.
BYPASSING-ADC LEVEL
AVCC
BYPASSING-BOARD LEVEL
OVCC
0.1µF
AVCC
0.1µF
1µF
D_0–D_11, OR_
10µF
47µF
ANALOG POWERSUPPLY SOURCE
10µF
47µF
DIGITAL/OUTPUT
DRIVER POWERSUPPLY SOURCE
OVCC
MAX19542
12
1µF
AGND
OGND
NOTE: EACH POWER-SUPPLY PIN (ANALOG
AND DIGITAL) SHOULD BE DECOUPLED WITH
AN INDIVIDUAL 0.1µF CAPACITOR AS CLOSE
AS POSSIBLE TO THE ADC.
Figure 12. Grounding, Bypassing, and Decoupling Recommendations for the MAX19542
20
______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
Aperture Jitter
Figure 13 depicts the aperture jitter (tAJ), which defines
the sample-to-sample variation in the aperture delay.
Aperture jitter is measured in psRMS.
Aperture Delay
Aperture delay (tAD) is the time defined between the
620ps rising edge of the sampling clock and the instant
when an actual sample is taken (Figure 13).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):
SNRdB[max] = 6.02dB x N + 1.76dB
In reality, other noise sources such as thermal noise,
clock jitter, signal phase noise, and transfer function
nonlinearities are also contributing to the SNR calculation and should be considered when determining the
SNR of an ADC.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components excluding the fundamental and the DC offset. In the case of the MAX19542,
SINAD is computed from a curve fit.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value
of the next-largest noise or harmonic distortion component. SFDR is usually measured in dBc with respect to
the carrier frequency amplitude or in dBFS with respect
to the ADC’s full-scale range.
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 2nd-order (or higher) intermodulation products. The individual input tone levels
are usually set to 7dB below full scale and intermodulation products IM2 through IM5 are considered for the
IMD calculation. The various intermodulation products
are defined as follows:
• 2nd-order intermodulation distortion (IM2):
fIN1 + fIN2, fIN2 - fIN1
• 3rd-order intermodulation distortion (IM3):
2fIN1 + fIN2, 2fIN1 - fIN2, 2fIN2 + fIN1, 2fIN2 - fIN1
• 4th-order intermodulation distortion (IM4):
3fIN1 + fIN2, 3fIN1 - fIN2, 3fIN2 + fIN1, 3fIN2 - fIN1
• 5th-order intermodulation distortion (IM5):
4fIN1 + fIN2, 4fIN1 - fIN2, 4fIN2 + fIN1, 4fIN2 - fIN1
Full-Power Bandwidth
A large -1dBFS analog input signal is applied to an
ADC and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. The -3dB point is defined as
the full-power input bandwidth frequency of the ADC.
CLKN
CLKP
ANALOG
INPUT
tAD
tAJ
SAMPLED
DATA (T/H)
T/H
TRACK
HOLD
TRACK
Figure 13. Aperture Jitter/Delay Specifications
______________________________________________________________________________________
21
MAX19542
Dynamic Parameter Definitions
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
22
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND
PATTERN NO.
68 QFN-EP
G6800+4
21-0122
90-0245
______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
REVISION
NUMBER
REVISION
DATE
0
11/04
Initial release
1
10/10
Updated Ordering Information and Electrical Characteristics
DESCRIPTION
PAGES
CHANGED
—
1, 3
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX19542
Revision History