ICS87993I Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH GENERAL DESCRIPTION FEATURES The ICS87993I is a PLL clock driver designed specifically for redundant clock tree designs. The HiPerClockS™ device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signal frequency and phase while the other three pairs generate 2x, phase aligned clock outputs. External PLL feedback is used to also provide zero delay buffer performance. • 5 differential 3.3V LVPECL outputs The ICS87993I Dynamic Clock Switch (DCS) circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary clock, the DCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. • Cycle-to-cycle jitter (RMS): 20ps (maximum) ,&6 • Selectable differential clock inputs • CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • VCO range: 200MHz to 500MHz • External feedback for “zero delay” clock regeneration with configurable frequencies • Output skew: 70ps (maximum), within one bank • 3.3V supply voltage • -40°C to 85°C ambient operating temperature • Pin compatible with MPC993 PIN ASSIGNMENT VCC nQB2 QB2 nQB1 QB1 nQB0 VCC QB0 24 23 22 21 20 19 18 17 nQA1 25 16 VCC QA1 26 15 INP0BAD nQA0 27 14 INP1BAD QA0 28 13 CLK_SELECTED VCC 29 12 VEE VCCA 30 11 nEXT_FB MAN_OVERRIDE 31 10 EXT_FB PLL_SEL 32 ICS87993I 32-Lead QFP (LQFP) 7mm x 7mm x 1.4mm package body Y Package Top View 9 5 6 7 8 CLK1 nCLK1 VEE nALARM_RESET PLL_SEL 4 CLK_SEL nMR BLOCK DIAGRAM 3 nCLK0 2 CLK0 1 VEE CLK_SELECTED INP1BAD INP0BAD Dynamic Switch Logic MAN_OVERRIDE nQB0 ALARM_RESET QB0 nQB1 SEL_CLK nCLK0 CLK0 nCLK1 CLK1 QB1 ÷2 ÷4 PLL QB2 nQA0 nEXT_FB QA0 EXT_FB nQA1 QA1 nMR 87993AYI nQB2 www.icst.com/products/hiperclocks.html 1 REV. B May 21, 2003 ICS87993I Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH TABLE 1. PIN DESCRIPTIONS Number Name Type 1 nMR Input 2 nALARM_RESET Input 3 CLK0 Input 4 nCLK0 Input 5 SEL_CLK Input 6 CLK1 Input Description Active LOW Master Reset. When logic LOW, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs Pullup nQx to go high. When logic HIGH, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. When LOW, resets the input bad flags and aligns CLK_SELECTED Pullup with SEL_CLK. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Clock select input. When LOW, selects CLK0, nCLK0 inputs. When Pulldown HIGH, selects CLK1, nCLK1 inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. 7 nCLK1 Input 8, 9, 12 VEE Power 10 EXT_FB Input 11 nEXT_FB Input 13 CLK_SELECTED Output 14 INP1BAD Output 15 INP0BAD Output VCC Power Core supply pins. nQB2, QB2 Output Differential output pair. LVPECL interface levels. 20, 21 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 22, 23 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 25, 26 nQA1, QA1 Output Differential output pair. LVPECL interface levels. 27, 28 nQA0, QA0 Output Differential output pair. LVPECL interface levels. 30 VCCA Power 31 MAN_OVERRIDE Input 32 PLL_SEL Input 16, 17, 24, 29 18, 19 Pullup Inver ting differential clock input. Negative supply pins. Pulldown Differential external feedback. Pullup Differential external feedback. LOW, when CLK0, nCLK0 is selected, HIGH, when CLK1, nCLK1 is selected. LVCMOS / LVTTL interface levels. Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asser ted. Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asser ted. Analog supply pin. Manual override. When HIGH, disables internal clock switch circuitr y. Pulldown LVCMOS / LVTTL interface levels. Selects between the PLL and reference clock as the input to the Pullup dividers. When LOW, selects reference clock.When HIGH, selects PLL. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ 87993AYI Test Conditions Minimum www.icst.com/products/hiperclocks.html 2 Typical Maximum Units REV. B May 21, 2003 ICS87993I Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VCC Core Supply Voltage Test Conditions 3.135 3.3 3.465 V 3.135 VCCA Analog Supply Voltage 3.3 3.465 V IEE Power Supply Current 80 180 mA ICCA Analog Supply Current 15 20 mA TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL VOH Test Conditions Maximum Units 2 3.3 V -0.3 0.8 V VIN = VCC = 3.465V 5 µA VIN = VCC = 3.465V 120 µA LVCMOS Inputs LVCMOS Inputs SEL_CLK, MAN_OVERRIDE Input High Current nALARM_RESET, PLL_SEL, nMR SEL_CLK, MAN_OVERRIDE Input Low Current nALARM_RESET, PLL_SEL, nMR Output High Voltage; NOTE 1 Minimum Typical VIN = 0V, VCC = 3.465V -5 µA VIN = 0V, VCC = 3.465V -120 µA 2.4 V VOL Output Low Voltage; NOTE 1 NOTE 1: Outputs terminated with 50Ω to VCC/2. See Parameter Measurement Information Section, "3.3V Output Load AC Test Circuit diagram". 0.5 V Maximum Units VIN = VCC = 3.465V 5 µA VIN = VCC = 3.465V 120 µA TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = -40°C TO 85°C Symbol IIH IIL VPP Parameter Test Conditions CLK0, CLK1, EXT_FB Input High Current nCLK0, nCLK1, nEXT_FB CLK0, CLK1, EXT_FB Input Low Current nCLK0, nCLK1, nEXT_FB Peak-to-Peak Input Voltage Minimum VIN = 0V, VCC = 3.465V -5 µA VIN = 0V, VCC = 3.465V -120 µA 0.15 Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended appliations, the maximum input voltage for CLK, nCLK is VCC + 0.3V. 87993AYI Typical www.icst.com/products/hiperclocks.html 3 1.3 V VCC - 0.85 V REV. B May 21, 2003 ICS87993I Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCC - 1.4 Typical VCC - 1.0 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 4. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions fVCO PLL VCO Lock Range Minimum tPWI CLKx to Q tPD Propagation Delay tR / tF Output Rise Time t sk(o) Output Skew; NOTE 3 ∆ PER/CYCLE Rate of change of Periods Maximum Units 200 500 MHz 25 75 % 2.8 3.45 4.1 ns -150 0 170 ps -150 0 200 ps 800 ps Within Bank 70 ps All Outputs 75MHz Output; NOTE 1, 4 150MHz Output; NOTE 1, 4 75MHz Output; NOTE 1, 5 150MHz Output; NOTE 1, 5 100 ps 20 50 ps/cycle 10 25 ps/cycle 200 400 ps/cycle 100 200 ps/cycle CLKx to EXT_FB; NOTE 2 PLL_SEL = LOW PLL_SEL = HIGH fVCO ≤ 360MHz PLL_SEL = HIGH fVCO ≤ 500MHz 20% to 80% @ 50MHz Typical Tested at typical conditions f ≤ 360MHz Output Duty Cycle 200 odc t jit(cc) 55 % Cycle-to-Cycle Jitter (RMS); NOTE 1 45 20 ps tL PLL Lock Time; NOTE 1 10 ms All parameters measured at fMAX unless noted otherwise. NOTE 1: These parameters are guaranteed by characterization. Not tested in production. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Specification holds for a clock switch between two signals no greater than 400ps out of phase. Delta period change per cycle is averaged over the clock switch excursion. NOTE 5: Specification holds for a clock switch between two signals no greater than ±π out of phase. Delta period change per cycle is averaged over the clock switch excursion. 87993AYI www.icst.com/products/hiperclocks.html 4 REV. B May 21, 2003 ICS87993I Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH PARAMETER MEASUREMENT INFORMATION VCC , VCCA = 2V VCC Qx SCOPE nCLK0, nCLK1 LVPECL V V Cross Points PP CMR CLK0, CLK1 nQx VEE VEE = -1.3V ± 0.165V DIFFERENTIAL INPUT LEVEL nQx nQAx, nQBx Qx nQAx, nQBx ➤ nQy tcycle ➤ 3.3V OUTPUT LOAD AC TEST CIRCUIT ➤ n tcycle n+1 ➤ Qy t jit(cc) = tcycle n –tcycle n+1 tsk(o) 1000 Cycles OUTPUT SKEW CYCLE-TO-CYCLE JITTER 80% nQAx, nQBx nQAx, nQBx 80% VSW I N G Clock Outputs 20% 20% tR Pulse Width t PERIOD tF odc = t PW t PERIOD OUTPUT RISE/FALL TIME 87993AYI odc & tPERIOD www.icst.com/products/hiperclocks.html 5 REV. B May 21, 2003 ICS87993I Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87993I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01µF 10 Ω VCCA .01µF 10 µF FIGURE 1. POWER SUPPLY FILTERING TERMINATION FOR LVPECL OUTPUTS drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50Ω 5 2 Zo FIN FOUT 5 2 Zo Zo = 50Ω Zo = 50Ω FOUT ➤ RTT = 1 (VOH + VOL / VCC –2) –2 VCC - 2V Zo = 50Ω RTT 3 2 Zo Zo FIGURE 2A. LVPECL OUTPUT TERMINATION 87993AYI FIN 50 Ω 50Ω 3 2 Zo FIGURE 2B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 6 REV. B May 21, 2003 ICS87993I Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 3 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 87993AYI www.icst.com/products/hiperclocks.html 7 REV. B May 21, 2003 ICS87993I Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 4A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER BY FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 87993AYI BY www.icst.com/products/hiperclocks.html 8 REV. B May 21, 2003 ICS87993I Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH SCHEMATIC EXAMPLE Figure 5A shows a schematic example of the ICS87993I. In this example, the CLK0/nCLK0 input is selected as primary. The input is driven by an LVPECL driver. Feedback can be either from Bank A or Bank B depending on the application. The decoupling capacitors should be physically located near the power pin. For ICS87993I, the unused outputs can be left floating. VCC VCC VCC R16 1K R15 1K Zo = 50 + R7 10 Zo = 50 VCCA C11 VCC C16 10u LVPECL Driv er R2 1K R9 50 R10 50 C7 (Option) 0.1u R11 50 nMR nALM_RS CLK0 nCLK0 CLK_SEL CLK1 nCLK1 VEE VEE EXT_FB nEXT_FB VEE CLK_SELECTED INP1BAD INP0BAD VCC CLK_SEL Zo = 50 Ohm 1 2 3 4 5 6 7 8 R1 50 32 31 30 29 28 27 26 25 PLL_SEL MAN_OVR VCCA VCC QA0 nQA0 QA1 nQA1 U1 VCC Zo = 50 Ohm R2 50 0.01u ICS87993I C5 (Option) 0.1u VCC QB0 nQB0 QB1 nQB1 QB2 nQB2 VCC R3 50 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 LVCMOS VCC LVCMOS Zo = 50 Ohm R5 50 R4 50 LVCMOS Zo = 50 Ohm LVPECL Driv er C8 (Option) 0.1u R12 50 C6 (Option) 0.1u R6 50 R13 50 R14 50 LVCMOS (U1-16) VCC (U1-17) C1 0.1uF (U1-24) C2 0.1uF (U1-29) C3 0.1uF C4 0.1uF FIGURE 5A. ICS87993I LVPECL SCHEMATIC EXAMPLE 87993AYI www.icst.com/products/hiperclocks.html 9 REV. B May 21, 2003 ICS87993I Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH The following component footprints are used in this layout example: trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. All the resistors and capacitors are size 0603. POWER AND GROUNDING • The differential 50Ω output traces should have same length. Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the • Make sure no other signal traces are routed between the clock trace pair. • The series termination resistors should be located as close to the driver pins as possible. GND R7 C16 C11 C4 VCC U1 C3 VCCA Pin 1 VIA 50 Ohm Traces C2 C1 FIGURE 5B. PCB BOARD LAYOUT FOR ICS87993I 87993AYI www.icst.com/products/hiperclocks.html 10 REV. B May 21, 2003 ICS87993I Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS87993I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS87993I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 180 = 624mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 30.2mW = 151mW Total Power_MAX (3.465V, with all outputs switching) = 624mW + 151mW = 775mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 5 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.775W * 42.1°C/W = 117.6°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 5. THERMAL RESISTANCE qJA FOR 32-PIN LQFP, FORCED CONVECTION qJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 87993AYI www.icst.com/products/hiperclocks.html 11 REV. B May 21, 2003 ICS87993I Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CC_MAX • – 1.0V OH_MAX OL_MAX CC_MAX CC_MAX ) = 1.0V -V For logic low, VOUT = V (V =V -V OL_MAX =V CC_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CC_MAX - 2V))/R ] * (V CC_MAX L -V ) = [(2V - (V OH_MAX CC_MAX -V OH_MAX ))/R ] * (V CC_MAX L -V OH_MAX )= [(2V - 1V)/50Ω] * 1V = 20.0mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 87993AYI www.icst.com/products/hiperclocks.html 12 REV. B May 21, 2003 ICS87993I Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS87993I is: 2745 87993AYI www.icst.com/products/hiperclocks.html 13 REV. B May 21, 2003 ICS87993I Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH PACKAGE OUTLINE - Y SUFFIX TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC L 0.45 0.60 0.75 q 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 87993AYI www.icst.com/products/hiperclocks.html 14 REV. B May 21, 2003 ICS87993I Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS87993AYI ICS87993AYI 32 Lead LQFP 250 per tray -40°C to 85°C ICS87993AYIT ICS87993AYI 32 Lead LQFP on Tape and Reel 1000 -40°C to 85°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87993AYI www.icst.com/products/hiperclocks.html 15 REV. B May 21, 2003 ICS87993I Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH REVISION HISTORY SHEET Rev A B Table T4 Page 4 7 1 Added "Wiring the Differential Input to Accept Single Ended Levels". Features Section - changed VCO max. from 360MHz to 500MHz. T1 2 Pin Descriptions Table - revised nMR description. T2 2 Pin Characteristics Table - changed CIN from max. 4pF to typical 4pF. 3 Absolute Maximum Ratings - changed VO to IO and included Continuous Current and Surge Current 4 AC Characteristics Table - changed fVCO from 360MHz to 500MHz. tPD - added test conditions to CLKx to EXT_FB. Added another line with 500MHz test conditions. odc - added test conditions. 8 Added Differential Clock Input Interface in the Application Information section. T4 9 & 10 87993AYI Description of Change AC Table - deleted Note 6. Date 1/16/03 5/21/03 Added Schematic Example. www.icst.com/products/hiperclocks.html 16 REV. B May 21, 2003