Maxim MAX8554EEE 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load application Datasheet

19-3017; Rev 0; 10/03
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
Features
♦ Up to 25A Output-Current Capability
♦ Quick-PWM Control for Fast Loop Response
♦ Up to 95% Efficiency
♦ 4.5V to 28V Input Voltage Range
♦ No External Bias Supply Required
♦ 0 to 3.6V Input REFIN Range (MAX8553)
♦ Automatically Sets VTT and VTTR to within ±1%
of 1/2 VREFIN- (MAX8553)
♦ Low 0.6V Feedback Threshold (MAX8554)
♦ 200kHz/300kHz/400kHz/550kHz Selectable
Switching Frequencies
♦ Adjustable Foldback Current Limit
♦ Overvoltage Protection
♦ Digital Soft-Start
Typical Operating Circuit
VIN
+5V
DH
EN/HSD
Applications
Wide-Input Power Supplies
Servers and Storage Applications
ASIC and CPU Core Voltages
Notebook and LCD-PC Power Supplies
POK
MAX8553
POK
VL
REFIN
REFIN
V+
BST
V+
LX
REF
DL
Ordering Information
ILIM
PGND
TEMP RANGE
PIN-PACKAGE
FSEL
VTT
MAX8553EEE
-40°C to +85°C
16 QSOP
GND
VTTR
MAX8554EEE
-40°C to +85°C
16 QSOP
DDR I and DDR II Memory Power Supplies
AGTL Bus Termination Supplies
PART
VOUT
VTTR
Pin Configurations appear at end of data sheet.
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX8553/MAX8554
General Description
The MAX8553 is a 4.5V to 28V input-voltage, synchronous step-down controller that provides a complete
power-management solution for DDR memory. The
MAX8553 generates 1/2 VREFIN voltage for VTT and
VTTR. The VTT and VTTR tracking voltages are maintained within 1% of 1/2 VREFIN. The MAX8554 is a 4.5V to
28V input voltage, nontracking step-down controller with
a low 0.6V feedback threshold voltage. The MAX8553/
MAX8554 use Maxim’s proprietary Quick-PWM™ architecture for fast transient response and operate with
selectable pseudo-fixed frequencies. Both controllers
can operate without an external bias supply.
The controllers operate in synchronous-rectification mode
to ensure balanced current sourcing and sinking capability of up to 25A. The MAX8553/MAX8554 also provide up
to 95% efficiency, making them ideal for server and pointof-load applications. Additionally, a low 5µA shutdown
current allows for longer battery life in notebook applications. Lossless current monitoring is achieved by monitoring the low-side MOSFET’s drain-to-source voltage. The
MAX8553/MAX8554 have an adjustable foldback current
limit to withstand a continuous output overload and short
circuit. Digital soft-start provides control of inrush current
during power-up. Overvoltage protection shuts the converter down and discharges the output capacitor. The
MAX8553/MAX8554 come in space-saving 16-pin QSOP
packages.
MAX8553/MAX8554
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
ABSOLUTE MAXIMUM RATINGS
V+, EN/HSD, EN, HSD to GND...............................-0.3V to +30V
PGND to GND .......................................................-0.3V to +0.3V
VTT, REFIN, POK, OUT, FB, VL to GND...................-0.3V to +6V
REF, VTTR, DL, ILIM, FSEL to GND ............-0.3V to (VVL + 0.3V)
LX to PGND ...............................................................-2V to +30V
BST to GND ............................................................-0.3V to +36V
DH to LX ...................................................................-0.3V to +6V
LX to BST..................................................................-6V to +0.3V
REF Short Circuit to GND ...........................................Continuous
Continuous Power Dissipation (TA = +70°C)
16-Pin QSOP (derated 8.3mW/°C above +70°C) ........667mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VV+ = VHSD = +12V, VEN/HSD = VREFIN = +2.5V, VEN = +5V, CVL = 4.7µF, CVTTR = 1µF, CREF = 0.22µF, VFSEL = 0V, ILIM = VL,
PGND = LX = GND, BST = VL, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise specified.)
PARAMETER
V+ Input Voltage Range
CONDITIONS
VL not connected to V+
MIN
TYP
6
MAX
UNITS
28
V
V+ Input Voltage Range
VL connected to V+
4.5
5.5
V
EN/HSD Input Voltage Range
MAX8553 enabled
1.5
28.0
V
EN Input Voltage Range
MAX8554 enabled
1.5
28.0
V
3
µA
MAX8554 enabled
1.5
EN Input Current
HSD Input Voltage Range
2
HSD Input Current
REFIN Input Voltage Range
28.0
V
20
40
µA
3.6
V
V+ Supply Current (MAX8553)
VVTT = +1.35V
0
0.8
1.2
mA
V+ Supply Current (MAX8554)
VFB = 630mV
0.62
0.90
mA
125
250
µA
5
10
µA
0.8
1.2
mA
REFIN Supply Current
EN/HSD Supply Current
VL Supply Current
VVL = VV+ = 5.5V, VVTT = +1.35V
V+ Shutdown Supply Current
EN/HSD = GND
REFIN Shutdown Supply Current
EN/HSD = GND
3
5
µA
1
µA
5
12
µA
4.25
4.40
V
VL Shutdown Supply Current
VVL = VV+ = +5.5V, VEN/HSD = 0V
VL Undervoltage-Lockout Threshold
Rising edge, typical hysteresis = 40mV
4.05
VVTT = +1.25V
-0.15
0
µA
0
1.8
V
VTT
VTT Input Bias Current
VTT Feedback Voltage Range
VTT Feedback Voltage Accuracy
FB Input Bias Current
2
VREFIN = VEN/HSD = +1.8V
49.5
50
50.5
VREFIN = VEN/HSD = +3.6V
49.5
50
50.5
MAX8554, VFB = +600mV
-0.15
_______________________________________________________________________________________
0
% VREFIN
µA
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
(VV+ = VHSD = +12V, VEN/HSD = VREFIN = +2.5V, VEN = +5V, CVL = 4.7µF, CVTTR = 1µF, CREF = 0.22µF, VFSEL = 0V, ILIM = VL,
PGND = LX = GND, BST = VL, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise specified.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.598
0.607
0.616
V
3.5
V
FB Regulation Voltage
MAX8554, VOUT = +2.5V, FSEL unconnected
Output Adjust Range
MAX8554 (Note 1)
VTT Line Regulation
VEN/HSD ±10%, VVTT = +1.25V, IOUT = 0A
±0.325
%
FB Line Regulation
MAX8554, VHSD ±10%, VOUT = +2.5V,
IOUT = 0A, FSEL unconnected
±0.325
%
VTT Load Regulation
0 < IOUT < +7A, VVTT = +1.25V
0.2
%
FB Load Regulation
MAX8554, 0 < IOUT < +7A, VOUT = +2.5V,
FSEL unconnected
0.2
%
0.6
REFERENCE
Reference Output Voltage
VV+ = VVL = +4.5 to +5.5V, IREF = 0
1.97
2.00
2.03
V
Reference Load Regulation
VV+ = VVL = +5V, IREF = 0 to 50µA
10
mV
Reference UVLO
VV+ = VVL = +5V, reference rising, hysteresis = 27mV
1.5
1.6
1.7
V
0
49.5
50
1.8
50.5
V
IVTTR = -5mA to +5mA
% VREFIN
VTTR
VTTR Output Voltage Range
VTTR Output Accuracy
Thermal Shutdown
IVTTR = -25mA to +25mA, VREFIN = +1.8V
49
50
51
IVTTR = -25mA to +25mA, VREFIN = +3.6V
49.5
50
50.5
Rising temperature, typical hysteresis = 15°C
°C
+160
SOFT-START
ILIM Ramp Period
Ramps the ILIM trip threshold from 20% to 100% in
20% increments
0.8
1.7
3.0
ms
Output Predischarge Period
Rising edge of EN/HSD to the start of internal digital
soft-start
0.8
1.7
3.0
ms
OSCILLATOR
Oscillator Frequency
FSEL = VL
200
FSEL = unconnected
300
FSEL = REF
400
FSEL = GND
On-Time
MAX8553, VVTT = +1.25V
(Note 2)
On-Time
MAX8554, VOUT = +2.5V
(Note 2)
Off-Time
(Note 2)
kHz
550
FSEL = VL
2.18
2.5
2.83
FSEL unconnected
1.45
1.67
1.89
FSEL = REF
1.09
1.25
1.41
FSEL = GND
0.82
0.91
1.00
FSEL = VL
0.89
1.02
1.16
FSEL unconnected
0.61
0.71
0.80
FSEL = REF
0.43
0.49
0.56
FSEL = GND
0.33
0.37
0.41
350
400
µs
µs
ns
_______________________________________________________________________________________
3
MAX8553/MAX8554
ELECTRICAL CHARACTERISTICS (continued)
MAX8553/MAX8554
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
ELECTRICAL CHARACTERISTICS (continued)
(VV+ = VHSD = +12V, VEN/HSD = VREFIN = +2.5V, VEN = +5V, CVL = 4.7µF, CVTTR = 1µF, CREF = 0.22µF, VFSEL = 0V, ILIM = VL,
PGND = LX = GND, BST = VL, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise specified.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
LX to PGND, ILIM = VL
80
100
115
LX to PGND, RILIM = 100kΩ
35
50
65
LX to PGND, RILIM = 400kΩ
160
200
230
LX to PGND, ILIM = VL, with respect to positive
current-limit threshold
-130
-110
-90
UNITS
CURRENT LIMIT
Current-Limit Threshold (Positive
Direction)
Current-Limit Threshold (Negative
Direction)
ILIM Input Current
5
mV
%
µA
FAULT DETECTION
MAX8553 (VREFIN > +1V)
57
60
63
MAX8553 (VREFIN ≤ +1V)
0.576
0.600
0.624
MAX8554
0.696
0.720
0.744
Output Voltage
+6V < VV+ <+28V, 1mA < IVL < 35mA
4.80
5.0
5.33
V
Line Regulation
+6V < VV+ < +28V, IVL = 10mA
35
mA
Overvoltage Threshold
% VREFIN
V
VL REGULATOR
0.2
RMS Output Current
Bypass Capacitor
ESR < 100mΩ
%
2.2
µF
DRIVER
DH Gate-Driver On-Resistance
VBST - VLX = +5V
1.4
2.5
Ω
DL Gate-Driver On-Resistance
(Source)
DL high state
1.6
3.0
Ω
DL Gate-Driver On-Resistance
(Sink)
DL low state
0.75
1.25
Ω
Dead Time
DL rising
32
DL falling
30
ns
FSEL LOGIC
Logic Input Current
-3
Logic Low (GND)
+3
µA
0.5
V
Logic REF Level
FSEL = REF
1.65
2.35
V
Logic Float Level
FSEL unconnected
3.15
3.85
V
Logic VL Level
FSEL = VL
VVL - 0.4
V
EN/HSD OR EN LOGIC
EN/HSD or EN Shutdown Current
Max IEN/HSD for VEN/HSD < +0.8V or VEN < +0.8V
0.5
Logic High
VVL = VV+ = +4.5 to +5.5V, 100mV hysteresis
1.5
Logic Low
VVL = VV+ = +4.5 to +5.5V
4
_______________________________________________________________________________________
3.0
µA
V
0.8
V
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
(VV+ = VHSD = +12V, VEN/HSD = VREFIN = +2.5V, VEN = +5V, CVL = 4.7µF, CVTTR = 1µF, CREF = 0.22µF, VFSEL = 0V, ILIM = VL,
PGND = LX = GND, BST = VL, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise specified.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POWER-OK OUTPUT
Upper VTT and VTTR Threshold
MAX8553
55
56
57
% VREFIN
Lower VTT and VTTR Threshold
MAX8553
43
44
45
% VREFIN
Upper Threshold
MAX8554
0.646
0.672
0.698
V
Lower Threshold
MAX8554
0.504
0.528
0.552
V
POK Output Low Level
ISINK = 2mA
0.4
V
POK Output High Leakage
VPOK = +5V
5
µA
ELECTRICAL CHARACTERISTICS
(VV+ = VHSD = +12V, VEN/HSD = VREFIN = +2.5V, VEN = +5V, CVL = 4.7µF, CVTTR = 1µF, CREF = 0.22µF, VFSEL = 0, ILIM = VL, PGND
= LX = POK = GND, BST = VL, TA = -40°C to +85°C, unless otherwise specified.) (Note 3)
PARAMETER
CONDITIONS
V+ Input Voltage Range
VL not connected to V+
V+ Input Voltage Range
VL connected to V+
MIN
MAX
UNITS
6
28
V
4.5
5.5
V
EN/HSD Input Voltage Range
MAX8553 enabled
1.5
28.0
V
EN Input Voltage Range
MAX8554 enabled
1.5
28.0
V
3
µA
EN Input Current
HSD Input Voltage Range
MAX8554 enabled
1.5
HSD Input Current
REFIN Input Voltage Range
0
28.0
V
40
µA
3.6
V
V+ Supply Current (MAX8553)
VVTT = +1.35V
1.2
mA
V+ Supply Current (MAX8554)
VFB = 630mV
0.90
mA
REFIN Supply Current
250
µA
EN/HSD Supply Current
10
µA
1.2
mA
VL Supply Current
VVL = VV+ = 5.5V, VVTT = +1.35V
V+ Shutdown Supply Current
EN/HSD = GND
5
µA
REFIN Shutdown Supply Current
EN/HSD = GND
1
µA
VL Shutdown Supply Current
VVL = VV+ = +5.5V, VEN/HSD = 0V
VL Undervoltage-Lockout Threshold
Rising edge, typical hysteresis = 40mV
4.05
12
µA
4.40
V
VVTT = +1.25V
-0.2
0
µA
0
1.8
V
VREFIN = VEN/HSD = +1.8V
49.5
50.5
VREFIN = VEN/HSD = +3.6V
49.5
50.5
VTT
VTT Input Bias Current
VTT Feedback Voltage Range
VTT Feedback Voltage Accuracy
FB Input Bias Current
MAX8554, VFB = +600mV
FB Regulation Voltage
MAX8554, VOUT = +2.5V, FSEL unconnected
Output Adjust Range
MAX8554 (Note 1)
% VREFIN
-0.2
0
µA
0.598
0.616
V
0.6
3.5
V
_______________________________________________________________________________________
5
MAX8553/MAX8554
ELECTRICAL CHARACTERISTICS (continued)
MAX8553/MAX8554
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
ELECTRICAL CHARACTERISTICS (continued)
(VV+ = VHSD = +12V, VEN/HSD = VREFIN = +2.5V, VEN = +5V, CVL = 4.7µF, CVTTR = 1µF, CREF = 0.22µF, VFSEL = 0, ILIM = VL, PGND
= LX = POK = GND, BST = VL, TA = -40°C to +85°C, unless otherwise specified.) (Note 3)
PARAMETER
CONDITIONS
MIN
MAX
UNITS
1.97
2.03
V
10
mV
1.7
V
V
REFERENCE
Reference Output Voltage
VV+ = VVL = +4.5 to +5.5V, IREF = 0
Reference Load Regulation
VV+ = VVL = +5V, IREF = 0 to 50µA
Reference UVLO
VV+ = VVL = +5V, reference rising, hysteresis = 27mV
1.5
0
1.8
IVTTR = -5mA to +5mA
49.5
50.5
IVTTR = -25mA to +25mA, VREFIN = +1.8V
49
51
IVTTR = -25mA to +25mA, VREFIN = +3.6V
49.5
50.5
ILIM Ramp Period
Ramps the ILIM trip threshold from 20% to 100% in
20% increments
0.8
3.0
ms
Output Predischarge Period
Rising edge of EN/HSD to the start of internal digital
soft-start
0.8
3.0
ms
FSEL = VL
2.18
2.83
FSEL unconnected
1.45
1.89
FSEL = REF
1.09
1.41
FSEL = GND
0.82
1.00
FSEL = VL
0.89
1.16
FSEL unconnected
0.61
0.80
FSEL = REF
0.43
0.56
FSEL = GND
0.33
0.41
VTTR
VTTR Output Voltage Range
VTTR Output Accuracy
% VREFIN
SOFT-START
OSCILLATOR
On-Time
MAX8553, VVTT = +1.25V
(Note 2)
On-Time
MAX8554, VOUT = +2.5V
(Note 2)
Off-Time
(Note 2)
420
µs
µs
ns
CURRENT LIMIT
Current-Limit Threshold (Positive
Direction)
Current-Limit Threshold (Negative
Direction)
LX to PGND, ILIM = VL
80
115
LX to PGND, RILIM = 100kΩ
30
65
LX to PGND, RILIM = 400kΩ
150
230
LX to PGND, ILIM = VL, with respect to positive
current-limit threshold
-130
-90
ILIM Input Current
mV
%
µA
FAULT DETECTION
Overvoltage Threshold
%
MAX8553 (VREFIN > +1V)
57
63
MAX8553 (VREFIN ≤ +1V)
0.576
0.624
MAX8554
0.696
0.744
+6V < VV+ < +28V, 1mA < IVL < 35mA
4.80
5.33
V
35
mA
ESR < 100mΩ
2.2
V
VL REGULATOR
Output Voltage
RMS Output Current
Bypass Capacitor
6
_______________________________________________________________________________________
µF
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
(VV+ = VHSD = +12V, VEN/HSD = VREFIN = +2.5V, VEN = +5V, CVL = 4.7µF, CVTTR = 1µF, CREF = 0.22µF, VFSEL = 0, ILIM = VL, PGND
= LX = POK = GND, BST = VL, TA = -40°C to +85°C, unless otherwise specified.) (Note 3)
PARAMETER
CONDITIONS
MIN
MAX
UNITS
DRIVER
DH Gate-Driver On-Resistance
VBST - VLX = +5V
2.5
Ω
DL Gate-Driver On-Resistance
(Source)
DL high state
3.0
Ω
DL Gate-Driver On-Resistance
(Sink)
DL low state
1.25
Ω
-3
+3
µA
0.5
V
FSEL LOGIC
Logic Input Current
Logic Low (GND)
Logic REF Level
FSEL = REF
1.65
2.35
V
Logic Float Level
FSEL unconnected
3.15
3.85
V
Logic VL Level
FSEL = VL
VVL - 0.4
V
EN/HSD OR EN LOGIC
EN/HSD or EN Shutdown Current
Max IEN/HSD for VEN/HSD < +0.8V or VEN < +0.8V
0.5
Logic High
VVL = VV+ = +4.5 to +5.5V, 100mV hysteresis
1.5
Logic Low
VVL = VV+ = +4.5 to +5.5V
3.0
µA
V
0.8
V
57
% VREFIN
POWER-OK OUTPUT
Upper VTT, and VTTR Threshold
MAX8553
55
Lower VTT, and VTTR Threshold
MAX8553
43
45
% VREFIN
Upper Threshold
MAX8554
0.646
0.698
V
Lower Threshold
MAX8554
0.504
0.552
V
POK Output Low Level
ISINK = 2mA
0.4
V
POK Output High Leakage
VPOK = +5V
5
µA
Note 1: Consult factory for applications that require higher than 3.5V output.
Note 2: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX forced to 0V, BST
forced to 5V, and a 250pF capacitor connected from DH to LX. Actual in-circuit times may differ due to MOSFET switching
speeds.
Note 3: Specifications to -40°C are guaranteed by design and are not production tested.
_______________________________________________________________________________________
7
MAX8553/MAX8554
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(VV+ = 12V, VOUT = 1.8V, circuit of Figure 1, TA = +25°C, unless otherwise noted.)
EFFICIENCY (%)
VIN = 2.5V
VOUT = 1.25V
60
60
50
40
40
30
0.1
1.0
600
550
500
450
400
0.1
10.0
1.0
10.0
100.0
-8
-6
-4
-2
0
2
4
6
8
LOAD CURRENT (A)
LOAD CURRENT (A)
OUTPUT CURRENT (A)
SWITCHING FREQUENCY
vs. INPUT VOLTAGE (CIRCUIT OF FIGURE 3)
FREQUENCY vs. TEMPERATURE
MAX8554 SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE
FREQUENCY (kHz)
280
260
240
200
190
180
220
170
200
160
6
8
10 12 14 16 18 20 22 24 26 28
MAX8553/4 toc06
210
5.0
4.5
SHUTDOWN SUPPLY CURRENT (µA)
300
MAX8553/4 toc05
220
MAX8553/4 toc04
320
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
V+ = HSD, EN = GND
0
-40
-15
10
35
60
4
85
8
12
16
20
24
INPUT VOLTAGE (V)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
MAX8553 SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE
LOAD REGULATION
(CIRCUIT OF FIGURE 1)
LOAD REGULATION
(CIRCUIT OF FIGURE 2)
4.0
1.84
OUTPUT VOLTAGE (V)
3.5
3.0
2.5
2.0
1.5
1.0
1.82
1.80
1.78
1.76
0.5
1.31
1.29
OUTPUT VOLTAGE (V)
4.5
28
MAX8553/4 toc09
1.86
MAX8553/4 toc07
5.0
MAX8553/4 toc08
SWITCHING FREQUENCY (kHz)
70
50
30
VTT CONNECTED
TO THE OUTPUT
1.27
1.25
1.23
VTT CONNECTED AS
SHOWN IN FIGURE 2
1.21
EN = GND
0
1.74
4
8
12
16
20
INPUT VOLTAGE (V)
8
VOUT = 1.8V
650
MAX8553/4 toc03
90
80
VIN = 1.8V
VOUT = 0.9V
70
VOUT = 2.5V
SWITCHING FREQUENCY (kHz)
80
MAX8553/4 toc02
90
EFFICIENCY (%)
100
MAX8553/4 toc01
100
SWITCHING FREQUENCY vs.
OUTPUT CURRENT (CIRCUIT OF FIGURE 2)
EFFICIENCY vs. LOAD CURRENT
(CIRCUIT OF FIGURE 1)
EFFICIENCY vs. LOAD CURRENT
(CIRCUIT OF FIGURE 2)
SHUTDOWN SUPPLY CURRENT (µA)
MAX8553/MAX8554
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
24
28
1.19
0
4.0
8.0
12.0
LOAD CURRENT (A)
16.0
20.0
0
2
4
LOAD CURRENT (A)
_______________________________________________________________________________________
6
8
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
LOAD TRANSIENT 0A TO 20A TO 0A
(CIRCUIT OF FIGURE 1)
LOAD TRANSIENT -8A TO +8A TO -8A
(CIRCUIT OF FIGURE 2)
MAX8553/4 toc10
IOUT
MAX8553/4 toc11
10A/div
100mV/div
AC-COUPLED
VOUT
VOUT
20mV/div
AC-COUPLED
IOUT
40µs/div
0
5A/div
40µs/div
VTT CONNECTED TO THE OUTPUT
SWITCHING WAVEFORMS WITH 20A LOAD
(CIRCUIT OF FIGURE 1)
LOAD TRANSIENT -8A TO +8A TO -8A
(CIRCUIT OF FIGURE 2)
MAX8553/4 toc12
MAX8553/4 toc13
20mV/div
AC-COUPLED
VOUT
VLX
5V/div
0
20mV/div
AC-COUPLED
VOUT
IOUT
0
5A/div
IL
10A/div
40µs/div
VTT CONNECTED AS SHOWN IN FIGURE 2
2µs/div
_______________________________________________________________________________________
9
MAX8553/MAX8554
Typical Operating Characteristics (continued)
(VV+ = 12V, VOUT = 1.8V, circuit of Figure 1, TA = +25°C, unless otherwise noted.)
MAX8553/MAX8554
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
Typical Operating Characteristics (continued)
(VV+ = 12V, VOUT = 1.8V, circuit of Figure 1, TA = +25°C, unless otherwise noted.)
POWER-DOWN WAVEFORMS WITH 20A LOAD
(CIRCUIT OF FIGURE 1)
POWER-UP WAVEFORMS WITH 20A LOAD
(CIRCUIT OF FIGURE 1)
MAX8553/4 toc15
MAX8553/4 toc14
VIN
VIN
10V/div
VOUT
1V/div
VPOK
5V/div
10V/div
VOUT
IL
10A/div
1V/div
VPOK
5V/div
IL
10A/div
0
0
1ms/div
2ms/div
STARTUP/SHUTDOWN WAVEFORMS WITH
20A LOAD (CIRCUIT OF FIGURE 1)
SHORT CIRCUIT AND RECOVERY
(CIRCUIT OF FIGURE 1)
MAX8553/4 toc16
MAX8553/4 toc17
VEN
5V/div
VLX
VOUT
1V/div
IL
VPOK
5V/div
20V/div
5A/div
1V/div
2A/div
IIN
0
2ms/div
10
0A
0V
VOUT
200µs/div
______________________________________________________________________________________
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
PIN
MAX8553
MAX8554
EN/HSD
—
—
HSD
REFIN
—
Reference Input. An applied voltage at REFIN sets VVTT and VVTTR to 1/2 VREFIN. REFIN voltage
range is from 0 to +3.6V.
—
EN
Enable. Drive EN high to enable the output. Drive EN low to shut down the IC. If the enable
function is not used, connect EN to V+.
POK
POK
VTT
—
VTT Feedback Input. Connect to VTT output.
—
FB
Output Feedback. Connect to the center of a resistor-divider between the output and ground to
set the output voltage. FB threshold is 0.6V.
5
ILIM
ILIM
Current-Limit Threshold Adjustment. Connect a resistor from ILIM to GND to set the current-limit
threshold, or connect ILIM to VL for the default setting. See the Setting the Current Limit section.
6
FSEL
FSEL
Frequency Select. Selects the switching frequency. See Tables 1 and 2 for configuration of
FSEL.
1
FUNCTION
Enable/High-Side Drain. Connect to the high-side N-channel MOSFET drain through a 5.1kΩ
resistor for normal operation. Connect to GND for low-power shutdown (Figure 2). If the enable
function is not used, connect EN/HSD directly to the high-side N-channel MOSFET drain.
High-Side Drain. Connect to the high-side N-channel MOSFET drain for normal operation.
2
3
4
Power-OK Output. POK is an open-drain output and is logic high when both VTT and VTTR are
within 12% of regulation. POK is pulled low in shutdown.
7
REF
REF
Reference. Connect a 0.22µF or greater capacitor from REF to GND.
8
GND
GND
Ground
VTTR
—
—
OUT
10
V+
V+
Input Supply Voltage. Supply input for the VL regulator. Bypass with a 0.22µF or greater
capacitor.
11
VL
VL
Internal Regulator Output. Connect a 2.2µF or greater capacitor from VL to GND. VL can be
connected to V+ if the operating range is from +4.5V to +5.5V.
12
DL
DL
Low-Side MOSFET Gate Drive. Connect to the gate of the low-side N-channel MOSFET. DL is
low in shutdown or in undervoltage lockout.
13
PGND
PGND
VTTR Reference Output. Connect a 1µF or greater capacitor from VTTR to GND. VTTR is
capable of sourcing and sinking up to 25mA.
9
Output Voltage. Connect directly to the output. OUT senses the output voltage to determine the
on-time for the high-side switching MOSFET.
Power Ground
14
BST
BST
Bootstrapped Supply. Drives high-side N-channel MOSFET. Connect a 0.1µF or greater
capacitor from BST to LX.
15
DH
DH
High-Side MOSFET Gate Drive. Connect to the high-side N-channel MOSFET gate. DH is low in
shutdown or in undervoltage lockout.
16
LX
LX
Inductor Switching Node
______________________________________________________________________________________
11
MAX8553/MAX8554
Pin Description
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
MAX8553/MAX8554
Functional Diagrams
ILIM
5µA
VTT
FSEL
ON-TIME
COMPUTE
Q
TRIG
ONE-SHOT
BST
/10
S
TON
DH
Q
TRIG
Q
R
ONE-SHOT
Σ
POK
LATCH
VTTR
POK
LX
VTT
Q
R
S
Σ
VL
REFIN
DL
EN/HSD
OVP
ERROR
COMP
PGND
60%
VTT
56%
V+
50%
44%
0.6V
VL
5V
REG
MAX8553
2V
REF
REF
GND
VTTR
12
______________________________________________________________________________________
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
OUT
ILIM
5µA
FSEL
ON-TIME
COMPUTE
Q
TRIG
ONE-SHOT
BST
/10
S
TON
DH
Q
TRIG
Q
R
ONE-SHOT
Σ
HSD
POK
LX
LATCH
FB
Q
POK
R
S
EN
Σ
VL
DL
OVP
ERROR
COMP
PGND
0.600V
FB
0.720V
V+
0.672V
0.528V
VL
5V
REG
MAX8554
2V
REF
REF
GND
______________________________________________________________________________________
13
MAX8553/MAX8554
Functional Diagrams (continued)
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
MAX8553/MAX8554
Typical Application Circuits
VL
R1
20kΩ
POK
POK
FSEL
V+
ON
VL
C7
0.22µF
10V
C4
0.47µF
10V
HSD
REF
VIN
12V
BST
EN
OFF
C3
4.7µF
6.3V
D1
CMPSH-3
DH
MAX8554
Q1
IRF7832
L1
1.0µH
30A
2.5V AT
20A VOUT
LX
Q2
2xIRF7832
DL
R4
25.5kΩ
R6
1Ω
R2
19.1kΩ
PGND
OUT
R5
110kΩ
C5
10µF
6.3V
C6
3x470µF
4V
C8
4700pF
ILIM
C1
10µF
16V
C2
2x470µF
16V
OPTIONAL
R3
6.04kΩ
PGND
GND
FB
Figure 1. Typical Application Circuit 1: 12V Input, 2.5V Output at Up to 20A with 200kHz Switching Frequency
VL
R2
5.1kΩ
R3
20kΩ
POK
POK
V+
REFIN
6V TO 28V
VL
V+
R8
20Ω
EN/HSD
SDN
R5
100kΩ
Q3
2N7002K
C2
2x330µF
6V
C4
0.47µF
6.3V
C11
1µF
C8
0.22µF
10V
VIN
2.5V
BST
REFIN
C9
0.47µF
25V
C3
4.7µF
6.3V
D1
CMPSH-3
MAX8553
Q1
IRF7821
DH
Q2
IRF7821
DL
PGND
VTT
ILIM
R4
0.002Ω
1.25V AT
VOUT
8A
LX
REF
R1
143kΩ
L1
0.68µH
9A
R7
3Ω
C10
2200µF
C5
10µF
6.3V
GND
C6
4x470µF
2V
PGND
FSEL
VTTR
C7
1µF
6.3V
R6
54.9kΩ
C1
10µF
6.3V
VTTR
TO VOUT
Figure 2. Typical Application Circuit 2: 2.5V Input, 1.25V VTT at Up to 8A, and 1.25V VTTR at Up to 25mA with 550kHz Switching
14
______________________________________________________________________________________
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
MAX8553/MAX8554
VL
R1
20kΩ
POK
POK
FSEL
V+
ON
VL
C7
0.22µF
10V
17V TO 21V
VIN
BST
C4
0.47µF
10V
EN
OFF
C3
4.7µF
6.3V
D1
CMPSH-3
HSD
DH
MAX8554
REF
C1
10µF
16V
C2
470µF
16V
Q1
IRF7807V
L1
2.5µH
10A
1.8V AT
VOUT
8A
LX
DL
R4
61.9kΩ
Q2
IRF7821
R6
3Ω
R2
12.1kΩ
C6
2x470µF
4V
C8
2200pF
PGND
OUT
ILIM
R5
80.6kΩ
C5
10µF
6.3V
R3
6.04kΩ
PGND
GND
FB
Figure 3. Typical Application Circuit 3: 19V Input, 1.8V Output at Up to 8A with 300kHz Switching Frequency
Detailed Description
Internal Linear Regulator
An internal regulator produces the +5V supply (VL) that
powers the PWM controller, MOSFET driver, logic, reference, and other blocks within the IC. This +5V lowdropout (LDO) linear regulator supplies up to 35mA for
MOSFET gate-drive and external loads. For supply voltages between +4.5V and +5.5V, connect VL to V+. This
bypasses the VL regulator, which improves efficiency
and allows the IC to function at lower input voltages.
On-Time One-Shot and
Switching Frequency
The heart of the PWM is the one-shot that sets the highside switch on-time. This fast, low-jitter, adjustable oneshot includes circuitry that varies the on-time in
response to both input and output voltages. The highside switch on-time is inversely proportional to the input
voltage as measured by the EN/HSD (HSD for the
MAX8554) input, and is directly proportional to the output voltage. This algorithm results in a nearly constant
switching frequency despite the lack of a fixed-frequency clock generator. The switching frequency can
be selected to avoid noise-sensitive regions such as
the 455kHz IF band. Also, with a constant switching frequency, the inductor ripple-current operating point
remains relatively constant, resulting in easy design
methodology and predictable output voltage ripple.
The general formula for the MAX8553 on-time (tON) is:
t ON = K × N ×
1
VEN / HSD
× VOUT
where VEN/HSD and VOUT are the voltages measured at
EN/HSD and the output, respectively, and K = 1.7µs.
The value of N depends on the configuration of FSEL
and is listed in Table 1.
For the MAX8554, the general formula for on-time (tON) is:
t ON = K × N ×
1
VHSD
× VOUT
where VHSD and VOUT are the voltages measured at
HSD and the output, respectively, and K = 1.7µs. The
value of N depends on the configuration of FSEL and is
listed in Table 2.
______________________________________________________________________________________
15
MAX8553/MAX8554
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
Table 1. Configuration of FSEL (MAX8553)
FSEL CONNECTED TO
N
tON (µs)
FREQUENCY (kHz)
CONDITION
Ground
1.07
0.91
550
VOUT / VEN/HSD = 0.5
REF
1.33
1.15
400
VOUT / VEN/HSD = 0.5
Floating
2.00
1.70
300
VOUT / VEN/HSD = 0.5
VL
3.00
2.55
200
VOUT / VEN/HSD = 0.5
Table 2. Configuration of FSEL (MAX8554)
FSEL CONNECTED TO
N
tON (µs)
FREQUENCY (kHz)
CONDITION
Ground
1.07
0.37
550
VHSD = 12V, VOUT = 2.5V
REF
1.33
0.49
400
VHSD = 12V, VOUT = 2.5V
Floating
2.00
0.71
300
VHSD = 12V, VOUT = 2.5V
VL
3.00
1.02
200
VHSD = 12V, VOUT = 2.5V
This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock
generator. The actual switching frequency, which is
given by the following equation, varies slightly due to
the voltage drop across the on-resistance of the
MOSFETs and the DC resistance of the output inductor:
fS =
1
D
≅
t ON
K × N
where D is the duty cycle:
D =
VOUT + IO (RDSONL + RDC )
VHSD + IO (RDSONL - RDSONH )
where IO is the output current, RDSONL is the on-resistance of the low-side MOSFET, RDSONH is the on-resistance of the high-side MOSFET, and RDC is the DC
resistance of the output inductor. The ideal switching frequency for VREFIN = 2.5V is about 550kHz. Switching frequency increases for positive (sourcing) load current
and decreases for negative (sinking) load current, due to
the changing voltage drop across the low-side MOSFET,
which changes the inductor-current discharge ramp
rate. The on-times guaranteed in the Electrical
Characteristics are also influenced by switching delays
caused by the loading effect of the external power
MOSFETs.
The switching frequency can also be adjusted to a
value other than the preset frequencies by adding a
resistor voltage-divider at HSD. See the Adjusting the
Switching Frequency section.
16
VTTR Reference (MAX8553 Only)
The MAX8553’s VTTR output is capable of sourcing or
sinking up to 25mA of current. The VTTR output voltage
is one-half of the voltage applied to REFIN. Bypass
VTTR with at least a 1µF ceramic capacitor.
Voltage Reference
The voltage at REF is nominally 2.00V. Connect a 0.22µF
ceramic bypass capacitor between REF and GND.
EN and HSD (MAX8554 Only)
EN is a logic input used to enable or shut down the
MAX8554. Drive EN high or connect to V+ to enable the
output. Drive EN low to place the MAX8554 in lowpower shutdown mode, reducing input current to less
than 5µA (typ).
HSD senses the input voltage at the drain of the high-side
MOSFET, which is used to set the high-side MOSFET ontime. For normal operation, connect HSD to the drain of
the high-side MOSFET.
EN/HSD Function (MAX8553 Only)
In order to reduce pin count and package size, the
MAX8553 features a dual-function input pin, EN/HSD.
When EN/HSD is pulled to ground, the internal circuitry
powers off, reducing current consumption to less than
5µA (typ). To enable normal operation, connect
EN/HSD to the drain of the high-side MOSFET through
a 5.1kΩ resistor (Figure 2). In this configuration, EN/HSD
becomes an input that monitors the high-side MOSFET
drain voltage (converter input voltage) and uses that
measurement to calculate the appropriate on-time for the
converter. If the enable function is not used, connect
EN/HSD directly to the high-side MOSFET drain.
______________________________________________________________________________________
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
Overvoltage Protection (OVP)
When the buck output voltage rises above 120% of the
nominal regulation voltage, the OVP circuit sets the
fault latch, shuts down the PWM controller, and immediately pulls DH low and forces DL high. The negative
current limit is also disabled. This turns on the low-side
MOSFET, which rapidly discharges the output capacitors and clamps the output to ground. Note that immediately latching DL high can cause the output voltage
to go slightly negative due to energy stored in the output LC at the instant the OVP occurs. If the load cannot
tolerate a negative voltage, place a power Schottky
diode from the output to PGND (anode to PGND) to act
as a reverse-polarity clamp. Cycle EN or input power to
reset the latch.
Digital Soft-Start
The current-limit circuit employs a unique “valley” current-sensing algorithm that uses the on-resistance of
the low-side MOSFET as a current-sensing element. If
the current-sense signal is above the current-limit
threshold, the PWM is not allowed to initiate a new
cycle. The actual peak current is greater than the current-limit threshold by an amount equal to the inductor
ripple current (Figure 4). Therefore, the exact currentlimit characteristic and maximum load capability are a
function of the MOSFET on-resistance, the inductor
value, and the input voltage. The reward for this uncertainty is robust, lossless overcurrent sensing. There is
also a negative current limit that prevents excessive
reverse inductor currents when VOUT is sinking current.
The negative current-limit threshold is set to approximately 110% of the positive current limit, and therefore
tracks the positive current limit when ILIM is adjusted.
The current-limit threshold can be adjusted with an
external resistor (RILIM) at ILIM. A precision 5µA pullup
current source at ILIM sets a voltage drop on this resistor, adjusting the current-limit threshold from approximately 50mV to 200mV. In the adjustable mode, the
current-limit threshold voltage is precisely 1/10 the voltage seen at ILIM. Therefore, choose RILIM equal to
2kΩ/mV of the current-limit threshold. The threshold
defaults to 100mV when ILIM is connected to VL. The
logic threshold for switchover to the 100mV default
value is approximately VVL - 1V. The adjustable current
limit can accommodate various MOSFETs. Alternately,
foldback current limit can also be implemented by
adding a resistor from ILIM to VOUT. See the Setting the
Current Limit section.
The digital soft-start allows a gradual increase of the
internal current-limit level during startup to reduce the
input surge current. The MAX8553/MAX8554 divide the
soft-start period into five phases. During the first phase,
the controller limits the current limit to only 20% of the
full current limit. If the output does not reach the regulation within 425µs, soft-start enters the second phase
and the current limit is increased by another 20%. This
process repeats until the maximum current limit is
reached (after 1.7ms) or when the output reaches the
nominal regulation voltage, whichever occurs first.
Adding a capacitor in parallel with the external ILIM
resistor creates a continuously adjustable analog softstart function. If the foldback current-limiting feature is
implemented in the application circuit, the maximum
current limit is also a function of the output voltage and
the resistors connected to ILIM.
Power-Good Output (POK)
POK is the open-drain output of the internal window
comparators that continuously monitor VTT and VTTR
for the MAX8553 and FB for the MAX8554. POK is
actively held low in shutdown, and becomes high
impedance when the outputs are within 12% of their
respective nominal regulation voltage.
Overcurrent Protection
______________________________________________________________________________________
17
MAX8553/MAX8554
Predischarge Mode
The MAX8553/MAX8554 discharge the output to GND
before the digital soft-start begins. When EN/HSD (EN)
is pulled high, the MAX8553 (MAX8554) starts an internal counter, and forces VDL to VVL. This discharges the
output to GND through the low-side MOSFET. If the output voltage is above ground before enable, the output
voltage goes slightly negative due to energy stored in
the output LC. If the load cannot tolerate a negative voltage, place a power Schottky diode from the output to
PGND (anode to PGND) to act as a reverse-polarity
clamp. The period for this discharge mode is 1.7ms.
Both the buck controller and the VTTR buffer are turned
off during this period. After the predischarge period,
both the buck controller and the VTTR buffer are turned
on and go through soft-start.
IPEAK
ILOAD
INDUCTOR CURRENT
MAX8553/MAX8554
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
IVALLEY
Design Procedure
Setting the Output Voltage
TIME
Figure 4. Inductor-Current Waveform
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the current-sense signals seen by LX and PGND. The IC must
be mounted close to the low-side MOSFET with short,
direct traces making a Kelvin-sense connection to the
source and drain terminals. See the PC Board Layout
section.
Voltage Positioning
The Quick-PWM control architecture responds virtually
instantaneously to transient load changes and eliminates the control loop delay of conventional PWM controllers. Therefore, a large portion of the voltage
deviation during a step load change is from the ESR
(equivalent series resistance) of the output capacitors.
For DDR termination applications, the maximum
allowed voltage deviation is ±40mV for any output load
transition from sourcing current to sinking current.
Passive voltage positioning adjusts the converter’s output voltage based on its load current to optimize transient response and minimize the required output
capacitance.
Voltage positioning is implemented by connecting a
low ohmic resistor (R4) as shown in Figure 2.
MOSFET Drivers
The DH and DL drivers are optimized to drive
MOSFETs that can deliver up to 25A output current. An
adaptive dead-time circuit monitors the DL output and
prevents the high-side MOSFET from turning on until
DL is fully off. There must be a low-resistance, lowinductance path from the DL driver to the MOSFET gate
in order for the adaptive dead-time circuit to work prop-
18
erly. Otherwise, the sense circuitry in the MAX8553/
MAX8554 can interpret the MOSFET gate as “off” while
there is actually still charge left on the gate. Use very
short, wide traces measuring 10 squares to 20 squares
(50 mils to 100 mils wide if the MOSFET is 1in from the
MAX8553/MAX8554). This adaptive dead-time delay is
in addition to a fixed delay of 30ns (typ). The dead time
at the other edge (DH turning off) is determined by a
fixed 32ns (typ) internal delay.
For the MAX8553, the output voltage, VVTT, is always
50% of VREFIN.
For the MAX8554, the output voltage can be adjusted
from 600mV to 3.5V using a resistive voltage-divider
(R2 and R3 in Figures 1 and 3). To set the voltage,
choose a value for R3 in the range of 1kΩ to 10kΩ, then
solve for R2 using the following equation:
V

R2 = R3  OUT - 1
 VFB

where VFB is 0.6V.
Inductor Selection
Three key inductor parameters must be specified:
inductance value (L), peak inductor current (IPEAK),
and DC resistance (R DC ). A good compromise
between size and efficiency is to set the inductor peakto-peak ripple current equal to 30% of the maximum
load current, thus LIR = 0.3. The switching frequency,
input voltage, output voltage, and selected LIR determine the inductor value as follows:
L =
VOUT(VIN
−
VOUT)
VIN x fS x ILOAD(MAX) x LIR
where fS is the switching frequency. The exact inductor
value is not critical and can be adjusted in order to
make trade-offs among size, cost, and efficiency.
Lower inductor values minimize size and cost and also
improve transient response but reduce efficiency and
increase output voltage ripple due to higher peak currents. Higher inductance increases efficiency by reducing the RMS current.
Find a low-loss inductor with the lowest possible DC
resistance that fits in the allotted dimensions. The
inductor’s current saturation rating must exceed the
______________________________________________________________________________________
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
 LIR 
IPEAK = ILOAD(MAX) + 
 ×I
 2  LOAD(MAX)
Output-Capacitor Stability Consideration
Stability is determined by the value of the ESR zero relative to the switching frequency. To ensure stability, the
following condition must be met:
f
fESR < S
π
Output-Capacitor Selection
The key selection parameters for the output capacitor
are the actual capacitance value, the ESR, the equivalent series inductance (ESL), and the voltage-rating
requirements, which affect the overall stability, output
ripple voltage, and transient response.
The worst-case output ripple has three components:
variations in the charge stored in the output capacitor,
the voltage drop across the capacitor’s ESR, and ESL
caused by the current into and out of the capacitor.
This can be approximated by:
VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C) + VRIPPLE(ESL)
The output voltage ripple due to the ESR is:
VRIPPLE(ESR) = IP-P × ESR
The output voltage ripple due to the output capacitance is:
VRIPPLE(C) =
IP-P
8 × COUT × fS
The output voltage ripple due to the ESL of the output
capacitor is:
VRIPPLE (ESL) = (VIN x ESL) / (L+ESL)
IP-P is the peak-to-peak inductor current:
IP-P =
VIN - VOUT VOUT
×
VIN
fS × L
After a load transient, the output voltage instantly
changes by ESR x ∆ILOAD + ESL x di/dt and the controllers respond within 100ns and try to regulate back to
the nominal output value.
Solid polymer or OSCON electrolytic capacitors are
recommended due to their low ESR and ESL at the
switching frequency. Higher output-current applications
require multiple output capacitors connected in parallel
to meet the output ripple-voltage requirements. Do not
exceed the capacitor’s voltage or ripple-current ratings.
where fS is the switching frequency and:
fESR =
1
2π × RESR × COUT
For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz.
Do not put high-value ceramic capacitors directly
across the feedback sense point without taking precautions to ensure stability. Large ceramic capacitors can
have a high-ESR zero frequency and cause erratic,
unstable operation. However, it is easy to add enough
series resistance by placing the capacitors a couple of
inches downstream from the feedback sense point,
which should be as close as possible to the inductor.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage-ripple envelope for overshoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under- or overshoot.
Input-Capacitor Selection
The input capacitor (CIN) reduces the current peaks
drawn from the input supply and reduces noise injection. The source impedance to the input supply largely
determines the value of CIN. High source impedance
requires high input capacitance. The input capacitor
must meet the ripple current requirement (I RMS )
imposed by the switching currents. The RMS input ripple current is given by:
IRMS = ILOAD ×
VOUT × (VIN - VOUT )
VIN
IRMS has a maximum value of 1/2 ILOAD, which occurs
when VIN is twice VOUT.
For optimal circuit reliability, choose a capacitor that
has less than 10°C temperature rise at the peak ripple
current.
______________________________________________________________________________________
19
MAX8553/MAX8554
peak inductor current at the maximum-defined load
current (ILOAD(MAX)):
MAX8553/MAX8554
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
Setting the Current Limit
Constant Current Limit
The adjustable current limit accommodates MOSFETs
with a wide range of on-resistance values. The currentlimit threshold is adjusted with an external resistor connected from ILIM to GND (R ILIM_ ). The adjustment
range is 50mV to 200mV measured across the low-side
MOSFET. The value of RILIM is calculated using the following formula:
DH
VOUT
MAX8553
LX
I
RILIM = 10 × VALLEY × RDS(ON)
5µA
DL
where IVALLEY is the valley current limit and RDS(ON) is
the on-resistance of the low-side MOSFET. To avoid
reaching the current at a lower current than expected,
use the maximum value for RDS(ON) at elevated junction temperature. Refer to the MOSFET manufacturer’s
data sheet for maximum values.
Foldback Current Limit
Foldback current limit is used to reduce power dissipation during overload and short-circuit conditions. This is
accomplished by lowering the current-limit threshold as
the output voltage drops due to the overload.
To use foldback current limit, connect a resistor
(RFOBK) from ILIM to the output, and connect a resistor
(RILIM) from ILIM to GND (Figure 5). The values of RILIM
and RFOBK are calculated as follows:
First, select the percentage of foldback, PFB. This percent corresponds to the current limit when VOUT equals
zero divided by the current limit when VOUT equals its
nominal voltage. Typical values range from 15% to
30%. To solve for the resistor values, use the following
equations:
RFOBK =
RILIM =
PFB × VOUT
(
5µA 1 - PFB
(
)
)
RILIM
ILIM
PGND
RFOBK
Figure 5. Setting the Foldback Current Limit with Two
Resistors, RILIM and RFOBK
Adjusting the Switching Frequency
The switching frequency of the MAX8553/MAX8554 can
be lowered from the value set by FSEL by adding a
resistor voltage-divider to EN/HSD (HSD) as shown in
Figure 6. This voltage-divider lowers the voltage the IC
measures on EN/HSD (HSD), which increases the ontime. The switching frequency with the added resistordivider is calculated as follows:
fS ≅
where K = 1.7µs and N is given in Tables 1 and 2. To set
the frequency, select a value for R2 between 10kΩ and
100kΩ, then calculate R1 from the following equation:
10 × RDS(ON) × IVALLEY × 1 - PFB × RFOBK
(
R2
1
×
K × N
R1 + R2
(
VOUT - 10 × RDS(ON) × IVALLEY × 1 - PFB
))
If RILIM results in a negative number, select another lowside MOSFET with lower RDS(ON) or increase PFB or a
combination of both for the best compromise of cost,
efficiency, and lower short-circuit power dissipation.
R1 =
R2
1
×
- R2
K × N fS
With the minimum input voltage, make sure that the
voltage present at EN/HSD (HSD) is greater than 1.5V
when the resistor-divider is used:
VIN(MIN) × R2
R1 + R2
20
> 1.5V
______________________________________________________________________________________
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
RDRP <
VOUT(TYP) - VOUT(MIN) - VRIPPLE / 2
IOUT(MAX)
R DRP introduces some power dissipation, which is
given by:
(
PD(DRP) = RDRP × IOUT(MAX)
)2
RDRP should be chosen to handle this power dissipation.
Power MOSFET Selection
The MAX8553/MAX8554 drive external, logic-level, Nchannel MOSFETs as the circuit-switch elements. The
key selection parameters are:
On-resistance (RDS(ON)): The lower, the better.
Maximum drain-to-source voltage (V DSS ): This
should be at least 20% higher than the input supply rail
at the high-side MOSFET’s drain.
Gate charges (QG, QGD, QGS): The lower, the better.
R1
VIN
POK
VL
V+
BST
REFIN
DH
MAX8553
Q3
2N7002
EN/HSD
LX
Choose the MOSFETs with rated RDS(ON) at VGS = 4.5V.
For a good compromise between efficiency and cost,
choose the high-side MOSFET that has a conduction
loss equal to switching loss at nominal input voltage and
maximum output current (see below). For the low-side
MOSFET, make sure that it does not spuriously turn on
because of the dV/dt caused by the high-side MOSFET
turning on, as this would result in shoot-through current
degrading the efficiency. MOSFETs with a lower QGD to
QGS ratio have higher immunity to dV/dt.
For proper thermal-management design, calculate the
power dissipation at the desired maximum operating
junction temperature, maximum output current, and
worst-case input voltage (for low-side MOSFET, worst
case is at VIN(MAX); for high-side MOSFET, it could be
either at VIN(MIN) or VIN(MAX)). The high-side MOSFET
and low-side MOSFET have different loss components
due to the circuit operation. The low-side MOSFET
operates as a zero voltage switch; therefore, major
losses are: the channel conduction loss (PLSCC), the
body-diode conduction loss (PLSDC), and the gatedrive loss (PLSDR):
 V

2
PLSCC = 1- OUT  × (ILOAD ) × RDS(ON)
VIN 

Use RDS(ON) at TJ(MAX):
PLSDC = 2 × ILOAD × VF × tDT × fS
where VF is the body-diode forward-voltage drop, tDT is
the dead time (~30ns), and fS is the switching frequency.
Because of the zero-voltage switch operation, low-side
MOSFET gate-drive loss occurs as a result of charging
and discharging the input capacitance (CISS). This loss
is distributed among the average DL gate driver’s
pullup and pulldown resistance, RDL (~1.2Ω), and the
internal gate resistance (RGATE) of the MOSFET (~2Ω).
The drive power dissipated is given by:
PLSDR = CISS × (VGS ) × fS ×
2
SDN
R2
R6
10kΩ
REF
DL
ILIM
PGND
FSEL
VTT
GND
VTTR
RGATE
RGATE + RDL
The high-side MOSFET operates as a duty-cycle control switch and has the following major losses: the
channel conduction loss (PHSCC), the VI overlapping
switching loss (PHSSW), and the drive loss (PHSDR).
The high-side MOSFET does not have body-diode conduction loss because the diode never conducts current.
Figure 6. A resistor-divider (R1 and R2) is used to lower the
switching frequency.
______________________________________________________________________________________
21
MAX8553/MAX8554
Setting Voltage Positioning
The droop resistor, RDRP (R4) in Figure 2, in series with
the output inductor before the output capacitor, sets the
droop voltage, VDRP. Choose RDRP such that the output
voltage at the maximum load current, including ripple, is
just above the lower limit of the output tolerance:
MAX8553/MAX8554
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
V
2
PHSCC = OUT × (ILOAD ) × RDS(ON)
VIN
Use RDS(ON) at TJ(MAX):
PHSSW = VIN × ILOAD × fS ×
QGS + QGD
IGATE
where IGATE is the average DH driver output current
determined by:
IGATE =
2.5V
RDH + RGATE
where RDH is the high-side MOSFET driver’s on-resistance (1.4Ω typ) and RGATE is the internal gate resistance of the MOSFET (~2Ω):
PHSDR = QG × VGS × fS ×
RGATE
RGATE + RDH
where VGS = VVL = 5V.
When the MAX8553 is sinking current, the high-side
MOSFET operates as a zero-voltage switch and the
low-side MOSFETs operate as a nonzero-voltage
switch.
In addition to the losses above, allow about 20% more
for additional losses due to MOSFET output capacitances and low-side MOSFET body-diode reverse
recovery charge dissipated in the high-side MOSFET
that is not well defined in the MOSFET data sheet. Refer
to the MOSFET data sheet for thermal-resistance specifications to calculate the PC board area needed to
maintain the desired maximum operating junction temperature with the above calculated power dissipations.
To reduce EMI caused by switching noise, add a 0.1µF
ceramic capacitor from the high-side switch drain to
the low-side switch source, or add resistors in series
with DH and DL to slow down the switching transitions.
Adding series resistors increases the power dissipation
of the MOSFET, so ensure that this does not overheat
the MOSFET.
22
Control IC Power Dissipation
Power dissipation in the MAX8553/MAX8554 IC is primarily due to the on-chip MOSFETs’ gate drivers (DH
and DL). This power dissipation depends on the gate
charge of the external MOSFETs used. Power dissipation in the MAX8553 also depends on the VTTR load
current (IVTTR). Use the following equation to calculate
the power dissipation:
[
PD = (VV + ) × fS × (QGH + QGL ) + IVTTR
]
where QGH and QGL are the total gate charge of the
high-side and low-side MOSFETs, respectively. Select
the switching frequency and VV+ correctly to ensure
the power dissipation does not exceed the package
power-dissipation requirement.
Applications Information
PC Board Layout
A properly designed PC board layout is important in
any switching regulator. The switching power stage
requires particular attention. If possible, mount all the
power components on the top-side of the board with
their ground terminals flush against one another. Follow
these guidelines for good PC board layout:
1) Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable, low-jitter operation.
2) Connect GND and PGND together at a single point.
3) Keep the power traces and load connections short.
This practice is essential for high efficiency. The use
of thick copper PC boards (2oz vs. 1oz) can noticeably enhance full-load efficiency. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance causes a measurable efficiency penalty.
4) LX and PGND connections to the low-side MOSFET
for current limiting must be made using Kelvinsense connections in order to guarantee the current-limit accuracy. With 8-pin SO MOSFETs, this
can be done by routing power to the MOSFETs from
______________________________________________________________________________________
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
5) When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor.
6) It may be desirable to deliberately introduce some
trace length (droop resistance) between the FB
inductor node and the output filter capacitor to
meet the stability criteria (fESR < fS / π).
7) Place feedback resistors as close as possible to
the IC.
8) Route high-speed switching nodes away from sensitive analog nodes.
9) Make all pin-strap control input connections (ILIM,
etc.) to GND or VL close to the chip, and do not
connect to PGND.
Pin Configurations
TOP VIEW
EN/HSD 1
16 LX
HSD 1
16 LX
REFIN 2
15 DH
EN 2
15 DH
14 BST
POK 3
POK 3
VTT 4
MAX8553
13 PGND
FB 4
14 BST
MAX8554
13 PGND
ILIM 5
12 DL
ILIM 5
12 DL
FSEL 6
11 VL
FSEL 6
11 VL
REF 7
10 V+
REF 7
10 V+
GND 8
9
GND 8
9
VTTR
QSOP
OUT
QSOP
Chip Information
TRANSISTOR COUNT: 2827
PROCESS: BiCMOS
______________________________________________________________________________________
23
MAX8553/MAX8554
outside using the top copper layer, while tying in
PGND and LX inside (underneath) the 8-pin SO
package.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
QSOP.EPS
MAX8553/MAX8554
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
21-0055
E
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.