TI1 LMV831MGENOPB Lmv831 single/ lmv832 dual/ lmv834 quad 3.3 mhz low power cmos, emi hardened Datasheet

LMV831, LMV832, LMV834
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SNOSAZ6A – AUGUST 2008 – REVISED OCTOBER 2008
LMV831 Single/ LMV832 Dual/ LMV834 Quad 3.3 MHz Low Power CMOS, EMI Hardened
Operational Amplifiers
Check for Samples: LMV831, LMV832, LMV834
FEATURES
DESCRIPTION
•
TI’s LMV831, LMV832, and LMV834 are CMOS input,
low power op amp IC's, providing a low input bias
current, a wide temperature range of −40°C to 125°C
and exceptional performance making them robust
general
purpose
parts.
Additionally,
the
LMV831/LMV832/LMV834 are EMI hardened to
minimize any interference so they are ideal for EMI
sensitive applications.
1
2
•
•
•
•
•
•
•
•
•
•
•
Unless Otherwise Noted, Typical Values at TA=
25°C, V+ = 3.3V
Supply Voltage 2.7V to 5.5V
Supply Current (per Channel) 240 µA
Input Offset Voltage 1 mV Max
Input Bias Current 0.1 pA
GBW 3.3 MHz
EMIRR at 1.8 GHz 120 dB
Input Noise Voltage at 1 kHz 12 nV/√Hz
Slew Rate 2 V/µs
Output Voltage Swing Rail-to-Rail
Output Current Drive 30 mA
Operating Ambient Temperature Range −40°C
to 125°C
APPLICATIONS
•
•
•
•
•
Photodiode Preamp
Piezoelectric Sensors
Portable/Battery-Powered Electronic
Equipment
Filters/Buffers
PDAs/Phone Accessories
The unity gain stable LMV831/LMV832/LMV834
feature 3.3 MHz of bandwidth while consuming only
0.24 mA of current per channel. These parts also
maintain stability for capacitive loads as large as 200
pF. The LMV831/LMV832/LMV834 provide superior
performance and economy in terms of power and
space usage.
This family of parts has a maximum input offset
voltage of 1 mV, a rail-to-rail output stage and an
input common-mode voltage range that includes
ground. Over an operating range from 2.7V to 5.5V
the LMV831/LMV832/LMV834 provide a PSRR of 93
dB, and a CMRR of 91 dB. The LMV831 is offered in
the space saving 5-Pin SC70 package, the LMV832
in the 8-Pin VSSOP and the LMV834 is offered in the
14-Pin TSSOP package.
Typical Application
R1
V
+
NO RF RELATED
DISTURBANCES
-
PRESSURE
SENSOR
+
-
R2
+
ADC
+
EMI HARDENED
EMI HARDENED
INTERFERING
RF SOURCES
Figure 1. EMI Hardened Sensor Application
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
LMV831, LMV832, LMV834
SNOSAZ6A – AUGUST 2008 – REVISED OCTOBER 2008
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Human Body Model
ESD Tolerance (3)
2 kV
Charge-Device Model
1 kV
Machine Model
200V
VIN Differential
± Supply Voltage
Supply Voltage (VS = V+ – V−)
6V
Voltage at Input/Output Pins
V++0.4V,
V− −0.4V
Storage Temperature Range
−65°C to 150°C
Junction Temperature (4)
150°C
Soldering Information
(1)
(2)
(3)
(4)
Infrared or Convection (20 sec)
260°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics Tables.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
Operating Ratings (1)
Temperature Range (2)
−40°C to 125°C
Supply Voltage (VS = V+ – V−)
Package Thermal Resistance (θJA
(1)
(2)
2.7V to 5.5V
(2)
)
5-Pin SC70
302°C/W
8-Pin VSSOP
217°C/W
14-Pin TSSOP
135°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics Tables.
The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
3.3V Electrical Characteristics (1)
Unless otherwise specified, all limits are guaranteed for at TA = 25°C, V+ = 3.3V, V− = 0V, VCM = V+/2, and RL =10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
VOS
Input Offset Voltage (4)
TCVOS
Input Offset Voltage Temperature
Drift (4) (5)
(1)
(2)
(3)
(4)
(5)
2
Min
Typ
Max
Units
±0.25
±1.00
±1.23
mV
LMV831,
LMV832
±0.5
±1.5
LMV834
±0.5
±1.7
(2)
(3)
(2)
μV/°C
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on
shipped production material.
The typical value is calculated by applying absolute value transform to the distribution, then taking the statistical average of the resulting
distribution.
This parameter is guaranteed by design and/or characterization and is not tested in production.
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3.3V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are guaranteed for at TA = 25°C, V+ = 3.3V, V− = 0V, VCM = V+/2, and RL =10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(2)
Typ
Max
Units
0.1
10
500
pA
(3)
IB
Input Bias Current (5)
IOS
Input Offset Current
CMRR
Common-Mode Rejection Ratio (4)
0.2V ≤ VCM ≤ V+ - 1.2V
76
75
91
PSRR
Power Supply Rejection Ratio (4)
2.7V ≤ V+ ≤ 5.5V,
VOUT = 1V
76
75
93
EMIRR
EMI Rejection Ratio, IN+ and IN- (6)
VRF_PEAK=100 mVP (−20 dBP),
f = 400 MHz
80
VRF_PEAK=100 mVP (−20 dBP),
f = 900 MHz
90
VRF_PEAK=100 mVP (−20 dBP),
f = 1800 MHz
110
VRF_PEAK=100 mVP (−20 dBP),
f = 2400 MHz
120
(2)
1
pA
dB
dB
dB
CMVR
Input Common-Mode Voltage Range
CMRR ≥ 65 dB
−0.1
AVOL
Large Signal Voltage Gain (7)
RL = 2 kΩ,
LMV831,
VOUT = 0.15V to 1.65V, LMV832
VOUT = 3.15V to 1.65V
LMV834
102
102
121
102
102
121
RL = 10 kΩ,
VOUT = 0.1V to 1.65V,
VOUT = 3.2V to 1.65V
LMV831,
LMV832
104
104
126
LMV834
104
103
123
RL = 2 kΩ to V+/2
LMV831,
LMV832
29
36
43
LMV834
31
38
44
LMV831,
LMV832
6
8
9
LMV834
7
9
10
R = 2 kΩ to V+/2
25
34
43
RL = 10 kΩ to V+/2
5
8
10
VOUT
Output Voltage Swing High
RL = 10 kΩ to V+/2
Output Voltage Swing Low
IOUT
Output Short Circuit Current
Sourcing, VOUT = VCM,
VIN = 100 mV
LMV831,
LMV832
27
22
28
LMV834
24
19
28
27
21
32
Sinking, VOUT = VCM,
VIN = −100 mV
IS
SR
(6)
(7)
(8)
Supply Current
Slew Rate (8)
2.1
dB
0.24
0.27
0.30
LMV832
0.46
0.51
0.58
LMV834
0.90
1.00
1.16
2
mV from
either rail
mA
LMV831
AV = +1, VOUT = 1 VPP,
10% to 90%
V
mA
V/μs
The EMI Rejection Ratio is defined as EMIRR = 20log ( VRF_PEAK/ΔVOS).
The specified limits represent the lower of the measured values for each output range condition.
Number specified is the slower of positive and negative slew rates.
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3.3V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are guaranteed for at TA = 25°C, V+ = 3.3V, V− = 0V, VCM = V+/2, and RL =10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(2)
Typ
(3)
Max
(2)
Units
GBW
Gain Bandwidth Product
3.3
MHz
Φm
Phase Margin
65
deg
en
Input Referred Voltage Noise Density
f = 1 kHz
12
f = 10 kHz
10
nV/√Hz
in
Input Referred Current Noise Density
f = 1 kHz
0.005
pA/√Hz
ROUT
Closed Loop Output Impedance
f = 2 MHz
500
Ω
CIN
Common-mode Input Capacitance
15
Differential-mode Input Capacitance
20
THD+N
Total Harmonic Distortion + Noise
f = 1 kHz, AV = 1, BW ≥ 500 kHz
pF
0.02
%
5V Electrical Characteristics (1)
Unless otherwise specified, all limits are guaranteed for at TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, and RL = 10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
VOS
Input Offset Voltage (4)
TCVOS
Input Offset Voltage Temperature
Drift (4) (5)
Min
Typ
Max
Units
±0.25
±1.00
±1.23
mV
LMV831,
LMV832
±0.5
±1.5
LMV834
±0.5
±1.7
0.1
10
500
(2)
(3)
μV/°C
IB
Input Bias Current (5)
IOS
Input Offset Current
CMRR
Common-Mode Rejection Ratio (4)
0V ≤ VCM ≤ V+ −1.2V
77
77
93
PSRR
Power Supply Rejection Ratio (4)
2.7V ≤ V+ ≤ 5.5V,
VOUT = 1V
76
75
93
EMIRR
CMVR
(1)
(2)
(3)
(4)
(5)
(6)
4
(2)
1
EMI Rejection Ratio, IN+ and IN-
(6)
Input Common-Mode Voltage Range
VRF_PEAK=100 mVP (−20 dBP),
f = 400 MHz
80
VRF_PEAK=100 mVP (−20 dBP),
f = 900 MHz
90
VRF_PEAK=100 mVP (−20 dBP),
f = 1800 MHz
110
VRF_PEAK=100 mVP (−20 dBP),
f = 2400 MHz
120
CMRR ≥ 65 dB
–0.1
pA
pA
dB
dB
dB
3.8
V
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on
shipped production material.
The typical value is calculated by applying absolute value transform to the distribution, then taking the statistical average of the resulting
distribution.
This parameter is guaranteed by design and/or characterization and is not tested in production.
The EMI Rejection Ratio is defined as EMIRR = 20log ( VRF_PEAK/ΔVOS).
Submit Documentation Feedback
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Product Folder Links: LMV831 LMV832 LMV834
LMV831, LMV832, LMV834
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SNOSAZ6A – AUGUST 2008 – REVISED OCTOBER 2008
5V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are guaranteed for at TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, and RL = 10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
AVOL
VOUT
Parameter
Conditions
Large Signal Voltage Gain (7)
Output Voltage Swing High
IOUT
Output Short Circuit Current
Slew Rate (8)
GBW
Gain Bandwidth Product
Φm
Phase Margin
en
Input Referred Voltage Noise
Max
(2)
107
106
127
LMV834
104
104
127
RL = 10 kΩ,
VOUT = 0.1V to 2.5V,
VOUT = 4.9V to 2.5V
LMV831,
LMV832
107
107
130
LMV834
105
104
127
RL = 2 kΩ to V+/2
LMV831,
LMV832
32
42
49
LMV834
35
45
52
LMV831,
LMV832
6
9
10
LMV834
7
10
11
RL = 2 kΩ to V+/2
27
43
52
RL = 10 kΩ to V+/2
6
10
12
Sourcing VOUT = VCM
VIN = 100 mV
Supply Current
SR
(3)
LMV831,
LMV832
Sinking VOUT = VCM
VIN = −100 mV
IS
Typ
(2)
RL = 2 kΩ,
VOUT = 0.15V to 2.5V,
VOUT = 4.85V to 2.5V
RL = 10 kΩ to V+/2
Output Voltage Swing Low
Min
LMV831,
LMV832
59
49
66
LMV834
57
45
63
LMV831,
LMV832
50
41
64
LMV834
53
41
63
dB
0.25
0.27
0.31
LMV832
0.47
0.52
0.60
LMV834
0.92
1.02
1.18
2
mV from
either rail
mA
LMV831
AV = +1, VOUT = 2VPP,
10% to 90%
Units
mA
V/μs
3.3
MHz
65
deg
f = 1 kHz
12
f = 10 kHz
10
nV/√Hz
in
Input Referred Current Noise
f = 1 kHz
0.005
pA/√Hz
ROUT
Closed Loop Output Impedance
f = 2 MHz
500
Ω
CIN
Common-mode Input Capacitance
14
Differential-mode Input Capacitance
20
THD+N
(7)
(8)
Total Harmonic Distortion + Noise
f = 1 kHz, AV = 1, BW ≥ 500 kHz
0.02
pF
%
The specified limits represent the lower of the measured values for each output range condition.
Number specified is the slower of positive and negative slew rates.
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Connection Diagram
Figure 2. 5-Pin SC70
Top View
6
Figure 3. 8-Pin VSSOP
Top View
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Figure 4. 14-Pin TSSOP
Top View
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Product Folder Links: LMV831 LMV832 LMV834
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SNOSAZ6A – AUGUST 2008 – REVISED OCTOBER 2008
Typical Performance Characteristics
At TA = 25°C, RL = 10 kΩ, V+ = 3.3V, V− = 0V, Unless otherwise specified.
VOS vs. VCM at V+ = 3.3V
VOS vs. VCM at V+ = 5.0V
125°C
85°C
0.3
0.2
0.1
VOS (mV)
VOS (mV)
0.2
125°C
85°C
0.3
25°C
0
-0.1
-40°C
-0.2
0.1
25°C
0
-0.1
-40°C
-0.2
-0.3
-0.3
+
+
V = 5.0V
V = 3.3V
-0.5 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-0.5
0.5
1.5
2.5
3.5
4.5
VCM (V)
VCM (V)
Figure 5.
Figure 6.
VOS vs. Supply Voltage
VOS vs. Temperature
5.5
125°C
85°C
0.3
0.1
VOS (µV)
VOS (mV)
0.2
25°C
0
-0.1
-40°C
-0.2
3.3V
200
150
100
50
0
-50
-100
-150
-200
5.0V
-0.3
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
VSUPPLY (V)
Figure 7.
Figure 8.
VOS vs. VOUT
Input Bias Current vs. VCM at 25°C
5
TA = 25°C
+
V = 5.0V, RL = 2k
4
6
3
2
2
IB (pA)
VOS (µV)
4
0
5V
1
0
-2
-1
-4
-2
3.3V
-3
-6
-4
0
1
2
3
VOUT (V)
4
5
-5
-1
0
1
2
3
4
5
6
VCM (V)
Figure 9.
Figure 10.
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Typical Performance Characteristics (continued)
At TA = 25°C, RL = 10 kΩ, V = 3.3V, V− = 0V, Unless otherwise specified.
+
Input Bias Current vs. VCM at 85°C
50
TA = 85°C
40
30
300
20
200
10
5.0V
0
-10
3.3V
-20
0
-300
-40
-400
0
1
5.0V
-100
-200
2
3
4
5
3.3V
-500
-1
6
0
1
2
3
4
5
6
VCM (V)
VCM (V)
Figure 11.
Figure 12.
Supply Current vs. Supply Voltage Single LMV831
Supply Current vs. Supply Voltage Dual LMV832
0.4
0.7
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
100
-30
-50
-1
TA = 125°C
400
IBIAS (pA)
IBIAS (pA)
Input Bias Current vs. VCM at 125°C
500
85°C
125°C
0.3
0.2
25°C
-40°C
125°C
0.6
85°C
0.5
0.4
25°C
0.3
0.1
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-40°C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 13.
Figure 14.
Supply Current vs. Supply Voltage Quad LMV834
Supply Current vs. Temperature Single LMV831
0.4
125°C
85°C
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
1.4
1.2
1.0
0.8
25°C
0.6
-40°C
0.3
5.0V
0.2
3.3V
0.4
0.1
2.5
8
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-50
-25
0
25
50
75
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 15.
Figure 16.
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100
125
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Typical Performance Characteristics (continued)
At TA = 25°C, RL = 10 kΩ, V = 3.3V, V− = 0V, Unless otherwise specified.
+
Supply Current vs. Temperature Dual LMV832
Supply Current vs. Temperature Quad LMV834
1.4
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
0.7
0.6
5.0V
0.5
0.4
3.3V
-50
-25
1.0
3.3V
0.8
0.6
0
25
50
75
100
125
-25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 17.
Figure 18.
Sinking Current vs. Supply Voltage
Sourcing Current vs. Supply Voltage
100
90
80
70
60
50
40
30
20
10
ISOURCE (mA)
25°C
-40°C
125°C
85°C
2.5
-50
TEMPERATURE (°C)
3.0
3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
100
90
80
70
60
50
40
30
20
10
6.0
25°C
-40°C
125°C
85°C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
Figure 19.
Figure 20.
Output Swing High vs. Supply Voltage RL = 2 kΩ
Output Swing High vs. Supply Voltage RL = 10 kΩ
60
RL = 10k
RL = 2k
VOUT FROM RAIL HIGH (mV)
ISINK (mA)
5.0V
0.4
0.3
VOUT FROM RAIL HIGH (mV)
1.2
125°C
50
85°C
40
30
20
25°C
10
12
10
125°C
85°C
8
6
4
2
25°C
0
-40°C
-40°C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 21.
Figure 22.
5.5
6.0
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Typical Performance Characteristics (continued)
At TA = 25°C, RL = 10 kΩ, V = 3.3V, V− = 0V, Unless otherwise specified.
+
Output Swing Low vs. Supply Voltage RL = 2 kΩ
RL = 2k
RL = 10k
125°C
VOUT FROM RAIL LOW (mV)
VOUT FROM RAIL LOW (mV)
60
Output Swing Low vs. Supply Voltage RL = 10 kΩ
50
85°C
40
30
25°C
20
10
12
125°C
85°C
10
8
6
4
25°C
2
-40°C
0
-40°C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.5
4.5
5.0
5.5
6.0
Figure 24.
Output Voltage Swing vs. Load Current at V+ = 3.3V
Output Voltage Swing vs. Load Current at V+ = 5.0V
SINK
125°C
2.0
1.6
1.2
0.8
0.4
0
-0.4
-0.8
-1.2
-1.6
-2.0
VOUT FROM RAIL (V)
+
-40°C
V = 3.3V
2.0
1.6
1.2
0.8
0.4
0
-0.4
-0.8
-1.2
-1.6
-2.0
125°C
125°C
SOURCE
SOURCE
SOURCE
0
5
10
15
20
25
30
35
40
0
40
50
Figure 26.
-40°C
GAIN
30
25°C
85°C
125°C
10
50
60
40
70
80
100
PHASE
20 pF 5 pF
80
100 pF
50 pF
GAIN
60
30
40
20
20
20
0
10
-40°C
-20
10M
1M
60
80
40
20
60
Open Loop Frequency Response vs. Load Conditions
100
GAIN (dB)
25°C, 85°C, 125°C
CL = 5 pF
0
10k
100k
30
Figure 25.
50
40
20
ILOAD (mA)
PHASE (°)
PHASE
10
ILOAD (mA)
Open Loop Frequency Response vs. Temperature
60
+
V = 5.0V
-40°C
CL = 5 pF
20 pF
50 pF
100 pF
0
10k
5 pF
100 pF
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 27.
Figure 28.
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PHASE (°)
VOUT FROM RAIL (V)
4.0
Figure 23.
125°C
GAIN (dB)
3.5
SUPPLY VOLTAGE (V)
SINK
10
3.0
SUPPLY VOLTAGE (V)
0
-20
10M
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Typical Performance Characteristics (continued)
At TA = 25°C, RL = 10 kΩ, V = 3.3V, V− = 0V, Unless otherwise specified.
+
Phase Margin vs. Capacitive Load
PSRR vs. Frequency
120
100
70
60
PSRR (dB)
PHASE(°)
3.3V
80
50
5.0V
40
30
20
5.0V
-PSRR
60
3.3V
5.0V
40
10
3.3V
0
20
1
10
100
+PSRR
0
100
1000
1k
10k
CLOAD (pF)
100k
1M
10M
FREQUENCY (Hz)
Figure 29.
Figure 30.
CMRR vs. Frequency
Channel Separation vs. Frequency
100
160
CMRR (dB)
80
DC
CMRR
60
40
V+ = 3.3V, 5.0V
20
100
1k
10k
100k
1M
CHANNEL SEPARATION (dB)
AC CMRR
140
120
100
80
60
1k
10M
V+ = 3.3V, 5.0V
10k
100k
1M
10M
Figure 32.
Large Signal Step Response with Gain = 1
Large Signal Step Response with Gain = 10
200 mV/DIV
FREQUENCY (Hz)
Figure 31.
100 mV/DIV
FREQUENCY (Hz)
f = 100 kHz
AV = +10
VIN = 100 mVPP
f = 100 kHz
AV = +1
VIN = 500 mVPP
1 µs/DIV
1 us/DIV
Figure 33.
Figure 34.
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Typical Performance Characteristics (continued)
At TA = 25°C, RL = 10 kΩ, V = 3.3V, V− = 0V, Unless otherwise specified.
+
20 mV/DIV
Small Signal Step Response with Gain = 10
20 mV/DIV
Small Signal Step Response with Gain = 1
f = 100 kHz
f = 100 kHz
AV = +1
VIN = 100 mVPP
AV = +10
VIN = 10 mVPP
1 µs/DIV
1 µs/DIV
Figure 35.
Figure 36.
Slew Rate vs. Supply Voltage
Input Voltage Noise vs. Frequency
100
FALLING EDGE
1.9
NOISE (nV/ Hz)
SLEW RATE (V/µs)
2.0
1.8
1.7
RISING EDGE
10
1.6
1.5 AV = +1
CL = 5 pF
2.5
3.0
+
1 V = 3.3V, 5.0V
3.5
4.0
4.5
5.0
5.5
6.0
10
100
1k
10k
SUPPLY VOLTAGE (V)
Figure 37.
Figure 38.
THD+N vs. Frequency
THD+N vs. Amplitude
AV = 10x
0.1 BW = >500 kHz
100k
FREQUENCY (Hz)
V+ = 5.0V
10
AV = 10x
+
V+ = 3.3V
0.01
1
VIN = 300 mVPP
THD + N (%)
THD + N (%)
V = 3.3V
VIN = 480 mVPP
0.001
VIN = 2.3 VPP
AV = 1x
0.1
0.01
AV = 1x
VIN = 3.8 VPP
+
V = 5.0V
0.001 f = 1 kHz
BW = >500 kHz
0.0001
10
100
1k
FREQUENCY (Hz)
10k
1m
Figure 39.
12
10m
100m
VOUT (VPP)
1
10
Figure 40.
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Typical Performance Characteristics (continued)
At TA = 25°C, RL = 10 kΩ, V = 3.3V, V− = 0V, Unless otherwise specified.
+
ROUT vs. Frequency
1k
EMIRR IN+ vs. Power at 400 MHz
AV = 100x
EMIRRV_PEAK (dB)
ROUT (:)
100
10
1
AV = 10x
0.1
140
130
120
110
100
90
80
70
60
50
40
30
20
125°C
85°C
25°C
-40°C
AV = 1x
0.01
fRF = 400 MHz
100
1k
10k
100k
1M
10M
-40
-10
0
10
Figure 42.
EMIRR IN+ vs. Power at 900 MHz
EMIRR IN+ vs. Power at 1800 MHz
140
130
120
110
100
90
80
70
60
50
40
30
20
125°C
85°C
EMIRRV_PEAK (dB)
EMIRRV_PEAK (dB)
-20
Figure 41.
125°C
25°C
-40°C
-30
85°C
140
130
120
110
100
90
80
70
60
50
40
30
20
25°C
-40°C
fRF = 1800 MHz
fRF = 900 MHz
-40
-30
RF INPUT PEAK VOLTAGE (dBVp)
FREQUENCY (Hz)
-20
-10
0
10
-40
-30
-20
-10
0
RF INPUT PEAK VOLTAGE (dBVp)
RF INPUT PEAK VOLTAGE (dBVp)
Figure 43.
Figure 44.
EMIRR IN+ vs. Power at 2400 MHz
EMIRR IN+ vs. Frequency
10
140
130
120
110
100
90
80
70
60
50
40
30
20
EMIRR V_PEAK (dB)
EMIRRV_PEAK (dB)
125°C
85°C
25°C
-40°C
125°C
140
130
120
110
100
90
80
70
60
50
40
30
20
85°C
25°C
-40°C
-40
-30
-20
+
V = 3.3V, 5.0V
VPEAK = -20 dBVp
fRF = 2400 MHz
-10
0
10
10
RF INPUT PEAK VOLTAGE (dBVp)
Figure 45.
100
1000
FREQUENCY (MHz)
10000
Figure 46.
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APPLICATION INFORMATION
INTRODUCTION
The LMV831, LMV832 and LMV834 are operational amplifiers with excellent specifications, such as low offset,
low noise and a rail-to-rail output. These specifications make the LMV831, LMV832 and LMV834 great choices
for medical and instrumentation applications such as diagnosis equipment. The low supply current is perfectly
suited for battery powered equipment. The small packages, SC70 package for the LMV831, the TSSOP package
for the dual LMV832 and the TSSOP package for the quad LMV834, make these parts a perfect choice for
portable electronics. Additionally, the EMI hardening makes the LMV831, LMV832 or LMV834 a must for almost
all op amp applications. Most applications are exposed to Radio Frequency (RF) signals such as the signals
transmitted by mobile phones or wireless computer peripherals. The LMV831, LMV832 and LMV834 will
effectively reduce disturbances caused by RF signals to a level that will be hardly noticeable. This again reduces
the need for additional filtering and shielding. Using this EMI resistant series of op amps will thus reduce the
number of components and space needed for applications that are affected by EMI, and will help applications,
not yet identified as possible EMI sensitive, to be more robust for EMI.
INPUT CHARACTERISTICS
The input common mode voltage range of the LMV831, LMV832 and LMV834 includes ground, and can even
sense well below ground. The CMRR level does not degrade for input levels up to 1.2V below the supply voltage.
For a supply voltage of 5V, the maximum voltage that should be applied to the input for best CMRR performance
is thus 3.8V.
When not configured as unity gain, this input limitation will usually not degrade the effective signal range. The
output is rail-to-rail and therefore will introduce no limitations to the signal range.
The typical offset is only 0.25 mV, and the TCVOS is 0.5 μV/°C, specifications close to precision op amps.
CMRR MEASUREMENT
The CMRR measurement results may need some clarification. This is because different setups are used to
measure the AC CMRR and the DC CMRR.
The DC CMRR is derived from ΔVOS versus ΔVCM. This value is stated in the tables, and is tested during
production testing. The AC CMRR is measured with the test circuit shown in Figure 47.
R2
1 k:
V+
R1
1 k:
-
VIN
LMV83x
+
R11
1 k:
R12 V995:
V+ BUFFER
Buffer
+
VOUT
V- BUFFER
P1
10:
Figure 47. AC CMRR Measurement Setup
The configuration is largely the usually applied balanced configuration. With potentiometer P1, the balance can
be tuned to compensate for the DC offset in the DUT. The main difference is the addition of the buffer. This
buffer prevents the open-loop output impedance of the DUT from affecting the balance of the feedback network.
Now the closed-loop output impedance of the buffer is a part of the balance. As the closed-loop output
impedance is much lower, and by careful selection of the buffer also has a larger bandwidth, the total effect is
that the CMRR of the DUT can be measured much more accurately. The differences are apparent in the larger
measured bandwidth of the AC CMRR.
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One artifact from this test circuit is that the low frequency CMRR results appear higher than expected. This is
because in the AC CMRR test circuit the potentiometer is used to compensate for the DC mismatches. So,
mainly AC mismatch is all that remains. Therefore, the obtained DC CMRR from this AC CMRR test circuit tends
to be higher than the actual DC CMRR based on DC measurements.
The CMRR curve in Figure 48 shows a combination of the AC CMRR and the DC CMRR.
100
AC CMRR
CMRR (dB)
80
DC
CMRR
60
40
V+ = 3.3V, 5.0V
20
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 48. CMRR Curve
OUTPUT CHARACTERISTICS
As already mentioned the output is rail-to-rail. When loading the output with a 10 kΩ resistor the maximum swing
of the output is typically 6 mV from the positive and negative rail.
The output of the LMV831/LMV832/LMV834 can drive currents up to 30 mA at 3.3V and even up to 65 mA at 5V
The LMV831/LMV832/LMV834 can be connected as non-inverting unity-gain amplifiers. This configuration is the
most sensitive to capacitive loading. The combination of a capacitive load placed at the output of an amplifier
along with the amplifier’s output impedance creates a phase lag, which reduces the phase margin of the
amplifier. If the phase margin is significantly reduced, the response will be under damped which causes peaking
in the transfer and, when there is too much peaking, the op amp might start oscillating. The
LMV831/LMV832/LMV834 can directly drive capacitive loads up to 200 pF without any stability issues. In order to
drive heavier capacitive loads, an isolation resistor, RISO, should be used, as shown in Figure 49. By using this
isolation resistor, the capacitive load is isolated from the amplifier’s output, and hence, the pole caused by CL is
no longer in the feedback loop. The larger the value of RISO, the more stable the amplifier will be. If the value of
RISO is sufficiently large, the feedback loop will be stable, independent of the value of CL. However, larger values
of RISO result in reduced output swing and reduced output current drive.
VIN
RISO
VOUT
+
CL
Figure 49. Isolating Capacitive Load
A resistor value of around 150Ω would be sufficient. As an example some values are given in the following table,
for 5V.
CLOAD
RISO
300 pF
165Ω
400 pF
175Ω
500 pF
185Ω
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EMIRR
With the increase of RF transmitting devices in the world, the electromagnetic interference (EMI) between those
devices and other equipment becomes a bigger challenge. The LMV831, LMV832 and LMV834 are EMI
hardened op amps which are specifically designed to overcome electromagnetic interference. Along with EMI
hardened op amps, the EMIRR parameter is introduced to unambiguously specify the EMI performance of an op
amp. This section presents an overview of EMIRR. A detailed description on this specification for EMI hardened
op amps can be found in Application Note AN-1698.
The dimensions of an op amp IC are relatively small compared to the wavelength of the disturbing RF signals. As
a result the op amp itself will hardly receive any disturbances. The RF signals interfering with the op amp are
dominantly received by the PCB and wiring connected to the op amp. As a result the RF signals on the pins of
the op amp can be represented by voltages and currents. This representation significantly simplifies the
unambiguous measurement and specification of the EMI performance of an op amp.
RF signals interfere with op amps via the non-linearity of the op amp circuitry. This non-linearity results in the
detection of the so called out-of-band signals. The obtained effect is that the amplitude modulation of the out-ofband signal is downconverted into the base band. This base band can easily overlap with the band of the op
amp circuit. As an example Figure 50 depicts a typical output signal of a unity-gain connected op amp in the
presence of an interfering RF signal. Clearly the output voltage varies in the rhythm of the on-off keying of the RF
carrier.
RF
RF SIGNAL
VOUT OPAMP
(AV = 1)
NO RF
VOS + VDETECTED
VOS
Figure 50. Offset voltage variation due to an interfering RF signal
EMIRR DEFINITION
To identify EMI hardened op amps, a parameter is needed that quantitatively describes the EMI performance of
op amps. A quantitative measure enables the comparison and the ranking of op amps on their EMI robustness.
Therefore the EMI Rejection Ratio (EMIRR) is introduced. This parameter describes the resulting input-referred
offset voltage shift of an op amp as a result of an applied RF carrier (interference) with a certain frequency and
level. The definition of EMIRR is given by:
§ VRF_PEAK·
¸
EMIRRV RF_PEAK = 20 log ¨
¨ 'VOS ¸
©
¹
In which
•
•
VRF_PEAK is the amplitude of the applied un-modulated RF signal (V)
ΔVOS is the resulting input-referred offset voltage shift (V)
(1)
The offset voltage depends quadratically on the applied RF level, and therefore, the RF level at which the EMIRR
is determined should be specified. The standard level for the RF signal is 100 mVP. Application Note AN-1698
addresses the conversion of an EMIRR measured for an other signal level than 100 mVP. The interpretation of
the EMIRR parameter is straightforward. When two op amps have an EMIRR which differ by 20 dB, the resulting
error signals when used in identical configurations, differ by 20 dB as well. So, the higher the EMIRR, the more
robust the op amp.
Coupling an RF Signal to the IN+ Pin
Each of the op amp pins can be tested separately on EMIRR. In this section the measurements on the IN+ pin
(which, based on symmetry considerations, also apply to the IN- pin) are discussed. In Application Note AN-1698
the other pins of the op amp are treated as well. For testing the IN+ pin the op amp is connected in the unity gain
configuration. Applying the RF signal is straightforward as it can be connected directly to the IN+ pin. As a result
the RF signal path has a minimum of components that might affect the RF signal level at the pin. The circuit
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diagram is shown in Figure 51. The PCB trace from RFIN to the IN+ pin should be a 50Ω stripline in order to
match the RF impedance of the cabling and the RF generator. On the PCB a 50Ω termination is used. This 50Ω
resistor is also used to set the bias level of the IN+ pin to ground level. For determining the EMIRR, two
measurements are needed: one is measuring the DC output level when the RF signal is off; and the other is
measuring the DC output level when the RF signal is switched on. The difference of the two DC levels is the
output voltage shift as a result of the RF signal. As the op amp is in the unity gain configuration, the input
referred offset voltage shift corresponds one-to-one to the measured output voltage shift.
C2
10 µF
+
VDD
C3
100 pF
RFin
+
R1
50:
Out
C4
100 pF
C1
22 pF
+
VSS
C5
10 µF
Figure 51. Circuit for coupling the RF signal to IN+
Cell Phone Call
The effect of electromagnetic interference is demonstrated in a setup where a cell phone interferes with a
pressure sensor application. The application is shown in Figure 53.
This application needs two op amps and therefore a dual op amp is used. The op amp configured as a buffer
and connected at the negative output of the pressure sensor prevents the loading of the bridge by resistor R2.
The buffer also prevents the resistors of the sensor from affecting the gain of the following gain stage. The op
amps are placed in a single supply configuration.
The experiment is performed on two different dual op amps: a typical standard op amp and the LMV832, EMI
hardened dual op amp. A cell phone is placed on a fixed position a couple of centimeters from the op amps in
the sensor circuit.
VOUT (0.5V/DIV)
When the cell phone is called, the PCB and wiring connected to the op amps receive the RF signal.
Subsequently, the op amps detect the RF voltages and currents that end up at their pins. The resulting effect on
the output of the second op amp is shown in Figure 52.
Typical Opamp
LMV832
TIME (0.5s/DIV)
Figure 52. Comparing EMI Robustness
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The difference between the two types of dual op amps is clearly visible. The typical standard dual op amp has an
output shift (disturbed signal) larger than 1V as a result of the RF signal transmitted by the cell phone. The
LMV832, EMI hardened op amp does not show any significant disturbances. This means that the RF signal will
not disturb the signal entering the ADC when using the LMV832.
R1
2.4 k:
VDD
PRESSURE
SENSOR
+
-
LMV832
+
VDD
R2
100 :
ADC
LMV832
+
VOUT
Figure 53. Pressure Sensor Application
DECOUPLING AND LAYOUT
Care must be given when creating a board layout for the op amp. For decoupling the supply lines it is suggested
that 10 nF capacitors be placed as close as possible to the op amp. For single supply, place a capacitor between
V+ and V−. For dual supplies, place one capacitor between V+ and the board ground, and a second capacitor
between ground and V−. Even with the LMV831/LMV832/LMV834 inherent hardening against EMI, it is still
recommended to keep the input traces short and as far as possible from RF sources. Then the RF signals
entering the chip are as low as possible, and the remaining EMI can be, almost, completely eliminated in the chip
by the EMI reducing features of the LMV831/LMV832/LMV834.
PRESSURE SENSOR APPLICATION
The LMV831/LMV832/LMV834 can be used for pressure sensor applications. Because of their low power the
LMV831/LMV832/LMV834 are ideal for portable applications, such as blood pressure measurement devices, or
portable barometers. This example describes a universal pressure sensor that can be used as a starting point for
different types of sensors and applications.
Pressure Sensor Characteristics
The pressure sensor used in this example functions as a Wheatstone bridge. The value of the resistors in the
bridge change when pressure is applied to the sensor. This change of the resistor values will result in a
differential output voltage, depending on the sensitivity of the sensor and the applied pressure. The difference
between the output at full scale pressure and the output at zero pressure is defined as the span of the pressure
sensor. A typical value for the span is 100 mV. A typical value for the resistors in the bridge is 5 kΩ. Loading of
the resistor bridge could result in incorrect output voltages of the sensor. Therefore the selection of the circuit
configuration, which connects to the sensor, should take into account a minimum loading of the sensor.
Pressure Sensor Example
The configuration shown in Figure 53 is simple, and is very useful for the read out of pressure sensors. With two
op amps in this application, the dual LMV832 fits very well. The op amp configured as a buffer and connected at
the negative output of the pressure sensor prevents the loading of the bridge by resistor R2. The buffer also
prevents the resistors of the sensor from affecting the gain of the following gain stage. Given the differential
output voltage VS of the pressure sensor, the output signal of this op amp configuration, VOUT, equals:
VOUT =
VDD
2
-
VS §
R1·
¨1+ 2× ¸¸
2 ¨©
R2¹
(2)
To align the pressure range with the full range of an ADC, the power supply voltage and the span of the pressure
sensor are needed. For this example a power supply of 5V is used and the span of the sensor is 100 mV. When
a 100Ω resistor is used for R2, and a 2.4 kΩ resistor is used for R1, the maximum voltage at the output is 4.95V
and the minimum voltage is 0.05V. This signal is covering almost the full input range of the ADC. Further
processing can take place in the microprocessor following the ADC.
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PACKAGE OPTION ADDENDUM
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24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMV831MG/NOPB
ACTIVE
SC70
DCK
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AFA
LMV831MGE/NOPB
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AFA
LMV831MGX/NOPB
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AFA
LMV832MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AU5A
LMV832MME/NOPB
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AU5A
LMV832MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AU5A
LMV834MT/NOPB
ACTIVE
TSSOP
PW
14
94
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV834
MT
LMV834MTX/NOPB
ACTIVE
TSSOP
PW
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV834
MT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
24-Jan-2013
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
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