ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 Data Sheet Improved Industry Standard Single-Ended Current Mode PWM Controller The ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 family of adjustable frequency, low power, pulse width modulating (PWM) current mode controllers is designed for a wide range of power conversion applications including boost, flyback, and isolated output configurations. Peak current mode control effectively handles power transients and provides inherent overcurrent protection. This advanced BiCMOS design is pin compatible with the industry standard 384x family of controllers and offers significantly improved performance. Features include low operating current, 60µA start-up current, adjustable operating frequency to 2MHz, and high peak current drive capability with 20ns rise and fall times. PART NUMBER RISING UVLO (V) MAX. DUTY CYCLE (%) ISL6840 7.0 100 ISL6841 7.0 50 ISL6842 14.4 100 ISL6843 8.4 100 ISL6844 14.4 50 ISL6845 8.4 50 February 23, 2012 FN9124.11 Features • 1A MOSFET Gate Driver • 60µA Start-up Current, 100µA Maximum • 25ns Propagation Delay Current Sense to Output • Fast Transient Response with Peak Current Mode Control • Adjustable Switching Frequency to 2MHz • 20ns Rise and Fall Times with 1nF Output Load • Trimmed Timing Capacitor Discharge Current for Accurate Deadtime/Maximum Duty Cycle Control • High Bandwidth Error Amplifier • Tight Tolerance Voltage Reference Over Line, Load, and Temperature • Tight Tolerance Current Limit Threshold • Pb-Free Available (RoHS Compliant) Applications • Telecom and Datacom Power • Wireless Base Station Power • File Server Power • Industrial Power Systems • PC Power Supplies Pinouts ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 (8 LD SOIC, MSOP) TOP VIEW COMP 1 • Isolated Buck and Flyback Regulators • Boost Regulators 8 VREF FB 2 7 VDD CS 3 6 OUT RTCT 4 5 GND ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 (8 LD DFN) TOP VIEW COMP 1 8 VREF FB 2 7 VDD CS 3 6 OUT RTCT 4 5 GND 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2004, 2005, 2007, 2008, 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 Ordering Information PART NUMBER (Note 4) PART MARKING TEMP RANGE (°C) PACKAGE PKG. DWG. # ISL6840IBZ (Notes 1, 3) 6840 IBZ -40 to +105 8 Ld SOIC (Pb-free) M8.15 ISL6840IRZ-T (Notes 2, 3) 40Z -40 to +105 8 Ld 2x3 DFN (Pb-free) L8.2x3 ISL6840IUZ (Notes 1, 3) 6840Z -40 to +105 8 Ld MSOP (Pb-free) M8.118 ISL6841IB-T ISL 6841IB -40 to +105 8 Ld SOIC M8.15 ISL6841IBZ (Notes 1, 3) 6841 IBZ -40 to +105 8 Ld SOIC (Pb-free) M8.15 ISL6841IRZ-T (Notes 2, 3) 41Z -40 to +105 8 Ld 2x3 DFN (Pb-free) L8.2x3 ISL6841IUZ (Notes 1, 3) 6841Z -40 to +105 8 Ld MSOP (Pb-free) M8.118 ISL6842IBZ (Notes 1, 3) 6842 IBZ -40 to +105 8 Ld SOIC (Pb-free) M8.15 ISL6842IRZ-T (Notes 2, 3) 42Z -40 to +105 8 Ld 2x3 DFN (Pb-free) L8.2x3 ISL6842IUZ (Notes 1, 3) 6842Z -40 to +105 8 Ld MSOP (Pb-free) M8.118 ISL6843CBZ (Notes 1, 3) 6843 CBZ 0 to +70 8 Ld SOIC (Pb-free) M8.15 ISL6843IBZ (Notes 1, 3) 6843 IBZ -40 to +105 8 Ld SOIC (Pb-free) M8.15 ISL6843IRZ-T (Notes 2, 3) 43Z -40 to +105 8 Ld 2x3 DFN (Pb-free) L8.2x3 ISL6843IU-T 6843 -40 to +105 8 Ld MSOP M8.118 ISL6843IUZ (Notes 1, 3) 6843Z -40 to +105 8 Ld MSOP (Pb-free) M8.118 ISL6844IBZ (Notes 1, 3) 6844 IBZ -40 to +105 8 Ld SOIC (Pb-free) M8.15 ISL6844IRZ-T (Notes 2, 3) 44Z -40 to +105 8 Ld 2x3 DFN (Pb-free) L8.2x3 ISL6844IUZ (Notes 1, 3) 6844Z -40 to +105 8 Ld MSOP (Pb-free) M8.118 ISL6845IBZ (Notes 1, 3) 6845 IBZ -40 to +105 8 Ld SOIC (Pb-free) M8.15 ISL6845IRZ-T (Notes 2, 3) 45Z -40 to +105 8 Ld 2x3 DFN (Pb-free) L8.2x3 ISL6845IUZ (Notes 1, 3) 6845Z -40 to +105 8 Ld MSOP (Pb-free) M8.118 ISL6841EVAL3Z Evaluation Board ISL6844EVAL1Z Evaluation Board ISL6844EVAL2Z Evaluation Board ISL6844EVAL3Z Evaluation Board NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. Contact Factory for Availability. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. For Moisture Sensitivity Level (MSL), please see device information page for ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845.For more information on MSL please see tech brief TB363. 2 FN9124.11 February 23, 2012 Functional Block Diagram VREF 5.00V VDD VREF UVLO COMPARATOR ENABLE VDD OK + - VREF FAULT - A 2.5V + - 3 VREF UV COMPARATOR 4.65V 4.80V GND BG A = 0.5 PWM COMPARATOR + - CS 100mV ERROR AMPLIFIER 2R 1.1V CLAMP + - FB + - ISL6841/ISL6844/ISL6845 ONLY Q R T Q COMP OUT VREF S Q R Q 2.6V 0.7V RESET DOMINANT ON OSCILLATOR COMPARATOR + RTCT 8.4mA FN9124.11 February 23, 2012 ON CLOCK P/N -40, -41 -42, -44 -43, -45 UVLO ON/OFF 7.0/6.6V 14.3/8.8V 8.4/7.2V ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 + BG +- Typical Application - 48V Input Dual Output Flyback CR5 +3.3V C21 T1 + C15 + C16 R21 VIN+ +1.8V C4 R3 CR4 C17 CR2 C5 + C20 C19 RETURN CR6 R1 36V TO 75V C1 R17 R16 C6 C3 R18 R19 U2 Q1 C14 R4 R22 C13 R15 U3 VIN- R27 R20 U4 R26 COMP VREF CS V DD FB OUT RTCT GND ISL684x R6 R10 CR1 Q3 C12 VR1 C8 R13 C11 ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 4 C2 C22 + FN9124.11 February 23, 2012 Typical Application - Boost Converter R8 C10 CR1 L1 VIN+ +VOUT + C3 5 R4 Q1 RETURN R5 C9 C1 R1 R2 U1 COMP ISL684x FB CS C4 RTCT R7 VREF C8 VIN+ VDD OUT GND R3 C5 C7 VIN- C6 R6 ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 C2 FN9124.11 February 23, 2012 ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD + 0.3V Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A Thermal Resistance (Typical) Operating Conditions Temperature Range ISL684xIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C ISL684xCx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Supply Voltage Range (Typical, Note 8) ISL6840, ISL6841. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5V to 14V ISL6843, ISL6845. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 16V ISL6842, ISL6844. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V to 18V θJA (°C/W) θJC (°C/W) DFN Package (Notes 5, 6) . . . . . . . . . . 77 6 SOIC Package (Note 5) . . . . . . . . . . . . 100 N/A MSOP Package (Notes 5, 7) . . . . . . . . 165 62 Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 7. For θJC, the “case temp” location is taken at the package top center. 8. All voltages are with respect to GND. Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” and “Typical Application” schematic on pages 3 and 4. VDD = 15V (Note 12), Rt = 10kΩ, Ct = 3.3nF, TA = -40°C to +105°C (Industrial) or TA = 0°C to +70°C (Commercial), Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C or 0°C to +70°C. Electrical Specifications MIN (Note 9) TYP MAX (Note 9) UNITS START Threshold (ISL6840, ISL6841) 6.5 7.0 7.5 V START Threshold (ISL6843, ISL6845) 7.8 8.4 9.0 V START Threshold (ISL6842, ISL6844) 13.3 14.3 15.3 V STOP Threshold (ISL6840, ISL6841) 6.1 6.6 6.9 V STOP Threshold (ISL6843, ISL6845) 6.7 7.2 7.7 V STOP Threshold (ISL6843C Only) 6.6 7.2 7.8 V STOP Threshold (ISL6842, ISL6844) 8.0 8.8 9.6 V Hysteresis (ISL6840, ISL6841) - 0.4 - V Hysteresis (ISL6843, ISL6845) - 0.8 - V Hysteresis (ISL6842, ISL6844) - 5.4 - V PARAMETER TEST CONDITIONS UNDERVOLTAGE LOCKOUT Start-up Current, IDD VDD < START Threshold - 60 100 µA Operating Current, IDD (Note 10) - 3.3 4.0 mA Operating Supply Current, ID Includes 1nF GATE loading - 4.1 5.5 mA 4.925 5.000 5.050 V 4.82 5.000 5.18 V - 5 - mV Fault Voltage 4.40 4.65 4.85 V VREF Good Voltage 4.60 4.80 VREF - 0.05 V 50 165 250 mV REFERENCE VOLTAGE Overall Accuracy Over line (VDD = 12V to 18V), load, temperature Overall Accuracy (ISL6843C Only) Long Term Stability TA = +125°C, 1000 hours (Note 11) Hysteresis 6 FN9124.11 February 23, 2012 ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” and “Typical Application” schematic on pages 3 and 4. VDD = 15V (Note 12), Rt = 10kΩ, Ct = 3.3nF, TA = -40°C to +105°C (Industrial) or TA = 0°C to +70°C (Commercial), Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C or 0°C to +70°C. (Continued) Electrical Specifications PARAMETER TEST CONDITIONS Current Limit, Sourcing Current Limit, Sinking MIN (Note 9) TYP MAX (Note 9) UNITS -20 - - mA 5 - - mA -1.0 - 1.0 µA CURRENT SENSE Input Bias Current VCS = 1V CS Offset Voltage VCS = 0V (Note 11) 95 100 105 mV COMP to PWM Comparator Offset Voltage VCS = 0V (Note 11) 0.80 1.15 1.30 V Input Signal, Maximum 0.91 0.97 1.03 V Input Signal, Maximum (ISL6843C Only) 0.9 0.97 1.07 V 2.5 3.0 3.5 V/V - 25 40 ns 70 ns - dB Gain, ACS = ΔVCOMP/ΔVCS 0 < VCS < 910mV, VFB = 0V (Note 11) CS to OUT Delay (Note 11) CS to OUT Delay (ISL6843C Only) (Note 11) ERROR AMPLIFIER Open Loop Voltage Gain (Note 11) 60 90 Open Loop Voltage Gain (ISL6843C Only) (Note 11) 55 Unity Gain Bandwidth (Note 11) 3.5 5 - MHz Reference Voltage VFB = VCOMP 2.475 2.514 2.55 V FB Input Bias Current VFB = 0V -1.0 -0.2 1.0 µA COMP Sink Current VCOMP = 1.5V, VFB = 2.7V 1.0 - - mA COMP Source Current VCOMP = 1.5V, VFB = 2.3V -0.4 - - mA COMP VOH VFB = 2.3V 4.80 - VREF V COMP VOL VFB = 2.7V 0.4 - 1.0 V PSRR Frequency = 120Hz, VDD = 12V to 18V (Note 11) 60 80 - dB Frequency Accuracy Initial, TJ = +25°C 49 52 55 kHz Frequency Variation with VDD T = +25°C (f18V - f12V)/f12V - 0.2 1.0 % Temperature Stability (Note 11) - - 5 % Amplitude, Peak-to-Peak - 1.9 - V RTCT Discharge Voltage - 0.7 - V 7.2 8.4 9.5 mA dB OSCILLATOR Discharge Current RTCT = 2.0V OUTPUT Gate VOH VDD to OUT, IOUT = -200mA - 1.0 2.0 V Gate VOL OUT to GND, IOUT = 200mA - 1.0 2.0 V Peak Output Current COUT = 1nF (Note 11) - 1.0 - A Rise Time COUT = 1nF (Note 11) - 20 40 ns Fall Time COUT = 1nF (Note 11) - 20 40 ns PWM 7 FN9124.11 February 23, 2012 ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” and “Typical Application” schematic on pages 3 and 4. VDD = 15V (Note 12), Rt = 10kΩ, Ct = 3.3nF, TA = -40°C to +105°C (Industrial) or TA = 0°C to +70°C (Commercial), Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C or 0°C to +70°C. (Continued) Electrical Specifications MIN (Note 9) TYP MAX (Note 9) UNITS ISL6840, ISL6842, ISL6843 94 96 - % ISL6841, ISL6844, ISL6845 47 48 - % ISL6840, ISL6842, ISL6843 - - 0 % ISL6841, ISL6844, ISL6845 - - 0 % PARAMETER TEST CONDITIONS Maximum Duty Cycle Minimum Duty Cycle NOTES: 9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 10. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current. 11. Limits established by characterization and are not production tested. 12. Adjust VDD above the start threshold and then lower to 15V. Typical Performance Curves 1.001 1.000 1.01 NORMALIZED VREF NORMALIZED FREQUENCY 1.02 1.00 0.99 0.98 0.97 -40 0.999 0.998 0.997 0.996 -10 20 50 80 0.995 -40 -25 -10 110 5 FIGURE 1. FREQUENCY vs TEMPERATURE 50 65 80 95 110 103 1.000 FREQUENCY (kHz) NORMALIZED EA REFERENCE 35 FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE 1.002 0.998 0.996 0.994 -40 -25 -10 20 TEMPERATURE (°C) TEMPERATURE (°C) 5 20 35 50 65 80 95 TEMPERATURE (°C) FIGURE 3. EA REFERENCE vs TEMPERATURE 8 110 100pF 100 220pF 330pF 470pF 1.0nF 10 2.2nF 3.3nF 4.7nF 1 10 20 30 40 50 60 RT (kΩ) 70 80 90 100 FIGURE 4. RESISTANCE FOR CT CAPACITOR VALUES GIVEN FN9124.11 February 23, 2012 ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 Pin Descriptions Functional Description RTCT - This is the oscillator timing control pin. The operational frequency and maximum duty cycle are set by connecting a resistor, RT, between VREF and this pin and a timing capacitor, CT, from this pin to GND. The oscillator produces a sawtooth waveform with a programmable frequency range up to 2.0MHz. The charge time, tC, the discharge time, tD, the switching frequency, f, and the maximum duty cycle, Dmax, can be calculated from Equations 1, 2, 3 and 4: Features t C ≈ 0.583 • RT • CT (EQ. 1) The ISL684x current mode PWMs make an ideal choice for low-cost flyback and forward topology applications. With its greatly improved performance over industry standard parts, it is the obvious choice for new designs or existing designs which require updating. Oscillator The ISL684x family of controllers have a sawtooth oscillator with a programmable frequency range to 2MHz, which can be programmed with a resistor from VREF and a capacitor to GND on the RTCT pin. (Please refer to Figure 4 for the resistor and capacitance required for a given frequency.) 0.0083 • RT – 4.3 t D ≈ – RT • CT • ln ⎛ ----------------------------------------------⎞ ⎝ 0.0083 • RT – 2.4⎠ (EQ. 2) f = 1 ⁄ (tC + tD) (EQ. 3) Soft-Start Operation (EQ. 4) Soft-start must be implemented externally. One method, illustrated in Figure 5, clamps the voltage on COMP. D = t C •f Figure 4 may be used as a guideline in selecting the capacitor and resistor values required for a given frequency. VREF FB - The output voltage feedback is connected to the inverting input of the error amplifier through this pin. The non-inverting input of the error amplifier is internally tied to a reference voltage. GND COMP ISL684x COMP - COMP is the output of the error amplifier and the input of the PWM comparator. The control loop frequency compensation network is connected between the COMP and FB pins. FIGURE 5. SOFT-START CS - This is the current sense input to the PWM comparator. The range of the input signal is nominally 0V to 1.0V and has an internal offset of 100mV. GND - GND is the power and small signal reference ground for all functions. OUT - This is the drive output to the power switching device. It is a high current output capable of driving the gate of a power MOSFET with peak currents of 1.0A. VDD - VDD is the power connection for the device. The total supply current will depend on the load applied to OUT. Total IDD current is the sum of the operating current and the average output current. Knowing the operating frequency, f, and the MOSFET gate charge, Qg, the average output current can be calculated in Equation 5: I OUT = Qg × f (EQ. 5) To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins as possible. VREF - The 5.00V reference voltage output. +1.0/-1.5% tolerance over line, load and operating temperature. Bypass to GND with a 0.1µF to 3.3µF capacitor to filter this output as needed. 9 Gate Drive The ISL684x family are capable of sourcing and sinking 1A peak current. To limit the peak current through the IC, an optional external resistor may be placed between the totem-pole output of the IC (OUT pin) and the gate of the MOSFET. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET’s input capacitance. Slope Compensation For applications where the maximum duty cycle is less than 50%, slope compensation may be used to improve noise immunity, particularly at lighter loads. The amount of slope compensation required for noise immunity is determined empirically, but is generally about 10% of the full scale current feedback signal. For applications where the duty cycle is greater than 50%, slope compensation is required to prevent instability. The minimum amount of slope compensation required corresponds to 1/2 the inductor downslope. Adding excessive slope compensation, however, results in a control loop that behaves more as a voltage mode controller than as a current mode controller. Slope compensation may be added to the CS signal shown in Figure 7. FN9124.11 February 23, 2012 CS SIGNAL (V) ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 DOWNSLOPE CURRENT SENSE SIGNAL TIME FIGURE 6. CURRENT SENSE DOWNSLOPE RTCT ISL684x VREF CS FIGURE 7. SLOPE COMPENSATION Fault Conditions A Fault condition occurs if VREF falls below 4.65V. When a Fault is detected, OUT is disabled. When VREF exceeds 4.80V, the Fault condition clears, and OUT is enabled. Ground Plane Requirements Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents associated with the output stage. VDD should be bypassed directly to GND with good high frequency capacitors. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN9124.11 February 23, 2012 ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 Package Outline Drawing M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) 5.80 (0.228) AREA 0.50 (0.20) x 45° 0.25 (0.01) 4.00 (0.157) 3.80 (0.150) 1 2 8° 0° 3 0.25 (0.010) 0.19 (0.008) SIDE VIEW “B” TOP VIEW 2.20 (0.087) SEATING PLANE 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 1 8 2 7 0.60 (0.023) 1.27 (0.050) 3 6 4 5 -C- 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW “A 0.25(0.010) 0.10(0.004) 5.20(0.205) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. 11 FN9124.11 February 23, 2012 ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 Package Outline Drawing M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 4, 7/11 5 3.0±0.05 A DETAIL "X" D 8 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.9±0.15 3.0±0.05 5 0.95 REF PIN# 1 ID 1 2 B 0.65 BSC GAUGE PLANE TOP VIEW 0.55 ± 0.15 0.25 3°±3° 0.85±010 H DETAIL "X" C SEATING PLANE 0.25 - 0.36 0.08 M C A-B D 0.10 ± 0.05 0.10 C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN 12 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. FN9124.11 February 23, 2012 ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 Package Outline Drawing L8.2x3 8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 3/10 2.00 A 2X 1.50 PIN 1 INDEX AREA 6X 0.50 B 1 1.80 +0.10/-0.15 3.00 6 PIN #1 INDEX AREA (4X) 0.15 8 8X 0.40 ±0.10 TOP VIEW 1.65 +0.10/-0.15 8X 0.25 +0.07/-0.05 4 0.10 M C A B BOTTOM VIEW SEE DETAIL "X" 0.90 ±0.10 0.10 C (1.65) (1.50) (8X 0.60) C BASE PLANE SEATING PLANE 0.08 C 0.05 MAX SIDE VIEW (2.80)(1.80) 0.20 REF C (6X 0.50) 0.05 MAX (8X 0.25) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be 7. Compies to JEDEC MO-229 VCED-2. either a mold or mark feature. 13 FN9124.11 February 23, 2012