MC74VHC1GT02 Single 2−Input NOR Gate/ CMOS Logic Level Shifter LSTTL−Compatible Inputs MARKING DIAGRAMS 5 5 1 SC−88A/SC70−5/SOT−353 DF SUFFIX CASE 419A VJ M G G 1 5 5 VJ M G G 1 TSOP−5/SOT23−5/SC59−5 DT SUFFIX CASE 483 1 VJ = Device Code M = Date Code* G = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. Features • • • • • • • • • http://onsemi.com M The MC74VHC1GT02 is a single gate 2−input NOR fabricated with silicon gate CMOS technology. The internal circuit is composed of multiple stages, including a buffer output which provides high noise immunity and stable output. The device input is compatible with TTL−type input thresholds and the output has a full 5 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic−level translator from 3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V CMOS Logic while operating at the high−voltage power supply. The MC74VHC1GT02 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHC1GT02 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage − input/output voltage mismatch, battery backup, hot insertion, etc. High Speed: tPD = 4.7 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2 V CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load Power Down Protection Provided on Inputs and Outputs PIN ASSIGNMENT Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 65 Pb−Free Packages are Available IN B 1 IN A 2 GND 5 IN A 3 GND 4 OUT Y 5 VCC VCC FUNCTION TABLE 4 OUT Y Figure 1. Pinout ≥1 © Semiconductor Components Industries, LLC, 2007 Output A B Y L L H H L H L H H L L L ORDERING INFORMATION OUT Y See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. Figure 2. Logic Symbol February, 2007 − Rev. 11 IN B 2 Inputs 3 IN A IN B 1 1 Publication Order Number: MC74VHC1GT02/D MC74VHC1GT02 MAXIMUM RATINGS Symbol Characteristics VCC DC Supply Voltage VIN DC Input Voltage VOUT DC Output Voltage VCC = 0 High or Low State IIK Input Diode Current IOK Output Diode Current IOUT DC Output Current, per Pin ICC DC Supply Current, VCC and GND TSTG TL Lead Temperature, 1 mm from Case for 10 Seconds TJ Junction Temperature Under Bias qJA Thermal Resistance PD Power Dissipation in Still Air at 85_C Moisture Sensitivity FR Flammability Rating VESD Unit −0.5 to +7.0 V −0.5 to +7.0 V −0.5 to 7.0 −0.5 to VCC + 0.5 V VOUT < GND; VOUT > VCC Storage Temperature Range MSL Value −20 mA +20 mA +25 mA +50 mA *65 to )150 _C 260 _C )150 _C SC70−5/SC−88A/SOT−353 (Note 1) SOT23−5/TSOP−5/SC59−5 350 230 _C/W SC70−5/SC−88A/SOT−353 SOT23−5/TSOP−5/SC59−5 150 200 mW Level 1 Oxygen Index: 28 to 34 ESD Withstand Voltage UL 94 V−0 @ 0.125 in u2000 u200 N/A Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) V $500 mA Above VCC and Below GND at 125_C (Note 5) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. ILATCHUP Latchup Performance RECOMMENDED OPERATING CONDITIONS Symbol Characteristics Min Max Unit VCC DC Supply Voltage 3.0 5.5 V VIN DC Input Voltage 0.0 5.5 V 0.0 0.0 5.5 VCC V −55 +125 °C 0 0 100 20 ns/V Operating Temperature Range VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V Time, Hours Time, Years 80 1,032,200 117.8 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 80_C Junction Temperature °C NORMALIZED FAILURE RATE DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES TJ = 110_C Input Rise and Fall Time TJ = 120_C tr , tf TJ = 130_C TA VCC = 0 High or Low State TJ = 90_C DC Output Voltage TJ = 100_C VOUT 1 1 10 100 1000 TIME, YEARS Figure 3. Failure Rate vs. Time Junction Temperature http://onsemi.com 2 MC74VHC1GT02 DC ELECTRICAL CHARACTERISTICS VCC Symbol Parameter Test Conditions Min 1.4 2.0 2.0 VIH Minimum High−Level Input Voltage 3.0 4.5 5.5 VIL Maximum Low−Level Input Voltage 3.0 4.5 5.5 VOH Minimum High−Level Output Voltage VIN = VIH or VIL VOL Maximum Low−Level Output Voltage VIN = VIH or VIL TA ≤ 85°C TA = 25°C (V) Typ Max Min 1.4 2.0 2.0 0.53 0.8 0.8 VIN = VIH or VIL IOH = −50 mA 3.0 4.5 2.9 4.4 VIN = VIH or VIL IOH = −4 mA IOH = −8 mA 3.0 4.5 2.58 3.94 VIN = VIH or VIL IOL = 50 mA 3.0 4.5 VIN = VIH or VIL IOL = 4 mA IOL = 8 mA Max 3.0 4.5 −55 ≤ TA ≤ 125°C Min Max 1.4 2.0 2.0 0.53 0.8 0.8 V 0.53 0.8 0.8 2.9 4.4 2.9 4.4 2.48 3.80 2.34 3.66 Unit V V V 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 0.36 0.36 0.44 0.44 0.52 0.52 V V IIN Maximum Input Leakage Current VIN = 5.5 V or GND 0 to 5.5 ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current VIN = VCC or GND 5.5 1.0 20 40 mA ICCT Quiescent Supply Current Per Input: VIN = 3.4 V Other Input: VCC or GND 5.5 1.35 1.50 1.65 mA IOFF Power Off Output Leakage Current VOUT = 5.5 V 0.0 0.5 5.0 10 mA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ Î ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎ AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns TA ≤ 85°C TA = 25°C Symbol tPLH, tPHL CIN Parameter Maximum Propagation Delay, Input A or B to Y Min Typ Max VCC = 3.3 ± 0.3 V CL = 15 pF CL = 50 pF 4.5 5.8 10.0 13.5 VCC = 5.0 ± 0.5 V CL = 15 pF CL = 50 pF 3.0 3.8 5.5 Test Conditions Maximum Input Capacitance Min Max −55 ≤ TA ≤ 125°C Min Max Unit 11.0 15.0 13.0 17.5 ns 6.7 7.7 7.5 8.5 8.5 9.5 10 10 10 pF Typical @ 25°C, VCC = 5.0 V CPD 11 Power Dissipation Capacitance (Note 6) pF 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. http://onsemi.com 3 MC74VHC1GT02 3.0 V A or B 50% GND tPHL tPLH VOH Y 50% VCC VOL Figure 4. Switching Waveforms TEST POINT OUTPUT INPUT CL* *Includes all probe and jig capacitance Figure 5. Test Circuit ORDERING INFORMATION Device Package MC74VHC1GT02DFT1 SC70−5/SC−88A/SOT−353 M74VHC1GT02DFT1G SC70−5/SC−88A/SOT−353 (Pb−Free) MC74VHC1GT02DFT2 SC70−5/SC−88A/SOT−353 M74VHC1GT02DFT2G SC70−5/SC−88A/SOT−353 (Pb−Free) MC74VHC1GT02DTT1 SOT23−5/TSOP−5/SC59−5 M74VHC1GT02DTT1G SOT23−5/TSOP−5/SC59−5 (Pb−Free) Shipping† 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 MC74VHC1GT02 PACKAGE DIMENSIONS SC−88A, SOT−353, SC−70 CASE 419A−02 ISSUE J A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A−01 OBSOLETE. NEW STANDARD 419A−02. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. G 5 4 −B− S 1 2 DIM A B C D G H J K N S 3 D 5 PL 0.2 (0.008) M B M N INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC −−− 0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087 J C K H SOLDERING FOOTPRINT* 0.50 0.0197 0.65 0.025 0.65 0.025 0.40 0.0157 1.9 0.0748 SCALE 20:1 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 mm Ǔ ǒinches MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC −−− 0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 MC74VHC1GT02 PACKAGE DIMENSIONS TSOP−5 CASE 483−02 ISSUE F NOTE 5 2X 0.10 T 2X 0.20 T D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. 5X 0.20 C A B 5 1 4 2 3 M B S K L DETAIL Z G A DIM A B C D G H J K L M S DETAIL Z J C 0.05 SEATING PLANE H T MILLIMETERS MIN MAX 3.00 BSC 1.50 BSC 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00 SOLDERING FOOTPRINT* 0.95 0.037 1.9 0.074 2.4 0.094 1.0 0.039 0.7 0.028 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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