a FEATURES CMOS 10-Bit 40 MSPS Sampling A/D Converter Power Dissipation: 74 mW (3 V Supply, 40 MSPS) 17 mW (3 V Supply, 5 MSPS) Operation Between 2.7 V and 3.6 V Supply Differential Nonlinearity: ⴞ0.25 LSB Power-Down (Standby) Mode, 0.65 mW ENOB: 9.55 @ fIN = 20 MHz Out-of-Range Indicator Adjustable On-Chip Voltage Reference IF Undersampling up to fIN = 130 MHz Input Range: 1 V to 2 V p-p Differential or Single-Ended Adjustable Power Consumption Internal Clamp Circuit APPLICATIONS CCD Imaging Video Portable Instrumentation IF and Baseband Communications Cable Modems Medical Ultrasound PRODUCT DESCRIPTION The AD9203 is a monolithic low power, single supply, 10-bit, 40 MSPS analog-to-digital converter, with an on-chip voltage reference. The AD9203 uses a multistage differential pipeline architecture and guarantees no missing codes over the full operating temperature range. Its input range may be adjusted between 1 V and 2 V p-p. The AD9203 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of an application. An external resistor can be used to reduce power consumption when operating at lower sampling rates. This yields power savings for users who do not require the maximum sample rate. This feature is especially useful at sample rates far below 40 MSPS. Excellent performance is still achieved at reduced power. For example, 9.7 ENOB performance may be realized with only 17 mW of power, using a 5 MHz clock. A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary or twos complementary output format by using the DFS pin. An out-of-range signal (OTR) indicates an overflow condition that can be used with the most significant bit to determine over or under range. 10-Bit, 40 MSPS, 3 V, 74 mW A/D Converter AD9203 FUNCTIONAL BLOCK DIAGRAM CLK AVDD DRVDD CLAMP AD9203 CLAMPIN AINP STBY A/D AINN SHA A/D GAIN D/A SHA A/D REFTF GAIN 3 STATE D/A CORRECTION LOGIC REFBF BANDGAP REFERENCE OTR OUTPUT BUFFERS 10 D9 (MSB) VREF REFSENSE 0.5V + – AVSS D0 (LSB) PWRCON DFS DRVSS The AD9203 is specified over industrial (–40°C to +85°C) temperature ranges and is available in a 28-lead TSSOP package. PRODUCT HIGHLIGHTS Low Power The AD9203 consumes 74 mW on a 3 V supply operating at 40 MSPS. In standby mode, power is reduced to 0.65 mW. High Performance Maintains better than 9.55 ENOB at 40 MSPS input signal from dc to Nyquist. Very Small Package The AD9203 is available in a 28-lead TSSOP. Programmable Power The AD9203 power can be further reduced by using an external resistor at lower sample rates. Built-In Clamp Function Allows dc restoration of video signals. The AD9203 can operate with a supply range from 2.7 V to 3.6 V, attractive for low power operation in high speed portable applications. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 (AVDD = +3 V, DRVDD = +3 V, FS = 40 MSPS, input span from 0.5 V to 2.5 V, Internal 1 V MIN to TMAX unless otherwise noted.) AD9203–SPECIFICATIONS Reference, PWRCON = AVDD, 50% clock duty cycle, T Parameter Symbol Min RESOLUTION MAX CONVERSION RATE Typ 10 FS 40 ANALOG INPUT Input Voltage Range Input Capacitance Aperture Delay Aperture Uncertainty (Jitter) Input Bandwidth (–3 dB) Input Referred Noise INTERNAL REFERENCE Output Voltage (0.5 V Mode) Output Voltage (1 V Mode) Output Voltage Tolerance (1 V Mode) Load Regulation POWER SUPPLY Operating Voltage Analog Supply Current Digital Supply Current AIN CIN TAP TAJ BW AVDD DRVDD IAVDD IDRVDD 2.7 2.7 Power Consumption Power-Down Power Supply Rejection Ratio DYNAMIC PERFORMANCE (AIN = 0.5 dBFS) Signal-to-Noise and Distortion f = 4.8 MHz f = 20 MHz Effective Bits f = 4.8 MHz f = 20 MHz Signal-to-Noise Ratio f = 4.8 MHz f = 20 MHz Total Harmonic Distortion f = 4.8 MHz f = 20 MHz Spurious Free Dynamic Range f = 4.8 MHz f = 20 MHz Two-Tone Intermodulation Distortion Differential Phase Differential Gain DIGITAL INPUTS High Input Voltage Low Input Voltage Clock Pulsewidth High Clock Pulsewidth Low Clock Period2 5.5 Clock Cycles ± 0.7 ± 1.4 ± 2.8 ± 4.0 LSB LSB % FSR % FSR 2 1.4 2.0 1.2 390 0.3 V p-p pF ns ps rms MHz mV 0.5 1 ±5 0.65 ± 30 1.2 V V mV mV 3.0 3.0 20.1 4.4 9.5 74 88.8 0.65 0.04 3.6 3.6 22.0 6.0 14.0 84.0 108.0 1.2 ± 0.25 V V mA mA mA mW mW mW % FS 1 VREF VREF PD PSRR Conditions MSPS ± 0.25 ± 0.65 ± 0.6 ± 0.7 DNL INL EZS EFS Units Bits PIPELINE DELAY DC ACCURACY Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error Max SINAD Switched, Single-Ended REFSENSE = VREF REFSENSE = GND 1.0 mA Load fIN = 4.8 MHz, Output Bus Load = 10 pF fIN = 20 MHz, Output Bus Load = 20 pF fIN = 4.8 MHz, Output Bus Load = 10 pF fIN = 20 MHz, Output Bus Load = 20 pF Note 1 57.2 59.7 59.3 dB dB 9.2 9.6 9.55 Bits Bits 57.5 60.0 59.5 dB dB –76.0 –74.0 –65.0 dB dB Note 1 80 78 68 0.2 0.3 dB dB dB Degree % Note 1 ENOB Note 1 SNR THD SFDR 67.8 IMD DP DG VIH VIL 2.0 0.4 11.25 11.25 25 –2– f = 44.49 MHz and 45.52 MHz NTSC 40 IRE Ramp V V ns ns ns REV. 0 AD9203 Parameter Symbol DIGITAL OUTPUTS High-Z Leakage Data Valid Delay Data Enable Delay Data High-Z Delay IOZ tOD tDEN tDHZ LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (I OH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 µA) VOH VOH VOL VOL Min Typ Max Units Conditions ± 5.0 µA ns ns ns Output = 0 to DRVDD CL = 20 pF CL = 20 pF CL = 20 pF 5 6 6 +2.95 +2.80 V V V V +0.3 +0.05 NOTES 1 Differential Input (2 V p-p). 2 The AD9203 will convert at clock rates as low as 20 kHz. Specifications subject to change without notice. N+1 N ANALOG INPUT N+2 N–1 N+3 N+4 N+6 N+5 CLOCK DATA OUT N–7 N–6 N–5 N–4 N–3 N–2 TOD = 3ns MIN 7ns MAX (CLOAD = 20pF) Figure 1. Timing Diagram REV. 0 –3– N–1 N N+1 AD9203 ABSOLUTE MAXIMUM RATINGS* Parameter AVDD DRVDD AVSS AVDD REFCOM CLK Digital Outputs AINP VREF REFSENSE REFTF, REFBF STBY CLAMP CLAMPIN PWRCON DFS 3-STATE Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect to Min AVSS DRVSS DRVSS DRVDD AVSS AVSS DRVSS AINN AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS –0.3 –0.3 –0.3 –3.9 –0.3 –0.3 –0.3 AVSS – 0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –65 THERMAL CHARACTERISTICS Max Units +3.9 +3.9 +0.3 +3.9 +0.3 AVDD + 0.3 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +150 +150 V V V V V V V V V V V V V V V V V °C °C +300 °C 28-Lead TSSOP θJA = 97.9°C/W θJC = 14.0°C/W ORDERING GUIDE Model Temperature Range AD9203ARU –40°C to +85°C AD9203-EB Package Description Package Option 28-Lead Thin Shrink RU-28 Small Outline Evaluation Board *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9203 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. 0 AD9203 PIN CONFIGURATION DRVSS 1 28 AVDD DRVDD 2 27 AVSS (LSB) D0 3 26 AINN D1 4 25 AINP D2 5 24 REFBF D3 6 AD9203 23 VREF D4 7 TOP VIEW 22 REFTF D5 8 (Not to Scale) 21 PWRCON D6 9 20 CLAMPIN D7 10 19 CLAMP D8 11 18 REFSENSE (MSB) D9 12 17 STBY OTR 13 16 3-STATE DFS 14 15 CLK PIN FUNCTION DESCRIPTIONS Pin Name Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DRVSS DRVDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 OTR DFS CLK 3-STATE STBY REFSENSE CLAMP CLAMPIN PWRCON REFTF VREF REFBF AINP AINN AVSS AVDD Digital Ground Digital Supply Bit 0, Least Significant Bit Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9, Most Significant Bit Out-of-Range Indicator Data Format Select. (HI: Twos Complement. LO: Straight Binary) Clock Input HI: High Impedance State Output. LO: Active Digital Output Drives HI: Power-Down Mode. LO: Normal Operation Reference Select HI: Enable Clamp. LO: Open Clamp Clamp Signal Input Power Control Input Top Reference Decoupling Reference In/Out Bottom Reference Decoupling Noninverting Analog Input Inverting Analog Input Analog Ground Analog Supply REV. 0 –5– AD9203 DEFINITIONS OF SPECIFICATIONS SPURIOUS FREE DYNAMIC RANGE (SFDR) INTEGRAL NONLINEARITY ERROR (INL) The difference in dB between the rms amplitude of the input signal and the peak spurious signal. Linearity error refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as “negative full scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. OFFSET ERROR First transition should occur for an analog value 1/2 LSB above –full scale. Offset error is defined as the deviation of the actual transition from that point. GAIN ERROR The first code transition should occur at an analog value 1/2 LSB above –full scale. The last transition should occur for an analog value 1 1/2 LSB below the +full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. DIFFERENTIAL NONLINEARITY ERROR (DNL, NO MISSING CODES) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 10-bit resolution indicates that all 1024 codes respectively, must be present over all operating ranges. SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD) RATIO POWER SUPPLY REJECTION The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. APERTURE JITTER EFFECTIVE NUMBER OF BITS (ENOB) Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D. For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, APERTURE DELAY Aperture delay is a measure of the Sample-and-Hold Amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. N = (SINAD – 1.76)/6.02 it is possible to get a measure of performance expressed as N, the effective number of bits. PIPELINE DELAY (LATENCY) Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. The number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided on every rising edge. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. SIGNAL-TO-NOISE RATIO (SNR) SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. –6– REV. 0 Typical Performance Characteristics– AD9203 (AVDD = +3 V, DRVDD = +3 V, FS = 40 MSPS, 1 V Internal Reference, PWRCON = AVDD, 50% Duty Cycle, unless otherwise noted) 85 61 80 2V SINGLE-ENDED INPUT 59 75 2V DIFFERENTIAL INPUT 1V DIFFERENTIAL INPUT 70 SFDR – dB SNR – dB 57 55 53 1V DIFFERENTIAL INPUT 65 1V SINGLEENDED INPUT 60 55 2V DIFFERENTIAL INPUT 50 51 2V SINGLEENDED INPUT 45 49 40 1V SINGLE-ENDED INPUT 47 35 0 20 40 60 80 INPUT FREQUENCY – MHz 120 100 20 40 60 80 INPUT FREQUENCY – MHz –75 55 –70 8.8 1V DIFFERENTIAL INPUT 8.0 1V DIFFERENTIAL INPUT THD – dB 50 ENOB SINAD – dB –65 7.1 1V SINGLEENDED INPUT 20 40 60 80 INPUT FREQUENCY – MHz –55 1V SINGLEENDED INPUT –50 –40 6.3 2V SINGLEENDED INPUT 0 2V DIFFERENTIAL INPUT –60 –45 40 35 120 –80 9.0 2V DIFFERENTIAL INPUT 45 100 Figure 5. SFDR vs. Input Frequency and Configuration Figure 2. SNR vs. Input Frequency and Configuration 60 0 2V SINGLEENDED INPUT –35 100 5.5 120 –30 Figure 3. SINAD vs. Input Frequency and Configuration 0 20 40 60 80 INPUT FREQUENCY – MHz 100 120 Figure 6. THD vs. Input Frequency and Configuration –75 –75 –70 –0.5dB –0.5dB –65 –65 THD – dB THD – dB –6.0dB –60 –6.0dB –55 –55 –20dB –50 –45 –20dB –45 –40 0 20 40 60 80 INPUT FREQUENCY – MHz 100 –35 120 Figure 4. THD vs. Input Frequency and Amplitude (Differential Input VREF = 0.5 V) REV. 0 0 20 40 60 80 INPUT FREQUENCY – MHz 100 120 Figure 7. THD vs. Input Frequency and Amplitude (Differential Input VREF = 1 V) –7– AD9203 1.2E+07 1.0 0.8 10000000 1.0E+07 0.6 0.4 8.0E+06 LSB HITS 0.2 6.0E+06 0.0 –0.2 4.0E+06 –0.4 –0.6 2.0E+06 –0.8 4560 0.0E+00 10310 N–1 N –1.0 N+1 0 100 200 300 400 500 600 700 800 900 1024 CODE Figure 11. Typical DNL Performance Figure 8. Grounded Input Histogram 10.0 80 SNR = 59.9dB THD = –75dB SFDR = 82dB 0.0 75 –10.0 –THD –20.0 70 –40.0 dB +SNR/–THD – dB –30.0 65 60 SNR –50.0 –60.0 –70.0 55 –80.0 50 –90.0 –100.0 45 –110.0 40 0 10 20 30 40 SAMPLE RATE – MSPS 50 –120.0 0E+0 2.5E+6 5E+6 7.5E+6 10E+6 12.5E+6 15E+6 17.5E+6 20E+6 60 Figure 9. SNR and THD vs. Sample Rate (fIN = 20 MHz) Figure 12. Single Tone Frequency Domain Performance (Input Frequency = 10 MHz, Sample Rate = 40 MSPS 2 V Differential Input, 8192 Point FFT) 1.0 80 0.8 75 0.6 –THD +SNR/–THD – dB 0.4 LSB 0.2 0.0 –0.2 –0.4 70 65 60 SNR –0.6 55 –0.8 –1.0 0 100 200 300 400 500 600 700 800 900 50 2.5 1024 Figure 10. Typical INL Performance 3.0 3.5 SUPPLY VOLTAGE – V 4.0 Figure 13. THD vs. Power Supply (fIN = 20 MHz, Sample Rate = 40 MSPS) –8– REV. 0 AD9203 APPLYING THE AD9203 0 THEORY OF OPERATION –1 The AD9203 implements a pipelined multistage architecture to achieve high sample rates while consuming low power. The AD9203 distributes the conversion over several smaller A/D subblocks, refining the conversion with progressively higher accuracy as it passes the results from stage to stage. As a consequence of the distributed conversion, the AD9203 requires a small fraction of the 1023 comparators used in a traditional 10-bit flash-type A/D. A sample-and-hold function within each of the stages permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. –2 AMPLITUDE – dB –3 –4 –5 –6 –7 –8 Each stage of the pipeline, excluding the last, consists of a low resolution flash A/D connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash A/D. –9 10 100 INPUT FREQUENCY – MHz 1000 Figure 14. Full Power Bandwidth 3500 The input of the AD9203 incorporates a novel structure that merges the input sample and hold amplifier (SHA) and the first pipeline residue amplifier into a single, compact switched capacitor circuit. This structure achieves considerable noise and power savings over a conventional implementation that uses separate amplifiers by eliminating one amplifier in the pipeline. By matching the sampling network of the input SHA with the first stage flash A/D, the AD9203 can sample inputs well beyond the Nyquist frequency with no degradation in performance. 3000 1V REFERENCE WAKE-UP TIME – ms 2500 2000 0.5V REFERENCE 1500 1000 Sampling occurs on the falling edge of the clock. 500 0 200 0 400 600 OFF-TIME – ms 800 OPERATIONAL MODES 1000 The AD9203 may be connected in several input configurations (see Table I). Figure 15. Wake-Up Time vs. Off Time (VREF Decoupling = 10 µ F) The AD9203 may be driven differentially from a source that keeps the signal peaks within the power supply rails. Alternatively, the input may be driven into AINP or AINN from a single-ended source. The input span will be 2× the programmed reference voltage. One input will accept the signal, while the opposite input will be set to midscale by connecting it to the internal or an external reference. For example, a 2 V p-p signal may be applied to AINP while a 1 V reference is applied to AINN. The AD9203 will then accept a signal varying between 2 V and 0 V. See Figures 17, 18 and 19 for more details. 0.2 VREF ERROR – % 0.1 0 0.5V –0.1 The AD9203’s single-ended (ac-coupled) input may also be clamped to ground by the AD9203’s internal clamp switch. This is accomplished by connecting the CLAMP pin to AINN or AINP. 1V –0.2 Digital output formats may be configured in binary and twos complement. This is determined by the potential on the DFS pin. If the pin is set to Logic “0,” the data will be in straight binary format. If the pin is asserted to Logic “1,” the data will be in twos complement format. –0.3 –0.4 –40 –20 0 20 40 TEMPERATURE – 8C 60 80 100 Figure 16. Reference Voltage vs. Temperature REV. 0 Power consumption may be reduced by placing a resistor between PWRCON and AVSS. This may be done to conserve power when not encoding high speed analog input frequencies or sampling at the maximum conversion rate. See Power Control section. –9– AD9203 Table I. Modes Name Figure Number Advantages 1 V Differential 2 V Differential 1 V Single-Ended Figure 26 with VREF Connected to REFSENSE Figure 26 with REFSENSE Connected to AGND Figure 18 2 V Single-Ended Figure 17 Differential Modes Yield the Best Dynamic Performance Differential Modes Yield the Best Dynamic Performance Video and Applications Requiring Clamping Require Single-Ended Inputs Video and Applications Requiring Clamping Require Single-Ended Inputs INPUT AND REFERENCE OVERVIEW Like the voltage applied to the top of the resistor ladder in a flash A/D converter, the value VREF defines the maximum input voltage to the A/D core. The minimum input voltage to the A/D core is automatically defined to be –VREF. The addition of a differential input structure gives the user an additional level of flexibility that is not possible with traditional flash converters. The input stage allows the user to easily configure the inputs for either single-ended operation or differential operation. The A/D’s input structure allows the dc offset of the input signal to be varied independently of the input span of the converter. Specifically, the input to the A/D core is the difference of the voltages applied at the AINP and AINN input pins. Therefore, the equation, VCORE = AINP – AINN ADC will equal the twice voltage at the reference pin for both an internal or external reference. Figure 17 illustrates the input configured with a 1 V reference. This will set the single-ended input of the AD9203 in the 2 V span (2 × VREF). This example shows the AINN input is tied to the 1 V VREF. This will configure the AD9203 to accept a 2 V input centered around 1 V. 2V 0V AINN REFTF ADC CORE (1) The voltage, VCORE, must satisfy the condition, 0.1mF 10mF + 0.5V 0.1mF – (2) where VREF is the voltage at the VREF pin. REFSENSE The actual span (AINP – AINN) of the ADC is ± VREF. AVSS – 0.3 V < AINP < AVDD + 0.3 V AVSS – 0.3 V < AINN < AVDD + 0.3 V 10mF 0.1mF REFBF 1V VREF While an infinite combination of AINP and AINN inputs exist that satisfy Equation 2, an additional limitation is placed on the inputs by the power supply voltages of the AD9203. The power supplies bound the valid operating range for AINP and AINN. The condition, 2V 0.1mF defines the output of the differential input stage and provides the input to the A/D core. –VREF ≤ VCORE ≤ VREF AINP LOGIC AD9203 Figure 17. Internal Reference Set for a 2 V Span (3) Figure 18 illustrates the input configured with a 0.5 V reference. This will set the single ended input of the ADC in a 1 V span (2 × VREF). The AINN input is tied to the 0.5 VREF. This will configure the AD9203 to accept a 1 V input centered around 0.5 V. where AVSS is nominally 0 V and AVDD is nominally +3 V, defines this requirement. The range of valid inputs for AINP and AINN is any combination that satisfies both Equations 2 and 3. 1V 0V AINP AINN REFTF 1.75V 0.1mF INTERNAL REFERENCE CONNECTION A comparator within the AD9203 will detect the potential of the VREF pin. If REFSENSE is grounded, the reference amplifier switch will connect to the resistor divider (see Figure 17). That will make VREF equal to 1 V. If resistors are placed between VREF, REFSENSE and ground, the switch will be connected to the REFSENSE position and the reference amplitude will depend on the external programming resistors (Figure 19). If REFSENSE is tied to VREF, the switch will also connect to REFSENSE and the reference voltage will be 0.5 V (Figure 18). REFTF and REFBF will drive the ADC conversion core and establish its maximum and minimum span. The range of the ADC CORE 10mF 0.1mF REFBF 1.25V 0.1mF VREF 10mF –10– + 0.5V 0.1mF – LOGIC REFSENSE AD9203 Figure 18. Internal Reference Set for a 1 V Span REV. 0 AD9203 Figure 19 shows the reference programmed by external resistors for 0.75 V. This will set the ADC to receive a 1.5 V span centered about 0.75 V. The reference is programmed according to the algorithm CLAMP OPERATION The AD9203 contains an internal clamp. It may be used when operating the input in a single-ended mode. The AD9203’s clamp is very useful for clamping NTSC and PAL video signals to ground. The clamp cannot be used in the differential input mode. VREF = 0.5 V × [1 + (RA/RB)] 1.5V 0V AINP REFSENSE AD9203 REFTF 1.875V AINN VREF 0.1mF ADC CORE 10mF 0.1mF AINN REFBF 1.125V CIN 0.1mF 10mF 1V p-p + VREF 0Vdc 50V TYP 0.5V 0.1mF ADC CORE AINP CLAMP IN – RA CLAMP LOGIC AD9203 REFSENSE SW1 RB Figure 19. Programmable Reference Configuration Figure 21. Clamp Configuration (VREF = 0.5 V) Figure 21 shows the internal clamp circuitry and the external control signals needed for clamp operation. To enable the clamp, apply a logic high “1” to the CLAMP pin. This will close the internal switch SW1. SW1 is opened by asserting the CLAMP pin low “0.” The capacitor holds the voltage across CIN constant until the next interval. The charge on the capacitor will leak off as a function of input bias current (see Figure 22). EXTERNAL REFERENCE OPERATION Figure 20 illustrates the use of an external reference. An external reference may be necessary for several reasons. Tighter reference tolerance will enhance the accuracy of the ADC and will allow lower temperature drift performance. When several ADC’s track one another, a single reference (internal or external) will be necessary. The AD9203 will draw less power when an external reference is used. 250 When the REFSENSE pin is tied to AVDD, the internal reference will be disabled, allowing the use of an external reference. The AD9203 contains an internal reference buffer. It will load the external reference with an equivalent 10 kΩ load. The internal buffer will generate positive and negative full-scale references for the ADC core. In Figure 20, an external reference is used to set the midscale set point for single-ended use. At the same time, it sets the input voltage span through a resistor divider. If the ADC is being driven differentially through a transformer, the external reference can set the center tap (common-mode voltage). INPUT BIAS – mA 200 150 100 50 0 –50 0 3.0V 2.0V 1.0V +5V AINP AD9203 EXTERNAL REF (2V) 0.1mF 0.1mF 1.5kV VREF A3 1V 0.1mF 1.5kV AVDD REFSENSE Figure 20. External Reference Configuration REV. 0 1 1.5 2 INPUT VOLTAGE – Volts 2.5 Figure 22. Input Bias Current vs. Input Voltage (FS = 40 MSPS) AINN 10mF 0.5 –11– 3 AD9203 DRIVING THE ANALOG INPUT C1 Figure 23 illustrates the equivalent analog input of the AD9203, (a switched capacitor input). Bringing CLK to a logic high, opens S3 and closes S1 and S2. The input source connected to AIN and must charge Capacitor CH during this time. Bringing CLK to a logic low opens S2, and then S1 opens followed by closing S3. This puts the input in the hold mode. R1 VIN AIN C2 AVDD/2 R2 + VBIAS = AD9203 Figure 25. AC-Coupled Input The f–3 dB point can be approximated by the equation: f–3 dB = 1/(2 π × [R2] CEQ ) AD9203 S1 where CEQ is the parallel combination of C1 and C2. Note that C1 is typically a large electrolytic or tantalum capacitor that becomes inductive at high frequencies. Add a small ceramic or polystyrene capacitor (on the order of 0.01 µF) that is negligibly inductive at higher frequencies while maintaining a low impedance over a wide frequency range. CH CP S3 CP S2 CH Figure 23. Input Architecture The structure of the input SHA places certain requirements on the input drive source. The combination of the pin capacitance, CP, and the hold capacitance, CH, is typically less than 5 pF. The input source must be able to charge or discharge this capacitance to 10-bit accuracy in one half of a clock cycle. When the SHA goes into track mode, the input source must charge or discharge capacitor CH from the voltage already stored on CH to the new voltage. In the worst case, a full-scale voltage step on the input source must provide the charging current through the RON (100 Ω) of Switch 1 and quickly (within 1/2 CLK period) settle. This situation corresponds to driving a low input impedance. Adding series resistance between the output of the signal source and the AIN pin reduces the drive requirements placed on the signal source. Figure 24 shows this configuration. The bandwidth of the particular application limits the size of this resistor. To maintain the performance outlined in the data sheet specifications, the resistor should be limited to 50 Ω or less. The series input resistor can be used to isolate the driver from the AD9203’s switched capacitor input. The external capacitor may be selected to limit the bandwidth into the AD9203. Two input RC networks should be used to balance differential input drive schemes (Figure 24). The input span of the AD9203 is a function of the reference voltage. For more information regarding the input range, see the Internal and External Reference sections of the data sheet. <50V AIN VS AD9203 Figure 24. Simple AD9203 Drive Configuration In many cases, particularly in single-supply operation, ac coupling offers a convenient way of biasing the analog input signal to the proper signal range. Figure 25 shows a typical configuration for ac-coupling the analog input signal to the AD9203. Maintaining the specifications outlined in the data sheet requires careful selection of the component values. The most important is the f–3 dB high-pass corner frequency. It is a function of R2 and the parallel combination of C1 and C2. There are additional considerations when choosing the resistor values for an ac-coupled input. The ac-coupling capacitors integrate the switching transients present at the input of the AD9203 and cause a net dc bias current, IB, to flow into the input. The magnitude of the bias current increases as the signal changes and as the clock frequency increases. This bias current will result in an offset error of (R1 + R2) × IB. If it is necessary to compensate for this error, consider modifying VBIAS to account for the resultant offset. In systems that must use dc coupling, use an op amp to level-shift ground-referenced signals to comply with the input requirements of the AD9203. OP AMP SELECTION GUIDE Op amp selection for the AD9203 is highly application dependent. In general, the performance requirements of any given application can be characterized by either time domain or frequency domain constraints. In either case, one should carefully select an op amp that preserves the performance of the A/D. This task becomes challenging when one considers the AD9203’s high performance capabilities coupled with other system level requirements such as power consumption and cost. The ability to select the optimal op amp may be further complicated by either limited power supply availability and/or limited acceptable supplies for a desired op amp. Newer, high performance op amps typically have input and output range limitations in accordance with their lower supply voltages. As a result, some op amps will be more appropriate in systems where accoupling is allowed. When dc-coupling is required, op amps’ headroom constraints (such as rail-to-rail op amps) or ones where larger supplies can be used, should be considered. The following section describes some op amps currently available from Analog Devices. Please contact the factory or local sales office for updates on Analog Devices latest amplifier product offerings. AD8051: f–3 dB = 110 MHz. Low cost. Best used for driving single-ended ac-coupled configuration. Operates on a 3 V power rail. AD8052: Dual Version of above amp. AD8138 is a higher performance version of AD8131. Its gain is programmable and provides 14-bit performance. –12– REV. 0 AD9203 DIFFERENTIAL MODE OF OPERATION Since not all applications have a signal preconditioned for differential operation, there is often a need to perform a single-endedto-differential conversion. In systems that do not need a dc input, an RF transformer with a center tap is a method to generate differential inputs beyond 20 MHz for the AD9203. This provides all the benefits of operating the A/D in the differential mode without contributing additional noise or distortion. An RF transformer also has the added benefit of providing electrical isolation between the signal source and the A/D. An improvement in THD and SFDR performance can be realized by operating the AD9203 in differential mode. The performance enhancement between the differential and single-ended mode is most considerable as the input frequency approaches and goes beyond the Nyquist frequency (i.e., fIN > FS/2). Transformers with other turns ratios may also be selected to optimize the performance of a given application. For example, selecting a transformer with a higher impedance ratio (e.g., Minicircuits T16–6T with a impedance ratio of 16) effectively “steps up” the signal amplitude, thus further reducing the driving requirements of the signal source. The AD9203 can be easily configured for either a 1 V p-p input span or 2 V p-p input span by setting the internal reference. Other input spans can be realized with two external gain setting resistors as shown in Figure 19 of this data sheet. Figures 32 and 33 demonstrate the SNR and SFDR performance over a wide range of amplitudes required by most communication applications. –80 1.0V REF +3V 499V 0.1mF 10mF 10mF 0.1mF 0.1mF 10kV 499V 49.9V AVDD AINP 20pF 49.9V 523V DRVDD AD9203 AD8138 AINN 49.9V DIGITAL OUTPUTS AVSS DRVSS –60 –50 –40 20pF 0.1mF 0.5V REF –70 THD – dB +3V 499V 10kV –30 0 Figure 26. AD8138 Driving an AD9203, a 10-Bit, 40 MSPS A/D Converter THD – dB THD SNR –60 –40 40.0 42.5 45.0 47.5 50.0 52.5 DUTY CYCLE – % 55.0 57.5 60.0 Figure 29. THD and SNR vs. Clock Duty Cycle (fIN = 5 MHz Differential, Clock = 40 MSPS) AD9203 VREF 0.1mF REFSENSE Figure 27. Transformer Coupled Input REV. 0 –70 –50 AINN 10mF 3.5 –80 The center tap of the transformer provides a convenient means of level-shifting the input signal to a desired common-mode voltage. Figure 28 illustrates the performance of the AD9203 over a wide range of common-mode levels. 1V 3.0 –90 Figure 27 shows the schematic of a suggested transformer circuit. The circuit uses a Minicircuits RF transformer, model number T4–1T, which has an impedance ratio of four (turns ratio of 2). AINP 1.0 1.5 2.0 2.5 COMMON-MODE VOLTAGE – Volts Figure 28. THD vs. Common-Mode Voltage vs. THD (AIN = 2 V Differential) (fIN = 5 MHz, fS = 40 MSPS) The AD8138 provides a convenient method of converting a single-ended signal to a differential signal. This is an ideal method for generating a direct coupled signal to the AD9203. The AD8138 will accept a signal and shift it to an externally provided common-mode level. The AD8138 configuration is shown in Figure 26. 2V 0.5 –13– AD9203 Table II. Power Programming Resistance Clock MHz fIN MHz THD dB SNR dB SINAD dB SFDR dB IAVDD mA IDRVDD mA Total Power Into 5 pF Load mW Power Control Resistor k⍀ 5 10 15 20 30 2.5 2.5 2.5 5 5 –72 –74.3 –74 –75.1 –75 60.6 60.7 60.1 53.4 59.5 59.9 60.4 59.9 53.2 59.4 77.9 77.8 77.7 78.9 74.8 5.0 5.9 6.7 7.8 10 0.86 1.2 1.8 2.4 4.0 17 21.3 25 30 42 37 37 37 50 50 POWER CONTROL Power consumed by the AD9203 may be reduced by placing a resistor between the PWRCON pin and ground. This function will be valuable to users who do not need the AD9203’s high conversion rate, but do need even lower power consumption. The external resistor sets the programming of the analog current mirrors. Table II illustrates the relationship between programmed power and performance. At lower clock rates, less power is required within the analog sections of the AD9203. Placing an external resistor on the PWRCON pin will shunt control current away from some of the current mirrors. This enables the ADC to convert low data rates with extremely low power consumption. INTERFACING TO 5 V SYSTEMS The AD9203 can be integrated into +5 V systems. This is accomplished by deriving a 3 V power supply from the existing 5 V analog power line through an AD3307-3 linear regulator. Care must be maintained so that logic inputs do not exceed the maximum rated values listed on the Specifications page. CLOCK INPUT AND CONSIDERATIONS The AD9203 internal timing uses the two edges of the clock input to generate a variety of internal timing signals. Sampling occurs on the falling edge. The clock input to the AD9203 operating at 40 MSPS may have a duty cycle between 45% to 55% to meet this timing requirement since the minimum specified tCH and tCL is 11.25 ns. For clock rates below 40 MSPS, the duty cycle may deviate from this range to the extent that both tCH and tCL are satisfied. See Figure 29 for dynamics vs. duty cyle. input frequency (fIN) due only to aperture jitter (tA) can be calculated with the following equation: SNR degradation = 20 log10 [1/2 π f IN tA] In the equation, the rms aperture jitter, tA, represents the rootsum square of all the jitter sources, which include the clock input, analog input signal, and A/D aperture jitter specification. Undersampling applications are particularly sensitive to jitter. Clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9203. Power supplies for clock drivers should be separated from the A/D output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing or other method), it should be retimed by the original clock at the last step. The clock input is referred to the analog supply. Its logic threshold is AVDD/2. DIGITAL INPUTS AND OUTPUTS Each of the AD9203 digital control inputs, 3-STATE, DFS and STBY are referenced to analog ground. CLK is also referenced to analog ground. A low power mode feature is provided such that for STBY = HIGH and the static power of the AD9203 drops to 0.65 mW. Asserting the DFS pin high will invert the MSB pin, changing the data to a twos complement format. The AD9203 has an OTR (out of range) function. If the input voltage is above or below full scale by 1 LSB, the OTR flag will go high. See Figure 30. High speed high resolution A/Ds are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale OTR OTR DATA OUTPUTS 1 0 0 11111 11111 11111 11111 11111 11110 0 0 1 00000 00000 00000 00001 00000 00000 +FS –FS –FS + 1 LSB +FS – 1 LSB Figure 30. Output Data Format –14– REV. 0 AD9203 G1 = 20dB SAW FILTER OUTPUT 50V BANDPASS MINI CIRCUITS FILTER T4-6T 1:4 G2 = 20dB 50V 50V 200V AINP 200V AINN 22.1V 93.1V AD9203 AVDD/2 Figure 31. Simplified IF Sampling Circuit Sampling IF signals above an ADC’s baseband region (i.e., dc to FS/2) is becoming increasingly popular in communication applications. This process is often referred to as Direct IF Down Conversion or Undersampling. There are several potential benefits in using the ADC to alias (i.e., or mix) down a narrow band or wide band IF signal. First and foremost is the elimination of a complete mixer stage with its associated amplifiers and filters, reducing cost and power dissipation. Second is the ability to apply various DSP techniques to perform such functions as filtering, channel selection, quadrature demodulation, data reduction, detection, etc. A detailed discussion on using this technique in digital receivers can be found in Analog Devices Application Notes AN-301 and AN-302. In Direct IF Down Conversion applications, one exploits the inherent sampling process of an ADC in which an IF signal lying outside the baseband region can be aliased back into the baseband region in a manner similar to a mixer downconverting an IF signal. Similar to the mixer topology, an image rejection filter is required to limit other potential interfering signals from also aliasing back into the ADC’s baseband region. A trade-off exists between the complexity of this image rejection filter and the ADC’s sample rate as well as dynamic range. The AD9203 is well suited for various IF sampling applications. The AD9203’s low distortion input SHA has a full-power bandwidth extending to 130 MHz, thus encompassing many popular IF frequencies. Only the 2 V span should be used for undersampling beyond 20 MHz. A DNL of ± 0.25 LSB combined with low thermal input referred noise allows the AD9203 in the 2 V span to provide >59 dB of SNR for a baseband input sine wave. Also, its low aperture jitter of 1.2 ps rms ensures minimum SNR degradation at higher IF frequencies. In fact, the AD9203 is capable of still maintaining 58 dB of SNR at an IF of 70 MHz with a 2 V input span. To maximize its distortion performance, the AD9203 should be configured in the differential mode with a 2 V span using a transformer. The center-tap of the transformer is biased to the reference output of the AD9203. Preceding the AD9203 and transformer is an optional bandpass filter as well as a gain stage. A low Q passive bandpass filter can be inserted to reduce out-ofband distortion and noise that lies within the AD9203’s 390 MHz bandwidth. A large gain stage(s) is often required to compensate for the high insertion losses of a SAW filter used for channel selection and image rejection. The gain stage will also provide adequate isolation for the SAW filter from the charge “kick back” currents associated with the AD9203’s switched capacitor input stage. The distortion and noise performance of an ADC at the given IF frequency is of particular concern when evaluating an ADC REV. 0 for a narrowband IF sampling application. Both single tone and dual tone SFDR vs. amplitude are very useful in assessing an ADC’s dynamic and static nonlinearities. SNR vs. amplitude performance at the given IF is useful in assessing the ADC’s noise performance and noise contribution due to aperture jitter. In any application, one is advised to test several units of the same device under the same conditions to evaluate the given applications sensitivity to that particular device. Figures 32 and 33 combine the dual tone SFDR as well as single tone SFDR and SNR performances at IF frequencies of 70 MHz, and 130 MHz. Note, the SFDR vs. amplitude data is referenced to dBFS while the single tone SNR data is referenced to dBc. The performance characteristics in these figures are representative of the AD9203 without any preceding gain stage. The AD9203 was operated in the differential mode (via transformer) with a 2 V span and a sample rate of 40 MSPS. The analog supply (AVDD) and the digital supply (DRVDD) were set to 3.0 V. 90 SFDR 2 TONE 80 70 SNR/SFDR – dB DIRECT IF DOWN CONVERSION USING THE AD9203 SFDR 1 TONE 60 50 SNR 40 30 20 10 0 0 5 10 15 20 25 INPUT POWER LEVEL – dB FULL SCALE 30 Figure 32. SNR/SFDR for IF @ 70 MHz (Clock = 40 MSPS) 80 SFDR 2 TONE 70 60 SFDR 1 TONE SNR/SFDR – dB APPLICATIONS 50 40 SNR 30 20 10 0 0 5 10 15 20 25 30 INPUT POWER LEVEL – dB FULL SCALE 35 Figure 33. SNR/SFDR for IF @ 130 MHz (Clock = 40 MSPS) –15– AD9203 The 74 mW power consumption gives the 40 MSPS AD9203 an order of magnitude improvement over older generation components. ULTRASOUND APPLICATIONS The AD9203 provides excellent performance in 10-bit ultrasound applications. This is demonstrated by its high SNR with analog input frequencies up to and including Nyquist. The presence of spurs near the base of a fundamental frequency bin is demonstrated by Figure 35. Note that the spurs near the noise floor are more than 80 dB below fIN. This is especially valuable in Doppler ultrasound applications where low frequency shifts from the fundamental are important. 10 FUND 0 SNR = 59.9dB THD = –75dB SFDR = 82dB –10 –20 –30 –40 dB CONDITIONED TRANSDUCER SIGNAL ANALOG INPUT SINGLEENDED ANALOG +3V –60 AD9203 –70 AINP AD604 TGC AMPLIFIER –50 –80 AD8138 –90 AINN –100 GAIN CONTROL –110 4.5E+6 4.7E+6 4.9E+6 5.1E+6 5.3E+6 5.5E+6 FIN 1.5V Figure 35. SFDR Performance Near the Fundamental Signal (8192 Point FFT, fIN = 5 MHz, F S = 40 MSPS) +3V Figure 34. Ultrasound Connection for the AD9203 EVALUATION BOARD Figure 34 illustrates the AD604 variable gain amplifier configured for time gain compensation (TGC). The low power AD9203 is powered from a 3 V supply rail while the high performance AD604 is powered from 5 V supply rails. An AD8138 is used to drive the AD9203. This is implemented due to the ability of differential drive techniques to cancel common mode noise and input anomalies. +3V + +3V – DRVDD SYNTHESIZER 1MHz 1.9V p-p HP8644 ANTIALIASING FILTER The AD9203 evaluation board is shipped wired for 2 V differential operation. The board should be connected to power and test equipment as shown in Figure 36. It is easily configured for single ended and differential operation as well as 1 V and 2 V spans. Refer to schematic on next page. – GND J1 ANALOG INPUT +3V + + +3-5d AVDD +3V – GND AD9203 EVALUATION BOARD SYNTHESIZER 40MHz 1V p-p HP8644 + – AVEE OUTPUT WORD DSP EQUIPMENT J5 EXTERNAL CLOCK Figure 36. Evaluation Board Connection –16– REV. 0 REV. 0 J1 Figure 37. Evaluation Board (Rev. C) –17– 2 1 R36 4.99kV C30 0.1mF R34 2kV R4 49.9V R1 49.9V 2 3 A 1 SW8 B R35 4.99V J4 2 1 J5 1 JP8 2 2 1 B C2 4.7mF 10V C1 0.1mF TP2 3 1 A SW7 2 AVDD 1 4 2 JP52 2 JP26 6 4 P 74LVX14 TPB 1 2 74LVX14 U6 U6 R53 49.9V 3 1 6 C4 0.1mF 1 2 3 1 JP65 2 R54 200kV C6 0.1mF 1 JP3 2 C12 0.1mF C11 0.1mF 10V C9 1mF 2 1+ AVDD C5 10mF 10V C3 0.1mF C10 0.1mF TP1 1 A SW6 2 3 B 1 JP64 2 R52 49.9V 74LVX14 U6 R2 100V S T1 5 TP12 R51 49.9V R103 10V R104 10V 1 JP54 JP53 2 2 B A C34 0.1mF 74LVX14 R101 TBD BY USER 1 8 74LVX14 U6 13 12 R102 TBD BY USER CLK U6 74LVX14 U6 11 10 9 TP3 1 JP1 2 1 JP2 2 AVDD 1 JP58 2 2 C100 20pF AVDD JP63 C33 10mF 10V 1 U6 BYPASS C102 0.1mF AVDD JP50 15 16 17 19 21 22 23 24 25 26 20 1 U1 AVSS 1 DRVSS R55 TBD BY USER 27 DFS REFSENSE AD9203 13 C18 10mF 10V 18 14 2 2 C19 0.1mF JP51 3 D0 4 D1 5 D2 6 D3 7 D4 8 D5 9 D6 10 D7 11 D8 12 D9 OTR 2 DRVDD 28 REFBF AINP AINN CLAMP IN 1 1 + AVDD CLK 3 STATE STBY CLAMP PWRCON REFTF VREF JP59 2 2 + 1 C17 10mF 10V C101 20pF 2 C16 0.1mF 1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 R56 JP60 JP61 2 2 TBD BY USER 1 1 OTR DRVDD AVDD AD9203 –18– 1 2 AGND3,4,5 1 J12 B4 1 TP4 TP20 R113 50V C7 33mF 16V L4 1 10mF 10V + C23 L1 1 R112 25V R111 1V FBEAD 2 FBEAD 2 C14 0.1mF AVSS R105 TBD 1 8 B 4 1 3 TP21 B C45 0.1mF 33mF 16V + C25 L2 1 C26 10mF 10V A V+ AD8131 OUT 2 U3 V– A 6 C13 0.1mF 5 AVDD R106 TBD C8 0.1mF AVEE C22 0.1mF DRVDD B3 + + B2 R107 1kV C24 0.1mF AVDD 10mF 10V + C15 10mF 10V + C44 FBEAD 2 1 DRVDD R108 1kV DRVDD B1 TP29 C41 0.1mF D2 D1 D0 LSB11 LSB12 OTR CLK C40 0.1mF D9 D8 D7 D6 D5 D4 D3 10mF 10V + C31 L3 1 21 24 23 22 13 14 15 16 17 18 19 20 21 24 23 22 13 14 15 16 17 18 19 20 FBEAD 2 U4 U5 10 9 8 7 6 5 4 3 A8 1 VCCA 2 T/R 11 GD2 12 GD3 A1 A2 A3 A4 A5 A6 A7 74LVXC4245WM GD1 NC1 OE B8 VCCB B1 B2 B3 B4 B5 B6 B7 3 10 9 8 7 6 5 4 A8 1 VCCA 2 T/R 11 GD2 12 GD3 A1 A2 A3 A4 A5 A6 A7 74LVXC4245WM GD1 NC1 OE B8 VCCB B1 B2 B3 B4 B5 B6 B7 C32 0.1mF +3–5D B5 B6 1 1 TP23 C21 0.1mF +3–5D C20 0.1mF +3–5D TP24 TP25 TP26 TP27 RN2 7 22V 8 RN2 6 22V 9 RN2 5 22V 10 RN2 4 22V 11 RN2 3 22V 12 RN2 2 22V 13 RN2 1 22V 14 RN1 7 22V 8 RN1 6 22V 9 RN1 5 22V 10 RN1 4 22V 11 RN1 3 22V 12 RN1 2 22V 13 RN1 1 22V 14 TP28 39 37 35 33 P1 P1 P1 P1 P1 P1 31 P1 29 P1 25 27 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 23 21 19 17 15 13 11 9 7 5 3 1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 AD9203 Figure 38. Evaluation Board (Rev. C) REV. 0 AD9203 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C3596–2–7/99 28-Lead Thin Shrink Small Outline (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 14 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 88 08 0.028 (0.70) 0.020 (0.50) PRINTED IN U.S.A. SEATING PLANE 0.0433 (1.10) MAX REV. 0 –19–