AD AD8016ARB-EVAL Low power, high output current xdsl line driver Datasheet

a
FEATURES
xDSL Line Driver that Features Full ADSL CO (Central
Office) Performance on 12 V Supplies
Low Power Operation
5 V to 12 V Voltage Supply
12.5 mA/Amp (Typ) Total Supply Current
Power Reduced Keep Alive Current of 4.5 mA/Amp
High Output Voltage and Current Drive
IOUT = 600 mA
40 V p-p Differential Output Voltage RL = 50 ,
VS = 12 V
Low Single-Tone Distortion
–75 dBc @ 1 MHz SFDR, RL = 100 , V O = 2 V p-p
MTPR = –75 dBc, 26 kHz to 1.1 MHz, ZLINE = 100 ,
PLINE = 20.4 dBm
High Speed
78 MHz Bandwidth (–3 dB), G = +5
40 MHz Gain Flatness
1000 V/s Slew Rates
PRODUCT DESCRIPTION
The AD8016 high output current dual amplifier is designed
for the line drive interface in Digital Subscriber Line systems
such as ADSL, HDSL2, and proprietary xDSL systems. The
drivers are capable, in full-bias operation, of providing 24.4 dBm
output power into low resistance loads, enough to power a
20.4 dBm line, including hybrid insertion loss.
Low Power, High Output Current
xDSL Line Driver
AD8016
PIN CONFIGURATION
24-Lead Batwing
20-Lead PSOP3
(RB-24)
(RP-20)
+V1
1
20
+V2
+V1
1
24
VOUT1
2
19
VOUT2
VOUT1
2
23
VOUT2
VINN1
3
18
VINN2
VINN1
3
22
VINN2
VINP1
4
17
VINP2
NC
5
16
NC
NC
6
15
NC
NC
– +
+ –
AD8016
7
14
NC
PWDN0
8
DGND
9
12
BIAS
–V1
10
11
–V2
13
PWDN1
NC = NO CONNECT
– +
+ –
+V2
VINP1
4
21
VINP2
AGND
5
20
AGND
AGND
6
19
AGND
AGND
7
18
AGND
AGND
8
17
AGND
PWDN0
9
16
PWDN1
DGND
10
15
BIAS
–V1
11
14
–V2
NC
12
13
NC
AD8016
NC = NO CONNECT
28-Lead TSSOP-EP
(RE-28-1)
NC
1
28
NC
NC
2
27
NC
NC
3
26
NC
+VIN2
4
25
NC
–VIN2
5
24
PWDN1
VOUT2
6
23
BIAS
+V2
7
22
–V2
+V1
8
21
–V1
VOUT1
9
20
DGND
–VIN1
10
19
NC
+VIN1
11
18
PWDN0
NC
12
17
NC
NC
13
16
NC
NC
14
15
NC
AD8016ARE
10dB/DIV
NC = NO CONNECT
–75dBc
549.3 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3
FREQUENCY (kHz)
Figure 1. Multitone Power Ratio; VS = ± 12 V, 20.4 dBm
Output Power into 100 Ω, Downstream
The AD8016 is available in a low cost 24-lead SO-Batwing,
a thermally enhanced 20-lead PSOP3, and a 28-lead TSSOP-EP
with an exposed lead frame (ePAD). Operating from ±12 V
supplies, the AD8016 requires only 1.5 W of total power
dissipation (refer to the Power Dissipation section for details)
while driving 20.4 dBm of power downstream using the
xDSL hybrid in Figure 33a and Figure 33b. Two digital bits
(PWDN0, PWDN1) allow the driver to be capable of full performance, an output keep-alive state, or two intermediate bias
states. The keep-alive state biases the output transistors enough
to provide a low impedance at the amplifier outputs for back
termination.
The low power dissipation, high output current, high output voltage
swing, flexible power-down, and robust thermal packaging enable
the AD8016 to be used as the Central Office (CO) terminal driver
in ADSL, HDSL2, VDSL, and proprietary xDSL systems.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
(@ 25C, VS = 12 V, RL = 100 , PWDN0, PWDN1 = (1, 1), TMIN = –40C,
MAX = +85C, unless otherwise noted.)
AD8016–SPECIFICATIONS T
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Peaking
Slew Rate
Rise and Fall Time
Settling Time
Input Overdrive Recovery Time
NOISE/DISTORTION PERFORMANCE
Distortion, Single-Ended
Second Harmonic
Third Harmonic
Multitone Power Ratio*
IMD
IP3
Voltage Noise (RTI)
Input Current Noise
Conditions
Min
G = +1, RF = 1.5 kΩ, VOUT = 0.2 V p-p
G = +5, RF = 499 Ω, VOUT < 0.5 V p-p
G = +5, RF = 499 Ω, VOUT = 0.2 V p-p
VOUT = 4 V p-p
VOUT = 0.2 V p-p < 50 MHz
VOUT = 4 V p-p, G = +2
VOUT = 2 V p-p
0.1%, VOUT = 2 V p-p
VOUT = 12.5 V p-p
VOUT = 2 V p-p, G = +5, RF = 499 Ω
fC = 1 MHz, RL = 100 Ω/25 Ω
fC = 1 MHz, RL = 100 Ω/25 Ω
26 kHz to 1.1 MHz, ZLINE = 100 Ω,
PLINE = 20.4 dBm
500 kHz, ∆f = 10 kHz, RL = 100 Ω/25 Ω
500 kHz, RL = 100 Ω/25 Ω
f = 10 kHz
f = 10 kHz
INPUT CHARACTERISTICS
RTI Offset Voltage
+Input Bias Current
–Input Bias Current
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
69
16
–75/–62
–88/–74
–84/–80
42/40
–3.0
–45
–75
–10
58
Single-Ended, RL = 100 Ω
G = 5, RL = 10 Ω, f1 = 100 kHz,
–60 dBc SFDR
400
Recovery Time
Shutdown Current
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
63
–40
Unit
MHz
MHz
MHz
MHz
dB
V/µs
ns
ns
ns
–77/–64
–93/–76
dBc
dBc
–75
–88/–85
43/41
2.6
18
dBc
dBc
dBm
nV/√Hz
pA√Hz
1.0
4
400
2
4.5
21
+3.0
+45
+75
+10
64
+11
600
2000
80
±3
PWDN1, PWDN0 = (1, 1)
PWDN1, PWDN0 = (1, 0)
PWDN1, PWDN0 = (0, 1)
PWDN1, PWDN0 = (0, 0)
To 95% of IQ
250 µA Out of Bias Pin
∆VS = ± 1 V
Max
380
78
38
90
0.1
1000
2
23
350
–11
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
Typ
12.5
8
5
4
25
1.5
75
mV
µA
µA
kΩ
pF
V
dB
V
mA
mA
pF
± 13
13.2
10
8
6
4.0
+85
V
mA/Amp
mA/Amp
mA/Amp
mA/Amp
µs
mA/Amp
dB
°C
*See Figure 43, R20, R21 = 0 Ω, R1 = open.
Specifications subject to change without notice.
–2–
REV. B
AD8016
SPECIFICATIONS
(@ 25C, VS = 6 V, RL = 100 , PWDN0, PWDN1 = (1, 1), TMIN = –40C,
TMAX = +85C, unless otherwise noted.)
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Peaking
Slew Rate
Rise and Fall Time
Settling Time
Input Overdrive Recovery Time
NOISE/DISTORTION PERFORMANCE
Distortion, Single-Ended
Second Harmonic
Third Harmonic
Multitone Power Ratio*
IMD
IP3
Voltage Noise (RTI)
Input Current Noise
Conditions
Min
G = +1, RF = 1.5 kΩ, VOUT = 0.2 V p-p
G = +5, RF = 499 Ω, VOUT < 0.5 V p-p
G = +5, RF = 499 Ω, VOUT = 0.2 V p-p
VOUT = 1 V rms
VOUT = 0.2 V p-p < 50 MHz
VOUT = 4 V p-p, G = +2
VOUT = 2 V p-p
0.1%, VOUT = 2 V p-p
VOUT = 6.5 V p-p
G = +5, VOUT = 2 V p-p, RF = 499 Ω
fC = 1 MHz, RL = 100 Ω/25 Ω
fC = 1 MHz, RL = 100 Ω/25 Ω
26 kHz to 138 kHz, ZLINE = 100 Ω,
PLINE = 13 dBm
500 kHz, ∆f = 110 kHz, RL = 100 Ω/25 Ω
500 kHz
f = 10 kHz
f = 10 kHz
INPUT CHARACTERISTICS
RTI Offset Voltage
+Input Bias Current
–Input Bias Current
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Quiescent Current
Recovery Time
Shutdown Current
Power Supply Rejection Ratio
70
10
–73/61
–80/–68
–87/–82
42/39
–3.0
–25
–30
–4
60
Single-Ended, RL = 100 Ω
G = +5, RL = 5 Ω, f = 100 kHz,
–60 dBc SFDR
Typ
320
71
15
80
0.7
300
2
39
350
–68
–88/–83
42/39
4
17
dBc
dBc
dBm
nV/√Hz
pA√Hz
0.2
10
10
400
2
5
20
+3.0
+25
+30
+4
66
+5
RS = 10 Ω
PWDN1, PWDN0 = (1, 1)
PWDN1, PWDN0 = (1, 0)
PWDN1, PWDN0 = (0, 1)
PWDN1, PWDN0 = (0, 0)
To 95% of IQ
250 µA Out of Bias Pin
∆VS = ± 1 V
8
6
4
3
23
1.0
80
OPERATING TEMPERATURE RANGE
1.0
MHz
MHz
MHz
MHz
dB
V/µs
ns
ns
ns
dBc
dBc
420
830
50
63
Unit
–75/–63
–82/–70
–5
300
Max
–40
mV
µA
µA
kΩ
pF
V
dB
V
mA
mA
pF
9.7
6.9
5.0
4.1
2.0
+85
mA/Amp
mA/Amp
mA/Amp
mA/Amp
µs
mA/Amp
dB
°C
NOTES
*See Figure 43, R20, R21 = 0 Ω, R1 = open.
Specifications subject to change without notice.
LOGIC INPUTS (CMOS Compatible Logic)
(PWDN0, PWDN1, VCC = 12 V or 6 V; Full Temperature Range)
Parameter
Min
Logic 1 Voltage
Logic 0 Voltage
2.2
0
REV. B
–3–
Typ
Max
Unit
VCC
0.8
V
V
AD8016
ABSOLUTE MAXIMUM RATINGS 1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V
Internal Power Dissipation
PSOP3 Package2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 W
SO-Batwing Package3 . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 W
TSSOP-EP Package4 . . . . . . . . . . . . . . . . . . . . . . . . 1.4 W
Input Voltage (Common-Mode) . . . . . . . . . . . . . . . . . . . . ± VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . ± VS
Output Short-Circuit Duration
. . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
The maximum power that can be safely dissipated by the AD8016
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
device is determined by the glass transition temperature of the
plastic, approximately 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package.
The output stage of the AD8016 is designed for maximum load
current capability. As a result, shorting the output to common
can cause the AD8016 to source or sink 2000 mA. To ensure
proper operation, it is necessary to observe the maximum power
derating curves. Direct connection of the output to either power
supply rail can destroy the device.
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device on a 4-layer board with 10 inches 2 of 1 oz. copper at 85°C
20-lead PSOP3 package: θJA = 18°C/W.
3
Specification is for device on a 4-layer board with 10 inches 2 of 1 oz. copper at 85°C
24-lead Batwing package: θJA = 28°C/W.
4
Specification is for device on a 4-layer board with 9 inches 2 of 1 oz. copper at 85°C
28-lead (TSSOP-EP) package: θJA = 29°C/W.
MAXIMUM POWER DISSIPATION (W)
8
7
6
PSOP3
5
4
SO-BATWING
3
TSSOP-EP
2
1
0
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE (C)
80
90
Figure 2. Maximum Power Dissipation vs.
Temperature for AD8016 for TJ = 125°C
ORDERING GUIDE
Model
AD8016ARP
AD8016ARP-REEL
AD8016ARP-EVAL
AD8016ARB
AD8016ARB-REEL
AD8016ARB-EVAL
AD8016ARE
AD8016ARE-REEL
AD8016ARE-REEL7
AD8016ARE-EVAL
Temperature
Range
Package
Description
Package
Option
–40°C to +85°C
–40°C to +85°C
20-Lead PSOP3
20-Lead PSOP3
Evaluation Board
24-Lead SO-Batwing
24-Lead SO-Batwing
Evaluation Board
28-Lead TSSOP-EP
28-Lead TSSOP-EP
28-Lead TSSOP-EP
Evaluation Board
RP-20A
RP-20A
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
RB-24
RB-24
RE-28-1
RE-28-1
RE-28-1
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8016 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REV. B
Typical Performance Characteristics– AD8016
10F
124
+VS
499
+
0.1F
VOUT
RL
+VIN
+VO
49.9
VIN
499
49.9
+VS
0.1F
+
10F
0.1F
+
10F
111
499
0.1F
–VIN
–VS
10F
+
Figure 6. Differential Test Circuit; G = +10
Figure 3. Single-Ended Test Circuit; G = +5
VOUT = 100mV
VOUT = 100mV
VOLTS
VOLTS
–VO
49.9
–VS
VIN = 20mV
VIN = 20mV
TIME (100ns/DIV)
TIME (100ns/DIV)
Figure 7. 100 mV Step Response; G = +5, VS = ± 12 V,
RL = 25 Ω, Single-Ended
Figure 4. 100 mV Step Response; G = +5, VS = ± 6 V,
RL = 25 Ω, Single-Ended
VOUT = 5V
VOLTS
VOLTS
VOUT = 4V
VIN = 800mV
VIN = 800mV
TIME (100ns/DIV)
TIME (100ns/DIV)
Figure 5. 4 V Step Response; G = +5, VS = ± 6 V,
RL = 25 Ω, Single-Ended
REV. B
RL
Figure 8. 4 V Step Response; G = +5, VS = ± 12 V,
RL = 25 Ω, Single-Ended
–5–
AD8016
–30
–30
–40
DISTORTION (dBc)
(1,0)
–60
–70
–80
PWDN1, PWDN0 = (1,1)
–60
PWDN1, PWDN0 = (1,1)
–80
–90
–100
–100
0.1
1
FREQUENCY (MHz)
10
–110
0.01
20
Figure 9. Distortion vs. Frequency; Second Harmonic,
VS = ± 12 V, RL = 50 Ω, Differential
–30
DISTORTION (dBc)
DISTORTION (dBc)
–60
–70
–80
PWDN1, PWDN0 = (1,1)
PWDN1, PWDN0 = (1,1)
–80
–100
–100
–110
0.01
20
Figure 10. Distortion vs. Frequency; Second Harmonic,
VS = ± 6 V, RL = 50 Ω, Different
(1,0)
–70
–90
10
(0,1)
–60
–90
0.1
10
1
FREQUENCY (MHz)
20
Figure 13. Distortion vs. Frequency; Third Harmonic,
VS = ± 6 V, RL = 50 Ω, Differential
–30
–30
RF = 499
G = +5
–35
RF = 499
G = +5
–40
–40
(1,0)
(0,0)
–45
DISTORTION (dBc)
DISTORTION (dBc)
20
(0,0)
–50
(1,0)
1
FREQUENCY (MHz)
RF = 499
G = +10
VO = 4V p-p
–40
(0,1)
0.1
10
1
FREQUENCY (MHz)
–30
–50
–110
0.01
0.1
Figure 12. Distortion vs. Frequency; Third Harmonic,
VS = ± 12 V, RL = 50 Ω, Differential
(0,0)
RF = 499
G = +10
VO = 4V p-p
(1,0)
–70
–90
–110
0.01
(0,1)
–50
(0,1)
–40
RF = 499
G = +10
VO = 4V p-p
–40
–50
DISTORTION (dBc)
(0,0)
(0,0)
RF = 499
G = +10
VO = 4V p-p
–50
–55
(0,0)
(0,1)
(1,0)
–60
–65
–70
–50
(0,1)
–60
–70
–80
PWDN1, PWDN0 = (1,1)
–75
–80
0
100
200
300
400
500
600
PEAK OUTPUT CURRENT (mA)
700
–90
800
Figure 11. Distortion vs. Peak Output Current; Second
Harmonic, VS = ± 12 V, RL = 10 Ω, f = 100 kHz, Single-Ended
PWDN1,
PWDN0 = (1,1)
0
100
300
400
500
200
PEAK OUTPUT CURRENT (mA)
600
700
Figure 14. Distortion vs. Peak Output Current, Third
Harmonic; VS = ± 12 V, RL = 10 Ω, G = +5, f = 100 kHz,
Single-Ended
–6–
REV. B
AD8016
–30
–30
RF = 499
G = +5
–35
–40
–40
–45
–45
DISTORTION (dBc)
DISTORTION (dBc)
–35
(0,0)
–50
(0,1)
–55
(1,0)
–60
–65
–50
(0,0)
–55
(0,1)
–60
(1,0)
–65
–70
–70
–75
–75
PWDN1, PWDN0 = (1,1)
PWDN1, PWDN0 = (1,1)
–80
–80
0
100
300
400
200
PEAK OUTPUT CURRENT (mA)
500
600
0
–30
–30
–40
–40
–50
–50
(0,0)
–60
(0,1)
–70
200
300
400
PEAK OUTPUT CURRENT (mA)
500
600
Figure 18. Distortion vs. Peak Output Current; Third
Harmonic, VS = ± 6 V, G = +5, RL = 5 Ω, f = 100 kHz,
Single-Ended
DISTORTION (dBc)
DISTORTION (dBc)
Figure 15. Distortion vs. Peak Output Current; Second
Harmonic, VS = ± 6 V, RL = 5 Ω, f = 100 kHz, Single-Ended
100
(1,0)
–80
(0,0)
(0,1)
–60
(1,0)
–70
–80
PWDN1, PWDN0 = (1,1)
PWDN1, PWDN0 = (1,1)
–90
–90
–100
0
5
10
15
20
25
30
DIFFERENTIAL OUTPUT (V p-p)
35
–100
40
0
Figure 16. Distortion vs. Output Voltage; Second
Harmonic, VS = ± 12 V, G = +10, f = 1 MHz, RL = 50 Ω,
Differential
5
10
15
20
25
30
DIFFERENTIAL OUTPUT (V p-p)
35
40
Figure 19. Distortion vs. Output Voltage; Third
Harmonic, VS = ± 12 V, G = +10, f = 1 MHz, RL = 50 Ω,
Differential
–30
–30
–40
–40
DISTORTION (dBc)
DISTORTION (dBc)
(0,0)
–50
–60
(0,0)
(0,1)
–70
–50
(0,1)
–60
(1,0)
–70
(1,0)
–80
PWDN1, PWDN0 = (1,1)
–80
PWDN1, PWDN0 = (1,1)
–90
–90
0
10
5
15
DIFFERENTIAL OUTPUT (V p-p)
0
20
Figure 17. Distortion vs. Output Voltage; Second
Harmonic, VS = ± 6 V, G = +10, f = 1 MHz, RL = 50 Ω,
Differential
REV. B
5
10
15
DIFFERENTIAL OUTPUT (V p-p)
20
Figure 20. Distortion vs. Output Voltage, Third Harmonic,
VS = ± 6 V, G = +10, f = 1 MHz, RL = 50 Ω, Differential
–7–
AD8016
6
NORMALIZED FREQUENCY RESPONSE (dB)
NORMALIZED FREQUENCY RESPONSE (dB)
3
0
–3
1,1
VIN = 40mV p-p
G = +5
RL = 100
–6
–9
1,0
–12
0,1
–15
–18
0,0
–21
–24
10
FREQUENCY (MHz)
100
500
Figure 21. Frequency Response; VS = ± 12 V,
@ PWDN1, PWDN0 Codes
–6
–9
1,0
–12
0,1
–15
–18
0,0
–21
10
FREQUENCY (MHz)
100
500
G = +5
RL = 100
RF = 499
8
OUTPUT VOLTAGE (dBV)
5
2
–1
–4
–7
–10
2
–1
–4
–7
–10
–13
–13
–16
–16
–19
VIN = 40mV p-p
G = +5
RL = 100
11
G = +5
RL = 100
RF = 499
5
OUTPUT VOLTAGE (dBV)
1,1
Figure 24. Frequency Response; VS = ± 6 V,
@ PWDN1, PWDN0 Codes
11
8
0
–3
–24
1
–27
1
3
1
10
FREQUENCY (MHz)
–19
500
100
Figure 22. Output Voltage vs. Frequency; VS = ± 12 V
0
10
FREQUENCY (MHz)
100
500
Figure 25. Output Voltage vs. Frequency; VS = ± 6 V
–10
20
10
1
RF = 499
VIN = 2V rms
RF = 602
–20
1,1
1,0
–30
+PSRR
–20
–30
PSRR (dB)
CMRR (dB)
–10
0,1
–40
–40
–50
–PSRR
–60
0,0
–50
–70
–60
–80
–70
–80
0.03
0.1
1
10
FREQUENCY (MHz)
100
–90
0.01
500
0.1
1
10
FREQUENCY (MHz)
100
500
Figure 26. PSRR vs. Frequency; VS = ± 12 V
Figure 23. CMRR vs. Frequency; VS = ± 12 V
@ PWDN1, PWDN0 Codes
–8–
REV. B
90
10M
360
160
80
100k
320
140
70
10k
280
120
60
100
50
40
60
30
+I NOISE
40
20
VIN NOISE
TRANSIMPEDANCE (k)
80
10
20
0
10
100k
1k
10k
FREQUENCY (MHz)
100
80
0.01
40
–2mV
(–0.1%)
VOUT –VIN
VOUT
5
10
15 20 25
TIME (ns)
30
35
40
100
1000
0
10000
0
–2mV
(–0.1%)
VIN
VOUT
0
5
VOUT –VIN
10
15 20 25
TIME (ns)
30
35
40
45
Figure 31. Settling Time 0.1%; VS = ± 6 V
1000
VOUT = 2V p-p
RF = 499
G = +5
RL = 100
100
OUTPUT IMPEDANCE ()
CROSSTALK (dB)
0.1
1
10
FREQUENCY (MHz)
+2mV
(–0.1%)
–5
–20
–40
0.01
G = +2
RF = 1k
VOUT = 2VSTEP
RL = 100
45
Figure 28. Settling Time 0.1%; VS = ± 12 V
–30
0.001
Figure 30. Open-Loop Transimpedance and Phase
vs. Frequency
0
0
120
0.1
+2mV
(–0.1%)
–5
160
1
OUTPUT VOLTAGE ERROR (2mV/DIV (0.1%/DIV))
OUTPUT VOLTAGE ERROR (2mV/DIV (0.1%/DIV))
10
G = +2
RF = 1k
VOUT = 2VSTEP
RL = 100
VIN
200
TRANSIMPEDANCE
0
0.0001
Figure 27. Noise vs. Frequency
240
100
0
10M
1M
PHASE
1k
–50
–60
–70
0,0
0,1
10
1,0
1
1,1
0.1
–80
–90
0.03
0.1
1
10
FREQUENCY (MHz)
100
0.01
0.03
500
1
10
FREQUENCY (MHz)
100
500
Figure 32. Output Impedance vs. Frequency
@ PWDN1, PWDN0 Codes
Figure 29. Output Crosstalk vs. Frequency
REV. B
0.1
–9–
PHASE (Degrees)
180
INPUT VOLTAGE NOISE (nV/ Hz)
+ INPUT CURRENT NOISE (pA/ Hz)
AD8016
AD8016
18
VIN = 2V/DIV
VOUT = 5V/DIV
16
PWDN1, PWDN0 = (1,1)
VOUT
14
12
IQ (mA)
[1,0]
0V
VIN
10
[0,1]
8
6
[0,0]
4
0V
2
–100
0
100
200
300 400 500
TIME (ns)
600
700
800
0
900
Figure 33a. Overload Recovery; VS = ± 12 V,
G = +5, RL = 100 Ω
0
50
100
IBIAS (A)
150
200
Figure 35. IQ vs. IBIAS Current; VS = ± 6 V
12
+VOUT, VS = 12V
8
VIN = 2V/DIV
VOUT = 5V/DIV
OUTPUT SWING (V)
+VOUT, VS = 6V
0V
VOUT
0V
4
0
–4
VIN
–VOUT, VS = 6V
–8
–VOUT, VS = 12V
–12
10
–100
0
100
200
300 400 500
TIME (ns)
600
700
800
100
1k
10k
RLOAD ()
900
Figure 36. Output Voltage vs. RLOAD
Figure 33b. Overload Recovery; VS = ± 12 V,
G = +5, RL = 100 Ω
25
PWDN1, PWDN0 = (1,1)
20
[1,0]
IQ (mA)
15
[0,1]
10
[0,0]
5
0
0
50
100
IBIAS (A)
150
200
Figure 34. IQ vs. IBIAS Current; VS = ± 12 V
–10–
REV. B
AD8016
THEORY OF OPERATION
FEEDBACK RESISTOR SELECTION
The AD8016 is a current feedback amplifier with high (500 mA)
output current capability. With a current feedback amplifier, the
current into the inverting input is the feedback signal and the
open-loop behavior is that of a transimpedance, dVO/dIIN or TZ.
The open-loop transimpedance is analogous to the open-loop
voltage gain of a voltage feedback amplifier. Figure 37 shows a
simplified model of a current feedback amplifier. Since RIN is
proportional to 1/gm, the equivalent voltage gain is just TZ × gm,
where gm is the transconductance of the input stage. Basic
analysis of the follower with gain circuit yields
In current feedback amplifiers, selection of feedback and gain
resistors has an impact on the MTPR performance, bandwidth,
and gain flatness. Care should be taken in selecting these resistors so that optimum performance is achieved. The table below
shows the recommended resistor values for use in a variety of
gain settings. These values are suggested as a good starting
point when designing for any application.
VO
VIN
=G×
Table I. Resistor Selection Guide
TZ ( S )
TZ ( S ) + G × RIN + RF
where:
G =1+
RIN =
1
RF
RG
Recognizing that G × RIN << RF for low gains, the familiar
result of constant bandwidth with gain for current feedback
amplifiers is evident, the 3 dB point being set when |TZ| = RF.
Of course, for a real amplifier there are additional poles that
contribute excess phase and there is a value for RF below which
the amplifier is unstable. Tolerance for peaking and desired flatness
determines the optimum RF in each application.
RF
RG
–
RIN
IIN
RN
1000
500
650
750
1000
∞
500
650
187
111
Table II. PWDN Code Selection Guide
VOUT
+
VIN
Figure 37. Simplified Block Diagram
The AD8016 is the first current feedback amplifier capable of
delivering 400 mA of output current while swinging to within
2 V of either power supply rail. This enables full CO ADSL
performance on only 12 V rails, an immediate 20% power saving.
The AD8016 is also unique in that it has a power management
system included on-chip. It features four user programmable
power levels (all of which provide a low output impedance of the
driver), as well as the provision for complete shutdown (high
impedance state). Also featured is a thermal shutdown with
alarm signal.
PWDN1
Code
PWDN0
Code
1
1
0
0
X
1
0
1
0
X
Quiescent Bias Level
100% (Full ON)
60%
40%
25% (Low ZOUT but Not OFF)
Full OFF (High ZOUT via 250 µA
Pulled Out of BIAS Pin)
The bias level can be controlled with TTL logic levels (High = 1)
applied to the PWDN1 and PWDN0 pins alone or in combination with the BIAS control pin. The DGND or digital ground
pin is the logic ground reference for the PWDN1 and PWDN0
pins. In typical ADSL applications where ± 12 V or ± 6 V
supplies (also single supplies) are used, the DGND pin is
connected to analog ground.
POWER SUPPLY AND DECOUPLING
The AD8016 should be powered with a good quality (i.e., low
noise) dual supply of ± 12 V for the best distortion and multitone
power ratio (MTPR) performance. Careful attention must be
paid to decoupling the power supply pins. A 10 µF capacitor
located in near proximity to the AD8016 is required to provide good decoupling for lower frequency signals. In addition,
0.1 µF decoupling capacitors should be located as close to
each of the four power supply pins as is physically possible.
All ground pins should be connected to a common low impedance ground plane.
REV. B
+1
–1
+2
+5
+10
RG ()
The AD8016 is designed to cover both CO (central office) and
CPE (customer premise equipment) ends of an xDSL application. It offers full versatility in setting quiescent bias levels for
the particular application from full ON to reduced bias (in three
steps) to full OFF (via BIAS pin). This versatility gives the
modem designer the flexibility to maximize efficiency while
maintaining reasonable levels of multitone power ratio (MTPR)
performance. Optimizing driver efficiency while delivering the
required DMT power is accomplished with the AD8016 through
the use of on-chip power management features. Two digitally
programmable logic pins, PWDN1 and PWDN0, may be used
to select four different bias levels: 100%, 60%, 40%, and 25%
of full quiescent power (see Table II).
+
TZ
RF ()
BIAS PIN AND PWDN FEATURES
≈ 25 Ω
gm
Gain
The BIAS control pin by itself is a means to continuously adjust
the AD8016 internal biasing and thus quiescent current IQ. By
pulling out a current of 0 µA (or open) to approximately 200 µA,
the quiescent current can be adjusted from 100% (full ON) to a
full OFF condition. The full OFF condition yields a high output
impedance. Because of an on-chip resistor variation of up to
± 20%, the actual amount of current required to fully shut down
the AD8016 can vary. To institute a full chip shutdown, a pulldown current of 250 µA is recommended. See Figure 38 for the
logic drive circuit for complete amplifier shutdown. Figures 34
and 35 show the relationship between current pulled out of the
–11–
AD8016
BIAS pin (IBIAS) and the supply current (IQ). A typical shutdown IQ is less than 1 mA total. Alternatively, an external pulldown resistor to ground or a current sink attached to the BIAS
pin can be used to set IQ to lower levels (see Figure 39). The
BIAS pin may be used in combination with the PWDN1 and
PWDN0 pins; however, diminished MTPR performance may
result when IQ is lowered too much. Current pulled away from
the BIAS pin shunts away a portion of the internal bias current.
Setting PWDN1 or PWDN0 to Logic 0 also shunts away a
portion of the internal bias current. The reduction of quiescent
bias levels due to the use of PWDN1 and PWDN0 is consistent
with the percentages established in Table II. When PWDN0 alone
is set to Logic 0, and no other means of reducing the internal
bias currents is used, full-rate ADSL signals may be driven while
maintaining reasonable levels of MTPR.
3.3V LOGIC
APPLICATIONS
The AD8016ARP and AD8016ARB dual xDSL line driver
amplifiers are the most efficient xDSL line drivers available on
the market today. The AD8016 may be applied in driving modulated signals including discrete multitone (DMT) in either
direction; upstream from CPE to the CO and downstream from
CO to CPE. The most significant thermal management challenge lies in driving downstream information from CO sites to
the CPE. Driving xDSL information downstream suggests the
need to locate many xDSL modems in a single CO site. The
implication is that several modems will be placed onto a single
printed circuit board residing in a card cage located in a variety
of ambient conditions. Environmental conditioners such as fans
or air conditioning may or may not be available, depending on
the density of modems and the facilities contained at the CO site.
To achieve long-term reliability and consistent modem performance, designers of CO solutions must consider the wide array
of ambient conditions that exist within various CO sites.
R1*
R2
50k
BIAS
2N3904
MULTITONE POWER RATIO OR MTPR
*R1 = 47k FOR 12VS OR +12VS,
R1 = 22k FOR 6VS.
Figure 38. Logic Drive of BIAS Pin for
Complete Amplifier Shutdown
THERMAL SHUTDOWN
The AD8016ARB and AD8016ARP have been designed to
incorporate shutdown protection against accidental thermal
overload. In the event of thermal overload, the AD8016 was
designed to shut down at a junction temperature of 165°C and
return to normal operation at a junction temperature 140°C.
The AD8016 continues to operate, cycling on and off, as long as
the thermal overload condition remains. The frequency of the
protection cycle depends on the ambient environment, severity
of the thermal overload condition, the power being dissipated,
and the thermal mass of the PCB beneath the AD8016. When
the AD8016 begins to cycle due to thermal stress, the internal
shutdown circuitry draws current out of the node connected in
common with the BIAS pin, while the voltage at the BIAS pin
goes to the negative rail. When the junction temperature returns
to 140°C, current is no longer drawn from this node, and the
BIAS pin voltage returns to the positive rail. Under these circumstances, the BIAS pin can be used to trip an alarm indicating the presence of a thermal overload condition.
Figure 39 also shows three circuits for converting this signal to a
standard logic level.
VCC
AD8016
200A
V = VCC – 0.2V
10k
BIAS
SHUTDOWN
BIAS
PWDN0
OR
0A–200A
VEE
5V
PWDN1
VCC
10k
5V
10k
BIAS
1M
ALARM
OR
BIAS
100k
1/4 HCF 40109B
SGS–THOMSON
Figure 39. Shutdown and Alarm Circuit
ALARM
MIN 350
ADSL systems rely on discrete multitone modulation to carry
digital data over phone lines. DMT modulation appears in the
frequency domain as power contained in several individual
frequency subbands, sometimes referred to as tones or bins, each
of which is uniformly separated in frequency. (See Figure 1 for
an example of downstream DMT signals used in evaluating
MTPR performance.) A uniquely encoded, quadrature amplitude
modulation (QAM) signal occurs at the center frequency of
each subband or tone. Difficulties arise when decoding these
subbands if a QAM signal from one subband is corrupted by the
QAM signal(s) from other subbands, regardless of whether
the corruption comes from an adjacent subband or harmonics
of other subbands. Conventional methods of expressing the
output signal integrity of line drivers, such as spurious-free
dynamic range (SFDR), single-tone harmonic distortion or
THD, two-tone intermodulation distortion (IMD), and thirdorder intercept (IP3) become significantly less meaningful when
amplifiers are required to drive DMT and other heavily modulated
waveforms. A typical xDSL downstream DMT signal may
contain as many as 256 carriers (subbands or tones) of QAM
signals. MTPR is the relative difference between the measured power in a typical subband (at one tone or carrier)
versus the power at another subband specifically selected to
contain no QAM data. In other words, a selected subband (or
tone) remains open or void of intentional power (without a
QAM signal), yielding an empty frequency bin. MTPR, sometimes referred to as the empty bin test, is typically expressed
in dBc, similar to expressing the relative difference between
single-tone fundamentals and second or third harmonic distortion components.
See Figure 1 for a sample of the ADSL downstream spectrum
showing MTPR results while driving 20.4 dBm of power onto a
100 Ω line. Measurements of MTPR are typically made at the
output (line side) of ADSL hybrid circuits. (See Figure 46a for
an example of Analog Devices’ hybrid schematic.) MTPR can
be affected by the components contained in the hybrid circuit,
including the quality of the capacitor dielectrics, voltage ratings,
and the turns ratio of the selected transformers. Other components aside, an ADSL driver hybrid containing the AD8016 can be
optimized for the best MTPR performance by selecting the turns
ratio of the transformers. The voltage and current demands from
the differential driver changes, depending on the transformer
–12–
REV. B
AD8016
turns ratio. The point on the curve indicating maximum dynamic
headroom is achieved when the differential driver delivers both
the maximum voltage and current while maintaining the lowest
possible distortion. Below this point, the driver has reserve
current-driving capability and experiences voltage clipping.
Above this point, the amplifier runs out of current drive capability before the maximum voltage drive capability is reached.
Since a transformer reflects the secondary load impedance back
to the primary side by the square of the turns ratio, varying the
turns ratio changes the load across the differential driver. In the
transformer configuration of Figure 46a and 46b, the turns ratio
of the selected transformer is effectively doubled due to the
parallel wiring of the transformer primaries within this ADSL
driver hybrid. The following equation may be used to calculate
the load impedance across the output of the differential driver,
reflected by the transformers, from the line side of the xDSL
driver hybrid. Z' is the primary side impedance as seen by the
differential driver; Z2 is the line impedance and N is the transformer turns ratio.
Z' ≡
Z2
(2 × N )
2
Figure 40 shows the dynamic headroom in each subband of a
downstream DMT waveform versus turns ratio running at 100%
and 60% of the quiescent power while maintaining –65 dBc of
MTPR at VS = ± 12 V.
4
The AD8016ARP-EVAL, AD8016ARB-EVAL, AD8016AREEVAL boards available through Analog Devices provide a platform
for evaluating the AD8016 in an ADSL differential line driver
circuit. The board is laid out to accommodate Analog Devices’
two transformer line driver hybrid circuits (see Figures 46a
and 46b) including line matching network, an RJ11 jack for
interfacing to line simulators, transformer coupled input for
single-to-differential input conversion, and accommodations for
the receiver function. Schematics and layout information are
available for both versions of the evaluation board. Also included
in the package are WFM files for use in generating 14-bit
DMT waveforms. Upstream data is contained in the ...24.wfm
files and downstream data in the ...128.wfm files.
3
DYNAMIC HEADROOM (dB)
VS = 11.4V
PWDN1, PWDN0 = (1,1)
2
VS = 12V
PWDN1, PWDN0 = (1,0)
0
VS = 11.4V
PWDN1, PWDN0 = (1,0)
–1
–2
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
DOWNSTREAM TURNS RATIO
1.8
1.9
2.0
Figure 40. Dynamic Headroom vs. XFMR Turns Ratio,
VS = ± 12 V
Once an optimum turns ratio is determined, the amplifier has an
MTPR performance for each setting of the power-down pins.
The table below demonstrates the effects of reducing the total
power dissipated by using the PWDN pins on MTPR performance when driving 20.4 dBm downstream onto the line with a
transformer turns ratio of 1:1.4.
Table III. Dynamic Power Dissipation for
Downstream Transmission
PWDN0
PD (W)
MTPR
1
1
0
0*
1
0
1
0
1.454
1.262
1.142
0.120
–78 dBc
–75.3 dBc
–57.2 dBc
N/A
REV. B
These DMT modulated signals are used to evaluate xDSL
products for multitone power ratio or MTPR performance.
The data files are used in pairs (adslu24.wfm and adsll24.wfm
go together, etc.) and are loaded into a TEK AWG2021 arbitrary waveform generator. The adslu24.wfm is loaded via the
TEK AWG2021 floppy drive into Channel 1, while the
adsll24.wfm is simultaneously loaded into Channel 2. The number in the file name, prefixed with “u,” goes into CH1 or upper
channel and the “l” goes into CH2 or the lower channel. 12 bits
from CH1 are combined with 2 bits from CH2 to achieve 14-bit
digital data at the digital outputs of the TEK AWG2021. The
resulting waveforms produced at the AD9754-EB outputs are then
buffered and amplified by the AD8002 differential driver to achieve
14-bit performance from this DMT signal source.
POWER DISSIPATION
PWDN1
*This mode is quiescent power dissipation.
At this time, DMT modulated waveforms are not typically menuselectable items contained within arbitrary waveform generators.
Even using AWG software to generate DMT signals, AWGs that
are available today may not deliver DMT signals sufficient in
performance with regard to MTPR due to limitations in the D/A
converters and output drivers used by AWG manufacturers.
Similar to evaluating single-tone distortion performance of an
amplifier, MTPR evaluation requires a DMT signal generator
capable of delivering MTPR performance better than that of the
driver under evaluation. Generating DMT signals can be accomplished using a Tektronics AWG 2021 equipped with opt 4,
(12/24-Bit, TTL digital data out), digitally coupled to Analog
Devices AD9754, a 14-bit TxDAC®, buffered by an AD8002
amplifier configured as a differential driver. See Figure 45 for
schematics of a circuit used to generate DMT signals that can
achieve down to –80 dBc of MTPR performance, sufficient for
use in evaluating xDSL drivers. Note that the DMT waveforms
available with the AD8016ARP-EVAL and AD8016ARB-EVAL
boards or similar WFM files are needed to produce the necessary digital data required to drive the TxDAC from the optional
TTL digital data output of the TEK AWG2021. Copies of these
WFM files can be obtained through the Analog Devices website,
at www.analog.com.
EVALUATION BOARDS
VS = 12V
PWDN1, PWDN0 = (1,1)
1
GENERATING DMT
In order to properly size the heat sinking area for the user’s
application, it is important to consider the total power dissipation of the AD8016. The dc power dissipation for VIN = 0 is IQ
(VCC – VEE), or 2 × IQ × VS.
For the AD8016 powered on +12 V and –12 V supplies (± VS),
the number is 0.6 W. In a differential driver circuit (Figure 6),
–13–
AD8016
one can use symmetry to simplify the computation for a dc
input signal.
PD = 2 × IQ × VS + 4 × (VS – VO )
VO
RL
where:
VO is the peak output voltage of an amplifier.
This formula is slightly pessimistic due to the fact that some of
the quiescent supply current is commutated during sourcing or
sinking current into the load. For a sine wave source, integration
over a half cycle yields
2
4 V V
V 
O S
PD = 2 × IQ × VS + 2 
− O 
 π RL
RL 

The situation is more complicated with a complex modulated
signal. In the case of a DMT signal, taking the equivalent sine
wave power overestimates the power dissipation by ~23%. For
example:
POUT = 23.4 dBm = 220 mW
THERMAL TESTING
A wind tunnel study was conducted to determine the relationship
between thermal capacity (i.e., printed circuit board copper area),
air flow, and junction temperature. Junction-to-ambient thermal resistance, θJA, was also calculated for the AD8016ARP,
AD8016ARE, and AD8016ARB packages. The AD8016 was
operated in a noninverting differential driver configuration, typical
of an xDSL application yet isolated from any other modem
components. Testing was conducted using a 1 oz. copper
board in an ambient temperature of ~24°C over air flows of
200, 150, 100, and 50 (0.200 and 400 for AD8016ARE) linear
feet per minute (LFM) and for ARP and ARB packages as well
as in still air. The 4-layer PCB was designed to maximize the
area of copper on the outer two layers of the board, while the
inner layers were used to configure the AD8016 in a differential
driver circuit. The PCB measured 3 inches × 4 inches in the
beginning of the study and was progressively reduced in size
to approximately 2 × 2 inches. The testing was performed in a
wind tunnel to control air flow in units of LFM. The tunnel is
approximately 11 inches in diameter.
VOUT @ 50 Ω = 3.31 V rms
VO = 2.354 V
at each amplifier output, which yields a PD of 1.81 W.
Through measurement, a DMT signal of 23.4 dBm requires
1.47 W of power to be dissipated by the AD8016. Figure 41
shows the results of calculation and actual measurements
detailing the relationship between the power dissipated by the
AD8016 versus the total output power delivered to the back
termination resistors and the load combined. A 1:2 transformer
turns ratio was used in the calculations and measurements.
2.5
2.0
CALCULATED
POWER DISSIPATION
of the die, allowing more drive within the CO design. The
AD8016, whether in a PSOP3 (ARP) or SO-Batwing (ARB)
package, can be designed to operate in the CO solution using
prudent measures to manage the power dissipation through careful
PCB design. The PSOP3 package is available for use in designing the highest density CO solutions. Maximum heat transfer to
the PCB can be accomplished using the PSOP3 package when
the thermal slug is soldered to an exposed copper pad directly
beneath the AD8016. Optimum thermal performance can be
achieved in the ARE package only when the back of the package
is soldered to a PCB designed for maximum thermal capacity
(see Figure 44). Thermal experiments with the PS0P3 package
were conducted without soldering the heat slug to the PCB.
Heat transfer was through physical contact only. The following
offers some insight into the AD8016 power dissipation and
relative junction temperature, as well as the effects of PCB size
and composition on the junction-to-air thermal resistance or θJA.
1.5
MEASURED
SINE
AIR FLOW TEST CONDITIONS
DUT Power: Typical DSL DMT signal produces about 1.5 W
of power dissipation in the AD8016 package. The fully biased
(PWDN0 and PWDN1 = Logic 1) quiescent current of the
AD8016 is ~25 mA. A 1 MHz differential sine wave at an
amplitude of 8 V p-p/amplifier into an RLOAD of 100 Ω differential
(50 Ω per side) produces the 1.5 W of power typical in the
AD8016 device. (See the Power Dissipation section for details.)
MEASURED
DMT
1.0
0.5
0
0
100
200
OUTPUT POWER (mW)
300
Figure 41. Power Dissipation vs. Output Power (Including
Back Terminations), See Figure 7 for Test Circuit
THERMAL ENHANCEMENTS AND PCB LAYOUT
There are several ways to enhance the thermal capacity of the
CO solution. Additional thermal capacity can be created using
enhanced PCB layout techniques such as interlacing (sometimes
referred to as stitching or interconnection) of the layers immediately beneath the line driver. This technique serves to increase
the thermal mass or capacity of the PCB immediately beneath
the driver. (See AD8016-EVAL boards for an example of this
method of thermal enhancement.) A cooling fan that draws
moving air over the PCB and xDSL drivers, while not always
required, may be useful in reducing the operating temperature
Thermal Resistance: The junction-to-case thermal resistance
(θJC) of the AD8016ARB or SO-Batwing package is 8.6°C/W, for
the AD8016ARE or TSSOP-EP it is 5.6°C/W, and for the
AD8016ARP or PSOP3 package it is 0.86°C/W. These package
specifications were used in this study to determine junction
temperature based on the measured case temperature.
PCB Dimensions of a Differential Driver Circuit: Several
components are required to support the AD8016 in a differential
driver circuit. The PCB area necessary for these components (i.e.,
feedback and gain resistors, ac-coupling and decoupling capacitors, termination and load resistors) dictated the area of the
smallest PCB in this study, 4.7 square inches. Further reduction
in PCB area, although possible, has consequences in terms of
the maximum operating junction temperature.
–14–
REV. B
AD8016
EXPERIMENTAL RESULTS
35
Note that the AD8016ARE is targeted at xDSL applications
other than full-rate CO ADSL. The AD8016ARE is targeted at
g.lite and other xDSL applications where reduced power dissipation can be achieved through a reduction in output power.
Extreme temperatures associated with full-rate ADSL using the
AD8016ARE should be avoided whenever possible.
ARB 0 LFM
ARB 50 LFM
30
JA (C/W)
The experimental data suggests that for both packages, and a
PCB as small as 4.7 square inches, reasonable junction temperatures can be maintained even in the absence of air flow. The graph
in Figure 42 shows junction temperature versus air flow for various
dimensions of 1 oz. copper PCBs at an ambient temperature of
24°C in both the ARB and ARP packages. For the worst-case
package, the AD8016ARB and the worst-case PCB at 4.7 square
inches, the extrapolated junction temperature for an ambient
environment of 85°C would be approximately 132°C with 0 LFM
of air flow. If the target maximum junction temperature of the
AD8016ARB is 125°C, a 4-layer PCB with 1 oz. copper covering
the outer layers and measuring 9 square inches is required
with 0 LFM of air flow.
ARB 150 LFM
20
ARP 50 LFM
15
ARP 150 LFM
10
4
ARP 200 LFM
7
PCB AREA (SQ-IN)
10
Figure 43. Junction-to-Ambient Thermal Resistance vs.
PCB Area
50
+24C AMBIENT
40
ARB 6 SQ-IN
70
JA (C/W)
35
65
ARB 7.125 SQ-IN
60
ARB 9 SQ-IN
ARE 0 LFM
30
ARE 200 LFM
25
ARP 4.7 SQ-IN
ARE 400 LFM
55
20
ARP 6 SQ-IN
50
15
45
10
0
ARP 9 SQ-IN
ARP 12 SQ-IN
40
ARB 200 LFM
ARP 0 LFM
45
ARB 4.7 SQ-IN
JUNCTION TEMPERATURE (C)
25
ARP 100 LFM
75
0
50
100
AIR FLOW (LFM)
150
200
1
2
3
4
5
6
PCB AREA (SQ-IN)
7
8
9
10
Figure 44. Junction-to-Ambient Thermal Resistance vs.
PCB Area
Figure 42. Junction Temperature vs. Air Flow
REV. B
ARB 100 LFM
–15–
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
–16–
A
J4
A
J3
R1
OUT2
OUT1
R2
C13
22pF
C12
22pF
A
A
R5
C4
10F
TP4
B3
1F
R6
49.9
1F
A
A
10k
10k
226
AVEE
16
15
14
13
12
11
10
9
AVEE
0.1F
AD8002
750
750
AD8002
0.1F
1
2
3
4
5
6
7
A
A
16
15
14
13
12
11
10
16 PINDIP
RES PK
1
2
3
4
5
6
7
8
16 PINDIP
RES PK
TP5
TP18
TP19
B4
AVCC
C30
C31
C32
C33
C34
C35
C36
C19
C1
C2
C25
C26
C27
C28
C29
A
AGND
DVDD
1
2 3 4 5 6 7 8 9 10
AVDD
10 9 8 7 6 5 4 3 2
1
49.9
1
2 3 4 5 6 7 8 9 10
10 9 8 7 6 5 4 3 2
1
3
5
7
9
11
TO TEK 13
15
AWG
17
2021
19
21
23
25
27
29
31
33
35
37
39
P1
1
DVDD
TP2
TP3
C3
10F
B2
DGND
B1
DVDD
R3
C6
10F
TP7
B6
249
249
R4
A
A
R7
R8
DVDD
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
J1
2 3 4 5 6 7 8 9 10
EXTCLK
10 9 8 7 6 5 4 3 2
1
DVDD
A
DIFFERENTIAL
DMT OUTPUTS
1
2 3 4 5 6 7 8 9 10
A
AVCC
10 9 8 7 6 5 4 3 2
1
C5
10F
TP6
B5
A
TP12
A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
CLK
JP1
R17
49.9
CLOCK
DVDD
DCOM
NC
AVDD
COMP2
IOUTA
IOUTB
ACOM
COMP1
FS ADJ
REFIO
REFLO
SLEEP
CT1
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AD9754
U1
1
R15
49.9
TP1
PDIN
J2
A
3
B
JP2
A
3
2
1
AVDD
TP11
AVDD
C7
1F
A
A
JP4
TP14
R
20k
R16
2k
TP10
AVDD
C11
0.1F
C8
0.1F
TP9
OUT2
TP8
OUT1
C10
0.1F
AVDD
A
C9
0.1F
TP13
AD8016
Figure 45. DMT Signal Generator Schematic
REV. B
AD8016
TP10
TP5
AGND3,4,5
+VT
C8
1
R9
4
S5
R11
R13
R24
3
AD8016
11
2
1 A B 3
–VT
T3
6
P4 1
1:1
R18
R17
2
R23
9
R25
22
U1
R14
21
S6
R16
C10
TP4
1
R3
C6
7
R4
C7
1
10
TP16
2
8
3
9
4
1
2
3
4
5
6
C9
7
P1
NC = 5, 6
+V
AD8016
24
TP8
+VT
+VR;8
–VR;4
TP17
S3
C5
TP14
TP1
R21 C12
23
R2
T1
PR2
14
–V
C4
NC = 5, 6
–VT
AGND3,4,5
TP11
8
3
R19
JP5
R15
2
R1
5 WATT
2
NC = 5
P4 3
10
1
1
3
4
P4 2
1
4
JP6
TP15
T2
R20 C11
2
U1
–V
TP13
TP7 PR1
TP6
+V
7 8
TP2
TP9
3
U2
2
AD8022
P3 3
R6
P3 2
R5
R7
P3 1
TP18
AD8022
7
S4
6
U2
5
+VR;8
–VR;4
Figure 46a. Schematic AD8016ARB-EVAL
TP19
TP3
L5
TB2
TB2
+VR
1
BEAD
C21
0.1F
C23
0.1F
+ C3
10F
25V
C24
0.1F
C22
0.1F
P2
2
16
JP1
3
JP3
1
2
JP4
TP12
TP24
+VL
BEAD
–VR
–VT
+ C2
10F
25V
C20
0.1F
TP23
TP25
C18
0.1F
Figure 46b. Schematic AD8016ARB-EVAL
REV. B
+VR
–VR
BEAD
L2
TB3
PWDN1
JP2
+VT
TP22
TB3
PWDN0
–17–
TP26
TP27
TP28
TP29
TP30
AGND
1
AGND
3
P2
2
L3
TB2
+ C13
10F
25V
P2
U1
AD8016
DGND
5
TP21
L4
9
20
TP20
BIAS
19
10
R12
AGND
15
BEAD
18
+VL
NC
12
R22
–VT
3
13
CW
R10
NC
C25
0.1F
AGND
C16
0.1F
AGND
C19
0.1F
R9
17
+ C1
10F
25V
S2
AGND
C26
0.1F
8
C15
0.1F
AGND
C17
0.1F
2
L1
TB1
+ C14
10F
25V
7
BEAD
AGND
TB1
+VT
6
TB1
1
AD8016
LAYOUT AD8016ARB-EVAL
Figure 47. Assembly
Figure 50. Layer 1
Figure 48. Layer 1
Figure 51. Silkscreen Bottom
Figure 49. Power/Ground Plane
–18–
REV. B
AD8016
ALP – EVALUATION BOARD – BILL OF MATERIALS
Quantity
Description
Vendor
Ref Desc.
5
10
2
2
1
3
2
1
2
4
2
1
2
2
2
4
2
2
1
5
5
5
1
1
3
1
1
4
4
10 µF 25 V Size Tantalum Chip Capacitor
0.1 µF 50 V 1206 Size Ceramic Chip Capacitor
49.9 Ω 1% 1/8 W 1206 Size Chip Resistor
100 Ω 1% 1/8 W 1206 Size Chip Resistor
100 Ω 5% 3.0 W Metal Film Power Resistor
1.00 kΩ 1% 1/6 W 1206 Size Chip Resistor
10.0 kΩ 1% 1/6 W 1206 Size Chip Resistor
Test Point (Black) [GND]
Test Point (Brown)
Test Point (Red)
Test Point (Orange)
Test Point (Yellow)
Test Point (Green)
Test Point (Blue)
Test Point (Violet)
Test Point (Grey)
Test Point (White)
3 Green Terminal Block. ONSHORE# EDZ250/3
2 Green Terminal Block. ONSHORE# EDZ250/2
1 Inch Center Shunt Berg# 65474-001
Male Header. 1 Inch Center. Berg #69157-102
Conn. BNC Vert. MT Telegartner # J01001A1944
AMP# 555154-1 MOD. JACK (SHIELDED) 6 6
3-Pin Gold Male Header Waldom #WM 2723-ND
3-Pin Gold Male Locking Header Waldom #WM 2701-ND
AD8016 ARB
AD8016 SOIC REV. B Evaluation PC Board
No. 4 –40 × 1/4" Panhead SS Machine Screw
No. 4 –40 × 1/2" Threaded Alum. Standoffs
ADS# 4-7-2
ADS# 4-5-18
ADS# 3-14-26
ADS# 3-18-40
ADS# 3-24-1
ADS# 3-18-11
ADS# 3-18-119
ADS# 12-18-44
ADS# 12-18-59
ADS# 12-18-43
ADS# 12-18-60
ADS# 12-18-32
ADS# 12-18-61
ADS# 12-18-62
ADS# 12-18-63
ADS# 12-18-64
ADS# 12-18-42
ADS# 12-19-14
ADS# 12-19-13
ADS# 11-2-38
ADS# 11-2-37
ADS# 12-6-22
D–K# A 9024
D–K# WM 2723-ND
D–K# WM 2701-ND
ADS# AD 8016 XRP
SIERRA/PROTO EXPRESS
ADS# 30-1-1
ADS# 30-16-2
C1 to C3, C13, C14
C15 to C21, C24 to C26
R11, R15
R8, R14
R1
R17 to R19
R13 and R16
GND
TP10, TP11
TP17 to TP19, TP21
TP3, TP15, TP16
TP12
TP7, TP9
TP20, TP22
TP4, TP5
TP1, TP2, TP13, TP14
TP6, TP8
TB1, TB2
TB3
J1 to J5
J1 to J5
S2 to S6
P1
JP6
P2 to P4
DUT
Eval PC Board
OPTION
2
1:1.4 Turns Ratio RF Transformer from CoEv
C1374 Rev. 2
T1, T2
OUTLINE DIMENSIONS
24-Lead Batwing SOIC, Thermally Enhanced w/Fused Leads [SOIC/W/BAT]
(RB-24)
Dimensions shown in millimeters
15.60
15.20
24
13
7.60
7.40
1
10.65
10.00
12
PIN 1
0.75
45
0.25
2.65
2.35
0.30
0.10
1.27
BSC
0.51
0.31
SEATING
PLANE
0.33
0.20
8
0
COMPLIANT WITH JEDEC STANDARDS MS-013AD
REV. B
–19–
1.27
0.40
AD8016
OUTLINE DIMENSIONS
20-Lead Power SOIC, Thermally Enhanced Package [PSOP3]
(RP-20A)
Dimensions shown in millimeters
C01019–0–11/03(B)
13.00
9.00
1.10 MAX 45
1
10
PIN 1
11.00
BSC
11
BOTTOM VIEW
20
1.10 MAX
2 PLACES
15.90
BSC
3.60
3.35
3.10
SEATING
PLANE
6.20
5.80
14.20
BSC
TOP VIEW
SIDE VIEW
1.00
0.90
0.80
8
0
0.53
0.40
1.27
BSC
2.90 MAX
2 PLACES
3.30
3.15
3.00
VIEW A
END VIEW
1.10
0.80
VIEW A
3.60
3.35
3.10
0.10
0.05
0.00
0.30
0.20
0.10
0.32
0.23
COMPLIANT TO JEDEC STANDARDS MO-166AA
28-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP-EP]
(RE-28-1)
Dimensions shown in millimeters
9.80
9.70
9.60
BOTTOM
VIEW
28
15
4.50
4.40
4.30
1
EXPOSED
PAD
(Pins Down)
6.40
BSC
3.00
BSC
14
PIN 1
0.65
BSC
1.20
MAX
0.15
0.00
0.30
0.19
3.50
BSC
1.05
1.00
0.80
SEATING
PLANE
0.20
0.09
8
0
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153AET
Revision History
Location
Page
11/03—Data Sheet changed from REV. A to REV. B.
Changes to ORDERING GUIDE ....................................................................................................................................................4
Changes to TPC 21 .........................................................................................................................................................................8
Updated OUTLINE DIMENSIONS........................................................................................................................................19-20
–20–
REV. B