Cypress CY7C1356B-166AC 9-mb (256k x 36/512k x 18) pipelined sram with nobl architecture Datasheet

CY7C1354B
CY7C1356B
9-Mb (256K x 36/512K x 18) Pipelined SRAM
with NoBL™ Architecture
Features
Functional Description
• Pin-compatible and functionally equivalent to ZBT
• Supports 225-MHz bus operations with zero wait states
— Available speed grades are 225, 200, and 166 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte Write capability
• Separate VDDQ for 3.3V or 2.5V I/O
• Single 3.3V power supply
The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and
512K x 18 Synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL) logic, respectively. They are designed to
support unlimited true back-to-back Read/Write operations
with no wait states. The CY7C1354B and CY7C1356B are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1354B and CY7C1356B are
pin compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
• Fast clock-to-output times
— 2.8 ns (for 225-MHz device)
— 3.2ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in 100 TQFP, 119 BGA, and 165 fBGA packages
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability–linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1354B and BWa–BWb for CY7C1356B)
and a Write Enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram-CY7C1354B (256K x 36)
ADDRESS
REGISTER 0
A0, A1, A
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWa
BWb
BWc
BWd
WRITE
DRIVERS
MEMORY
ARRAY
WE
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
ZZ
Cypress Semiconductor Corporation
Document #: 38-05114 Rev. *C
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPa
DQPb
DQPc
DQPd
E
INPUT
REGISTER 0 E
READ LOGIC
SLEEP
CONTROL
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised June 16, 2004
CY7C1354B
CY7C1356B
Logic Block Diagram-CY7C1356B (512K x 18)
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
BWb
WE
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
D
A
T
A
R
E
G
I
S
T
E
R
S
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
ZZ
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPa
DQPb
E
INPUT
REGISTER 0 E
READ LOGIC
Sleep
Control
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
CY7C1354B-225
CY7C1356B-225
2.8
250
35
CY7C1354B-200
CY7C1356B-200
3.2
220
35
CY7C1354B-166
CY7C1356B-166
3.5
180
35
Unit
ns
mA
mA
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05114 Rev. *C
Page 2 of 29
CY7C1354B
CY7C1356B
Pin Configurations
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NC
DQPb
NC
DQb
NC
DQb
VDDQ VDDQ
VSS
VSS
NC
DQb
DQb
NC
DQb
DQb
DQb
DQb
VSS
VSS
V
DDQ
VDDQ
DQb
DQb
DQb
DQb
NC
VSS
VDD
NC
CY7C1356B
(512K × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
E(36)
E(72)
VSS
VDD
E(288)
E(144)
A
A
A
A
A
A
A
E(36)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD
NC
VSS
ZZ
DQb
DQa
DQa
DQb
VDDQ VDDQ
VSS
VSS
DQa
DQb
DQa
DQb
DQa DQPb
NC
DQa
VSS
VSS
VDDQ VDDQ
NC
DQa
DQa
NC
DQPa
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
Document #: 38-05114 Rev. *C
E(72)
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
CY7C1354B
(256K × 36)
VSS
VDD
NC
E(288)
E(144)
DQc
DQc
NC
VDD
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DQPc
DQc
DQc
VDDQ
A
A
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
E(18)
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
E(18)
A
100-pin TQFP Packages
Page 3 of 29
CY7C1354B
CY7C1356B
Pin Configurations (continued)
119-ball BGA Pinout
CY7C1354B (256K × 36) – 14 × 22 BGA
1
2
3
4
5
6
7
A
VDDQ
A
A
E(18)
A
A
VDDQ
B
C
D
E
F
G
H
J
K
L
M
N
P
NC
NC
DQc
CE2
A
DQPc
A
A
VSS
ADV/LD
VDD
NC
A
A
VSS
CE3
A
DQPb
NC
NC
DQb
CE1
VSS
DQb
DQb
OE
A
VSS
DQb
VDDQ
BWb
DQb
DQb
WE
VDD
VSS
NC
DQb
VDD
DQb
VDDQ
CLK
NC
VSS
BWa
DQa
DQa
DQa
DQa
R
T
U
DQc
DQc
VSS
VDDQ
DQc
VSS
DQc
DQc
DQc
VDDQ
DQc
VDD
BWc
VSS
NC
DQd
DQd
DQd
DQd
BWd
VDDQ
DQd
VSS
DQa
VDDQ
DQd
VSS
CEN
A1
VSS
DQd
VSS
DQa
DQa
DQd
DQPd
VSS
A0
VSS
DQPa
DQa
NC
A
MODE
VDD
NC
E(72)
A
A
NC
A
A
NC
E(36)
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
VSS
CY7C1356B (512K x 18)–14 x 22 BGA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Document #: 38-05114 Rev. *C
1
2
3
4
5
6
7
VDDQ
A
A
E(18)
A
A
VDDQ
NC
CE2
A
A
NC
A
VSS
ADV/LD
VDD
NC
A
NC
DQb
A
VSS
CE3
A
DQPa
NC
NC
CE1
VSS
NC
DQa
OE
A
VSS
DQa
VDDQ
NC
DQa
VDD
DQa
NC
VDDQ
NC
NC
DQb
VSS
VDDQ
NC
VSS
NC
DQb
VDDQ
DQb
NC
VDD
BWb
VSS
NC
WE
VDD
VSS
VSS
NC
VSS
NC
DQa
BWa
VSS
DQa
NC
NC
VDDQ
VSS
DQa
NC
NC
DQb
VSS
CLK
DQb
NC
VSS
NC
VDDQ
DQb
VSS
DQb
NC
VSS
CEN
A1
NC
DQPb
VSS
A0
VSS
NC
DQa
NC
NC
A
MODE
VDD
NC
A
E(72)
A
A
E(36)
A
A
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Page 4 of 29
CY7C1354B
CY7C1356B
Pin Configurations (continued)
165-Ball fBGA Pinout
CY7C1354B (256K × 36) – 13 × 15 fBGA
4
5
6
7
1
2
3
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
E(288)
A
CE1
BWc
BWb
CE3
ADV/LD
A
A
NC
CLK
CEN
WE
OE
E(18)
VSS
VSS
VSS
VDD
VDDQ
R
NC
A
CE2
DQPc
DQc
NC
DQc
VDDQ
VDDQ
BWd
VSS
VDD
BWa
VSS
VSS
VSS
VSS
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
A
E(144)
VDDQ
NC
DQb
DQPb
DQb
VDDQ
DQb
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
NC
DQd
DQc
NC
DQd
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
DQb
NC
DQa
DQb
ZZ
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQPd
DQd
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
DQa
DQPa
NC
E(72)
A
A
TDI
A1
TDO
A
A
A
NC
MODE
E(36)
A
A
TMS
A0
TCK
A
A
A
A
NC
CY7C1356B (512K × 18) – 13 × 15 fBGA
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
E(288)
A
CE1
BWb
NC
CE3
CEN
ADV/LD
A
A
A
R
NC
A
CE2
NC
BWa
CLK
E(144)
VDDQ
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
OE
VSS
VDD
A
NC
DQb
WE
VSS
VSS
E(18)
NC
NC
VDDQ
VDDQ
NC
NC
DQPa
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
NC
DQb
DQb
NC
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
NC
DQa
DQa
ZZ
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
DQPb
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
NC
NC
NC
E(72)
A
A
TDI
A1
TDO
A
A
A
NC
MODE
E(36)
A
A
TMS
A0
TCK
A
A
A
A
Document #: 38-05114 Rev. *C
NC
Page 5 of 29
CY7C1354B
CY7C1356B
Pin Definitions
Pin Name
I/O Type
Pin Description
A0
A1
A
InputSynchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
BWa
BWb
BWc
BWd
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc
controls DQc and DQPc, BWd controls DQd and DQPd.
WE
InputSynchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
ADV/LD
InputSynchronous
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
OE
InputAsynchronous
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the data portion of a Write sequence, during the first clock when emerging from a deselected state and when the device has been deselected.
CEN
InputSynchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
DQa
DQb
DQc
DQd
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by addresses during the previous clock rise of the Read cycle. The direction of the pins
is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQa–DQd are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless of the state of
OE.
DQPa
DQPb
DQPc
DQPd
I/OSynchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[a:d]. During
write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled
by BWc, and DQPd is controlled by BWd.
MODE
Input Strap Pin
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
TDO
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Synchronous
TDI
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
Synchronous
TMS
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous
TCK
JTAG-Clock
VDD
Power Supply
VDDQ
VSS
Clock input to the JTAG circuitry.
Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground
Document #: 38-05114 Rev. *C
Ground for the device. Should be connected to ground of the system.
Page 6 of 29
CY7C1354B
CY7C1356B
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
–
–
No connects. This pin is not connected to the die.
These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M
and 288M densities.
InputAsynchronous
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin can be connected to VSS or left
floating.
NC
E(18,36,
72, 144,
288)
ZZ
Introduction
Functional Overview
The CY7C1354B and CY7C1356B are synchronous-pipelined
Burst NoBL SRAMs designed specifically to eliminate wait
states during Write/Read transitions. All synchronous inputs
pass through input registers controlled by the rising edge of
the clock. The clock signal is qualified with the Clock Enable
input signal (CEN). If CEN is HIGH, the clock signal is not
recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(tCO) is 2.8 ns (225-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE). BW[d:a] can be used to
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
Writes are simplified with on-chip synchronous self-timed
Write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the address register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.8 ns
(225-MHz device) provided OE is active LOW. After the first
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
Document #: 38-05114 Rev. *C
of the chip enable signals, its output will three-state following
the next clock rise.
Burst Read Accesses
The CY7C1354B and CY7C1356B have an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the Write signal WE
is asserted LOW. The address presented to A0∠A16 is loaded
into the Address Register. The write signals are latched into
the Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354B and DQa,b/DQPa,b for
CY7C1356B). In addition, the address for the subsequent
access (Read/Write/Deselect) is latched into the address
register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354B and DQa,b/DQPa,b for
CY7C1356B) (or a subset for byte write operations, see Write
Cycle Description table for details) inputs is latched into the
device and the Write is complete.
The data written during the Write operation is controlled by BW
(BWa,b,c,d for CY7C1354B and BWa,b for CY7C1356B)
signals. The CY7C1354B/56B provides Byte Write capability
that is described in the Write Cycle Description table. Asserting
the Write Enable input (WE) with the selected Byte Write
Select (BW) input will selectively write to only the desired
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the Write operations. Byte Write
capability has been included in order to greatly simplify
Page 7 of 29
CY7C1354B
CY7C1356B
Read/Modify/Write sequences, which can be reduced to
simple Byte Write operations.
Because the CY7C1354B and CY7C1356B are common I/O
devices, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354B and DQa,b/DQPa,b for
CY7C1356B) inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ and DQP (DQa,b,c,d/
DQPa,b,c,d for CY7C1354B and DQa,b/DQPa,b for
CY7C1356B) are automatically three-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1354B/56B has an on-chip burst counter that allows
the user the ability to supply a single address and conduct up
to four WRITE operations without reasserting the address
inputs. ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct BW
(BWa,b,c,d for CY7C1354B and BWa,b for CY7C1356B) inputs
must be driven in each cycle of the burst write in order to write
the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive for
the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
00
01
10
11
A1,A0
01
00
11
10
A1,A0
10
11
00
01
A1,A0
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
00
01
10
11
A1,A0
01
10
11
00
A1,A0
10
11
00
01
A1,A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Document #: 38-05114 Rev. *C
Test Conditions
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max
35
2tCYC
2tCYC
2tCYC
0
Unit
mA
ns
ns
ns
ns
Page 8 of 29
CY7C1354B
CY7C1356B
Truth Table[1, 2, 3, 4, 5, 6, 7]
Operation
Address
Used
CE ZZ
ADV/LD
WE
BWx
OE
CEN CLK
DQ
Deselect Cycle
None
H
L
L
X
X
X
L
L-H
Three-State
Continue
Deselect Cycle
None
X
L
H
X
X
X
L
L-H
Three-State
Read Cycle
(Begin Burst)
External
L
L
L
H
X
L
L
L-H
Data Out (Q)
Read Cycle
Next
(Continue Burst)
X
L
H
X
X
L
L
L-H
Data Out (Q)
NOP/Dummy
Read
(Begin Burst)
L
L
L
H
X
H
L
L-H
Three-State
Dummy Read
Next
(Continue Burst)
X
L
H
X
X
H
L
L-H
Three-State
Write Cycle
(Begin Burst)
L
L
L
L
L
X
L
L-H
Data In (D)
X
L
H
X
L
X
L
L-H
Data In (D)
L
L
L
L
H
X
L
L-H
Three-State
WRITE ABORT Next
(Continue Burst)
X
L
H
X
H
X
L
L-H
Three-State
IGNORE
CLOCK EDGE
(Stall)
Current
X
L
X
X
X
X
H
L-H
-
Sleep MODE
None
X
H
X
X
X
X
X
X
External
External
Write Cycle
Next
(Continue Burst)
NOP/WRITE
ABORT
(Begin Burst)
None
Three-State
Notes:
1. X = “Don't Care”, 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx =
Valid signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BW[a:d]. See Write Cycle Description table for details.
3. When a write cycle is detected, all I/Os are three-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[a:d] = Three-state when
OE is inactive or when the device is deselected, and DQs = data when OE is active.
Document #: 38-05114 Rev. *C
Page 9 of 29
CY7C1354B
CY7C1356B
Partial Write Cycle Description[1, 2, 3, 8]
Function (CY7C1354B)
WE
H
BWd
X
X
X
X
Write –No bytes written
L
H
H
H
H
Write Byte a– (DQa and DQPa)
L
H
H
H
L
Write Byte b – (DQb and DQPb)
L
H
H
L
H
Read
BWc
BWb
BWa
Write Bytes b, a
L
H
H
L
L
Write Byte c – (DQc and DQPc)
L
H
L
H
H
Write Bytes c, a
L
H
L
H
L
Write Bytes c, b
L
H
L
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQd and DQPd)
L
L
H
H
H
Write Bytes d, a
L
L
H
H
L
Write Bytes d, b
L
L
H
L
H
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Note:
8. Table only lists a partial listing of the byte write combinations. Any combination of BW[a:d] is valid. Appropriate write will be done based on which byte write is active.
Function (CY7C1356B)
WE
BWb
BWa
Read
H
x
x
Write – No Bytes Written
L
H
H
Write Byte a − (DQa and DQPa)
L
H
L
Write Byte b – (DQb and DQPb)
L
L
H
Write Both Bytes
L
L
L
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1354B/CY7C1354B incorporates a serial boundary
scan Test Access Port (TAP) in the BGA package only. The
TQFP package does not offer this functionality. This port
operates in accordance with IEEE Standard 1149.1-1900, but
does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 3.3V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Document #: 38-05114 Rev. *C
Test Access Port–Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Page 10 of 29
CY7C1354B
CY7C1356B
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a High-Z state.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
TAP Registers
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller
cannot be used to load address, data, or control signals into
the SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The ×36 configuration has a 69-bit-long
register, and the ×18 configuration has a 69-bit-long register.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
Document #: 38-05114 Rev. *C
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the TAP controller, and
therefore this device is not compliant to the 1149.1 standard.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1-compliant.
When the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
Page 11 of 29
CY7C1354B
CY7C1356B
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Bypass
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05114 Rev. *C
Page 12 of 29
CY7C1354B
CY7C1356B
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
TEST-LOGIC/
IDLE
1
1
SELECT
DR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
0
SHIFT-DR
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
SHIFT-IR
1
0
1
SELECT
IR-SCAN
0
UPDATE-IR
1
0
Note:
9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05114 Rev. *C
Page 13 of 29
CY7C1354B
CY7C1356B
0
Bypass Register
Selection
Circuitry
2
1
0
Selection
Circuitry
TDO
Instruction Register
TDI
31 30
29
.
.
2
1
0
1
0
Identification Register
68 .
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[10, 11]
Parameter
VOH1
VOH2
Description
Output HIGH Voltage
Output HIGH Voltage
Test Conditions
Min.
Max.
Unit
IOH = 2.0 mA, VDDQ = 3.3V
2.0
V
IOH = 2.0 mA, VDDQ = 2.5V
1.7
V
IOH = 100 µA, VDDQ = 3.3V
2.0
V
IOH = 100 µA, VDDQ = 2.5V
2.0
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.7
V
VOL2
Output LOW Voltage
IOL = 100 µA
0.2
V
VIH
Input HIGH Voltage
1.7
VDD + 0.3
V
VIL
Input LOW Voltage
–0.3
0.7
V
IX
Input Load Current
GND ≤ VI ≤ VDDQ
–30
30
µA
IX
Input Load Current TMS and TDI
GND ≤ VI ≤ VDDQ
–30
30
µA
TAP AC Switching Characteristics Over the Operating Range
Parameter
[12, 13]
Description
Min.
Max.
Unit
10
MHz
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
100
ns
tTH
TCK Clock HIGH
40
ns
tTL
TCK Clock LOW
40
ns
10
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
tTDIS
TDI Set-up to TCK Clock Rise
10
ns
tCS
Capture Set-up to TCK Rise
10
ns
Notes:
10. All voltage referenced to ground.
11. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) > –0.5V for t < tTCYC/2.
12. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
13. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document #: 38-05114 Rev. *C
Page 14 of 29
CY7C1354B
CY7C1356B
TAP AC Switching Characteristics Over the Operating Range (continued)[12, 13]
Parameter
Description
Min.
Max.
Unit
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
10
ns
tTDIH
TDI Hold after Clock Rise
10
ns
tCH
Capture Hold after clock rise
10
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
20
ns
0
ns
TAP Timing and Test Conditions
1.5V for 3.3V VDDQ
1.25V for 2.5V VDDQ
ALL INPUT PULSES
3.0V
1.5V
50Ω
VSS
1.5 ns
1.5 ns
TDO
Z0 = 50Ω
CL = 20 pF
tTL
tTH
(a)
GND
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Identification Register Definitions
Instruction Field
CY7C1354B
CY7C1356B
Revision Number (31:29)
001
Cypress Device ID (28:12)
01010001000100110
Cypress JEDEC ID (11:1)
00000110100
00000110100
ID Register Presence (0)
1
1
Document #: 38-05114 Rev. *C
001
Description
Reserved for version number.
01010001000010110 Reserved for future use.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Page 15 of 29
CY7C1354B
CY7C1356B
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
69
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and
TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100
Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO.
Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function
and is therefore not 1149.1-compliant.
RESERVED
Do Not Use: This instruction is reserved for future use.
101
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
Boundary Scan Exit Order (×36) (continued)
Boundary Scan Exit Order (×36)
Bit #
119-Ball ID
165-Ball ID
Bit #
119-Ball ID
165-Ball ID
1
K4
B6
24
M6
K11
L7
L11
2
H4
B7
25
3
M4
A7
26
K6
M11
P6
N11
4
F4
B8
27
5
B4
A8
28
T4
R11
A3
R10
6
G4
A9
29
7
C3
B10
30
C5
P10
B5
R9
8
B3
A10
31
9
D6
C11
32
A5
P9
C6
R8
10
H7
E10
33
11
G6
F10
34
A6
P8
P4
R6
12
E6
G10
35
13
D7
D10
36
N4
P6
R6
R4
14
E7
D11
37
15
F6
E11
38
T5
P4
T3
R3
16
G7
F11
39
17
H6
G11
40
R2
P3
R3
R1
18
T7
H11
41
19
K7
J10
42
P2
N1
P1
L2
20
L6
K10
43
21
N6
L10
44
L2
K2
K1
J2
N2
M2
22
P7
M10
45
23
N7
J11
46
Document #: 38-05114 Rev. *C
Page 16 of 29
CY7C1354B
CY7C1356B
Boundary Scan Exit Order (×36) (continued)
Boundary Scan Exit Order (×18) (continued)
Bit #
119-Ball ID
165-Ball ID
Bit #
119-Ball ID
165-Ball ID
47
N1
M1
16
G7
F11
48
M2
L1
17
H6
G11
49
L1
K1
18
T7
H11
50
K2
J1
19
K7
J10
51
Not Bonded
(Preset to 1)
Not Bonded
(Preset to 1)
20
L6
K10
52
H1
G2
21
N6
L10
53
G2
F2
22
P7
M10
54
E2
E2
23
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
55
D1
D2
24
56
H2
G1
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
57
G1
F1
25
58
F2
E1
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
59
E1
D1
26
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
60
D2
C1
27
61
C2
B2
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
62
A2
A2
28
T6
R11
A3
R10
63
E4
A3
29
64
B2
B3
30
C5
P10
B5
R9
65
L3
B4
31
66
G3
A4
32
A5
P9
C6
R8
67
G5
A5
33
68
L5
B5
34
A6
P8
A6
35
P4
R6
69
B6
Boundary Scan Exit Order (×18)
36
N4
P6
37
R6
R4
Bit #
119-Ball ID
165-Ball ID
38
T5
P4
1
K4
B6
39
T3
R3
2
H4
B7
40
R2
P3
3
M4
A7
41
R3
R1
4
F4
B8
42
5
B4
A8
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
6
G4
A9
43
7
C3
B10
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
8
B3
A10
44
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
45
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
9
T2
A11
10
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
11
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
12
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
13
D6
C11
50
K2
J1
51
Not Bonded
(Preset to 1)
Not Bonded
(Preset to 1)
52
H1
G2
14
E7
D11
15
F6
E11
Document #: 38-05114 Rev. *C
46
P2
N1
47
N1
M1
48
M2
L1
49
L1
K1
Page 17 of 29
CY7C1354B
CY7C1356B
Boundary Scan Exit Order (×18) (continued)
Bit #
119-Ball ID
165-Ball ID
53
G2
F2
54
E2
E2
55
D1
D2
56
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
57
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
58
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
59
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
60
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
61
C2
B2
62
A2
A2
63
E4
A3
64
B2
B3
65
Not Bonded
(Preset to 0
Not Bonded
(Preset to 0)
66
G3
Not Bonded
(Preset to 0)
67
Not Bonded
(Preset to 0
A4
68
L5
B5
69
B6
A6
Document #: 38-05114 Rev. *C
Page 18 of 29
CY7C1354B
CY7C1356B
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Range
Ambient
Temperature
DC to Outputs in Three-State.............. –0.5V to VDDQ + 0.5V
Commercial
0°C to +70°C
DC Input Voltage....................................–0.5V to VDD + 0.5V
Industrial
VDD
VDDQ
3.3V – 5%/+10% 2.5V – 5%
to VDD
–40°C to +85°C
Electrical Characteristics Over the Operating Range[14, 15]
Parameter
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW
Voltage[14]
Input Load Current
Test Conditions
Min.
Max.
Unit
3.135
3.6
V
VDDQ = 3.3V
3.135
VDD
V
VDDQ = 2.5V
2.375
2.625
V
VDD = Min., IOH = −4.0 mA, VDDQ = 3.3V
2.4
V
VDD = Min., IOH = −1.0 mA, VDDQ = 2.5V
2.0
V
VDD = Min., IOL= 8.0 mA, VDDQ = 3.3V
0.4
V
VDD = Min., IOL= 1.0 mA, VDDQ = 2.5V
0.4
V
VDDQ = 3.3V
2.0
VDD + 0.3V
V
VDDQ = 2.5V
1.7
VDD + 0.3V
V
VDDQ = 3.3V
–0.3
0.8
V
VDDQ = 2.5V
–0.3
0.7
V
–5
5
µA
–30
30
µA
GND ≤ VI ≤ VDDQ
Input Current of MODE
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
5
µA
4.4-ns cycle, 225 MHz
250
mA
5-ns cycle, 200 MHz
220
mA
6-ns cycle, 166 MHz
180
mA
–5
ISB1
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected, All speed grades
VIN ≥ VIH or VIN ≤ VIL, f = fMAX =
1/tCYC
50
mA
ISB2
Max. VDD, Device Deselected, All speed grades
Automatic CE
Power-down
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
Current—CMOS Inputs f = 0
35
mA
ISB3
Automatic CE
Max. VDD, Device Deselected, All speed grades
Power-down
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
Current—CMOS Inputs f = fMAX = 1/tCYC
50
mA
ISB4
Automatic CE
Power-down
Current—TTL Inputs
All speed grades
40
mA
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
Shaded areas contain advance information.
Notes:
14. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).
15. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05114 Rev. *C
Page 19 of 29
CY7C1354B
CY7C1356B
Capacitance[16]
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
BGA Max.
TA = 25°C, f = 1 MHz,
VDD = 3.3V VDDQ = 2.5V
fBGA Max.
TQFP Max.
Unit
5
5
5
pF
5
5
5
pF
7
7
5
pF
AC Test Loads and Waveforms
R=1667/317Ω
VDDQ
OUTPUT
Z0 = 50Ω
RL = 50Ω
VL = 1.5V/1.25V
(a)
ALL INPUT PULSES
VDD
DQ
5 pF
INCLUDING
JIG AND
SCOPE
90%
10%
[16]
90%
10%
1.5/1.25V
0V
R = 1538/351Ω
< 1.0 ns
< 1.0 ns
(c)
(b)
Thermal Resistance[16]
Parameters
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
BGA Typ.
fBGA Typ.
TQFP Typ.
Unit
Notes
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per EIA
/ JESD51.
25
27
25
°C/W
17
6
6
9
°C/W
17
Switching Characteristics Over the Operating Range [21, 22]
-225
Parameter
tPower
[17]
Description
VCC (typical) to the First Access Read or
Write
Min.
-200
Max.
Min.
-166
Max.
Min.
Max.
Unit
1
1
1
ms
4.4
5
6
ns
Clock
tCYC
Clock Cycle Time
FMAX
Maximum Operating Frequency
tCH
Clock HIGH
1.8
2.0
2.4
ns
tCL
Clock LOW
1.8
2.0
2.4
ns
225
200
166
MHz
Output Times
tCO
Data Output Valid after CLK Rise
2.8
3.2
3.5
ns
tEOV
OE LOW to Output Valid
2.8
3.2
3.5
ns
tDOH
Data Output Hold after CLK Rise
1.25
tCHZ
Clock to High-Z[18, 19, 20]
1.25
tCLZ
Clock to
Low-Z[18, 19, 20]
1.25
tEOHZ
OE HIGH to Output High-Z[18, 19, 20]
OE LOW to Output Low-Z[18, 19, 20]
tEOLZ
1.5
2.8
1.5
1.5
2.8
0
1.5
3.2
1.5
1.5
3.2
0
ns
3.5
ns
3.5
0
ns
ns
ns
Shaded areas contain advance information.
Notes:
16. Tested initially and after any design or process changes that may affect these parameters.
17. This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be
initiated.
18. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
19. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
20. This parameter is sampled and not 100% tested.
21. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
22. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05114 Rev. *C
Page 20 of 29
CY7C1354B
CY7C1356B
Switching Characteristics Over the Operating Range (continued)[21, 22]
-225
Parameter
Description
Min.
Max.
-200
Min.
Max.
-166
Min.
Max.
Unit
Set-up Times
tAS
Address Set-up before CLK Rise
1.4
1.5
1.5
ns
tDS
Data Input Set-up before CLK Rise
1.4
1.5
1.5
ns
CEN Set-up before CLK Rise
WE, BWx Set-up before CLK Rise
1.4
1.5
1.5
ns
1.4
1.5
1.5
ns
1.5
1.5
ns
tCES
ADV/LD Set-up before CLK Rise
Chip Select Set-up
1.4
1.4
1.5
1.5
ns
tAH
Address Hold after CLK Rise
0.4
0.5
0.5
ns
tDH
Data Input Hold after CLK Rise
0.4
0.5
0.5
ns
tCENH
tCENS
tWES
tALS
Hold Times
CEN Hold after CLK Rise
0.4
0.5
0.5
ns
tWEH
WE, BWx Hold after CLK Rise
0.4
0.5
0.5
ns
tALH
ADV/LD Hold after CLK Rise
Chip Select Hold after CLK Rise
0.4
0.5
0.5
ns
0.4
0.5
0.5
ns
tCEH
Document #: 38-05114 Rev. *C
Page 21 of 29
CY7C1354B
CY7C1356B
Switching Waveforms
Read/WriteTiming[23,24,25]
1
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCH
tCL
CEN
tCES
tCEH
CE
ADV/LD
WE
BWX
A1
ADDRESS
A2
tCO
tAS
tDS
tAH
Data
tDH
D(A1)
tCLZ
D(A2)
D(A2+1)
tDOH
Q(A3)
tOEV
Q(A4)
tCHZ
Q(A4+1)
D(A5)
Q(A6)
n-Out (DQ)
tOEHZ
tDOH
tOELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
Document #: 38-05114 Rev. *C
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Page 22 of 29
CY7C1354B
CY7C1356B
Switching Waveforms (continued)
NOP,STALL AND DESELECT CYCLES[23,24,26]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWX
ADDRESS
A5
tCHZ
D(A1)
Data
Q(A2)
D(A4)
Q(A3)
Q(A5)
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
DON’T CARE
Document #: 38-05114 Rev. *C
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Page 23 of 29
CY7C1354B
CY7C1356B
Switching Waveforms (continued)
ZZ Mode Timing [27,28]
CLK
t
ZZ
I
t
t
ZZ
ZZREC
ZZI
SUPPLY
I
t RZZI
DDZZ
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Note:
23. For this waveform ZZ is tied low.
24. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
25. Order of the Burst sequence is determined by the status of the MODE (0=Linear, 1=Interleaved).Burst operations are optional.
26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle
27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
28. I/Os are in High-Z when exiting ZZ sleep mode..
Ordering Information
Speed
(MHz)
225
Ordering Code
CY7C1354B-225AC
Package
Name
Package Type
Operating
Range
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Commercial
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Industrial
CY7C1356B-225AC
CY7C1354B-225AI
CY7C1356B-225AI
CY7C1354B-225BGC
BG119
119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Commercial
BG119
119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Industrial
CY7C1356B-225BGC
CY7C1354B-225BGI
CY7C1356B-225BGI
CY7C1354B-225BZC
BB165A
165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
Commercial
BB165A
165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
Industrial
CY7C1356B-225BZC
CY7C1354B-225BZI
CY7C1356B-225BZI
Document #: 38-05114 Rev. *C
Page 24 of 29
CY7C1354B
CY7C1356B
Ordering Information
Speed
(MHz)
200
Ordering Code
CY7C1354B-200AC
Package
Name
Package Type
Operating
Range
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Commercial
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Industrial
CY7C1356B-200AC
CY7C1354B-200AI
CY7C1356B-200AI
CY7C1354B-200BGC
BG119
119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Commercial
BG119
119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Industrial
CY7C1356B-200BGC
CY7C1354B-200BGI
CY7C1356B-200BGI
CY7C1354B-200BZC
BB165A
165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
Commercial
BB165A
165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
Industrial
CY7C1356B-200BZC
CY7C1354B-200BZI
CY7C1356B-200BZI
166
CY7C1354B-166AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Commercial
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Industrial
CY7C1356B-166AC
CY7C1354B-166AI
CY7C1356B-166AI
CY7C1354B-166BGC
BG119
119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Commercial
BG119
119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Industrial
CY7C1356B-166BGC
CY7C1354B-166BGI
CY7C1356B-166BGI
CY7C1354B-166BZC
BB165A
165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
Commercial
BB165A
165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
Industrial
CY7C1356B-166BZC
CY7C1354B-166BZI
CY7C1356B-166BZI
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05114 Rev. *C
Page 25 of 29
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1354B
CY7C1356B
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
SEE DETAIL
50
0.20 MAX.
1.60 MAX.
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
GAUGE PLANE
0.10
0° MIN.
0°-7°
A
51
31
R 0.08 MIN.
0.20 MAX.
12°±1°
(8X)
SEATING PLANE
R 0.08 MIN.
0.20 MAX.
0.60±0.15
0.20 MIN.
1.00 REF.
DETAIL
Document #: 38-05114 Rev. *C
A
51-85050-*A
Page 26 of 29
CY7C1354B
CY7C1356B
Package Diagrams (continued)
119-Lead BGA (14 x 22 x 2.4mm) BG119
51-85115-*B
Document #: 38-05114 Rev. *C
Page 27 of 29
CY7C1354B
CY7C1356B
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05114 Rev. *C
Page 28 of 29
CY7C1354B
CY7C1356B
Document History Page
Document Title: CY7C1354B/CY7C1356B 9-Mb (256K x 36/512K x 18) Pipelined SRAM
NoBL™ Architecture
Document Number: 38-05114
REV.
ECN No.
Issue Date
Orig. of
Change
with
Description of Change
**
117904
08/28/02
RCS
New Data Sheet
*A
126207
08/27/03
DPM
Removed Preliminary status
Removed 250-MHz Speed bin
Added 225-MHz speed bin
Increased TCO, TEOV, TCHZ, TEOHZ for 200 MHz to 3.2 ns from 3.0 ns
Updated JTAG revision number and device depth
Updated JTAG boundary scan orders
Added tPower specification
Changed footnotes ordering
Added Industrial operating range
Changed Capacitance table to have TQFP, BGA, and fBGA columns.
*B
205060
See ECN
NJY
Removed footnote 13 “Minimum voltage equals –2.0V for pulse durations of less than 20 ns.”
Removed footnote 14 “TA is the case temperature.”
Changed footnote 15 from “Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot:
VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t <
200 ms. “to footnote 13“Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2),
undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2). “
Added footnote 14 “TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200ms.
During this time VIH < VDD and VDDQ < VDD. “
Added footnote 20 “Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when
VDDQ = 2.5V.”
Changed footnote 21 from “Test conditions shown in (a), (b) and (c) of AC Test Loads. “to
“Test conditions shown in (a) of AC Test Loads unless otherwise noted. “
Updated ZZ Mode Electrical Characteristics.
Updated ISB1 and ISB3 currents in Electrical Characteristics table.
Modified functional block diagram.
Modified Truth Table and Write Cycle Descriptions.
Updated Ordering Information.
*C
230388
See ECN
Document #: 38-05114 Rev. *C
VBL
Modified ID code
Changed balls B4 and A5 from BWd and BWb to NC and ball A4 from BWc
to BWb for 165-ball FBGA package for CY7C1356B
Changed balls C11 from DQPb to DQPa and balls D11,E11,F11 and G11
from DQb to DQa for CY7C1356B.
Update Ordering Info section: changed BZC to BZI in Industrial part
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