LINER LT5546 40mhz to 500mhz vga and i/q demodulator with 17mhz baseband bandwidth Datasheet

LT5546
40MHz to 500MHz VGA
and I/Q Demodulator with
17MHz Baseband Bandwidth
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FEATURES
DESCRIPTIO
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The LT®5546 is a 40MHz to 500MHz monolithic integrated
quadrature demodulator with variable gain amplifier (VGA)
and 17MHz I/Q baseband bandwidth designed for low voltage operation. It supports standards that use a linear modulation format. The chip consists of a VGA, quadrature downconverting mixers and 17MHz lowpass noise filters (LPF).
The LO port consists of a divide-by-two stage and LO
buffers. The IC provides all building blocks for IF downconversion to I and Q baseband signals with a single
supply voltage of 1.8V to 5.25V. The VGA gain has a linearin-dB relationship to the control input voltage. Hard-clipping amplifiers at the mixer outputs reduce the recovery
time from a signal overload condition. The lowpass filters
reduce the out-of-band noise and spurious frequency
components. The –3dB corner frequency of the noise
filters is approximately 17MHz and has a first order rolloff. The standby mode provides reduced supply current
and fast transient response into the normal operating mode
when the I/Q outputs are AC-coupled to a baseband chip.
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17MHz I/Q Lowpass Output Noise Filters
Wide Range 1.8V to 5.25V Supply Voltage
Frequency Range: 40MHz to 500MHz
THD < 0.14% (–57dBc)
at 800mVP-P Differential Output Level
IF Overload Detector
Log Linear Gain Control Range: –7dB to 56dB
Baseband I/Q Amplitude Imbalance: 0.2dB
Baseband I/Q Phase Imbalance: 0.6°
7.8dB Noise Figure at Max Gain
Input IP3 at Low Gain: – 1dBm
Low Supply Current: 24mA
Low Delay Shift Over Gain Control Range: 2ps/dB
Outputs Biased Up While in Standby
16-Lead QFN 4mm × 4mm Package with Exposed Pad
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APPLICATIO S
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GPS IF Receivers
Satellite IF Receivers
VHF/UHF Receivers
Wireless Local Loop
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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TYPICAL APPLICATIO
280MHz
IF INPUT
C2
1µF
IF +
L1
15nH
C3
10pF
L2
15nH
C1
1nF
VCC
–30
IOUT+
IF DET
VCTRL
L3
39nH
+
QOUT
÷2
STBY
–40
–45
–50
QOUT
GND
LT5546
5546 TA01
ENABLE STANDBY
fIF, 1 = 280MHz
fIF, 2 = 280.1MHz
f2xLO = 570MHz
800mVP-P DIFFERENTIAL OUT
–
2xLO –
EN
C3
1.8pF
THD (dBc)
–35
IOUT–
2xLO +
C5
3.3pF
–25
IF –
GAIN CONTROL
2xLO
C4
560MHz
3.3pF
INPUT
Total Harmonic Distortion vs
IF Input Level at 1.8V Supply
1.8V
–55
–60
–60
–40
–30
–20
–50
IF INPUT POWER EACH TONE (dBm)
–10
5546 TA01b
5546fa
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LT5546
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ABSOLUTE
AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
NUMBER
QOUT–
QOUT+
IOUT+
IOUT–
TOP VIEW
Supply Voltage ....................................................... 5.5V
Differential Voltage Between 2xLO+ and 2xLO– .......... 4V
IF+, IF– ............................................. –500mV to 500mV
IOUT+, IOUT–, QOUT+, QOUT– .................. VCC – 1.8V to VCC
Operating Ambient Temperature
(Note 2) ...................................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
Voltage on Any Pin
Not to Exceed ........................ –500mV to VCC + 500mV
16 15 14 13
GND 1
LT5546EUF
12 STBY
IF+ 2
11 2xLO+
17
IF – 3
10 2xLO–
GND 4
6
7
8
VCC
VCTRL
IF DET
VCC
9
5
EN
UF PART MARKING
5546
UF PACKAGE
16-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD IS GND (PIN 17)
(MUST BE SOLDERED TO PCB)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
VCC = 3V, f2xLO = 570MHz, P2xLO = –5dBm (Note 5), f IF = 284MHz,
PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IF Input
fIF
Frequency Range
40 to 500
MHz
Nominal Input Level
RSOURCE = 200Ω Differential
–76 to –19
dBm
Input Impedance
IF+, IF– to GND, EN = VCC
IF+, IF– to GND, EN = GND
100Ω//1.2pF
1pF
NF
Noise Figure at Max Gain
VCTRL = 1.7V
7.8
GL
Min Gain (Note 4)
VCTRL = 0.2V
1.6
49
dB
6
dB
GH
Max Gain (Note 4)
VCTRL = 1.7V
56
dB
IIP3
Input IP3, Min Gain
Input IP3, Max Gain
PIF = –22.5dBm (Note 7)
PIF = –75dBm (Note 7)
–1
–49
dBm
dBm
IIP2
Input IP2, Min Gain
Input IP2, Max Gain
VCTRL = 0.2V (Note 9)
VCTRL = 1.7V (Note 9)
36
–25
dBm
dBm
Nominal Voltage Swing
(Note 6)
0.8
VP-P
Clipping Level
(Note 6)
1.47
VP-P
Demodulator I/Q Output
DC Common Mode Voltage
I/Q Amplitude Imbalance
ro
VCC – 1.19
V
(Note 8)
0.14
0.6
dB
I/Q Phase Imbalance
(Note 8)
0.6
3
Deg
DC Offset
(Notes 6, 8)
21
mV
Output Driving Capability
Single Ended, CLOAD ≤ 10pF
1.5
kΩ
Small-Signal Output Impedance
(Note 6)
2
180
Ω
STBY to Turn-On Delay
0.3
µs
I/Q Output 1dB Compression
–10
dBm
– 49
dBc
I/Q Output IM3
PIF, 1 = –25.5dBm, 280MHz
PIF, 2 = –25.5dBm, 280.1MHz (Note 7)
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LT5546
ELECTRICAL CHARACTERISTICS
VCC = 3V, f2×LO = 570MHz, P2×LO = –5dBm (Note 5), f IF = 284MHz,
PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Variable Gain Amplifier (VGA)
Gain Slope Linearity Error
VCTRL = 0V to 1.4V
±0.5
dB
Temperature Gain Shift
T = –40°C to 85°C, VCTRL = 0V to 1.4V
±0.4
dB
Gain Control Response Time
Settled within 10% of Final Value
90
ns
0 to 1.7
V
Gain Control Voltage Range
Gain Control Slope
41
dB/V
Gain Control Input Impedance
To Internal 0.2V Reference
25
kΩ
Delay Shift Over Gain Control
Measured Over 10dB Step
2
ps/dB
17
MHz
Amplitude Roll-Off at 50MHz
–9
dB
Group Delay Ripple
1
ns
Baseband Lowpass Filter (LPF)
–3dB Cutoff Frequency
13
2xLO Input
f2xLO
Frequency Range
P2xLO
Input Power
1:2 Transformer with 240Ω Shunt Resistor (Note 5)
Input Power
LC Balun (Note 5)
Input Impedance
Differential Between 2xLO+ and 2xLO–
–20
80 to 1000
MHz
–5
dBm
–10
dBm
800Ω//0.4pF
DC Common Mode Voltage
VCC – 0.4
V
–30 to 8
dBm
IF Detector
IF Detector Range
Referred to IF Input
Output Voltage Range
For PIF = –30dBm to 8dBm
Detector Response Time
With External 1.8pF Load,
Settling within 10% of Final Value
0.27 to 1.2
V
80
ns
Power Supply
VCC
Supply Voltage
1.8
5.25
V
ICC
Supply Current
EN = High, STBY = Low or High
24
34
mA
IOFF
Shutdown Current
EN, STBY < 350mV
0.2
30
µA
ISTBY
Standby Current
EN = Low; STBY = High
3.6
6
mA
Enable
Enable Pin Voltage
EN = High
Disable
Enable Pin Voltage
EN = Low
Standby
Standby Pin Voltage
STBY = High
No Standby
Standby Pin Voltage
STBY = Low
Mode
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Specifications over the –40°C to 85°C temperature range are
assured by design, characterization and correlation with statistical process
controls.
Note 3: Tests are performed as shown in the configuration of Figure 6. The
IF input transformer loss is substracted from the measured values.
Note 4: Power gain is defined here as the I (or Q) output power into a 4kΩ
differential load, divided by the IF input power in dB. To calculate the
voltage gain between the differential I output (or Q output) and the IF
input, including ideal matching network, 10 • log(4kΩ/50) = 19dB has to
be added to this power gain.
1
V
0.5
1
V
V
0.5
V
Note 5: If a narrow-band match is used in the 2xLO path instead of a 1:2
transformer with 240Ω shunt resistor, 2xLO input power can be reduced
to –10dBm, without degrading the phase imbalance. See Figure 11 and
Figure 6.
Note 6: Differential between IOUT+ and IOUT– (or differential between
QOUT+ and QOUT–).
Note 7: The gain control voltage VCTRL is set in such a way that the
differential output voltage between IOUT+ and IOUT– (or differential between
QOUT+ and QOUT–) is 800mVP-P, with the given input power PIF. IF
frequencies are 280MHz and 280.1MHz, with f 2xLO = 570MHz.
Note 8: The typical parameter is defined as the mean of the absolute
values of the data distribution.
Note 9: IF frequency is 125MHz, with f 2xLO = 502MHz.
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TYPICAL PERFOR A CE CHARACTERISTICS
VCC = 3V, f2×LO = 570MHz, P2×LO = –5dBm
(Note 5), f IF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC,
unless otherwise noted. (Note 3)
Gain and Noise Figure
Supply Current vs Supply Voltage
vs Control Voltage at 3V Supply
28
60
85°C
GAIN AND NOISE FIGURE (dB)
SUPPLY CURRENT (mA)
50
26
25°C
24
–40°C
22
40
30
20
NF
10
GAIN
0
20
1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25
SUPPLY VOLTAGE (V)
fIF = 284MHz
f2xLO = 570MHz
–10
0
0.6
0.3
0.9
1.2
5546 G02
Gain and Noise Figure
vs Control Voltage at 1.8V Supply
Gain Flatness
vs Control Voltage at 3V Supply
0.5
GAIN AND NOISE FIGURE (dB)
50
40
30
20
GAIN
0
fIF = 284MHz
f2xLO = 570MHz
–10
0
0.3
0.6
0.9
1.2
1.5
GAIN AT –40°C
NF AT 25°C
GAIN AT 25°C
NF AT –40°C
GAIN AT 85°C
NF AT 85°C
GAIN DEVIATI0N FROM LINEAR FIT (dB)
60
NF
–40°C
0.4
0.3
0.2
85°C
0.1
0
–0.1
25°C
–0.2
–0.3
–0.4
–0.5
0
1.8
VCTRL (V)
0.3
0.9
0.6
VCTRL (V)
1.2
1.5
5546 G04
5546 G03
Gain and Noise Figure
vs IF Frequency at 3V Supply
Gain and Noise Figure
vs Control Voltage and VCC
60
60
50
50
GAIN, VCTRL = 1.6V
40
30
20
NF
10
GAIN
0
fIF = 284MHz
f2xLO = 570MHz
–10
0
0.3
0.6
0.9
1.2
1.5
1.8
VCTRL (V)
5546 G05
GAIN AT 1.8V
NF AT 1.8V
GAIN AT 3V
NF AT 3V
GAIN AT 5.25V
NF AT 5.25V
GAIN AND NOISE FIGURE (dB)
GAIN AND NOISE FIGURE (dB)
1.8
1.5
VCTRL (V)
5546 G01
10
GAIN AT 25°C
NF AT 25°C
GAIN AT –40°C
NF AT –40°C
GAIN AT 85°C
NF AT 85°C
NF, VCTRL = 0.2V
40
GAIN, VCTRL = 0.9V
30
NF, VCTRL = 0.9V
20
NF, VCTRL = 1.6V
10
0
GAIN, VCTRL = 0.2V
–10
10
100
IF FREQUENCY (MHz)
1000
5546 G06
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LT5546
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TYPICAL PERFOR A CE CHARACTERISTICS
VCC = 3V, f2×LO = 570MHz, P2×LO = –5dBm
(Note 5), f IF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC,
unless otherwise noted. (Note 3)
Total Harmonic Distortion
vs IF Input Power and IF
Frequency
Total Harmonic Distortion
vs IF Input Power at 3V Supply
and 800mVP-P Differential Out
–25
–25
fIF,1 = 280MHz
fIF,2 = 280.1MHz
f2xLO = 570MHz
–30
–30
–25
800mVP-P DIFFERENTIAL OUT
3V SUPPLY
25°C
–45
–40°C
–40
–45
–50
85°C
–55
–50
–40
–20
–30
IF INPUT POWER EACH TONE (dBm)
fIF = 40MHz
–60
–60
–10
–55
–50
–40
–20
–30
IF INPUT POWER EACH TONE (dBm)
–25
–30
THD (dBc)
THD (dBc)
–45
5.25V
–55
–40
–20
–30
IF INPUT POWER EACH TONE (dBm)
–2
–40°C
–45
25°C
LPF Frequency Response
vs Baseband Frequency and
Supply Voltage
0
85°C
–4
–5
25°C
–6
–7
–8
–60
–9
–10
–35
–30
–25
IF INPUT POWER EACH TONE (dBm)
5546 G10
–40°C
–3
–55
–65
–40
–10
VCC = 3V
–1
–40
–50
–50
–20
85°C
0
5 10 15 20 25 30 35 40 45 50 55
BASEBAND FREQUENCY (MHz)
5546 G12
5546 G11
IF Detector Output Voltage vs
IF Input CW Power at 3V Supply
1.4
TA = 25°C
–10
5546 G09
0
fIF,1 = 280MHz
fIF,2 = 280.1MHz
f2xLO = 570MHz
VCC = 3V
–35
3V
–50
–40
–20
–30
IF INPUT POWER EACH TONE (dBm)
LPF Frequency Response
vs Baseband Frequency
and Temperature
–20
800mVP-P DIFFERENTIAL OUT
fIF,1 = 280MHz
–30 f
IF,2 = 280.1MHz
f2xLO = 570MHz
–35
–50
–60
–60
–10
5546 G08
–25
–60
–60
–45
Total Harmonic Distortion
vs IF Input Power at 500mVP-P
Differential Out
Total Harmonic Distortion vs IF
Input Power and Supply Voltage
1.8V
–40
fIF = 500MHz
5546 G07
–40
85°C
–40°C
–50
–55
–60
–60
25°C
fIF = 280MHz
MAGNITUDE (dB)
–50
–35
THD (dBc)
THD (dBc)
–40
fIF,1 = 280MHz
fIF,2 = 280.1MHz
f2xLO = 570MHz
–30
–35
–35
THD (dBc)
Total Harmonic Distortion
vs IF Input Power at 1.8V Supply
and 800mVP-P Differential Out
IF Detector Output Voltage vs
IF Input CW Power at 1.8V Supply
1.4
fIF = 280MHz
fIF = 280MHz
–1
–4
–5
3V
–6
–7
–8
0
1.0
85°C
0.8
25°C
0.6
0.4
5.25V
–9
5 10 15 20 25 30 35 40 45 50 55
BASEBAND FREQUENCY (MHz)
5546 G13
IF DET OUTPUT (V)
IF DET OUTPUT (V)
MAGNITUDE (dB)
1.8V
–3
–10
1.2
1.2
–2
–30
–20
–10
0
IF INPUT CW POWER (dBm)
85°C
0.8
10
5546 G14
25°C
0.6
0.4
–40°C
0.2
–40
1.0
–40°C
0.2
–40
–30
–20
–10
0
IF INPUT CW POWER (dBm)
10
5546 G15
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LT5546
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TYPICAL PERFOR A CE CHARACTERISTICS
VCC = 3V, f2×LO = 570MHz, P2×LO = –5dBm
(Note 5), f IF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC,
unless otherwise noted. (Note 3)
IF Detector Output Voltage
vs IF Input CW Power and
Supply Voltage
1.4
fIF = 280MHz
IF DET OUTPUT (V)
IF DET OUTPUT (V)
5.25V
1.0
3V
1.8V
0.8
0.6
94
fIF = 280MHz
93
fIF = 40MHz
0.8
0.6
0.4
0.2
–40
0.2
–40
10
fIF = 500MHz
1.0
0.4
–30
–20
–10
0
IF INPUT CW POWER (dBm)
95
VCC = 3V
1.2
1.2
Phase Relation Between I and Q
Outputs vs LO Input Power
PHASE (DEG)
1.4
IF Detector Output Voltage vs IF
Input CW Power and IF Frequency
fIF = 284MHz, 25°C
fIF = 284MHz, –40°C
fIF = 284MHz, 85°C
fIF = 40MHz, 25°C
fIF = 500MHz, 25°C
92
91
90
89
–30
–20
–10
0
IF INPUT CW POWER (dBm)
5546 G16
10
5546 G17
VCC = 3V
88
–20 –15
0
–5
–10
LO INPUT POWER (dBm)
5
10
5546 G18
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PI FU CTIO S
GND (Pins 1, 4 and 17): Ground. Pins 1 and 4 are
connected to each other internally. The exposed pad (Pin
17) is not connected internally to Pins 1 and 4. For chip
functionality, the exposed pad and either Pin 1 or Pin 4
must be connected to ground. For best RF performance,
Pin 1, Pin 4 and the exposed pad should be connected to
RF ground.
IF+, IF– (Pins 2, 3): Differential Inputs for the IF Signal.
Each pin must be DC grounded through an external
inductor or RF transformer with central ground tap. This
path should have a DC resistance lower than 2Ω to ground.
EN (Pin 9): Enable Input. When the enable pin voltage is
higher than 1V, the IC is completely turned on. When the
input voltage is less than 0.5V, the IC is turned off, except
the part of the circuit associated with standby mode.
2xLO–, 2xLO+ (Pins 10, 11): Differential Inputs for the
2xLO Input. The 2xLO input frequency must be twice that
of the IF frequency. The internal bias voltage is VCC – 0.4V.
STBY (Pin 12): Standby Input. When the STBY pin is
higher than 1V, the standby mode circuit is turned on to
prebias the I/Q buffers. When the STBY pin is less than
0.5V, the standby mode circuit is turned off.
VCC (Pins 5 and 8): Power Supply. These pins should be
decoupled to ground using 1000pF and 0.1µF capacitors.
QOUT–, QOUT+ (Pins 13, 14): Differential Baseband Outputs of the Q Channel. Internally biased at VCC – 1.19V.
VCTRL (Pin 6): VGA Gain Control Input. This pin controls
the IF gain and its typical input voltage range is 0.2V to
1.7V. It is internally biased via a 25k resistor to 0.2V,
setting a low gain if the VCTRL pin is left floating.
IOUT–, IOUT+ (Pins 15, 16): Differential Baseband Outputs
of the I Channel. Internally biased at VCC – 1.19V.
IF DET (Pin 7): IF Detector Output. For strong IF input
signals, the DC level at this pin is a function of the IF input
signal level.
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LT5546
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BLOCK DIAGRA
VCC
VCC
5
IF + 2
VGA
8
I-MIXER
IF – 3
LPF
CLIPPER
16 IOUT+
15 IOUT–
90°
7 IF DET
VCTRL 6
2×LO +
DETECTOR
Q-MIXER LPF
11
÷2
0°
CLIPPER
2×LO – 10
9
1
EN
4
+
14 QOUT
17
12
STBY
–
13 QOUT
5546 BD
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APPLICATIO S I FOR ATIO
The LT5546 consists of a variable gain amplifier (VGA),
I/Q demodulator, quadrature LO generator, lowpass filters (LPFs), clipping amplifiers (clippers) and bias circuitry.
The IF signal is fed to the inputs of the VGA. The VGA gain
is typically set by an external signal in such a way that the
amplified IF signal delivered to the I/Q mixers is constant.
The IF signal is then converted into I/Q baseband signals
using the I/Q down-converting mixers. The quadrature LO
signals that drive the mixers are internally generated from
the on-chip divide-by-two circuit. The I/Q signals are
passed through first-order low-pass filters and subsequently a pair of hard-clipping amplifiers (clippers). After
externally setting the required gain, these amplifiers should
not clip. However, in the event of overload, they reduce the
settling time of any (optional) external AC coupling capacitors by preventing asymmetrical charging and discharging effects. The I/Q baseband outputs are buffered by
output drivers.
VGA and Input Matching
The VGA has a nominal 60dB gain control range with a
frequency range of 40MHz to 500MHz. The inputs of the
VGA must have a DC return to ground. This can be done
using a transformer with a central tap (on the secondary)
or an LC matching circuit with a matched impedance at the
frequency of interest and near zero impedance at DC. The
differential AC input impedance of the LT5546 is about
200Ω, thus a 1:4 (impedance ratio) RF transformer with
center tap can be used. In Figure 6, the evaluation board
schematic is shown using a 1:4 transformer. The measured input sensitivity of this board is about –80.5dBm for
a 10dB signal-to-noise ratio. In the case of an L-C matching circuit, the circuit of Figure 1 can be used. In Table 1
the matching network component values are given for a
range of IF frequencies. The matching circuit of Figure 1
approaches 180° phase shift between IF+ and IF– in a
broad range around its center frequency. However, some
amplitude mismatch occurs if the circuit is not tuned to the
center frequency. This leads to reduced circuit linearity
performance, because one of the inputs carries a higher
signal compared to the perfectly balanced case. A 10%
frequency shift from the center frequency results in about
a 2dB gain difference between the IF+ and IF– inputs. This
results in a 1.5dB higher IM3 contribution from the input
stage which leads to a 0.75dB drop in IIP3. Moreover, the
IIP2 of the circuit is also reduced which can lead to a higher
second order harmonic contribution. The circuit can be
driven single ended, but this is not recommended because
it leads to a 3dB drop in gain and a considerable increase
in IM5 and IM7 components. The single-ended noise
figure increases by 4dB if one IF input is directly grounded
and increases by 1.5dB if one IF input is grounded via a
1µH inductor. An IF input cannot be left open or connected
via a resistor to ground because this will disturb the
internal biasing, reducing the gain, noise and linearity
performance. For optimal performance, it is important to
keep the DC impedance to ground of both IF inputs lower
than 2Ω. In the matching network of Figure 1, inductor L3
is used for supplying the DC bias current to the IF+ input.
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LT5546
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APPLICATIO S I FOR ATIO
C3
56pF
L1
56nH
IF
INPUT
TO IF
IF
INPUT
+
TO IF +
C1
10pF
TO IF –
TO IF –
L3
120nH
C1
5.6pF
L2
56nH
L1
15nH
C2
5.6pF
L2
15nH
VBIAS
75Ω
1mA
1mA
IF +
75Ω
IF –
5546 F02
5546 F01
(2a)
(2b)
Figure 1. Example L-C IF Input Matching Network at 280MHz
Figure 2a. Simplified IF Input Matching Network at 280MHz
and Figure 2b. Simplified Circuit Schematic of the IF Inputs
Table 1. The Component Values of Matching Network L1, L2, L3,
C1, C2 and C3.
degrees, depending on the quality factor of the network.
This will result in a reduction in the gain. The higher the
chosen quality factor, the closer the phase difference will
approach 180 degrees. However, a higher quality factor
will reduce bandwidth and create more loss in the matching network. For minimum board space, 0402 components are used. The measured noise figure for maximum
gain with this matching network is about 9.4dB, and the
maximum gain is about 55dB. Assuming 0402 inductors
with Q = 35, the insertion loss of this network is about
2.5dB. The tolerance for the components in Figure 2a can
be 10% for a return loss higher than 10dB and a gain
reduction due to mismatch less than 0.5dB. The measured
input sensitivity for this matching network (see also Figure 11) is about –78.3dBm for a 10dB signal-to-noise
ratio.
fIF(MHz)
L1, L2(nH)
C1, C2(pF)
L3(nH)
C3(pF)
50
340
34
1800
820
100
159
15.9
470
220
150
106
10.6
470
220
200
80
8.0
470
220
250
64
6.4
120
56
300
53
5.3
120
56
350
45
4.5
120
56
400
40
4.0
120
56
450
35
3.5
120
56
500
32
3.2
120
56
To keep the DC resistance of L3 below 2Ω, 120nH is used.
This disturbs the matching network slightly by causing the
frequency where the S11 is minimal to be lower than the
frequency where the amplitudes of IF+ and IF– are equal.
To compensate for this, the value of coupling capacitor C3
is lowered and will contribute some correcting reactance.
For low frequencies, it might not be possible to find any
practical inductor value for L3 with DC resistance smaller
than 2Ω. In that case it is recommended to use a transformer with a center tap. The tolerance for the components
in Figure 1 can be 10% for a return loss higher than 16dB
and a gain reduction due to mismatch less than 0.3dB.
It is possible to simplify the input matching circuit and
compromise the performance. In Figure 2a, the simplified
matching network is given.
This matching network can deliver equal amplitudes to the
IF + and IF – inputs for a narrow frequency region, but the
phase difference between the inputs will not be exactly 180
degrees. In practice, the phase shift will be around 145
The gain of the VGA is set by the voltage at the VCTRL pin.
For high gain settings, both the noise figure and the input
IP3 will be low. From a noise figure point of view, it is
advantageous to work as closely as possible to the maximum gain point. However, if the voltage at the VCTRL pin
is increased beyond the maximum gain point (where
additional increase in control voltage does not give an
increase in gain), the response time of the gain control
circuit is increased. If control speed is crucial, a few dB of
gain margin should be allowed from the highest gain point
to be sure that at all temperatures, the maximum gain
setting is not crossed. At low gain settings, the noise figure
and the input IP3 will be high. Optionally, the control
voltage VCTRL can be set lower than 0.2V. The normal
range is from VCTRL = 0.2V to 1.7V, which results in a
nominal gain range from 1.6dB to 56.8dB. The linear-indB gain relation with the VCTRL voltage still holds for
control voltages as low as –0.35V. This results in an
5546fa
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LT5546
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extended gain control range of –23dB to 57dB. The VCTRL
pin is a very sensitive input because of its high input
impedance and therefore should be well shielded. Signal
pickup on the VCTRL pin can lead to spurs and increased
noise floor in the I/Q baseband outputs. It can degrade the
linearity performance and it can cause asymmetry in the
two-tone test. If control speed is not important, 1µF
bypass capacitors are recommended between VCTRL and
ground.
VCC
VCC
+
400mV
–
2xLO +
8k
8k
2xLO –
IF DET
1k
3.8k
5546 F03
A fast responding peak detector is connected to the VGA
input, sensitive to signal levels above the signal levels
where the VGA is operating in the linear range. It is active
from –22dBm up to 5dBm IF input signal levels. The DC
output voltage of this detector (IF DET) can be used by the
baseband controller to quickly determine the presence of
a strong input level at the desired channel, and adjust gain
accordingly. Figure 3a shows the simplified circuit schematic of the IF DET output.
(3b)
(3a)
Figure 3a. Simplified Circuit Schematic of the
IF DET Output and Figure 3b. The 2xLO Inputs
3.3pF
2xLO
INPUT
100pF
2xLO
INPUT
TO 2xLO+
39nH
2xLO
INPUT
1:4
TO 2xLO–
TO 2xLO+
56Ω
TO 2xLO+
TO 2xLO–
240Ω
100pF
3.3pF
TO 2xLO–
I/Q Demodulators
The quadrature demodulators are double balanced mixers, down-converting the amplified IF signal from the VGA
into I/Q baseband signals. The quadrature LO signals are
generated internally from a double frequency external CW
signal. The nominal output voltage of the differential I/Q
baseband signals should be set to 0.8VP-P or lower,
depending on the linearity requirements. The magnitudes
of I and Q are well matched and their phases are 90° apart.
Quadrature LO Generator
The quadrature LO generator consists of a divide-by-two
circuit and LO buffers. An input signal (2xLO) with twice
the desired IF signal frequency is used as the clock for the
divide-by-two circuit, producing the quadrature LO signals
for the demodulators. The outputs are buffered and then
drive the down-converting mixers. With a fully differential
approach, the quadrature LO signals are well matched.
Second harmonic content (or higher order even harmonics) in the external 2xLO signal can degrade the 90° phase
shift between I and Q. Therefore, such content should be
minimized. In disable or standby mode, the divide-by-two
stage is powered down. After enabling the circuit, the phase
relation between the IF signal and the baseband (I or Q)
signals can be either 0° or 180°, since the circuit cannot
distinguish between the two subsequent identical sinusoi-
5546 F04
(4a)
(4b)
(4c)
Figure 4. 2xLO Input Matching Networks for 4a) Narrow Band
Tuned to 570MHz, 4b) Wide Band, 4c) Single-Ended Wide Band
dal waveforms of the 2xLO input signal. The phase relation between I and Q is always 90°, i.e. I always leads Q by
90° for fIF > 1/2 • f2xLO. Figure 3b shows the simplified circuit
schematic of the 2xLO inputs. Depending on the application, different 2xLO input matching networks can be chosen. In Figure 4, three examples are given. The first network provides the best 2xLO input sensitivity because it
can boost the 2xLO differential input signal using a narrow-band resonant approach. The second network gives
a wide-band match, but the 2xLO input sensitivity is about
2dB lower. The third network gives a simple and less
expensive wide-band match, but 2xLO input sensitivity
drops by about 9dB. The IF input sensitivity doesn’t change
significantly using any of the three 2xLO matching
networks.
Baseband Circuit
The baseband circuit consists of I/Q low-pass filters, I/Q
hard limiters (clippers) and I/Q output buffers. The hard
limiters operate as linear amplifiers normally. However, if
a high level input temporarily overloads a linear amplifier,
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then the circuit will limit symmetrically, which will help to
prevent the output buffer from overloading. This speeds
up recovery from an overload event, which can occur
during the gain settling. The clipping level is approximately constant over temperature. The first order integrated lowpass filters are used for noise filtering of the
down-converted baseband signals for both the I channel
and the Q channel. These filters are well matched in gain
response. The –3dB corner frequency is typically 17MHz.
The I/Q outputs can drive 2kΩ in parallel with a maximum
capacitive loading of 10pF at 5MHz, from all four pins to
ground. The outputs are internally biased at VCC – 1.19V.
Figure 5 shows the simplified output circuit schematic of
the I channel or Q channel.
large charging time constants. Table 2 shows the logic of
the EN pin and STBY pin. In both normal operating mode
and standby mode, the maximum discharging current is
about 300µA, and the maximum charging current is more
than 4mA. In Figure 5 the simplified circuit schematic of
the STBY (or EN) input is shown.
Table 2. The Logic of Different Operating Modes
EN
STBY
Comments
Low
Low
Shutdown Mode
Low
High
Standby Mode
High
Low or High
Normal Operation Mode
VCC
The I/Q baseband outputs can be DC-coupled to the inputs
of a baseband chip. For AC-coupled applications with large
capacitors, the STBY pin can be used to pre-bias the
outputs to nominal VCC – 1.19V at much reduced current.
This mode draws only 3.6mA supply current. When the EN
pin is then driven high (>1V), the chip is quickly switched
to normal operating mode, avoiding the introduction of
OPTIONAL
VCC
IOUT+
(OR QOUT+)
IOUT–
(OR QOUT–)
I CHANNEL (OR
Q CHANNEL):
DIFFERENTIAL
SIGNALS
FROM LPF
300µA
300µA
5546 F05
Figure 5. Simplified Circuit Schematic of I Channel
(or Q Channel) Outputs and STBY (or EN) Input
IOUT+ IOUT– QOUT+ QOUT–
VCC3
C37
0.1µF
J1
22k
STBY
(OR EN)
R47
49.9Ω
C31
1µF
7
IOUT
+
U3
LT1818CS
6
–
4
R48
3.09k
C35
4.7µF
R50
2k
C1
5.6pF
R46
3.09k
R49
2k
R39
3.09k
3
C2
5.6pF
2
+
C32
1pF
–
C29
1pF
16
15
14
C30
1µF
7
U2
LT1818CS
R42
2k
C28
0.1µF
C33
0.1µF
5V
C38
0.1µF
R43
2k
C27
0.1µF R41
1k
C34
R45 0.1µF
1k
3
2
C36
4.7µF
6
R44
49.9Ω
J2
QOUT
4
R40
3.09k
13
IOUT+ IOUT– QOUT+ QOUT–
J3
IFIN
C43
22nF
T1, 1:4,TR-R
JTX-4-10T
MINI-CIRCUITS
1
6
1
2
3
4
GND
STBY
IF +
U1
LT5546
IF –
2XLO+
2XLO –
GND
EN
T2, 1:4, TR-R C45
22nF
JTX-4-10T
MINI-CIRCUITS
12
R35
20k
J4
11
VCC2
2XLO
R52
240Ω
10
6
9
1
R36
20k
IF
VCC VCTRL DET VCC
5
6
7
8
17
GND
1 = EN
2 = STBY
VCC1
C22
1µF
C15
1nF
C16
1nF
VCTRL
R51
100Ω
C25
1.5pF
SW1
OVERLOAD
C26
NOTE: OUTPUT BUFFERS U2 AND U3 WITH ASSOCIATED
1.8pF COMPONENTS ARE INCLUDED FOR EVALUATION ONLY.
DEMO BOARD: DC696A
C43, C45, C22, R51, C25, C26 AND C39 ARE OPTIONAL
C39
1µF
5546 F04
Figure 6. Evaluation Circuit Schematic with I/Q Output Buffers
5546fa
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Evaluation Board
The evaluation circuit schematic is drawn in Figure 6. The
components associated with buffers U2 and U3 are included to drive a 50Ω load for evaluation purposes only.
There is a unity voltage gain relationship for AC signals
between the evaluation board outputs (I and Q) and the
IOUT+, IOUT– or QOUT+ and QOUT– outputs of the LT5546
when the evaluation board outputs are terminated in 50Ω.
Figure 7. Component Side Silkscreen of Evaluation Board
Figure 8. Component Side Layout of Evaluation Board
Figure 9. Bottom Side Silkscreen of Evaluation Board
Figure 10. Bottom Side Layout of Evaluation Board
15nH
1.8V
RX INPUT:
2.4GHz TO 2.5GHz
1µF
10pF
280MHz
IF SAW BP FILTER
VCC 5, 8
2
VGA
RX
FRONT END
1ST LO,
2.12GHz
TO 2.22GHz
MAIN
SYNTHESIZER
AUX
SYNTHESIZER
15nH
1nF
I-MIXER
LPF
BASEBAND
PROCESSOR
HARD
CLIPPER
3
16
15
I-OUTPUTS
7
IF DET
6
VCTRL
14
13
Q-OUTPUTS
0°
Q-MIXER
2ND LO,
560MHz
–10dBm
90°
11
3.3pF
39nH
LPF
A/D
D/A
A/D
HARD
CLIPPER
f/2
12
10
LT5546
3.3pF
A/D
STBY
9
1,4,17
EN
5546 F11
Figure 11. 2.4GHz to 2.5GHz Receiver Application (RX IF = 280MHz)
5546fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT5546
U
PACKAGE DESCRIPTIO
UF Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1692)
BOTTOM VIEW—EXPOSED PAD
0.75 ± 0.05
4.00 ± 0.10
(4 SIDES)
0.72 ±0.05
4.35 ± 0.05
R = 0.115
TYP
15
PIN 1 NOTCH R = 0.20 TYP
OR 0.35 × 45° CHAMFER
16
0.55 ± 0.20
PIN 1
TOP MARK
(NOTE 6)
1
2.15 ± 0.05
(4 SIDES)
2
2.15 ± 0.10
(4-SIDES)
2.90 ± 0.05
(UF16) QFN 10-04
0.30 ± 0.05
0.200 REF
0.30 ±0.05 PACKAGE OUTLINE
0.65 BSC
0.00 – 0.05
0.65 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
RELATED PARTS
PART NUMBER
Infrastructure
LT5511
LT5512
LT5515
DESCRIPTION
COMMENTS
High Signal Level Upconverting Mixer
High Signal Level Downconverting Mixer
1.5GHz to 2.5GHz Direct-Conversion
Quadrature Demodulator
LT5516
800MHz to 1.5GHz Direct-Conversion
Quadrature Demodulator
LT5522
600MHz to 2.7GHz High Signal Level
Downconverting Mixer
RF Power Detectors
LT5504
800MHz to 2.7GHz RF Measuring Receiver
LTC5505
RF Power Detectors with >40dB Dynamic Range
LTC5507
100kHz to 1000MHz RF Power Detector
LTC5508
0.3GHz to 7GHz RF Power Detector
LTC5509
300MHz to 3GHz RF Power Detector
LTC5532
300MHz to 7GHz Precision RF Power Detector
RF Receiver Building Blocks
LT5500
1.8GHz to 2.7GHz Receiver Front End
LT5502
400MHz Quadrature IF Demodulator with RSSI
LT5503
1.2GHz to 2.7GHz Direct IQ Modulator and Mixer
LT5506
40MHz to 500MHz Quadrature IF Demodulator
with VGA
RF Output to 3GHz, 17dBm IIP3, Integrated LO Buffer
DC-3GHz, 20dBm IIP3, Integrated LO Buffer
20dBm IIP3, NF =16.8dB, Integrated LO Quadrature Generator
4V to 5.25V Supply, 21.5dBm IIP3, NF = 12.8dB,
Integrated LO Quadrature Generator
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50Ω Single-Ended
RF and LO Ports
2.7V to 5.25V Supply, 80dB Dynamic Range, Temperature Compensated
2.7V to 6V Supply, 300MHz to 3.5GHz, Temperature Compensated
2.7V to 6V Supply, 48dB Dynamic Range, Temperature Compensated
2.7V to 6V Supply, 44dB Dynamic Range, Temperature Compensated
–30dBm to 6dBm, 600µA Supply Current, Temperature Compensated
Precision VOUT Offset Control, Adjustable Gain and Offset
1.8V to 5.25V Supply, Dual-Gain LNA, Mixer
1.8V to 5.25V Supply, 70MHz to 400MHz IF, 84dB Limiting Gain, 90dB RSSI Range
1.8V to 5.25V Supply, Four Step RF Power Control, 120MHz Modulation Bandwidth
1.8V to 5.25V, I/Q Baseband Bandwidth 8.8MHz, –40dB to 57dB Linear Power Gain
5546fa
12
Linear Technology Corporation
LT/LWI/LT 0705 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2003
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