ICST ICS83840BHLF Ddr sdram mux Datasheet

ICS83840B
Integrated
Circuit
Systems, Inc.
DDR SDRAM MUX
GENERAL DESCRIPTION
FEATURES
The ICS83840B is a DDR SDRAM MUX and is
ICS
a member of the HiPerClockS™ family of High
HiPerClockS™ Performance Clock Solutions from ICS. The device has 10 Host Lines and each host line can
be passed to 4 Data Ports. The 10 channels are
allocated as follows in the DDR SDRAM application: 8 data lines, 1 strobe line and 1 DQm line. The Host/
Data Ports are compatible with single-ended SSTL-2 and the
device operates from a 2.5V supply.
• 40 low skew single-ended DIMM ports
Guaranteed low output skew makes the ICS83840B ideal
for demanding applications which require well defined performance and repeatability.
• 0°C to 70°C ambient operating temperature
SIMPLIFIED SCHEMATIC
LOGIC DIAGRAM
• 4 SSTL-2 compatible enable inputs
• Maximum Switching Speed: 3ns
• Output skew: 120ps (maximum)
• Bank skew: 60ps (maximum)
• ron = 8Ω (typical)
• Full 2.5V supply modes
• Pin compatible with the CBTV4010
HP0
RON
0DP0
Sw
1DP0
Sw
2DP0
Sw
HPx
nDPx
Sw
3DP0
400Ω
HP9
RON
0DP9
Sw
1DP9
Sw
nSn
2DP9
Sw
Sw
3DP9
nS0
SW
nS1
nS2
nS3
PIN ASSIGNMENT
1
2
3
A
VDD
nS1
nc
B
nS2
VDD
nS0
C
nc
nS3
GND
3DP2
3DP9
0DP3
1DP3
D
E
2DP9
4
GND
5
6
7
1DP0
2DP0
3DP0
0DP0
HP0
0DP1
8
1DP1
9
10
11
2DP1
3DP1
0DP2
HP1
GND
1DP2
HP2
2DP2
F
1DP9
HP9
HP 3
2DP3
G
H
0DP9
3DP8
GND
3DP3
2DP8
0DP4
J
1DP8
HP8
K
L
0DP8
GND
HP7
3DP7
2DP7
1DP7
83840BH
0DP7
3DP6
HP6
GND
2DP6
1DP6
0DP6
3DP5
HP4
1DP4
HP5
3DP4
2DP4
2DP5
1DP5
0DP5
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1
ICS83840B
64-Ball TFBGA
7mm x 7mm x 1.2mm
package body
H Package
Top View
REV. A JANUARY 30, 2004
ICS83840B
Integrated
Circuit
Systems, Inc.
DDR SDRAM MUX
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
A1, B2
VDD
Power
Positive supply pins.
B4, B10, D2, G10, K2, K7
GND
Power
Power supply ground.
A 3, C 1
nc
Unused
No connect.
A2, B1, C2, B3
B6, B9, C10, F2, F10,
J2, J10, K3, K6, K9
A5, A6, A7, B5
nS1, nS2, nS3, nS0
HP0, HP1, HP2, HP9, HP3,
HP8, HP4, HP7, HP6, HP5
1DP0, 2DP0, 3DP0, 0DP0
Por t
Select pins.
Por t
Host por ts.
Por t
DIMM por ts.
A9, A10, B7, B8
2DP1, 3DP1, 0DP1, 1DP1
Por t
DIMM por ts.
A11, B11, C11, D10
0DP2, 1DP2, 2DP2, 3DP2
Por t
DIMM por ts.
E10, E11, F11, G11
ODP3, 1DP3, 2DP3, 3DP3
Por t
DIMM por ts.
H10, J11, K10, K11
0DP4, 1DP4, 3DP4, 2DP4
Por t
DIMM por ts.
K8, L9, L10, L11
3DP5, 2DP5, 1DP5, 0DP5
Por t
DIMM por ts.
K5, L5, L6, L7
3DP6, 2DP6, 1DP6, 0DP6
Por t
DIMM por ts.
K4, L1, L2, L3
0DP7, 3DP7, 2DP7, 1DP7
Por t
DIMM por ts.
G2, H2, J1, K1
3DP8, 2DP8, 1DP8, 0DP8
Por t
DIMM por ts.
E1, E2, F1, G1
2DP9, 3DP9, 1DP9, 0DP9
Por t
DIMM por ts.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
nSx
VI = 0V or VDD
5
pF
CON
Channel on Capacitance
HPx
VIN = 1.5V
14
pF
NOTE: Capacitance values are measured at 10MHz and a bias voltage 3V. Capacitance is not production tested.
TABLE 3. FUNCTION TABLE
Control Input
nSx
L
H
83840BH
Function
Host Por t = DIMM Por t
Host Por t = Disconnected
DIMM Por t = 400Ω to GND
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2
REV. A JANUARY 30, 2004
ICS83840B
Integrated
Circuit
Systems, Inc.
DDR SDRAM MUX
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
-0.5V to +3.3V
NOTE: Stresses beyond those listed under Absolute
Inputs, VI
-0.3V to VDD + 0.3 V
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
Ports
operation of product at these conditions or any conditions be-
DC Input Clamp Current, IIK
-50mA
Package Thermal Impedance, θJA
50.04°C/W (0 mfps)
istics is not implied. Exposure to absolute maximum rating
-65°C to 150°C
conditions for extended periods may affect product reliability.
Storage Temperature, TSTG
yond those listed in the DC Characteristics or AC Character-
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V ± 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
VDD
Positive Supply Voltage
IDD
Power Supply Current
Minimum
Typical
Maximum
Units
2.3
2.5
2.7
V
50
µA
Maximum
Units
TABLE 4B. DC CHARACTERISTICS, VDD = 2.5V ± 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
VIH
Input High Voltage
nSx
VIL
Input Low Voltage
nSx
VIK
Input Clamp Voltage
IL
Input Leakage
Current
nSx
Host Por t
DIMM Por t
rON
On Resistance; NOTE 1
Minimum
Typical
1.6
V
0.9
V
VDD = 2.3V; II = -18mA
-1.2
V
VDD = 2.5V; VI = VDD or GND;
nS = VDD
±100
µA
±100
µA
nS = GND for IIL(test)
±100
µA
13
Ω
VDD = 2.5V; VA = 0.8V; VB = 1.0V
5
8
5
8
13
VDD = 2.5V; VA = 1.7V; VB = 1.5V
Ω
NOTE 1: Calculated from the current measure, between the Host and the DIMM terminals at the indicated voltages on
each side of the switch.
TABLE 5. AC CHARACTERISTICS, VDD = 2.5V ± 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Propagation Delay;
From HPx or xDPx to
tPD
80
160
250
ps
NOTE 1, 4
xDPx or HPx
Output
From nSx to
1.2
ns
t EN
Enable Time
HPx or nDPx
Output
From nSx to
tDIS
1.2
ns
Disable Time
HPx or nDPx
Output Skew;
Any Por t to any Por t
120
ps
tOSK
NOTE 2, 4
Bank Skew;
Any Por t to any Por t
60
ps
tBSK
NOTE 3, 4
within the same bank
NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew within a bank with equal load conditions.
NOTE 4: Not production tested, guaranteed by characterization.
83840BH
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3
REV. A JANUARY 30, 2004
ICS83840B
Integrated
Circuit
Systems, Inc.
DDR SDRAM MUX
PARAMETER MEASUREMENT INFORMATION
VDD = 1.25V ± 0.1V
V
SCOPE
V DD
DD
nDPx
2
Qx
LVCMOS
V
DD
nDPy
GND
2
t sk(o)
-1.25V ± 0.1V
This circuit is used for test purposes only,
not intended for application use.
2.5V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Sn
(Low-level
enabling)
VDD
2
XDP0:XDP9
2.5V
1.25V
1.25V
0V
VDD
2
XDP0:XDP9
tPZH →
t sk(o)
Output nDPx
(See Note)
tPHZ
→
1.25V
←
VOH
VOH - 0.15V
VOL
NOTE: The output is high except when disabled by the Sn control.
BANK SKEW (where X denotes outputs in the same bank)
3-STATE OUTPUT ENABLE/DISABLE TIMES
VDD
2
D or H
VDD
2
H or D
t
PD
PROPAGATION DELAY
83840BH
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4
REV. A JANUARY 30, 2004
ICS83840B
Integrated
Circuit
Systems, Inc.
DDR SDRAM MUX
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
θJA by Velocity (Millimeter Feet per Second)
Two-Layer PCB, JEDEC Standard Test Boards
0
1
2
50.04°C/W
43.18°C/W
41.17°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83840B is: 320
83840BH
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5
REV. A JANUARY 30, 2004
ICS83840B
Integrated
Circuit
Systems, Inc.
DDR SDRAM MUX
PACKAGE OUTLINE - H SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
FBGA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
64 Balls, 7x7mm, 11x11 Pattern
A
1.0
1.1
1.2
A1
0.165
0.2
0.235
A2
0.16
0.2
0.24
A3
0.675
0.7
0.725
b
0.25
0.3
0.35
D
7.00 BSC
D1
5.00 BSC
E
7.00 BSC
E1
5.00 BSC
e
0.50 BSC
REFERENCE DOCUMENT: JEDEC PUBLICATION 95
83840BH
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6
REV. A JANUARY 30, 2004
ICS83840B
Integrated
Circuit
Systems, Inc.
DDR SDRAM MUX
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS83840BH
ICS83840BH
64-Ball TFBGA
416 per tray
0°C to 70°C
ICS83840BHT
ICS83840BH
64-Ball TFBGA on Tape and Reel
1000
0°C to 70°C
ICS83840BHLF
ICS3840BLF
64-Ball, Lead Free, TFBGA
416 per tray
0°C to 70°C
ICS83840BHLFT
ICS3840BLF
64-Ball, Lead Free, TFBGA on Tape and Reel
1000
0°C to 70°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
83840BH
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7
REV. A JANUARY 30, 2004
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