Mitel MT9080B Cmos smx - switch matrix module Datasheet

CMOS MT9080B
SMX - Switch Matrix Module
Features
DS5140
ISSUE 4
March 1999
Ordering Information
•
•
•
•
•
•
16 bit wide data bus I/O
16 bit address bus
Microprocessor Interface
2048 x 16 bit wide memory SRAM
Interfaces with Mitel’s MT9085B to form larger
switch mitoses
Variable clock and frame rates
MT9080BP
-40°C to 70°C
Description
The MT9080B is a flexible memory module suitable
for use as a basic building block in the construction
of customized digital switching matrices. It can be
configured as either a Data Memory or a Connection
Memory, and is designed to interface with Mitel’s
MT9085B. Interface to the device is via 16 bit wide
data and address busses. The MT9080B can
operate with variable clock rates up to 16.7 MHz.
Applications
•
•
•
Small and medium digital switch matrices
Telephony equipment - PBX, CO equipment,
digital cross connect, digital local loop
Datacom equipment - access concentrators,
Lan/Wan gateways
16
16
D0i/D15i
A0-A15
84 Pin PLCC
D0o/
D15o
2048 x 16
16
Static
Memory
16
Address
MUX
CRC
11
WR
ENABLE
11 Bit
Counter
PRECHARGE
CD
Control Interface
Counter
Reset
ME
FP
CK
ODE DS
CS R/W
Mx
My
Mz
DTA
Figure 1 - Functional Block Diagram
2-101
D9o
D8o
D10o
76
D11o
VSS
78
D12o
D13o
80
D14o
D15o
82
VDD
VSS
84
D0i
D1i
2
D2i
D3i
4
VSS
D4i
6
D5i
D6i
12
8
D7i
D8i
VSS
CMOS
10
MT9080B
74
D9i
D10i
D7o
14
72
16
70
18
68
20
66
D11i
VSS
22
64
62
26
60
28
58
30
56
A12
A11
DTA
A10
A8
A7
54
A6
A5
52
50
A4
A3
A2
A1
48
46
A0
NC
44
VDD
VSS
IC
IC
42
40
NC
Mz
My
Mx
38
36
ME
ODE
NC
34
A9
32
VSS
NC
A14
A13
DS
R/W
CD
A15
FP
CS
VSS
VDD
24
IC
IC
D1o
D0o
84 PIN PLCC
VDD
VSS
D3o
D2o
VSS
CK
D4o
VSS
D14i
D15i
D6o
D5o
D12i
D13i
VSS
Figure 2 - Pin Connections
Pin Description
Pin #
Name
1
VSS
2-5
D0i-D3i
6
VSS
7-10
D4i-D7i
11
VSS
12-15
16
17-20
Description
Ground.
Input/Microport Data Bus. This is part of a 16 bit data bus. The data bus is bidirectional in
Connect Memory mode where it is typically interfaced to a microprocessor. In all other
modes the data bus is an input. Data to be switched through the device is clocked in at this
port.
Ground.
Input/Microport Data Bus. See description for pins 2-5 above.
Ground.
D8i-D11i Input/Microport Data Bus. See description for pins 2-5 above.
VSS
Ground.
D12i-D15i Input/Microport Data Bus.
See description for pins 2-5 above.
21
VSS
Ground.
22
CK
Clock. Master clock input which is used to clock data into and out of the device. It also clocks
the internal 11 bit counter.
23
VDD
+5V supply input.
24
VSS
Ground.
25,26
IC
Internal Connection. Should be tied to VSS for normal operation.
27
FP
Frame Pulse. An active low signal that serves as a synchronous clear for the internal 11 bit
counter in all modes except Shift Register mode. The counter is cleared on a rising edge of
CK. In the Shift Register mode, FP serves to align channel boundaries.
2-102
CMOS
MT9080B
Pin Description
Pin #
Name
Description
28
CS
Chip Select. Active Low input. Selects the device for microport access in connect memory,
data memory, external and shift register modes. Tying CS high will disable output data
drivers (D0-D15o) in all modes except connect memory and shift register modes.
29
DS
Data Strobe. Active low input. Indicates to the SMX that valid data is present on the
microport data bus during a write operation or that the SMX must output data on a read
operation.
In Connect Memory modes, a low level applied to this input during a write operation indicates
to the SMX that valid data is present on the microport data bus. During a read operation the
low going signal indicates to the SMX that it must output data on the microport data bus.
In Data Memory and External modes, when DS is high, the output data bus D0o-D15o will be
disabled. The input data bus D0i-D15i is not affected.
The DS input has no effect on the input and output busses in Counter or Shift Register
modes.
30
R/W
Read/Write Enable. Data is written into the device when R/W is low and read from it when it
is high. This control input is disabled in data memory and shift register modes. It should be
tied to VSS or VDD in these modes. In counter and external modes, the state of R/W pin is
clocked in with the rising edge of CK. The actual read or write operation will be implemented
on the next rising clock edge.
31
DTA
Data Transfer Acknowledge. Open drain output which is pulled low to acknowledge
completion of microport data transfer. On a read of the SMX, DTA low indicates that the SMX
has put valid data on the data bus. On a write, DTA low indicates that the SMX has
completed latching the data in.
32
NC
No Connection.
33
VSS
Ground.
34
NC
No Connection.
35
ODE
Output Data Enable. Control input which enables the output data bus. Pulling this input low
will place the data bus in a high impedance state. The level on this pin is latched by a rising
edge of CK. The output drivers will be enabled or disabled with the rising edge in the next
timeslot (see Fig. 24 for applicable timing in different modes).
36
ME
Message Enable. When tied high the data latched in on the address bus is clocked out on
D0o-D15o. When ME is tied low, the contents of the addressed memory location will be
output on the bus. The level on this pin is latched in with the rising edge of the clock. The
actual mode change is implemented on the rising edge in the next timeslot. Refer to Figures
25 and 26 for more timing information.
37
Mx
Mode X. One of three inputs which permit the selection of different operating modes for the
device. Refer to Table 1 for description of various modes.
38
My
Mode Y. See description for pin 37.
39
Mz
Mode Z. See description for pin 37.
40
NC
No Connection.
41, 42
IC
Internal Connection. Leave open for normal operation.
43
VSS
Ground.
44
VDD
Supply Voltage. +5V.
45
NC
No Connection.
2-103
MT9080B
CMOS
Pin Description
Pin #
Name
Description
46-61
A0-A15
Address Bus. These inputs have three different functions. Inputs A0-A10 are used to
address internal memory locations during read or write operations in all modes except Shift
Register mode. In Shift Register mode, the levels latched in on A0-A10 program the delay
through the device. When the ME pin is tied high, the data latched in on A0-A15 is clocked
out on to the data bus (D0o-D15o).
62
CD
Change Detect. Open drain output which is pulled low when a change in the memory
contents from one frame to the next is detected by a Cyclic Redundancy Check (CRC).
Changes in memory contents resulting from microprocessor access do not cause CD to go
low. The output is reset to its normal high impedance state when the DS input is strobed,
while the device has been selected (CS is low).
63
VDD
Supply Voltage. +5V.
64
VSS
Ground.
65-68
69
70-73
74
D0o-D3o Output Data Bus. These three state outputs are part of a 16 bit data bus which is used to
clock out data from the device. Data is clocked out with the rising edge of the clock. See
Figures 24 to 26 for timing information. The bus is actively driven when ODE is tied high. It is
disabled when ODE is tied low. Tying CS high will also disable the output data bus in all
modes except Connect Memory and Shift Register Modes.
VSS
Ground.
D4o-D7o Output Data Bus. See description for pins 65-68.
VSS
Ground.
75-78 D8o-D11o Output Data Bus. See description for pins 65-68.
79
80-83
84
2-104
VSS
Ground.
D12o-D15 Output Data Bus. See description for pins 65-68.
o
VDD
Supply Voltage. +5V.
MT9080B
CMOS
Functional Description
Data Memory Mode-1
The SMX is a flexible memory module suitable for
use in the construction of timeslot interchange
circuits used in PCM voice or data switches. The
device can be configured as a data memory or a
connection memory.
Data Memory Mode-1 is designed for use in the
construction of a 1024 Channel Switch Matrix. Data
on the D0-D15 input bus is clocked into the SMX and
stored in memory locations addressed by the internal
11 bit counter. Data is clocked out according to the
addresses asserted on the address bus. The pin
configuration of the device in this mode is illustrated
in Figure 3
The SMX has separate 16 bit input and output data
busses. A 16 bit address bus and a full
microprocessor interface is also provided.
Data is clocked into and out of the device with the
signal applied at the CK (clock) input. Depending on
the mode of operation, the memory locations for the
read or write operation can be addressed
sequentially by the internal counter or randomly via
the external address bus. A messaging sub-mode,
which permits the data latched in on the address bus
to be multiplexed on to the output data bus, is also
available (see ME pin description).
CK
FP
Data
Output
Data
Input
16
D0o-D15o
D0i-D15i
16
CS
DS
CD
DTA
The SMX ensures integrity of the stored data by
performing a Cyclic Redundancy Check (CRC) on a
per frame basis. When a change in the memory
contents is detected from one frame to the next, the
Change Detect (CD) pin is pulled low. The output will
be reset to its normal high impedance state when DS
input is strobed while CS is low (i.e., while the device
has been selected for microprocessor access). The
CD output is not pulled low when the memory
contents have been modified by a processor access
to the device.
Modes Of Operation
The SMX can be programmed to operate in one of
eight modes as summarized in Table 1. The different
modes are used to realize specific switch
implementations. For example, to implement a 1024
channel switch, two SMXs are required. One is
operated in Data Memory mode, while the second is
operated in Connect Memory mode. A 2048 channel
switch can be realized using three SMXs. Two of the
devices are operated, alternatively, in Counter and
External modes, the third serves as the Connection
Memory.
A
detailed
description
of
the
implementation is presented in the Applications
section of this data sheet. An outline of the device
functionality in each mode is presented below.
Mode
MX
MY
MZ
1
2
3
4
5
6
7
8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Name
Data Memory - 1
Data Memory - 2
Connect Memory - 1
Connect Memory - 2
Counter Mode
External Mode
Shift Register Mode
Data Memory - 3
Table 1. SMX Modes of Operation
Abbr.
DM-1
DM-2
CM-1
CM-2
CNT
EXT
SR
DM-3
MODE
A0-A15
ME
ODE Z
Y
Z
From Control Interface
Figure 3 - Data Memory Modes 1 and 2 Pinout
The timing for the read and write operation is
illustrated in Figure 4. The first half of each clock
period is used for precharging the internal bus. Data
is latched in and out of the device with rising edge of
the CK clock. Correct operation of the device in this
mode requires 2048 clock cycles in a single frame
defined by the frame pulse. Consequently, for
switching of 64 kbit/s PCM voice channels, the clock
frequency must be 16.384 Mbit/s with a frame rate of
8 kHz.
The address supplied on the address bus is latched
in with the first positive clock edge in a channel
timeslot. The contents of the memory location
addressed will be clocked out on D0-D15o with the
first positive clock edge in the next timeslot (see
Figure 4).
In Data Memory Mode-1, the delay through the
switch depends on the number of channel timeslots
between the input channel and the output channel. If
the time difference between the input channel and
output channel is less than two channels, data
clocked into the device in the current frame will be
clocked out in the next frame. If the difference is
greater than or equal to two channels, data will be
clocked out in the same frame.
This concept is
further illustrated in Figure 5.
2-105
MT9080B
CMOS
➀
②
➂
P
CK
External
Address
Bus A0-A15
CH X
W
P
➃
R
CH Y
CH Z
Data Output
D0-D15o
CH X
CH Y
CH Z
FP
Counter Reset
Address
generated by
Internal 11
Bit Counter
1023
1022
Data Input
D0-D15i
0
1023
1
0
1
2
P = Precharge
R = Read Memory
W = Write Memory
Data is clocked out of the memory location addressed by external address bus. The address is latched in with CK edge
marked ➀. Data is clocked out with CK edge marked ②.
Data is latched into the device with the last rising edge of CK in the timeslot (e.g., edge ➂ in diagram). It is stored in the
memory location address by the internal 11 bit counter with the next rising clock edge (edge ➃ in diagram).
Figure 4 - Data Memory Mode Functional Timing
➀
②
P
CK
Input
Data
W
P
2
1
Output
Timeslots
1
R
2
3
3
4
4
P = Precharge
R = Read Memory
W = Write Memory
Data on the input bus of the SMX is latched into the device with last rising edge of the clock within a timeslot. It is
written into the internal memory with the following positive edge.
Data is clocked out of the memory location and latched onto the output data bus with first positive clock edge in the
timeslot.
Switching channel 1 to channel 1 or channel 2 will result in one frame delay. Note that channel 2 is clocked out by CK
edge labelled ➀ while channel 1 is written into the memory with edge ②. However, if channel 1 is switched to channel
3, there will be only one channel delay.
Figure 5 - Throughput Delay in Data Memory Mode-1
2-106
5
CMOS
This mode provides minimum delay through the SMX
for any switching configuration.
Data Memory Mode-2
Data Memory Mode-2 is designed for use in
constructing a 1024 by 1024 channel double buffered
switch. This mode is similar in most respects to Data
Memory Mode-1. The double buffering is achieved by
dividing the internal 2048 memory into two equal
blocks. In a single frame, data is written into the first
block and read from the second. In the next frame,
the data will be written into the second and read from
the first (see Figure 6). Frame sequence integrity of
the data will be maintained for all switching
configurations if the output frame is delayed by one
channel with respect to the input frame. In this case,
data clocked into the device during any of the
channels in the current frame will be clocked out in
the next frame. However, if the input and output
frames are aligned, then data switched from any
input channel to output channels 0 or 1 will be
clocked out one frame after the next - consequently
frame sequence integrity is not maintained for
channels 0 or 1. Frame sequence integrity will be
maintained for data switched to any of the other
output channels. (See SMX/PAC Application Note,
MSAN-135, for more information.)
It is possible to switch between Data Memory
Mode-1 and Mode-2 on a per timeslot basis.
Data Memory Mode-3
This mode is similar to Data Memory Mode-1.
However, there is no restriction on the minimum
MT9080B
acceptable clock frequency or frame rate. In this
mode, the size of the switching matrix depends on
the clock and frame rates provided as per the
following relationship:
S=
F CK
2 X F FP
where S is the number of channels in the switching
matrix FFP is the frame pulse frequency in Hz, and
FCK is the clock frequency in Hz. The following table
shows how the size of a switching matrix can be
varied by selecting a suitable combination of clock
and frame rates.
CK (MHz)
FP (kHz)
Number of channels in
the switching matrix
16.384
16.384
16.384
12.288
12.288
8.192
8.192
4
8
16
4
8
4
8
2,048
1,024
512
1,536
768
1,024
512
It is not possible to switch between Data Memory
Mode-3 and other modes on per-timeslot basis.
Connect Memory Mode -1
In Connect Memory Mode-1, the input data bus is
bidirectional. Internal memory locations can be
randomly accessed via the microprocessor bus. The
pinout of the device in this mode is illustrated in
Figure 7.
CK
Data
Input
1023
0
Written to Block 0
FRAME 0
1023
1023
1
Written to
Block 1
Data
Output
FRAME 2
FRAME 1
FRAME 0
0
Written to Block 1
FRAME 1
0
1
1
FRAME 2
1023
0
1
Read from
Block 0
Read from Block 1
Read from Block 0
Note: No input and output channel alignment is implied in the example shown above. It is assumed that the frame pulse for the
connection memory used to generate adresses for the read operation has a specific phase relationship with respect to the Data
Memory frame pulse.
Figure 6 - Data Memory Mode-2 Functional Timing
2-107
MT9080B
CMOS
Connect Memory Mode-2
CK
FP
16
Microprocessor
Interface
D0-D15
16
D0o-D15o
A0-A15
CS
Connect Memory Mode-2 is designed specifically for
2048 channel switching applications. Data is clocked
out on D0o-D15o with every rising clock edge from
memory locations addressed sequentially by the
internal counter (see Figure 9). This counter is
incremented with each clock period and is reset with
FP or when a count of 2047 is reached.
ODE
DS
R/W
DTA
FP
CD
ME
Z
0/1
MODE
Y
X
1
0
CK
DATA
OUTPUT
2047
0
1
2
Figure 7 - Connect Memory Modes Pinout
Data is clocked out on D0o-D15o from memory
locations addressed sequentially by the internal
counter. This counter is incremented every second
clock period and is reset with FP. The frequency of
the clock signal used should be twice the data rate.
A timing diagram showing the relationship between
the data output and the clock signal is presented in
Figure. 8. With a clock rate of 16.384 MHz, the
maximum number of addresses that can be
generated in an 8 kHz frame period is 1024.
FP
CK
Data
Out
1023
0
Fig. 9 - Connect Memory Mode-2 Functional
Timing
The clock frequency should be 16.384 MHz for a
connection memory designed to support a 2048
channel switch.
Microprocessor access is similar to Connect Memory
Mode-1.
Counter Mode
This mode is designed for 2048 channel switching
applications. In the counter mode all read and write
addresses are generated sequentially by the internal
11 bit counter. The 11 bit counter is incremented with
each clock pulse. It will wrap around when it reaches
a count of binary 2047 or when it is reset by FP. The
active input/output pins in this mode are illustrated in
Figure 10.
Fig. 8 - Connect Memory Mode-1 Functional
Timing
CK
Microprocessor access timing is shown in Figures 28
and 29. During a microprocessor read cycle, DS low
indicates to the SMX that the processor is ready to
receive data. The SMX responds by pulling DTA low
when there is valid data present on the bus. The
processor latches the data in and sets DS high. The
SMX completes the bus cycle by disabling the DTA.
DS should be kept low until after DTA is issued by the
SMX. CS, R/W and the address lines should also be
asserted for the duration of the access. A MPU write
cycle is similar to the read cycle. Data will be latched
into the device approximately three clock (CK) cycles
after DS goes low.
When the device has latched
the data in, it will pull DTA low. DS can subsequently
be set high.
2-108
FP
D0o-D15o
D0i-D15i
16
16
CS
ODE
DTA
CD
R/W
ME
X
1
Y
Z
0
0
All other inputs should
be tied Low
Fig. 10 - Counter Mode Pinout
MT9080B
CMOS
The device can perform either a read or a write,
depending on the level asserted at the R/W pin.
When R/W is high, the contents of the memory
addressed by the internal counter will be clocked out
on to the output data bus. Setting R/W low will
enable data on the input data bus to be written into
the device. During a write operation, the output bus
is actively driven by the data latched out in the
previous read operation.
example, if the address asserted is Hex 02, the delay
through the switch is equal to six clock cycles.
CK
FP
D0o-D15o
D0i-D15i
CS
DS
Data is clocked in or out of the device on the positive
edge of the clock. See Figure 11.
ODE
ME
CK
CD
DTA
R/W
A0-A11
FP
Internal
Counter
16
16
Z Y X
1 0 1
All other inputs should
be tied Low
2047
Data Clocked In
(R/W LOW)
0
0
1
1
2
3
Figure 12 - External Mode Pinout
3
2
CK
Data Clocked Out
(R/W High)
2047
0
1
2
FP
Figure 11 - Counter Mode Functional Timing
External Mode
ADDR
CH X
CH Y
The external mode, which is designed for use in
2048 switching applications, permits random access
to the memory both for input and output operations.
The pinout for external mode is shown in Fig. 12.
The address asserted on the external address bus is
used to specify the memory location to be accessed
for the read or write operation. The level asserted on
R/W during a specific clock period determines
whether the addressed memory is written to or read
from. During a write operation, the output data bus is
actively driven with data latched out in the previous
read operation.
Data In
(R/W Low)
X
Y
Data is clocked into or out of the device on the
positive edges of the clock as shown in Figure 13.
Shift Register Mode
Data Out
(R/W High)
CH Z
Z
CH X
CH Y
CH Z
Figure 13 - External Mode Functional Timing
Maximum permissible delay is equal to 4096 clock
cycles.
The pertinent timing parameters are illustrated in
Figure 14. Data is clocked in and out of the device
with rising edge of the clock.
The address is latched in with the negative edge of
DS while the CS is low.
In this mode, data clocked into the SMX is delayed
by a number of clock cycles before being clocked out
of the device. The delay introduced (in number of
clock cycles) is equal to two times the binary value of
the address latched into the device plus 2. For
2-109
MT9080B
CMOS
CK
FP
Data
In
CH X
CH Y
CH Z
Data
Out
CH X
CH Y
CH Z
td
td = (Address x 2) + 2 Clock Cycles
Figure 14 - Shift Register Mode Data Input/Output Timing
Applications
counter, this word will be clocked out of the memory
on to the data bus (D0o-D15o).
1024 Channel Switch Matrix
A 1024 channel, non-blocking, timeslot interchange
switch can be constructed using two SMX devices
(refer to Figure 15). One SMX is operated in the Data
Memory mode, while the second device is operated
in Connect Memory Mode-1.
Data to be switched is clocked into the data memory
via the 16 bit input data bus and stored sequentially
in memory locations addressed by the internal 11 bit
counter. The data is read out of the Data Memory
(SMX#1) according to the external address supplied
by the Connection Memory (SMX#2). The
Connection memory clocks out contents of the
memory according to the addresses supplied by the
internal counter.
The clock applied at the CK input of both the devices
has a frequency of 16.384 MHz. There are two clock
periods in each channel timeslot (see Figure 16). A
framing signal (FP) with a frequency of 8 kHz is used
to delineate frames with 1024 channels each. The
FP input to the Data Memory is delayed by seven
clock periods from the Connection Memory frame
pulse. This phase delay synchronizes the internal
counters of the two SMXs such that the Connection
Memory clocks out addresses one channel ahead of
the affected timelsot.
The output on the Connect Memory data bus
(D0o-D9o) is used to specify the Data Memory
location to be read out during any particular timeslot.
The Connection Memory is programmed in a manner
that permits specific addresses to be output in
certain timeslots. The Data Memory will clock out
data from internal memory locations according to the
address asserted on its address bus. As mentioned
earlier, this address is latched into Data Memory with
a positive edge of the clock. The contents of the
appropriate addressed memory location will be
clocked out of the device at the beginning of the next
channel timeslot.
Connection Memory bit 10 controls the level on the
ODE input. The ODE pin is used to enable the output
drivers of the Data Memory. The capability to
selectively enable or disable the output drivers
during specific channel timeslots is required when
constructing larger switches using the 1024 channel
switch as a building block.
Using the connections illustrated in Figure 15, the
Data Memory address and control functions can be
mapped onto specific bits of the Connect Memory to
form a 16 bit control word, as shown in Figure 17.
The Message Enable (ME) input of the Data Memory
is controlled by D11. Setting this particular bit high
will result in the data latched into the address bus
being clocked out on to the Data Memory output bus.
Note that only 10 of the 16 address inputs are
actually connected to the data bus of the Connection
Memory. Consequently, only 10 of the 16 data output
bits on the Data Memory can be dynamically
controlled through the Connection Memory. In other
applications, all 16 of the address bits may be
connected to the data output bus of the Connection
Memory.
The 16 bit control word is written into the Connection
Memory by the processor. Subsequently, when the
memory location is addressed by the internal
The mode of operation of the Data Memory can be
changed from Data Memory Mode-1 to Data Memory
Mode-2 by setting or resetting D12 in the connection
2-110
CMOS
memory. The delay through the matrix can be
optimized for specific applications by selectively
enabling one of the two modes. Data Memory-1
(DM-1) is designed for voice switching applications
where it is generally desirable to minimize delay
through the switch. As mentioned earlier in the DM-1
description, the delay through the switch depends
upon the difference between the input channel
timeslot and the output channel timeslot.
Consecutive output channels switched from
non-contiguous input channels will not always
originate from the same input frame. For example, if
channels 3, 6 and 8 are to be switched to channels 5,
6 and 7; output channel 5 will contain data input in
the current frame, while channels 6 and 7 will contain
data clocked in one frame earlier. Data Memory-2
MT9080B
(DM-2) is designed for data switching applications
where concatenation of a number of channels is
often necessary. Data clocked out of the device will
originate from the previous frame, regardless of the
input/output time difference. There is one exception,
when channel 1023 is switched to channel 0, the
contents of Channel 0 will not originate from the
previous frame but rather from the frame before it.
The capability to selectively change between DM-1
and DM-2 allows a single switch to handle both voice
and data effectively.
External bus drivers can be controlled with D13 of
the Connection Memory data bus. This bit will be
output along with the remaining bits one channel
SMX #1
DM-1/2
Parallel Input Data
D0i-D15i
16
D0o-D15o
DATA
MEMORY
Parallel Output Data
16
A10-A15
FP
+5
R/W
CS
DS
CK
MODE
A0-A9
FP#1
ODE
ME
Z
Y
X
CK
Timing
Generator
External
Tristate
Control
10
FP#2
D0o-D9o
D10o
D11o
D12o
D13o
CK
X
SMX #2
CM-1
FP
MODE
CONNECTION
MEMORY
Y
Z
A11-A15
0
1
0
+5
A10
CD
CS
D0-D15
R/W
DTA
DS
A0-A9
Address
Decode
D0-D15
IRQ
R/W
HALT
DS
16-BIT MPU
Note: All other inputs not shown in this diagram should be connected to GND.
Figure 15 - 1024 Channel Switch Matrix
2-111
MT9080B
CMOS
➀
②
➂
➃
1
2
3
4
5
0
1
2
3
4
CK
CONNECTION MEMORY TIMING
FP #2
Internal
Counter
(Read
Address)
1023
0
addresses
Data Output
D0o-D15o
1022
1023
DATA MEMORY TIMING
Data Output
D0o-D15o
addresses
1021
1022
1023
0
1
2
3
1021
1022
1023
0
1
2
FP #1
Internal Counter
(Write Address)
Data In
D0i-D15i
1021
1022
1023
0
1
2
SMX #1 Data Input/Output Frame Boundary
Note 1: Address is latched into the Data Memory by the first positive clock edge in a timeslot (edge ➀ for Ch. 0). Data will be
clocked out by the first positive clock edge in the next timeslot (edge ② for Ch. 0).
Note 2: Data is latched into the Data Memory by the first rising edge in a timeslot (edge ➂ for Ch. 0) and is written into the
memory location addressed by the internal counter with the next rising edge (edge ➃ for Ch. 0).
Figure 16 - 1024 Channel Switch Timing
ahead of time; i.e., one channel before the
addressed data is clocked out of the Data Memory. It
may be necessary to provide an external bus enable
one channel ahead of time in applications where
precharging of the external data bus is required. In
other applications where no precharge is required,
control bit from the next channel may be used in
order to ensure that the external bus is enabled at
the same time as the channel is being clocked out of
the device.
D15 - D14
Unused
D13
External
Driver
Enable
D12
DM-1 or
DM-2
Select
The Change Detect (CD) output of the Connection
Memory is used to interrupt the MPU. As mentioned
in the Pin and Functional descriptions, CD goes low
when the internal CRC performed by the device
indicates a change in memory contents. This feature
is particularly useful in switching applications where
the Connection Memory is configured once and is
not modified for long periods of time, e.g., in network
digital
access
crossconnect
systems.
Any
inadvertent corruption of the memory contents will
cause CD to interrupt the processor.
D11
Message
Enable
D10
ODE
Control
D9 - D0
Source
Channel
Address
Figure 17 - Mapping of Address and Control Signals onto Connect Memory Data Bits
2-112
CMOS
Switching any input channel to an output channel
timeslot is possible by merely writing the address of
the input channel in the Connection Memory location
corresponding to the output channel timeslot. For
example, to switch channel 1 to output channel 5 and
enable output drivers during channel 5, the
Connection Memory location corresponding to
channel 5 should be loaded with Hex 2001. This
word will be clocked out of the Connection Memory
during timeslot 4 and will cause the Data Memory to
clock out contents of the memory corresponding to
channel 1 during the channel 5 timeslot. The 16 bit
word clocked out by the Connection Memory will also
enable Data Memory output drivers, and, external
drivers.
2048 Channel Switch Matrix
A 2048 channel, double buffered timeslot
interchange switch can be constructed with three
SMXs as shown in Figure 18. SMX#1 and SMX#2
are used to store data and switch it in time, while the
third SMX functions as a Connection Memory.
SMX#1 and 2 are operated in the Counter Mode and
External Mode alternatively in consecutive frames. In
any specific frame, one of the two is in Counter mode
while the other is in External mode. The functions
are reversed in the successive frame. The SMX in
counter mode is programmed to write data
CNT/EXT
SMX #1
CNT/EXT
SMX #2
16
16
D0-D15i
C16
CK
FP
D0-D15o
Mx
DATA
MEMORY
16
DFP
CFP
16
D0-D15i
+5
C16
My
CK
FP
CS
Mz
DS
R/W
ODE ME A0-A10
Timing
Generator
MT9080B
D0-D15o
Mx
DATA
MEMORY
+5
Data
Output
My
CS
Mz
DS
R/W
ODE ME A0-A10
11
11
U2
C16
16.384 MHz
U1
D11
FP
D0o-D10o
CM-2
SMX #3
ODE
CONNECTION Mz
MEMORY
My
+5
Mx
CK
DTA
DS
R/W
CS
A0-A15
CD
D0-D15
C16
MPU Interface
Notes:
1) U1 and U2 are required if the data output bus is to be enabled/disabled via the microprocessor interface.
2) All inputs not shown should be connected to Ground (VSS).
Figure 18 - 2048 Channel Timeslot Interchange Circuit
2-113
MT9080B
CMOS
CK
DFP
(SMX #1)
DFP
(SMX #2)
Written to SMX #2
Data In
(SMX1/2)
Written to SMX #1
2045
2046
2047
0
1
2
SMX #3
Int. Counter
2046
2047
0
1
2
SMX #3
D0o-D10o
2045
2046
2047
0
1
Written from SMX #2
2045
2046
2047
0
1
2046
2047
0
1
2
2045
2046
2047
0
1
CFP
(SMX #3)
2
Read from SMX #1
Data Out
(SMX 1/2)
2044
2045
2046
Read from SMX #2
2047
0
1
2
2044
2045
2046
2047
Figure 19 - 2048 Channel Switch Timing
Data
In
LARGE MATRIX 1
LARGE MATRIX 2
CH 1-2,048
DM
DM
CM
ODE
ODE
Data
In
LARGE MATRIX 3
LARGE MATRIX 4
CH 2,049-4,096
ODE
ODE
CH 1-2,048
Data Out
Figure 20 - Extended Switching Matrix
2-114
CH 2,049-4,096
Data Out
MT9080B
CMOS
into its memories addressed by the internal counter.
The SMX in the external mode reads data out from
memory locations addressed by the Connection
memory. In this manner, incoming data is continually
written into one memory block while it is being read
out of the other block. The device in counter mode
has its output drivers disabled.
CK
DM-1/DM-2
16
D0-D15i
This configuration results in a maximum throughput
delay of two frames. Data clocked into the device in
the current frame is clocked out in the next frame.
The appropriate timing parameters are illustrated in
Figure 19. The clock signal applied to all three SMXs
has the same frequency.
SMX#3 is operated in Connect Memory Mode-2. In
this mode, data is clocked out of the device at the
same rate as the clock, i.e., at 16.384 Mbps.
D0-D15o
CS
A0-A11
DS
+5V
ADDRESS DS
A 1024 Switch Matrix with messaging capability can
be constructed with three SMXs as shown in Figure
22. The first SMX is used for performing the actual
switching function. The second SMX is configured as
the connection memory. As discussed in the 1024
switch application, by enabling the messaging
feature, data clocked out of the connection memory
and latched into the data memory address bus will
be clocked out on to the data bus directly. Incoming
data is read by the microprocessor using the third
HALT IRQ
D0-D15
MPU
Figure 21 - Reading the Data Memory with a
Microprocessor
SMX. The data output bus of the third SMX is
connected to the data bus of the MPU.
SMX #1
DATA MEMORY
DM-1/2
Data out
Data in
16
16
In some system architectures the PCM voice signals
and system status information is transmitted and
received over a common backplane. To facilitate
microprocessor access to the backplane, the SMX
can be used to read incoming data or write to a
channel on the output data bus.
Data clocked into the SMX can be read from the
device by a microprocessor interfaced to the output
data bus and the address bus (see Figure 21). Data
can be written to a specific timeslot on the output
data bus directly by the microprocessor using the
messaging feature (enabled by tying the ME pin
high).
16
DTA CD R/W
Address
Decode
Construction of matrices larger than 4K may require
external drivers to accommodate the greater
capacitive loading on the outputs.
Using the SMX for Messaging
+5V
ODE
Z
Y
X
Extended Switching Matrix
Larger extended switch matrices can be created
using the 1024/2048 channel switch as a building
block. As shown in Figure 20, a 4096 channel matrix
would require four smaller 2048 channel building
blocks.
FP
ADDR
+5V
16
SMX #2
CONNECTION
MEMORY
SMX #3
MESSAGING
DM-1
16
D0iD15i
D0oD15o
ADDR
ME
CM-1/2
16
ADDR
DATA
DATA ADDR
MPU
Figure 22 - A 1024 Channel Switch Matrix with
Message Capability
2-115
MT9080B
CMOS
Parallel-to-Serial Conversion
The SMX can be used in systems which employ
serial architectures by converting the parallel I/O into
a serial format. The Mitel MT9085 Parallel Access
Circuit (PAC) is designed to interface to the parallel
busses of the SMX. A single PAC can convert the
output of a1024 channel switch into 2.048 Mbit/s or
4.096 Mbit/s serial format. A second PAC can be
configured to implement serial to parallel conversion
(see Figure 23).
The PAC generates all framing signals required to
implement a 1024 or 2048 channel matrix. Refer to
the MT9085 data sheet for more information on
operation of the PAC.
For more information, see Mitel’s Application Note
MSAN-135 “Design of Large Digital Switching
Matrices using the SMX/PAC“.
Timing
Source
C16
F0 C4 C16
C4
F0
F0i C4i C16i
PAC
S/P
S0
S31
•
•
•
•
S0
•
•
•
•
S31
F0i C4i C16i
SMX #1
DM - 1/2
P0-P7
8
D0-D7o
D0-D7i
C16
CK
FP
Mz
DFPo
CFPo
2/4S
DATA
MEMORY
R/W
+5
PAC
P/S
8
S0
•
•
•
•
S31
2/4S
P0-P7
Mx
My
•
•
•
•
S0
S31
CS
DS
OE CKD MCA MCB
ODE
OE CKD MCA
MCB
A0-A9 ME
+5
+5
10
D12
D0-D9 D11
SMX #2
CM - 1
FP
ODE
Mx
CONNECTION My
MEMORY
+5
+5
Mz
CK
DTA
DS
R/W
CS
A0-A15
CD
D0-D15
C16
D10
NOTE:
Connect all inputs not shown to VSS
MPU Interface
Figure 23 - 1024 Channel Serial Switch Matrix Using the PAC and SMX
2-116
MT9080B
CMOS
Absolute Maximum Ratings*
Parameter
Symbol
Min
Max
Units
VDD
-0.3
7
V
1
Supply Voltage VDD-VSS
2
All Input Voltages
Vi
VSS-0.3
VDD +0.3
V
3
All Output Voltages
Vo
VSS-0.3
VDD +0.3
V
4
Storage Temperature Range
TS
-40
125
°C
5
Current at Digital Outputs
IO
150
mA
2
W
6 Continuous Power Dissipation
PD
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
5.0
5.75
V
70
°C
1
Supply Voltage
VDD
4.75
2
Operating Temperature
TOP
-40
3
Input High Voltage
VIH
0.7VDD
4
‡
Input low Voltage
VIL
Typical figures are at 25°C and are for design aid only:
Test Conditions
V
0
0.3VDD
V
not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
120
200
mA
Test Conditions
1
Supply Current
IDD
Outputs unloaded
2
Input High Voltage
VIH
0.7VDD
3
Input Low Voltage
VIL
0
4
Input Leakage Current
IIL
5
Output High Current (all outputs
except D0i-D15i)
IOH
8
mA
VOH=0.7 VDD
6
Output Low Current (all outputs
except DTA, CD and D0i-D15i)
IOL
8
mA
VOL=0.3 VDD
7
Output High Current D0i-D15i
IOH
2
mA
VOH=0.7 VDD
8
Output Low Current DTA & CD
IOL
2
mA
VOL=0.3 VDD
9
Input Capacitance
Ci
10
Output Pin Capacitance
Co
V
0.3VDD
V
±10
µA
10
10
pF
pF
VDD=5.0V±10%.
High Impedance Leakage
IOZ
10
µA
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
11
‡
2-117
MT9080B
CMOS
AC Electrical Characteristics† - Output Drive Enable Timing (see Fig. 24) - Voltages are with respect
to Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
1
ODE Setup
tOS
0
ns
2
ODE Hold
tOH
20
ns
3
Data Output High Z to Active
tDZA
35
ns
Test Conditions
CL=30pF
4 Data Output Active to High Z
tDAZ
30
ns
† Timing is over recommended temperature and power supply voltages.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
1.
Data Memory Modes And Connect Memory Mode - 1
CHANNEL N
CHANNEL N + 1
CK
tOS
tOS
ODE
tOH
tOH
90%
D0oD15o
10%
tDZA
2.
tDAZ
Counter, External And Connect Memory Mode - 2
CHANNEL
N
CK
tOS
CHANNEL
N+1
CHANNEL
N+2
tOH
tOS
tOH
tOS
tOH
ODE
90%
D0oD15o
10%
tDZA
tDAZ
HIGH IMPEDANCE STATE - OUTPUT DRIVERS DISABLED
Figure 24 - Output Drive Enable Timing
2-118
CMOS
MT9080B
AC Electrical Characteristics† - Data Memory, Connect Memory-1 and Shift Register
Mode Timing (See Fig. 25) - Voltages are with respect to Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
1
Address Setup
tAS
0
ns
2
Address Hold
tAH
18
ns
3
Data Output Delay
tDD
4
Data Input Setup
tDS
2
ns
5
Data Input Hold
tDH
4
ns
6
ME, Mx, My, Mz Setup
tMES
0
ns
7
ME, Mx, My, Mz Hold
tMEH
26
ns
8
CK Clock Period
tPCK
60
ns
9
34
ns
Test Conditions
CL = 30 pF
† Timing is over recommended temperature and power supply voltages.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Channel Timeslot
CK
tPCK
tAS
tAH
tAH
A0-A15*
tAS
tMES
tAS
tMEH
tMEH
ME/Mx/y/z
tMES
D0o-D15o
tDD
tDD
D0i-D15i*
tDS
tDS
tDH
tDH
*Timing applicable to Data Memory and Shift Register modes only.
Figure 25 - Data Memory, Connect Memory-1 and Shift Register Mode Timing
AC Electrical Characteristics† - External, Connect Memory-2 and Counter Mode Timing
(See Fig. 26) - Voltages are with respect to Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
1
ADDR, R/W Hold Time
tWEH
10
ns
2
ADDR,R/W Setup Time
tWES
2
ns
3
Data Setup
tDS
2
ns
4
Data Hold
tDH
4
ns
5
Data Output Delay
tDD
6
ME, Mx, My, Mz Setup
tMES
0
ns
7
ME, Mx, My, Mz Hold
tMEH
26
ns
9
34
ns
Test Conditions
CL = 30 pF
† Timing is over recommended temperature and power supply voltages.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
2-119
MT9080B
CMOS
Channel Timeslot
CK
A0-A15*,
R/W**
tWES
tWEH
tWES
tWEH
ME/Mx/y/z
tMES
tMES
tMEH
tMEH
D0i-D15i**
tDS
tDS
tDH
tDH
D0o-D15o
tDD
tDD
* Timing applicable to External mode only.
** Timing applicable to External and Counter modes.
Figure 26 - External, Connect Memory-2 and Counter Mode Timing
AC Electrical Characteristics† - Address Bus Timing In Shift Register Mode (See Fig. 27) Voltages are with respect to Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
1
Address Setup
tAS
0
ns
2
Address Hold
tAH
12
ns
3
Chip Select Setup
tCSS
0
ns
Test Conditions
4 Chip Select Hold
tCSH
0
ns
† Timing is over recommended temperature and power supply voltages.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
CS
tCSS
tCSH
DS
A0-A15
tAS
tAH
Figure 27 - Address Bus Timing in Shift Register Mode
2-120
CMOS
MT9080B
AC Electrical Characteristics† - Microprocessor Read Timing for Connect Memory, Data
Memory & External Modes (See Fig. 28) - Voltages are with respect to Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
1
Chip Select Setup
tCSS
0
ns
2
Chip Select Hold
tCSH
0
ns
3
ADDR
tAS
0
ns
4
R/W Setup
tAS
3
ns
5
ADDR, R/W Hold
tAH
0
ns
6
DTA Delay
tDTAD
4.5
7
DTA Hold
tDTAH
0
ns
8
Valid Data Out to DTA Low
tRD
3
TCK*
9
DS High to Data Invalid
tDH
0
9
27
Test Conditions
TCK*
ns
31
ns
10 Output Data Active to High Z
tDHZ
* TCK= Clock (CK) Period
† Timing is over recommended temperature and power supply voltages.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
DS
CS
tCSS
tCSH
tAS
tAH
A0-A15, R/W
DTA
tDTAH
tDTAD
Data Bus*
tDHZ
tRD
tDH
* In Data Memory Mode and External Mode, data is clocked out on D0o-D15o; in Connect Memory Mode data is clocked out on
D0i-D15i (bidirectional).
Figure 28 - Microprocessor Read Timing for Connect Memory Mode, Data Memory Mode and
External Mode
2-121
MT9080B
CMOS
AC Electrical Characteristics† - Microprocessor Write Timing for Connect Memory Mode
(See Fig. 29) - Voltages are with respect to Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
1
Chip Select Setup
tCSS
0
ns
2
Chip Select Hold
tCSH
0
ns
3
ADDR, R/W Setup
tAS
0
ns
4
ADDR, R/W Hold
tAH
0
ns
5
DTA Delay
tDTAD
4.5
6
DTA Hold
tDTAH
0
7
DS Low to Data in Delay
tDD
8
DTA Low to Data in Hold
tDH
0
ns
9
DS Hold Time
tDSH
0
ns
7.5
Test Conditions
TCK*
ns
4.5
TCK*
* TCK= Clock (CK) Period
† Timing is over recommended temperature and power supply voltages.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
tDSH
DS
CS
tCSH
tCSS
A0-A15,R/W
tAH
tAS
DTA
tDTAD
tDH
D0-D15i
tDD
* This parameter is specified with respect to the rising edge of DS or CS depending on which signal goes high first.
Figure 29 - Microprocessor Write Timing for Connect Memory Mode
2-122
tDTAH*
CMOS
MT9080B
AC Electrical Characteristics† - Frame Pulse, Clock and Change Detect Timing (See Fig.
30) - Voltages are with respect to Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
1
Frame Pulse Setup
tFPS
6
ns
2
Frame Pulse Hold
tFPH
3
ns
3
Change Detect Delay
tCDD
38
Test Conditions
ns
4 Change Detect Reset Delay
tCDRD
0
13
ns
† Timing is over recommended temperature and power supply voltages.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
CK
FP
tFPS
tFPH
DS / CS
CD
tCDD*
tCDRD
* Assumes change in memory contents detected in previous frame
Figure 30 - Frame Pulse and Change Detect Timing
2-123
Package Outlines
F
A
G
D1
D2
D
H
E
E1
e: (lead coplanarity)
A1
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) For D & E add for allowable Mold Protrusion 0.010"
I
E2
20-Pin
28-Pin
44-Pin
68-Pin
84-Pin
Dim
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
A
0.165
(4.20)
0.180
(4.57)
0.165
(4.20)
0.180
(4.57)
0.165
(4.20)
0.180
(4.57)
0.165
(4.20)
0.200
(5.08)
0.165
(4.20)
0.200
(5.08)
A1
0.090
(2.29)
0.120
(3.04)
0.090
(2.29)
0.120
(3.04)
0.090
(2.29)
0.120
(3.04)
0.090
(2.29)
0.130
(3.30)
0.090
(2.29)
0.130
(3.30)
D/E
0.385
(9.78)
0.395
(10.03)
0.485
(12.32)
0.495
(12.57)
0.685
(17.40)
0.695
(17.65)
0.985
(25.02)
0.995
(25.27)
1.185
(30.10)
1.195
(30.35)
D1/E1
0.350
(8.890)
0.356
0.450
0.456
0.650
0.656
0.950
0.958
1.150
1.158
(9.042) (11.430) (11.582) (16.510) (16.662) (24.130) (24.333) (29.210) (29.413)
D2/E2
0.290
(7.37)
0.330
(8.38)
0.390
(9.91)
0.430
(10.92)
0.590
(14.99)
0.630
(16.00)
0.890
(22.61)
0.930
(23.62)
1.090
(27.69)
1.130
(28.70)
e
0
0.004
0
0.004
0
0.004
0
0.004
0
0.004
F
0.026
(0.661)
0.032
(0.812)
0.026
(0.661)
0.032
(0.812)
0.026
(0.661)
0.032
(0.812)
0.026
(0.661)
0.032
(0.812)
0.026
(0.661)
0.032
(0.812)
G
0.013
(0.331)
0.021
(0.533)
0.013
(0.331)
0.021
(0.533)
0.013
(0.331)
0.021
(0.533)
0.013
(0.331)
0.021
(0.533)
0.013
(0.331)
0.021
(0.533)
H
I
0.050 BSC
(1.27 BSC)
0.020
(0.51)
0.050 BSC
(1.27 BSC)
0.020
(0.51)
0.050 BSC
(1.27 BSC)
0.020
(0.51)
Plastic J-Lead Chip Carrier - P-Suffix
General-10
0.050 BSC
(1.27 BSC)
0.020
(0.51)
0.050 BSC
(1.27 BSC)
0.020
(0.51)
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