ON MC100EPT23DTR2G Dual differential lvpecl to lvttl translator Datasheet

MC100EPT23
3.3VDual Differential
LVPECL/LVDS to LVTTL
Translator
The MC100EPT23 is a dual differential LVPECL/LVDS to LVTTL
translator. Because LVPECL (Positive ECL) or LVDS levels are used,
only +3.3 V and ground are required. The small outline 8-lead package
and the dual gate design of the EPT23 makes it ideal for applications
which require the translation of a clock and a data signal.
The EPT23 is available in only the ECL 100K standard. Since there
are no LVPECL outputs or an external VBB reference, the EPT23 does
not require both ECL standard versions. The LVPECL/LVDS inputs
are differential. Therefore, the MC100EPT23 can accept any standard
differential LVPECL/LVDS input referenced from a VCC of +3.3 V.
•
•
•
•
•
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MARKING
DIAGRAMS*
8
SOIC−8
D SUFFIX
CASE 751
8
1
KPT23
ALYW
1
1.5 ns Typical Propagation Delay
8
Maximum Operating Frequency > 275 MHz
24 mA LVTTL Outputs
TSSOP−8
DT SUFFIX
CASE 948R
8
Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
1
KA23
ALYW
1
Pb−Free Packages are Available
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
 Semiconductor Components Industries, LLC, 2005
February, 2005 − Rev. 11
1
Publication Order Number:
MC100EPT23/D
MC100EPT23
Table 1. PIN DESCRIPTION
D0
D0
1
8
2
7
LVPECL
D1
VCC
Pin
Q0
LVTTL
3
6
Q1
Function
Q0, Q1
LVTTL Outputs
D0**, D1**
D0**, D1**
Differential LVPECL Inputs
VCC
Positive Supply
GND
Ground
** Pins will default to VCC/2 when left open.
D1
4
5
GND
(Top View)
Figure 1. 8−Lead Pinout and Logic Diagram
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
50 k
Internal Input Pullup Resistor
50 k
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 1500 V
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
91 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
3.8
V
3.8
V
50
100
mA
mA
VCC
Power Supply
GND = 0 V
VI
Input Voltage
GND = 0 V
Iout
Output Current
Continuous
Surge
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
JA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
JC
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−8
41 to 44
°C/W
JA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
JC
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−8
41 to 44
°C/W
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
265
°C
VI VCC
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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MC100EPT23
Table 4. PECL DC CHARACTERISTICS VCC = 3.3 V, GND = 0 V (Note 2)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
ICCH
Power Supply Current (Outputs set to HIGH)
10
18
25
10
18
25
10
18
25
mA
ICCL
Power Supply Current (Outputs set to LOW)
15
26
36
15
26
36
15
26
36
mA
VIH
Input HIGH Voltage
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage
1355
1675
1355
1675
1355
1675
mV
VIHCMR
Input HIGH Voltage Common Mode Range
(Note 3)
1.2
3.3
1.2
3.3
1.2
3.3
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
0.5
A
150
D
D
−150
−150
150
−150
−150
−150
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. All values vary 1:1 with VCC.
3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 5. TTL DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V, TA = −40°C to 85°C
Symbol
Characteristic
Condition
VOH
Output HIGH Voltage
IOH = −3.0 mA
VOL
Output LOW Voltage
IOL = 24 mA
IOS
Output Short Circuit Current
Min
Typ
Max
Unit
2.4
V
−180
0.5
V
−50
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0.0 V (Note 4)
−40°C
25°C
Characteristic
Min
Typ
fmax
Maximum Frequency (Figure 2)
275
350
tPLH,
tPHL
Propagation Delay to
Output Differential (Note 5)
1.2
1.2
1.5
1.5
1.8
1.8
tSK+ +
tSK− −
tSKPP
Output−to−Output Skew++
Output−to−Output Skew−−
Part−to−Part Skew (Note 6)
15
35
70
tJITTER
Random Clock Jitter (RMS) (Figure 2)
VPP
Input Voltage Swing (Differential Configuration)
tr tf
Output Rise/Fall Times (0.8 V − 2.0 V)
Symbol
Q, Q
Max
85°C
Min
Typ
275
350
Max
Min
Typ
275
350
1.2
1.1
1.5
1.5
1.8
1.8
60
80
500
15
40
70
5
10
150
800
1200
330
600
900
Max
1.3
1.1
1.7
1.5
2.4
1.8
ns
70
80
500
30
40
140
125
80
500
ps
5
10
5
10
ps
150
800
1200
150
800
1200
mV
330
600
900
330
650
900
ps
Unit
MHz
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measured with a 750 mV 50% duty−cycle clock source. RL = 500 to GND and CL = 20 pF to GND. Refer to Figure 3.
5. Reference (VCC = 3.3V ± 5%; GND = 0 V)
6. Skews are measured between outputs under identical conditions.
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3
MC100EPT23
12
VOL 0.5 V
VOH
8
VOH (V)
2.0
JITTER
4
1.0
0.0
0
100
200
300
0
400
FREQUENCY (MHz)
Figure 2. Typical VOH / Jitter versus Frequency (25C)
APPLICATION
TTL RECEIVER
CHARACTERISTIC TEST
*CL includes
fixture
capacitance
CL *
RL
AC TEST LOAD
GND
Figure 3. TTL Output Loading Used for Device Evaluation
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4
RANDOM CLOCK JITTER (ps RMS)
3.0
MC100EPT23
ORDERING INFORMATION
Package
Shipping†
SOIC−8
98 Units / Rail
MC100EPT23DG
SOIC−8
(Pb−Free)
98 Units / Rail
MC100EPT23DR2
SOIC−8
2500 / Tape & Reel
MC100EPT23DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
MC100EPT23DT
TSSOP−8
100 Units / Rail
MC100EPT23DTG
TSSOP−8
(Pb−Free)
100 Units / Rail
MC100EPT23DTR2
TSSOP−8
2500 / Tape & Reel
MC100EPT23DTR2G
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
Device
MC100EPT23D
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPS I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1642/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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5
MC100EPT23
PACKAGE DIMENSIONS
SOIC−8 NB
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751−07
ISSUE AE
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 8 0.010
0.020
0.228
0.244
MC100EPT23
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x
0.15 (0.006) T U
K REF
0.10 (0.004)
S
2X
L/2
8
1
PIN 1
IDENT
S
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
5
0.25 (0.010)
B
−U−
L
0.15 (0.006) T U
M
M
4
A
−V−
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
D
−W−
G
DETAIL E
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DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0
6
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0
6
MC100EPT23
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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For additional information, please contact your
local Sales Representative.
MC100EPT23/D
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