Y2280 CY2280 100 MHz Pentium® II Clock Synthesizer/Driver with Spread Spectrum for Mobile or Desktop PCs Features Functional Description The CY2280 is a Spread Spectrum clock synthesizer/driver for a Pentium II, or other similar processor-based PC requiring 100-MHz support. All of the required system clocks are provided in a space-saving 48-pin SSOP package. The CY2280 can be used with the CY231x for a total solution for systems with SDRAM. The CY2280 provides the option of spread spectrum clocking on the CPU and PCI clocks for reduced EMI. A downspread percentage is introduced when the SEL_SS input is asserted. The device can be run without spread spectrum when the SEL_SS input is deasserted. The percentage of spreading is EPROM-programmable to optimize EMI-reduction. • Mixed 2.5V and 3.3V operation • Clock solution for Pentium® II, and other similar processor-based motherboards — Four 2.5V CPU clocks up to 100 MHz — Eight 3.3V sync. PCI clocks, one free-running — Two 3.3V 48-MHz USB clocks — Three 3.3V Ref. clocks at 14.318 MHz — Two 2.5V APIC clocks at 14.318 MHz or PCI/2 • EMI control — Spread spectrum clocking — Factory-EPROM programmable spread spectrum margin — Factory-EPROM programmable output drive and slew rate • Factory-EPROM programmable CPU clock frequencies for custom configurations • Available in space-saving 48-pin SSOP package Table 1. The CY2280 has power-down, CPU stop, and PCI stop pins for power management control. The signals are synchronized on-chip, and ensure glitch-free transitions on the outputs. When the CPU_STOP input is asserted, the CPU clock outputs are driven LOW. When the PCI_STOP input is asserted, the PCI clock outputs (except the free-running PCI clock) are driven LOW. When the PWR_DWN pin is asserted, the reference oscillator and PLLs are shut down, and all outputs are driven LOW. CY2280 Selector Guide. CY2280 Configuration Options Clock Outputs –1 –11S –21S CPU (66.6, 100 MHz) 4 4 4 PCI (CPU/2, CPU/3) 8 8 8 USB (48 MHz) 2 2 2 APIC (14.318 MHz) 2 2 — APIC (PCI/2) — — 2 Reference (14.318 MHz) 3 3 3 1.54.0 ns 1.54.0 ns 1.54.0 ns — — 2.0–4.5 ns N/A 0.6% 0.6% CPU-PCI delay CPU-APIC delay Spread Spectrum (Downspread) Logic Block Diagram -1 -2 CPU_STOP XTALIN XTALOUT APIC [0:1] VDDAPIC REF [0-2] 14.318 MHz OSC. VDDREF STOP LOGIC CPU PLL Divider PWR_DWN SEL0 SEL1 SEL100 SEL_SS CPUCLK [0-3] VDDCPU PCICLK_F EPROM VDDPCI Delay STOP LOGIC PCI [1-7] VDDPCI PCI_STOP SYS PLL USBCLK [0:1] VDDUSB Rev 1.0, November 25, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Page 1 of 11 Tel:(408) 855-0555 Fax:(408) 855-0550 www.SpectraLinear.com CY2280 Pin Configurations REF1 VSS XTALIN 1 2 3 48 47 46 4 VDDREF REF0 REF2 REF1 VSS XTALIN VDDAPIC APIC0 5 6 43 PCICLK_F 7 42 VSS RESERVED 8 9 10 11 12 41 VDDCPU 40 39 38 CPUCLK0 37 36 35 34 VDDCPU CPUCLK2 CPUCLK3 PCICLK1 VDDPCI PCICLK2 PCICLK3 VSS 48-pin SSOP (Top View) XTALOUT VSS 45 44 APIC1 PCICLK4 PCICLK5 VDDPCI 13 PCICLK6 16 33 PCICLK7 VSS AVDD VSS VDDUSB 17 32 VSS 18 31 19 20 30 29 21 28 PCI_STOP CPU_STOP PWR_DWN N/C USBCLK0 USBCLK1 VSS 22 27 23 24 26 25 14 15 VSS AVDD SEL0 SEL1 SEL100 CY2280-1 4 VDDREF REF2 VDDAPIC APIC0 APIC1 XTALOUT VSS 5 6 43 PCICLK_F 7 42 VSS RESERVED 8 9 10 11 12 41 VDDCPU 40 39 38 CPUCLK0 37 36 35 34 VDDCPU CPUCLK2 CPUCLK3 PCICLK2 PCICLK3 VSS VSS 48 47 46 45 44 PCICLK1 VDDPCI CPUCLK1 1 2 3 48-pin SSOP (Top View) REF0 CPUCLK1 VSS PCICLK4 PCICLK5 VDDPCI 13 PCICLK6 16 33 PCICLK7 VSS AVDD VSS VDDUSB 17 32 VSS 18 31 19 20 30 29 21 28 PCI_STOP CPU_STOP PWR_DWN SEL_SS USBCLK0 USBCLK1 VSS 22 27 23 24 26 25 14 15 VSS AVDD SEL0 SEL1 SEL100 CY2280-11S CY2280-21S Pin Summary Name Pins Description VDDPCI 15, 9 3.3V Digital voltage supply for PCI clocks VDDUSB 21 3.3V Digital voltage supply for USB clocks VDDREF 48 3.3V Digital voltage supply for REF clocks VDDAPIC 46 2.5V Digital voltage supply for APIC clocks VDDCPU 41, 37 2.5V Digital voltage supply for CPU clocks AVDD 33, 19 Analog voltage supply, 3.3V VSS 3, 6, 12, 18, 20, 24, 32, 34, 38, 43 Ground XTALIN[1] 4 Reference crystal input XTALOUT[1] 5 Reference crystal feedback PCI_STOP 31 Active LOW control input to stop PCI clocks CPU_STOP 30 Active LOW control input to stop CPU clocks PWR_DWN 29 Active LOW control input to power down device SEL_SS 28 Spread spectrum select input (-11S and -21S options) N/C 28 Spread spectrum select input (-1 option) SEL0 27 CPU frequency select input, bit 0 (see Function Table) SEL1 26 CPU frequency select input, bit 1 (see Function Table) SEL100 25 CPU frequency select input, selects between 100 MHz and 66.6 MHz (see Function Table) CPUCLK[0:3] 40, 39, 36, 35 CPU clock outputs PCICLK[1:7] 8, 10, 11, 13, 14, 16, 17 PCI clock outputs, at one-half or one-third the CPU frequency of 66.6 MHz or 100 MHz respectively PCICLK_F 7 Free-running PCI clock output APIC[0:1] 45, 44 APIC clock outputs REF[0:2] 1, 2, 47 3.3V Reference clock outputs USBCLK[0:1] 22, 23 USB clock outputs RESERVED 42 Reserved Note: 1. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. Rev 1.0, November 25, 2006 Page 2 of 11 CY2280 Function Table (-11S Option) CPU/PCI Ratio SEL_SS[2] SEL100 SEL1 SEL0 PCICLK_F PCICLK CPUCLK REF APIC USBCLK 0 0 0 N/A 2 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 0 1 N/A 2 Reserved Reserved 14.318 MHz 14.318 MHz 48 MHz 0 1 0 N/A 2 Reserved Reserved 14.318 MHz 14.318 MHz 48 MHz 0 1 1 0 (downspread) 2 66.66 MHz 33.33 MHz 14.318 MHz 14.318 MHz 48 MHz 0 1 1 1 (no spread) 2 66.66 MHz 33.33 MHz 14.318 MHz 14.318 MHz 48 MHz 1 0 0 N/A 3 TCLK/2 TCLK/6 TCLK[3] TCLK[3] TCLK/2 1 0 1 N/A 3 Reserved Reserved 14.318 MHz 14.318 MHz 48 MHz 1 1 0 N/A 3 Reserved Reserved 14.318 MHz 14.318 MHz 48 MHz 1 1 1 0 (downspread) 3 100 MHz 33.33 MHz 14.318 MHz 14.318 MHz 48 MHz 1 1 1 1 (no spread) 3 100 MHz 33.33 MHz 14.318 MHz 14.318 MHz 48 MHz Function Table (-21S Option) CPU/PCI Ratio SEL_SS[2] SEL100 SEL1 SEL0 PCICLK_F PCICLK CPUCLK REF APIC USBCLK 0 0 0 N/A 2 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 0 1 N/A 2 Reserved Reserved 14.318 MHz Reserved 48 MHz 0 1 0 N/A 2 Reserved Reserved 14.318 MHz Reserved 48 MHz 0 1 1 0 (downspread) 2 66.66 MHz 33.33 MHz 14.318 MHz 16.67 MHz 48 MHz 0 1 1 1 (no spread) 2 66.66 MHz 33.33 MHz 14.318 MHz 16.67 MHz 48 MHz 1 0 0 N/A 3 TCLK/2 TCLK/6 TCLK[3] TCLK/12[3] TCLK/2 1 0 1 N/A 3 Reserved Reserved 14.318 MHz Reserved 48 MHz 1 1 0 N/A 3 Reserved Reserved 14.318 MHz Reserved 48 MHz 1 1 1 0 (downspread) 3 100 MHz 33.33 MHz 14.318 MHz 16.67 MHz 48 MHz 1 1 1 1 (no spread) 3 100 MHz 33.33 MHz 14.318 MHz 16.67 MHz 48 MHz Actual Clock Frequency Values Clock Output Target Frequency Actual Frequency (MHz) (MHz) PPM CPUCLK 66.67 66.654 –195 CPUCLK 100 99.77 –2346 USBCLK 48.0 48.008 167 Power Management Logic CPU_STOP PCI_STOP PWR_DWN CPUCLK PCICLK PCICLK_F Other Clocks Osc. PLLs X X 0 Low Low Low Low Off 0 0 1 Low Low Running Running Running Running Off 0 1 1 Low Running Running Running Running Running 1 0 1 Running Low Running Running Running Running 1 1 1 Running Running Running Running Running Running Notes: 2. Target frequency is modulated by percentage shown (max.) when SEL_SS = 0. 3. TCLK supplied on the XTALIN pin in Test Mode. Rev 1.0, November 25, 2006 Page 3 of 11 CY2280 Maximum Ratings Storage Temperature (Non-Condensing) ....–65qC to +150qC (Above which the useful life may be impaired. For user guidelines, not tested.) Junction Temperature................................................ +150qC Supply Voltage.................................................–0.5 to + 7.0V Package Power Dissipation.............................................. 1W Input Voltage............................................ –0.5V to VDD + 0.5 Static Discharge Voltage .......................................... > 2000V (per MIL-STD-883, Method 3015, like VDD pins tied together) Operating Conditions[4] Min. Max. Unit AVDD, VDDPCI, VDDUSB, VDDREF Parameter Analog and Digital Supply Voltage Description 3.135 3.465 V VDDCPU CPU Supply Voltage 2.375 2.625 V VDDAPIC APIC Supply Voltage 2.375 2.625 V TA Operating Temperature, Ambient 0 70 qC CL Max. Capacitive Load on CPUCLK PCICLK APIC, REF USB f(REF) Reference Frequency, Oscillator Nominal Value tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) pF 20 30 20 20 14.318 14.318 MHz 0.05 50 ms Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit [5] VIH High-level Input Voltage Except Crystal Inputs VIL Low-level Input Voltage Except Crystal Inputs[5] 2.0 VOH High-level Output Voltage[6] VDDCPU = VDDAPIC = 2.375V IOH = 12 mA CPUCLK VOL Low-level Output Voltage[6] VDDCPU = VDDAPIC = 2.375V IOL = 12 mA CPUCLK IOL = 18 mA APIC VOH High-level Output Voltage[6] VDDPCI, AVDD, VDDREF, VDDUSB = 3.135V IOH = 14.5 mA PCICLK V 0.8 2.0 V V IOH = 18 mA APIC 0.4 2.4 V V IOH = 16 mA USBCLK IOH = 16 mA REF VOL Low-level Output Voltage[6] VDDPCI, AVDD, VDDREF, VDDUSB= 3.135V IOL = 9.4 mA PCICLK IOL = 9 mA USBCLK IOL = 9 mA REF 0.4V V –10 +10 PA 10 PA –10 +10 PA IIH Input High Current IIL Input Low Current VIL = 0V IOZ Output Leakage Current Three-state IDD25 Power Supply Current for 2.5V Clocks[6] VDDCPU = 2.625V, VIN = 0 or VDD, Loaded Outputs, CPU = 66.6 MHz 70 mA IDD25 Power Supply Current for 2.5V Clocks[6] VDDCPU = 2.625V, VIN = 0 or VDD, Loaded Outputs, CPU = 100 MHz 100 mA IDD33 Power Supply Current for 3.3V Clocks[6] VDD = 3.465V, VIN = 0 or VDD, Loaded Outputs 170 mA IDDS Power-down Current[6] Current draw in power-down state 500 PA VIH = VDD Notes: 4. Electrical parameters are guaranteed with these operating conditions. 5. Crystal Inputs have CMOS thresholds. 6. Parameter is guaranteed by design and characterization. Not 100% tested in production. Rev 1.0, November 25, 2006 Page 4 of 11 CY2280 Switching Characteristics[6, 7] Parameter Output Description Test Conditions Min. Typ. Max. Unit 45 50 55 % 1.0 4.0 V/ns 1.0 4.0 V/ns 0.5 2.0 V/ns -1,-11S, -21S 0.4 1.6 ns -1,-11S, -21S 0.4 1.6 ns 175 ps 4.0 ns 250 ps 4.5 ns 100 175 ps 200 250 ps 250 500 ps 3 ms t1 All Output Duty Cycle[8] t1 = t1A y t1B t2 CPUCLK, APIC CPU and APIC Clock Rising and Falling Edge Rate Between 0.4V and 2.0V -1,-11S, -21S t2 PCICLK PCI Clock Rising and Falling Edge Rate Between 0.4V and 2.4V -1,-11S, -21S t2 USBCLK, REF USB, REF Rising and Falling Edge Rate Between 0.4V and 2.4V t3 CPUCLK CPU Clock Rise Time Between 0.4V and 2.0V t4 CPUCLK CPU Clock Fall Time Between 2.0V and 0.4V t5 CPUCLK CPU-CPU Clock Skew [9] Measured at 1.25V t6 CPUCLK, PCICLK CPU-PCI Clock Skew Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks t7 PCICLK, PCICLK PCI-PCI Clock Skew Measured at 1.5V t8 CPUCLK, APIC CPU-APIC Clock Skew[10] Measured at 1.25V for 2.5V clocks t9 APIC APIC-APIC Clock Skew Measured at 1.25V t10 CPUCLK Cycle-Cycle Clock Jitter Measured at 1.25V t11 PCICLK Cycle-Cycle Clock Jitter Measured at 1.5V t12 CPUCLK, PCICLK Power-up Time CPU, PCI clock stabilization from power-up 100 -1,-11S, -21S -21S -1,-11S, -21S 1.5 2.0 Notes: 7. All parameters specified with loaded outputs. 8. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 9. PCI lags CPU for -11S and -21S options. 10. APIC lags CPU for -21S option. Rev 1.0, November 25, 2006 Page 5 of 11 CY2280 Switching Waveforms Duty Cycle Timing t1A t1B OUTPUT All Outputs Rise/Fall Time VDD OUTPUT 0V t2 t3 t2 t4 CPU-CPU Clock Skew CPUCLK CPUCLK t5 CPU-PCI Clock Skew CPUCLK PCICLK t6 PCI-PCI Clock Skew PCICLK PCICLK t7 CPU-APIC Clock Skew (-21S only) CPUCLK APIC t8 Rev 1.0, November 25, 2006 Page 6 of 11 CY2280 Switching Waveforms (continued) APIC-APIC Clock Skew APIC APIC t9 CPU_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPUCLK (External) PCI_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External) PWR_DOWN CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock. Rev 1.0, November 25, 2006 Page 7 of 11 CY2280 Spread Spectrum Clocking Spread Spectrum Disabled Amplitude (dB) Spread Spectrum Enabled Frequency (MHz) Table 2. Description Modulation Frequency Configuration Outputs Max. Unit 30.0 33.0 kHz Down Spread Margin at the Fundamental Frequency -11S CPU, PCI 0.0 –0.6 % Down Spread Margin at the Fundamental Frequency -21S CPU, PCI, APIC 0.0 –0.6 % Rev 1.0, November 25, 2006 All (except -1) Min. Page 8 of 11 CY2280 Application Information Clock traces must be terminated with either series or parallel termination, as is normally done. Application Circuit Summary • A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints must be laid out for flexibility. • Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 PF. In some cases, smaller value capacitors may be required. • The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating resistor. Rseries > Rtrace – Rout • Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. • A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50: impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout and Termination Techniques for Cypress Clock Generators” for more details. • If a Ferrite Bead is used, a 10 PF–22 PF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. Rev 1.0, November 25, 2006 Page 9 of 11 CY2280 Test Circuit VDDPCI, VDDCORE, VDDUSB, VDDREF 3, 6, 12, 18, 20, 24, 32, 34, 38, 43 9, 15, 19, 21, 33, 48 0.1 PF CY2280 VDDCPU, VDDAPIC OUTPUTS 37, 41, 46 CLOAD 0.1 PF Notes: Each supply pin must have an individual decoupling capacitor. All capacitors must be placed as close to the pins as is possible. Rev 1.0, November 25, 2006 Page 10 of 11 CY2280 Ordering Information Ordering Code Package Name Package Type Operating Range CY2280PVC-1 O48 48-Pin SSOP Commercial CY2280PVC-11S O48 48-Pin SSOP Commercial CY2280PVC-21S O48 48-Pin SSOP Commercial Package Diagram 48-Lead Shrunk Small Outline Package O48 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 25, 2006 Page 11 of 11