Datasheet System Motor Driver Series for CD・DVD・BD Player 9ch System Motor Driver For Car AV BD8256EFV-M General Description Key Specifications Ron(Spindle): Ron(Loading): Power Supply Voltage Range: BD8256EFV-M is a 9ch motor driver developed for driving coil actuator (3ch), sled motor (2ch), a loading motor, and a three-phase motor for spindle. This chip has a built-in 2ch LVDS (Low Voltage Differential Signaling) output for spherical aberration. This can drive the motor and coil of blu-ray drive. It has a built-in Serial Peripheral Interface (SPI) with a max clock frequency of 35MHz, for interfacing with the Micro-controller. Package 1.0Ω(Typ) 1.5Ω(Typ) 4.5V to 10.5V W(Typ) × D(Typ) × H(Max) 18.50mm × 9.50mm × 1.00mm HTSSOP-B54 Features Built-in Serial Peripheral Interface(SPI) High efficiency at 180° PWM for spindle driver Built-in 2-channel stepping motor driver for sled Built-in actuator over current protection circuit Built-in loading driver short-circuit protection AEC-Q100 Qualified Applications Car navigation Car AV HTSSOP-B54 Typical Application Circuit VCC VCC PREVCC HALL HALL HALL PREVCC FCTLRNF TKRNF FCTLCDET TKCDET SLRNF1 SLRNF2 BHLD SPRNF SDI SDO SCLK SLV MUTEB HU+ HUHV+ HVHW+ HW- HALL_VC PREGND PREVCC SPGND VCC BD8256EFV-M SLGND SHV ACTGND ERROUT PRTLIM PRTT PRTFT PRTOUT FCTLO1+ FCTLO1- FCTLO2+ TKO+ FCTLO2- TKO- LDO+ LDO- SLO1- SLO1+ SLO2+ SLO2- U_OUT V_OUT W_OUT FG SPCNF VREG SAO1+ SAO1SAO2+ SAO2- M M SHV SHV SHV Figure 1. Typical Application Circuit ○Product structure：Silicon monolithic integrated circuit .www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・14・001 ○This product is not designed protection against radioactive rays 1/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M PREVCC 53 TKRNF HV+ 3 52 FCTLRNF HV- 4 51 FCTLCDET HW+ 5 50 TKCDET HW- 6 49 SAO1+ HALL_VC 7 48 SAO1- SPCNF 8 47 SAO2+ BHLD 9 46 SAO2- FCTLRNF TKRNF FCTLCDET TKCDET Regulator VREG PRTLIM PRTFT PRTT PRTOUT Over Current Protect ERROUT SDO SHV Level Shift 54 2 DAC SDI FCTLO1+ FCTLO1- SCLK Level Shift 1 HU- VCC HU+ PREVCC Block Diagram SPI Pin Configuration (TOP VIEW) DAC SLV FCTLO2+ FCTLO2- Level Shift MUTEB DAC SPRNF 10 45 FCTLO1+ FG 11 44 FCTLO1- W_OUT 12 43 FCTLO2+ V_OUT 13 42 FCTLO2- U_OUT 14 41 TKO+ SPGND 15 40 TKO- SLGND 16 39 ACTGND SLO1+ 17 38 LDO+ SLO1- 18 37 LDO- SLRNF1 SLRNF1 19 36 PRTOUT SLRNF2 SLO2+ 20 35 MUTEB SLO2- 21 34 PRTLIM SLRNF2 22 33 VCC ERROUT 23 32 PRTFT TKO+ TKO- LDO- SAO1+ SAO1SAO2+ SAO2- PREGND SCLK 26 29 SHV SLV 27 28 VREG HU+ HUHV+ HVHW+ HW- Matrix V_OUT FF FF W_OUT Hall Amp / Reverse Protect FG HALL_VC Figure 2. Pin configuration Duty Control U_OUT OSC ACTGND 30 SLO2- SPCNF Current Detector SPRNF SLGND 25 SLO1- DAC PRTT SDI SLO2+ BHLD SPGND 31 SLO1+ OSC LIMIT PREGND 24 PRE LOGIC LIMIT Current Detector Current Detector PRE LOGIC DAC DAC SDO Level Shift LDO+ DAC Figure 3. Block diagram Pin Description Pin No. 1 HU+ Hall amp. U positive input Pin No. 28 2 HU- Hall amp. U negative input 29 SHV 3 HV+ Hall amp. V positive input 30 PREGND 4 HV- Hall amp. V negative input 31 PRTT 5 HW+ Hall amp. W positive input 32 PRTFT HW- Hall amp. W negative input 33 VCC 34 PRTLIM Limit setting for actuator protect Mute input 6 7 Pin Name Function HALL_VC Hall bias 8 SPCNF 9 BHLD 10 SPRNF 11 FG 12 13 Pin Name VREG Function Inside power supply for SPI logic Power supply for SDO output Pre block ground Protect time setting for tracking Protect time setting for focus and tilt Power supply for pre driver and loading Spindle driver loop filter 35 MUTEB Spindle current bottom hold 36 PRTOUT Spindle power supply and current sense 37 LDO- Loading driver negative output FG output 38 LDO+ Loading driver positive output W_OUT Spindle driver W output 39 ACTGND V_OUT Spindle driver V output 40 TKO- Tracking driver negative output 14 U_OUT Spindle driver U output 41 TKO+ Tracking driver positive output 15 SPGND Spindle power ground 42 FCTLO2- Focus tilt driver 2 negative output 16 SLGND Sled power ground 43 FCTLO2+ Focus tilt driver 2 positive output 17 SLO1+ Sled driver 1 positive output 44 FCTLO1- Focus tilt driver 1 negative output 18 SLO1- Sled driver 1 negative output 45 FCTLO1+ Focus tilt driver 1 positive output 19 SLRNF1 Sled 1 power supply and current sense 46 SAO2- Sphere aberration 2 negative output 20 SLO2+ Sled driver 2 positive output 47 SAO2+ Sphere aberration 2 positive output 21 SLO2- Sled driver 2 negative output 48 SAO1- Sphere aberration 1 negative output 22 SLRNF2 Sled 2 power supply and current sense 49 SAO1+ Sphere aberration 1 positive output 23 ERROUT Serial data error output 50 24 SDO Serial data output 51 FCTLCDET Current detect for focus tilt drive 25 SDI Serial data input 52 FCTLRNF Focus tilt power supply and current sense 26 SCLK Serial clock input 53 TKRNF Tracking power supply and current sense 27 SLV Serial slave input 54 PREVCC www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 2/49 TKCDET Protect output Actuator and loading power ground Current detect for tracking drive Pre driver power supply TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M Absolute Maximum Ratings (Ta = 25°C) Parameter Pre Power supply voltage Power MOS power supply voltage PWM control / BTL power supply voltage Serial Output power supply Input pin voltage 1 Input pin voltage 2 Symbol Rating Unit VVCC 15 V VSPRNF,VSLRNF1,VSLRNF2 15 V VPREVCC,VTKRNF,VFCTLRNF 7 V VSHV 7 V 15 V 7 V 15 V VIN1 (1) VIN2 (2) VOUT1 (3) Output pin voltage 2 VOUT2 (4) Power Consumption Pd Output pin voltage 1 Operating temperature range Storage temperature range Junction temperature (1) (2) (3) (4) (5) 7 2.0 V (5) W Topr -40 to +90 °C Tstg -55 to +150 °C Tjmax 150 °C BHLD, SPCNF HU+, HU-, HV+, HV-, HW+, HW-, HALL_VC, PRTFT, PRTT, SLV, SCLK, SDI, TKCDET, FCTLCDET, MUTEB FG, U_OUT, V_OUT, W_OUT, SLO1+, SLO1-, SLO2+, SLO2-, ERROUT, PRTLIM, PRTOUT, LDO+, LDOSDO, VREG, FCTLO1+, FCTLO1-, FCTLO2+, FCTLO2-, TKO+, TKO-, SAO1+, SAO1-, SAO2+, SAO2Ta=25°C, PCB (70mm×70mm×1.6mm, glass epoxy standard board) mounting. Derated by 16mW/°C when operating above 25°C Caution: Operating the IC over the absolute maximum ratings may damage the IC. In addition, it is impossible to predict all destructive situations such as short-circuit modes, open circuit modes, etc. Therefore, it is important to consider circuit protection measures, like adding a fuse, in case the IC is operated in a special mode exceeding the absolute maximum ratings. Recommended Operating Ratings (Ta = -40°C to +90°C) Parameter Symbol Pre /Loading driver power supply voltage Spindle driver power supply voltage (6) (7) (6) Typ Max. Unit VVCC 4.5 8 10.5 V - VVCC - V VSLRNF1, VSLRNF2 - VVCC - V VPREVCC 4.5 5 5.5 V VFCTLRNF, VTKRNF 4.5 5 VPREVCC V VSHV 3.0 3.3 3.6 V (6) Actuator driver power supply voltage Serial output power supply (6)(7) Min. VSPRNF (6)(7) Sled motor driver power supply voltage PWM control power supply voltage (6) Limits (6) Consider power consumption when deciding power supply voltage. Set the voltage same as VVCC. www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 3/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M Electrical Characteristics (Unless otherwise specified, Ta=25°C, V VCC =V SPRNF =V SLRNF1 =V SLRNF2 =8V, V PREVCC =V TKRNF =V FCTLRNF =5V, V SHV =3.3V, RSPRNF=0.33Ω, RSLRNF=0.56Ω) Limits Parameter Symbol Min. Typ Max. Circuit Current PREVCC Quiescent Current IQ1 18 30 VCC Quiescent Current IQ2 7 14 PREVCC Standby Current IST1 3 6 VCC Standby Current IST2 1 2 Spindle Driver Hall Bias Voltage VHB 0.45 0.9 1.35 Input Bias Current IHIB 0.5 3 Input Level VHIM 50 Common Mode Input Range VHICM 1.5 3.8 Input Dead Zone (One Side) VDZSP 0 10 40 Input-Output Gain gmSP 0.98 1.24 1.50 Output ON Resistance (Total Sum) RONSP 1 1.8 Output limit Current ILIMSP 0.85 1.06 1.27 PWM Frequency fOSC 100 FG Output Low Level Voltage VFGL 0.1 0.3 Sled Motor Driver Input Dead Zone (One Side) VDZSL 5 15 30 Input-Output Gain gmSL 0.84 1.10 1.36 Output ON Resistance (Total sum) RONSL 2.2 3.3 Output Limit Current ILIMSL 0.79 0.93 1.07 PWM Frequency fOSC 100 Actuator Driver Output Offset Voltage VOFACT -50 0 50 Output ON Resistance RONACT 1.5 2.0 Voltage Gain 1 GVACT1 10.5 11.7 12.9 Voltage Gain 2 GVACT2 16.4 17.7 18.9 Loading Driver Output Offset Voltage VOFLD -100 0 100 Output ON Resistance RONLD 1.5 2.5 Voltage Gain 1 GVLD1 15.2 17.2 19.2 Voltage Gain 2 GVLD2 16.7 18.7 20.7 Actuator Protection Circuit PRTT/PRTF Default Voltage VPRTREF 1.00 1.06 1.12 PRTT/PRTF Protect Detection Voltage VPRTDET 2.77 2.95 3.13 PRTLIM Voltage VPRTLIM 500 530 560 Detection Input Offset Voltage VOFDET -5 0 5 Protect Sign Output PRTOUT Low Level Output Voltage VOL1 0.1 0.3 ERROUT Low Level Output Voltage VOL2 0.1 0.3 Logic Inputs (SDI,SCLK,SLV,MUTEB) Low Level Input Voltage VINL 0.5 High Level Voltage VINH 2.2 High Level Current IINH 33 66 (SDI,SCLK,MUTEB) Low Level Current (SLV) IINL -60 -30 Function VCC Drop Mute Voltage VMVCC 3.4 3.8 4.2 LVDS Output Difference Movement Output Voltage VOD 250 950 Offset Voltage VOC 0.95 1.25 1.55 TSD (1) TTSD 150 175 200 TSD Junction Temperature (1) THYS 25 TSD Hysteresis Temperature Unit Conditions mA mA mA mA MUTEB=High SPI=72h FE, 70h FE V μA mVpp V mV A/V Ω A kHz V MUTEB=Low IHB=10mA RSPRNF=0.33Ω, RL=2Ω IL=500mA RSPRNF=0.33Ω RL=2Ω 33KΩ pull-up(3.3V) mV A/V Ω A kHz RSLRNF1,2=0.56Ω, RL=8Ω IL=500mA RSLRNF1,2=0.56Ω RL=8Ω mV Ω dB dB Low Gain mode, RL=8Ω IL=500mA Low Gain mode, RL=8Ω High Gain mode, RL=8Ω mV Ω dB dB Low Gain mode, RL=8Ω IL=500mA Low Gain mode, RL=8Ω High Gain mode, RL=8Ω V V mV mV V V 33kΩ pull-up(3.3V) 33kΩ pull-up(3.3V) V V μA SDI,SCLK,MUTEB=3.3V μA SLV=0V V mV V RL=100Ω RL=100Ω °C °C (1) These items are specified by design,not tested during production www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 4/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M Electrical Characteristics (Unless otherwise specified, Ta=-40°C~90°C, V VCC =V SPRNF =V SLRNF1 =V SL RNF2 =8V, V PREVCC =V TKRNF =V FCTLRNF =5V, V SHV =3.3V, RSPRNF=0.33Ω, RSLRNF=0.56Ω) Limits Parameter Symbol Min. Typ Max. Circuit Current PREVCC Quiescent Current IQ1 18 36 VCC Quiescent Current IQ2 7 14 PREVCC Standby Current IST1 3 6 VCC Standby Current IST2 1 2 Spindle Driver Hall Bias Voltage VHB 0.45 0.9 1.35 Input Bias Current IHIB 0.5 3 Input Level VHIM 50 Common Mode Input Range VHICM 1.5 3.8 Input Dead Zone (One Side) VDZSP 0 10 45 Input-Output Gain gmSP 0.85 1.24 1.63 Output ON Resistance (Total Sum) RONSP 1 1.8 Output limit Current ILIMSP 0.85 1.06 1.27 PWM Frequency fOSC 100 FG Output Low Level Voltage VFGL 0.1 0.3 Sled Motor Driver Input Dead Zone (One Side) VDZSL 3 15 35 Input-Output Gain gmSL 0.84 1.10 1.36 Output ON Resistance (Total sum) RONSL 2.2 3.3 Output Limit Current ILIMSL 0.79 0.93 1.07 PWM Frequency fOSC 100 Actuator Driver Output Offset Voltage VOFACT -50 0 50 Output ON Resistance RONACT 1.5 2.0 Voltage Gain 1 GVACT1 9.4 11.7 13.5 Voltage Gain 2 GVACT2 15.4 17.7 19.5 Loading Driver Output Offset Voltage VOFLD -110 0 110 Output ON Resistance RONLD 1.5 2.5 Voltage Gain 1 GVLD1 14.1 17.2 19.5 Voltage Gain 2 GVLD2 15.6 18.7 21.0 Actuator Protection Circuit PRTT/PRTF Default Voltage VPRTREF 0.98 1.06 1.14 PRTT/PRTF Protect Detection Voltage VPRTDET 2.65 2.95 3.25 PRTLIM Voltage VPRTLIM 490 530 570 Detection Input Offset Voltage VOFDET -7 0 7 Protect Sign Output PRTOUT Low Level Output Voltage VOL1 0.1 0.3 ERROUT Low Level Output Voltage VOL2 0.1 0.3 Logic Inputs (SDI,SCLK,SLV,MUTEB) Low Level Input Voltage VINL 0.5 High Level Voltage VINH 2.2 High Level Current IINH 33 75 (SDI,SCLK,MUTEB) Low Level Current (SLV) IINL -75 -30 Function VCC Drop Mute Voltage VMVCC 3.4 3.8 4.2 LVDS Output Difference Movement Output Voltage VOD 250 950 Offset Voltage VOC 0.95 1.25 1.55 www.rohm.com © 2013 ROHM Co., Ltd. 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TSZ22111・15・001 5/49 Unit Conditions mA mA mA mA MUTEB=High SPI=72h FE, 70h FE V μA mVpp V mV A/V Ω A kHz V MUTEB=Low IHB=10mA RSPRNF=0.33Ω, RL=2Ω IL=500mA RSPRNF=0.33Ω RL=2Ω 33KΩ pull-up(3.3V) mV A/V Ω A kHz RSLRNF1,2=0.56Ω, RL=8Ω IL=500mA RSLRNF1,2=0.56Ω RL=8Ω mV Ω dB dB Low Gain mode, RL=8Ω IL=500mA Low Gain mode, RL=8Ω High Gain mode, RL=8Ω mV Ω dB dB Low Gain mode, RL=8Ω IL=500mA Low Gain mode, RL=8Ω High Gain mode, RL=8Ω V V mV mV V V 33kΩ pull-up(3.3V) 33kΩ pull-up(3.3V) V V μA SDI,SCLK,MUTEB=3.3V μA SLV=0V V mV V RL=100Ω RL=100Ω TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M 14 20 13 19 Gain : GVACT2 (dB) Gain : GVACT1 (dB) Typical Performance Curves 12 11 PREVCC=5V GAIN_SELFCTL=0 DIFF_FCTL=1 10 18 17 PREVCC=5V GAIN_SELFCTL=1 DIFF_FCTL=1 16 9 15 -50 -25 0 25 50 Temparature (ºC) 75 100 -50 14 20 13 19 12 11 PREVCC=5V GAIN_SELFCTL=0 DIFF_FCTL=1 10 0 25 50 Temparature (ºC) 75 100 FCTL1 Voltage gain 2 (High gain mode) Gain : GVACT2 (dB) Gain : GVACT1 (dB) FCTL1 Voltage gain 1 (Low gain mode) -25 18 17 PREVCC=5V GAIN_SELFCTL=1 DIFF_FCTL=1 16 9 15 -50 -25 0 25 50 Temparature (ºC) 75 100 FCTL2 Voltage gain 1 (Low gain mode) www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 -50 -25 0 25 50 Temparature (ºC) 75 100 FCTL2 Voltage gain 2 (High gain mode) 6/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M 14 20 13 19 Gain : GVACT2 (dB) Gain : GVACT1 (dB) Typical Performance Curves - continued 12 11 PREVCC=5V GAIN_SELTK=0 10 18 17 PREVCC=5V GAIN_SELTK=1 16 9 15 -50 -25 0 25 50 Temparature (ºC) 75 100 -50 TK Voltage gain 1 (Low gain mode) -25 0 25 50 Temparature (ºC) 75 100 75 100 TK Voltage gain 2 (High gain mode) 22 20 21 19 Gain : GVLD2 (dB) Gain : GVLD1 (dB) 20 18 17 16 VCC=8V GAIN_SELLD=0 19 18 VCC=8V GAIN_SELLD=1 17 15 16 14 15 -50 -25 0 25 50 Temparature (ºC) 75 100 LD Voltage gain 1 (Low gain mode) www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 -50 -25 0 25 50 Temparature (ºC) LD Voltage gain 2 (High gain mode) 7/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M Description of Blocks ■ Serial Peripheral Interface (SPI) 16 bit serial interfaces (SLV, SCLK, SDI, SDO) are provided to perform setting of operations and output levels. SPI communication is performed while SLV terminal is in Low. SDI data are sent to internal shift register at the rising edge of SCLK terminal. Shift register data are loaded into 12 bit internal shift register at the rising edge of SLV terminal according to the address map. Readout operation is performed when readout bit is set to 1. Then state is read out at the falling edge of SCLK terminal and output to SDO terminal. ◆ Input-Output Timing Figure 4 shows write/read timing of the serial ports. Minimum timing of each item is as shown in the table below. In order to prevent increase in delay of SPI input/output timing, wiring between SLV/SCLK/SDI/SDO and the microcomputer should be as short as possible to minimize the wiring capacitance. Symbol A B C D E F G H I J K Item SDI setup time * SDI hold time * Setup SLV to SCLK rising edge * SCLK high pulse width * SCLK low pulse width * Setup SCLK rising edge to SLV * SLV pulse width * SDO delay time * SDO hold time * SDO OFF time * SCLK frequency Min 9 9 9 10 10 9 15 2 - Typ - Max 10 20 35 Unit ns ns ns ns ns ns ns ns ns ns MHz * Guaranteed Design Items SLV C D F E G SCLK A SDI B C3 C2 D0 H D7 SDO J H DN DN-1 D0 I Figure 4. SPI Input Timing www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 8/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M ◆ DAC Register 1. Input / Output Sequence Enter the register address in the SDI input on the first 4 bits and data for a specific DAC voltage in the next 12 bits. When specified as REG=02h (address for focus), REG 77h data is output to the SDO. When specified as REG≠02h (address for non-focus), SDO becomes Hi-Z. SLV SCLK SDI SDO C3 C2 C1 C0 DB DA D9 D8 Hi-Z D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 Figure 5. 12bit Write / 8bit Read Sequence (when specified as REG=02h) SLV SCLK SDI SDO C3 C2 C1 C0 DB DA D9 D8 D7 D6 D5 D4 D3 Hi-Z Figure 6. 12bit Write Sequence (when specified as REG≠02h, C3, C2≠1, 1) 2. Address Map (hereinafter register address is referred to as REG) DAC Register Address Map REG NAME R/W DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh N/A DFCTL1 DFCTL2 DTK DSL1 DSL2 DSA1 DSA2 DSP DLD N/A N/A W W W W W W W W W - 11 11 11 11 11 11 11 11 11 - 10 10 10 10 10 10 10 - 9 9 9 9 9 9 9 - 8 8 8 8 8 8 8 - 7 7 7 7 7 7 7 - 6 6 6 6 6 6 6 - 5 5 5 5 5 5 5 - 4 4 4 4 4 4 4 - 3 3 3 3 3 3 3 - 2 2 2 2 2 2 2 - 1 1 1 1* 1* 1 1 - 0 0 0 0* 0* 0 0 - Reset ** B B B B B B B B B - Default : 0 * : fixed at 0 ** : refer to P.15 about reset - : not affected even when data is written www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 9/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M ◆ Control register 1. Input / Output Sequence When writing data to the control register, enter the register address in the first 7 bits of the SDI input, then set the 1bit R/W to 0 and enter the data of each setting in the last 8 bits. SDO is Hi-Z when R/W=0. When reading data from the control register, enter the register address in the first 7 bits of the SDI input, then set the 1 bit R/W to 1. The last 8 bits are ignored. When R/W=1, 8-bit data of specified address is output to the SDO. SLV SCLK SDI A6 A5 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 Hi-Z SDO Figure 7. Control Register 8 bit Write Sequence (A6, A5=1,1, R/W= 0) SLV SCLK SDI A6 A5 A4 A3 A2 A1 A0 R/W Hi-Z SDO D7 D6 D5 D4 D3 Figure 8. Control Register 8 bit Read Sequence (A6, A5=1,1, R/W= 1) 2. Address Map Control Register Address Map REG NAME R/W D7 D6 D5 D4 D3 D2 D1 D0 70h OUTPUT _EN1 R/W FCTL1 _OUTEN FCTL2 _OUTEN TK _OUTEN SL _OUTEN SA _OUTEN SP _OUTEN LD _OUTEN N/A 71h - - - - - - - - - - 72h POWER _SAVE1 R/W FCTL1 _PSB FCTL2 _PSB TK _PSB SL _PSB SA _PSB SP _PSB LD _PSB N/A 73h - - - - - - - - - - 74h DRIVER _SET R/W N/A W RST _DAC DIFF _FCTL RST _OCP LD _BRAKE RST _SHORT N/A RESET GAIN _SELTK RST _PKTSTOP PKTSTOP _TIME0 SHORT _LD GAIN _SELLD 75h SP _BRAKE RST _CTLREG N/A N/A 76h 77h PKT _TIME STATUS _FLAG1 R/W N/A N/A R ALL _ERR OCP _FCTL GAIN _SELFCTL RST _PKTERR PKTSTOP _TIME1 OCP _TK N/A N/A N/A N/A TSD PKT _ERR PKT _STOP UVLO _VCC 78h TEST0 R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 79h TEST1 R/W Reserved Reserved Reserved Reserved Reserved N/A N/A N/A 7Ah TEST2 R/W N/A N/A Reserved N/A Reserved Reserved Reserved N/A 7Bh RST _CHECK R/W RST _CHECKA RST _CHECKB N/A N/A N/A N/A N/A N/A 7Ch - - - - - - - - - - 7Dh - - - - - - - - - - 7Eh - - - - - - - - - - 7Fh - - - - - - - - - - Write access to "Reserved" bits should be made by "0" input. Read access to "N/A" bits will return "0". www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 10/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M 3. Details of Control Registers Functions of each register are as shown below. ・ REG 70h OUTPUT_EN1 (Read / Write) Each driver output settings (Hi-Z/Active) can be changed in REG 70h. Bit Name Default Function Set "0" Set "1" Reset 7 FCTL1_OUTEN 0 FCTL1 Output Enable Disable Enable A 6 FCTL2_OUTEN 0 FCTL2 Output Enable Disable Enable A 5 TK_OUTEN 0 TK Output Enable Disable Enable A 4 SL_OUTEN 0 SL1,SL2 Output Enable Disable Enable A 3 SA_OUTEN 0 SA1,SA2 Output Enable Disable Enable A 2 SP_OUTEN 0 SP Output Enable Disable Enable A 1 LD_OUTEN 0 LD Output Enable Disable Enable A 0 N/A 0 - - - - ・ REG 71h - Bit Name Default Function Set "0" Set "1" Reset 7 - - - - - - 6 - - - - - - 5 - - - - - - 4 - - - - - - 3 - - - - - - 2 - - - - - - 1 - - - - - - 0 - - - - - - ・ REG 72h POWER_SAVE1 (Read / Write) Power save mode settings for each block can be set in REG 72h. Power save mode makes the output Hi-Z and turns OFF the internal circuit to reduce the current consumption. Bit Name Default Function Set "0" Set "1" Reset 7 FCTL1_PSB 0 FCTL1 Block Power Save Enable Disable A 6 FCTL2_PSB 0 FCTL2 Block Power Save Enable Disable A 5 TK_PSB 0 TK Block Power Save Enable Disable A 4 SL_PSB 0 SL1,SL2 Block Power Save Enable Disable A 3 SA_PSB 0 SA1,SA2 Block Power Save Enable Disable A 2 SP_PSB 0 SP Block Power Save Enable Disable A 1 LD_PSB 0 LD Block Power Save Enable Disable A 0 N/A 0 - - - - www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 11/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M ・ REG 73h - Bit Name Default Function Set "0" Set "1" Reset 7 - - - - - - 6 - - - - - - 5 - - - - - - 4 - - - - - - 3 - - - - - - 2 - - - - - - 1 - - - - - - 0 - - - - - - ・ REG 74h DRIVER_SET (Read / Write) Operation mode settings of the driver can be changed in REG 74h. Bit Name Default Function Set "0" Set "1" Reset 7 N/A 0 - - - - 6 SP_BRAKE 0 SP Brake Mode Short Brake Reverse Brake A 5 GAIN_SELFCTL 0 Gain Select FCTL Low Gain High Gain A 4 GAIN_SELTK 0 Gain Select TK Low Gain High Gain A 3 DIFF_FCTL 0 Differential FCTL Control Mode Differential Control Independent Control A A 2 LD_BRAKE 0 LD Brake Mode LD Output Active LD Output Short Brake 1 GAIN_SELLD 0 Gain Select LD Low Gain High Gain A 0 N/A 0 - - - - <Bit 6> Short brake/reverse brake can be selected as spindle brake mode. <Bit 5> Low/high gain mode of the focus/tilt driver's gain can be selected. <Bit 4> Low/high gain mode of the tracking driver's gain can be selected. <Bit 3> Differential/independent drive of the focus and tilt driver can be selected. See page 18 for more information. <Bit 2> Short brake mode (both positive & negative output low) can be activated when loading output is "Active". <Bit 1> Low/high gain mode of the loading driver's gain can be switched. ・ REG 75h RESET (Write) Resister settings and latched error flag can be reset in REG 75h. Bit 7 6 Name RST_DAC RST_CTLREG Default Function Set "0" Set "1" Reset 0 DAC Reset Normal Reset E 0 Control Register Reset Normal Reset E 5 RST_PKTERR 0 Packet Bit Counts Error Reset Normal Reset E 4 RST_PKTSTOP 0 No Packet Input Error Reset Normal Reset E 3 RST_OCP 0 Actuator Overcurrent Protection Latch Off Reset Normal Reset E Normal Reset E 2 RST_SHORT 0 LD Supply/Ground-Fault Protection Latch Off Reset 1 N/A 0 - - - - 0 N/A 0 - - - - <Bit 7>Reset all DAC register value to 0. <Bit 6>Reset all control register value to default. <Bit 5>Reset packet bit counts error flag register value to 0. <Bit 4>Reset no packet input error flag register value to 0. <Bit 3>Reset actuator overcurrent protection flag register value to 0. <Bit 2>Reset loading supply/ground-fault protection flag register value to 0. www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 12/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M ・ REG 76h PKT_TIME (Read / Write) In REG 76h, you can specify or disable wait time until error operation in case of no SPI input. Bit Name Default Function Set "0" Set "1" Reset 7 N/A 0 - - - - 6 N/A 0 - - - 5 PKTSTOP_TIME1 0 4 PKTSTOP_TIME0 0 SPI Packet Watchdog Timer Operation Time Selection 3 N/A 0 - - - - 2 N/A 0 - - - - 1 N/A 0 - - - - 0 N/A 0 - - - - (00)=Disabled, (01)=1ms, (10)=100μs, (11)=30μs A A ・ REG 77h STATUS_FLAG (Read) REG 77h outputs each protection state flag Bit Name Default Function Set "0" Set "1" Reset 7 ALL_ERR 0 All Error Flags Normal Abnormal * 6 OCP_FCTL 0 Normal Abnormal C 5 OCP_TK 0 Normal Abnormal C 4 SHORT_LD 0 Normal Abnormal C 3 TSD 0 TSD Detection Flag (All Output Hi-Z) Normal Abnormal F Normal Abnormal C FCTL Overcurrent Detection Flag (FCTL1, 2, TK Output Hi-Z) TK Overcurrent Detection Flag (FCTL1, 2, TK Output Hi-Z) LD Supply/Ground-Fault Protection Detection Flag (LD Output Hi-Z) 2 PKT_ERR 0 Number of Packet Bits Error Flag (Flag Only) 1 PKT_STOP 0 Packet Watchdog Timer (All Output Hi-Z) Normal Abnormal C 0 UVLO_VCC 0 VCC Low Voltage Fault Flag (All Output Hi-Z) Normal Abnormal D <Bit7> *How to reset: ALL_ERR outputs all the error flags (OCP_FCTL, OCP_TK, SHORT_LD, TSD, PKT_ERR, PKT_STOP, UVLO_VCC). Therefore, reset conditions are depending on each flags. ・ REG 78h TEST0 (Read / Write) Bit Name Default Function Set "0" Set "1" Reset 7 Reserved 0 - - - D 6 Reserved 0 - - - D 5 Reserved 0 - - - D 4 Reserved 0 - - - D 3 Reserved 0 - - - D 2 Reserved 0 - - - D 1 Reserved 0 - - - D 0 Reserved 0 - - - D www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 13/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M ・ REG 79h TEST1 (Read / Write) Bit Name Default Function Set "0" Set "1" Reset 7 Reserved 0 - - - F 6 Reserved 0 - - - F 5 Reserved 0 - - - F 4 Reserved 0 - - - F 3 Reserved 0 - - - F 2 N/A 0 - - - - 1 N/A 0 - - - - 0 N/A 0 - - - - ・ REG 7Ah TEST2 (Read / Write) Bit Name Default Function Set "0" Set "1" Reset 7 N/A 0 - - - - 6 N/A 0 - - - - 5 Reserved 0 - - - F 4 N/A 0 - - - - 3 Reserved 0 - - - F 2 Reserved 0 - - - F 1 Reserved 0 - - - F 0 N/A 0 - - - - ・ REG 7Bh RST_CHECK (Read / Write) REG 7Bh is the flag confirming reset completion of registers listed in page 15. Bit Name Default Function Set "0" Set "1" Reset 7 RST_CHECKA 0 Reset A Completion Check Flag 0 1 A 6 RST_CHECKB 0 Reset B Completion Check Flag 0 1 B 5 N/A 0 - - - - 4 N/A 0 - - - - 3 N/A 0 - - - - 2 N/A 0 - - - - 1 N/A 0 - - - - 0 N/A 0 - - - - www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 14/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M ◆ Register Reset Operations Type "A" ： MODE Setting Bit (REG 70h, 72h, 74h, 76h, 7Bh[7]) Reset Conditions： VCC < 3.8V or PREVCC < 3.8V or VREG < 2.0V or MUTEB < 0.5V or RST_CTLREG(75h[6]) = 1 Type "B" ： DAC Setting Bit (REG 01h~09h, 7Bh[6]) Reset Conditions： VCC < 3.8V or PREVCC < 3.8V or VREG < 2.0V or MUTEB < 0.5V or RST_DAC(75h[7]) = 1 Type "C" ：Operational State (Latched) Output Bit (REG 77h[1,2,4,5,6]) Reset Conditions： VCC < 3.8V or PREVCC < 3.8V or VREG < 2.0V or MUTEB < 0.5V or RST_CTLREG (75h[6]) = 1 or RST_PKTERR (75h[5]) = 1 (for PKT_ERR(77h[2])) or RST_PKTSTOP (75h[4]) = 1 (for PKT_STOP(77h[1])) or RST_OCP (75h[3]) = 1 (for OCPFCTL(77h[6]) and OCPTK(77h[5])) or RST_SHORT (75h[2]) = 1 (for SHORT_LD(77h[4])) Type "D" ：Operational State (Continuously Updated) Output Bit 1 (REG 77h[0]) Reset Conditions： PREVCC < 2.0V or VREG < 1.2V or MUTEB < 0.5V Type "E" ：Reset Setting Bit (REG 75h) Reset Conditions： Self-reset (If set to 1, automatically returns to "0" following reset operation) Type "F" ：Operational State (Continuously Updated) Output Bit 2 (REG 77h[3]) Reset Conditions： VCC < 3.8V or PREVCC < 3.8V or VREG < 2.0V or MUTEB < 0.5V Reset Operations Control REG DAC REG Reset condition 01h ~ 09h 70h VCC < 3.8V PREVCC < 2.0V Hard PREVCC < 3.8V MUTEB < 0.5V RST_SHORT 75h[2] = 1 RST_OCP 75h[3] = 1 RST_PKTSTOP 75h[4] = 1 Soft RST_PKTERR 75h[5] = 1 RST_CTLREG 75h[6] = 1 RST_DAC 75h[7] = 1 Self reset ○ ○ ○ ○ ○ ○ ○ ○ ○ 72h 74h ○ ○ ○ ○ ○ ○ ○ ○ ○ 75h 76h ○ ○ ○ ○ ○ ○ ○ D7 ○ ○ ○ ○ *1 *1 *1 *1 *1 *1 D6 ○ ○ ○ ○ D5 ○ ○ ○ ○ ○ ○ 77h D4 D3 ○ ○ ○ ○ ○ ○ ○ ○ ○ D2 ○ ○ ○ ○ D1 ○ ○ ○ ○ D0 ○ ○ 7Bh D7 D6 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ *1 Reset conditions of REG 77h[7] are dependent upon REG 77h[6]-77h[0]. www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 15/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M ■ SPI Input / Output Terminal Processing Provided with input terminals SLV, SCLK and SDI, and output terminal SDO, as serial interfaces. Input terminals SLV, SCLK and SDI have built-in 100kΩ (Typ) pull-up/pull-down resistor. Output terminal SDO is able to output the voltage set at SHV as high level voltage in 3-state CMOS output. 100kΩ(Typ) VREG SHV SLV 100kΩ (Typ) SCLK SDO 100kΩ (Typ) SDI Figure 9. SPI Input / Output Terminal Processing www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 16/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M ■ DAC and Gain Setting ◆ Actuator (FCTL1, FCTL2, TK) Suppose that voltage difference between positive/negative outputs is VOUT, VOUT can be expressed as follows. VOUT = GVACT ×VDAC Here, GVACT value will be different as below depending upon gain mode settings. Low Gain Mode (REG 74h[5] GAIN_SELFCTL, REG74h[4] GAIN_SELTK = 0 (Default)) GVACT1 = 3.85 times (11.7dB) High Gain Mode (GAIN_SELFCTL, GAIN_SELTK = 1) GVACT2 = 7.67 times (17.7dB) VDAC, the DAC output voltage, can be obtained from DAC register settings through the following equation. MSB=0: 1 2 3 11 VDAC = 1.0×(bit[10]×0.5 +bit[9]×0.5 +bit[8]×0.5 +…+bit[0]×0.5 ) MSB=1:: 1 2 3 11 11 VDAC = (-1.0)×(^bit[10]×0.5 +^bit[9]×0.5 +^bit[8]×0.5 +…+^bit[0]×0.5 +0.5 ) DAC format (DFCTL1, DFCTL2, DTK) REG 01h(DFCTL1), 02h(DFCTL2), 03h(DTK) MSB Digital input (BIN) LSB Hex Dec VDAC [V] VOUT [V]* 1000_0000_0000 800h -2048 -0.9995 -3.848 1000_0000_0001 801h -2047 -0.9995 -3.848 1000_0000_0010 802h -2046 -0.9990 -3.846 1111_1111_1111 FFFh -1 -0.0005 -0.002 0000_0000_0000 000h 0 0 0.000 0000_0000_0001 001h +1 +0.0005 +0.002 0111_1111_1110 7FEh +2046 +0.9990 +3.846 0111_1111_1111 7FFh +2047 +0.9995 +3.848 * In low gain mode setting. Output voltage saturation is not taken into account in the table. VOUT [V] VDAC [V] +3.848 +0.9995 800h 0 7FFh -3.848 DAC code -0.9995 Figure 10. DAC Setting vs. VDAC/VOUT (in low gain mode) www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 17/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M ◆ FCTL 1, FCTL 2 Differential Drive Mode If you set REG 74h[3] DIFF_FCTL to 0, FCTL1 and FCTL2 turn into differential drive mode. In this mode, 12 bit data to be input into DAC of FCTL1 and FCTL2 will be the values obtained by the following equations. DAC FCTL1, 2 shows 12-bit data to be input into respective DACs. Note that the DAC output voltage V DAC, gain GVACT and output voltage VOUT are to be in accordance with page 17. DACFCTL1 = DFCTL2 + DFCTL1 DACFCTL2 = DFCTL2 – DFCTL1 Operation images during the differential drive mode are as shown below. FCTL1, 2 Differential Operation Images when DIFF_FCTL=0 VOUT DFCTL1 > 0x000 If DFCTL2=100h and DFCTL2=100h, DFCTL1=080h DFCTL1=080hの場合 DFCTL2+DFCTL1 : 180h DFCTL2-DFCTL1 : 080h A B FCTL1 0 DFCTL2 Code DFCTL1 = 0x000 VOUT 800h 7FFh FCTL2 A : +FCTL1 B : -FCTL1 0 DFCTL2 Code 7FFh DFCTL1 < 0x000 VOUT 800h FCTL1 FCTL2 If DFCTL2=100h and DFCTL2=100h, DFCTL1=F80h DFCTL1=F80hの場合 DFCTL2+DFCTL1 : 080h DFCTL2-DFCTL1 : 180h B A FCTL2 0 DFCTL2 Code 800h 7FFh FCTL1 A : +FCTL1 B : -FCTL1 www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 18/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M ◆Loading (LD) Suppose that voltage difference between positive/negative outputs is V OUT, VOUT can be expressed as follows. VOUT = GVLD ×VDAC Here, GVLD value will be different as below depending upon gain mode settings. Low Gain Mode (REG 74h[1] GAIN_SELLD = 0 (Default)) GVLD1 = 7.24 times (17.2dB) High Gain Mode (GAIN_SELLD =1) GVLD2 = 8.51 times (18.7dB) VDAC, the DAC output voltage, can be obtained from DAC register settings through the following equation. MSB=0: 1 2 3 11 VDAC = 1.0×(bit[10]×0.5 +bit[9]×0.5 +bit[8]×0.5 +…+bit[0]×0.5 ) MSB=1 : 1 2 3 11 11 VDAC = (-1.0)×(^bit[10]×0.5 +^bit[9]×0.5 +^bit[8]×0.5 +…+^bit[0]×0.5 +0.5 ) DAC format (DLD) REG 09h(DLD) MSB Digital input (BIN) LSB Hex Dec VDAC [V] VOUT [V]* 1000_0000_0000 800h -2048 -0.9995 -7.236 1000_0000_0001 801h -2047 -0.9995 -7.236 1000_0000_0010 802h -2046 -0.9990 -7.233 1111_1111_1111 FFFh -1 -0.0005 -0.004 0000_0000_0000 000h 0 0 0.000 0000_0000_0001 001h +1 +0.0005 +0.004 0111_1111_1110 7FEh +2046 +0.9990 +7.233 0111_1111_1111 7FFh +2047 +0.9995 +7.236 * In low gain mode setting. Output voltage saturation is not taken into account in the table. VOUT [V] VDAC [V] +7.236 +0.9995 800h 0 7FFh -7.236 DAC code -0.9995 Figure 11. DAC Setting vs. VDAC/VOUT (in low gain mode) www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 19/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M ◆ Sled (SL1, SL2) Suppose that IO PEAK represents peak output current, IO PEAK can be expressed in the following ways. IO PEAK = 0 IO PEAK = gmSL × | VDAC | IO PEAK = ILIMSL ( | VDAC | < VDZSL ) ( gmSL × | VDAC | < ILIMSL ) ( gmSL × | VDAC | > ILIMSL ) Where VDZSL is input deadzone (single-sided) of 15mV (Typ). The gmSL is output/input gain and ILIMSL is output limit current, and they can be obtained respectively as follows. gmSL = 0.616 / RSLRNF [A/V] ILIMSL = 0.52 / RSLRNF [A] VDAC, the DAC output voltage, can be obtained from DAC register settings through the following equation. MSB=0 1 2 3 9 VDAC = 1.0×(bit[10]×0.5 +bit[9]×0.5 +bit[8]×0.5 +…+bit[2]×0.5 ) MSB=1 1 2 3 9 9 VDAC = (-1.0) × (^bit[10]×0.5 +^bit[9]×0.5 +^bit[8]×0.5 +…+^bit[2]×0.5 +0.5 ) DAC format (DSL1, DSL2) REG MSB Digital input (BIN) LSB Hex Dec VDAC [V] IO PEAK [A]* 1000_0000_0000 800h -2048 -0.9980 -1.098 1000_0000_0100 804h -2044 -0.9980 -1.098 1111_1110_0000 FE0h -32 -0.0156 -0.017 1111_1110_0100 FE4h -28 -0.0137 0 1111_1111_1100 FFCh -4 0.0020 0 04h(DSL1), 0000_0000_0000 000h 0 0 0 05h(DSL2) 0000_0000_0100 004h +4 +0.0020 0 0000_0001_1100 01Ch +28 +0.0137 0 0000_0010_0000 020h +32 +0.0156 +0.017 0111_1111_1000 7F8h +2040 +0.9961 +1.096 0111_1111_1100 7FCh +2044 +0.9980 +1.098 *Output voltage saturation and limit current setting are not taken into account in the table. Condition:RSLRNF=0.56Ω IO PEAK [A] VDAC [V] +1.098 +0.998 +0.93 =ILIMSL(Limit Current) 1.10 A/V =gmSL(Input-output Gain) 800h FE4h 0 01Ch 7FCh DAC code +/- 15mV =VDZSL(Input Deadzone) -0.93 -1.098 -0.998 Figure 12. IO PEAK Characteristics (When set as RSLRNF=0.56 Ω). www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 20/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M ◆ Spindle (SP) Suppose that IO PEAK represents peak output current, IO PEAK can be expressed in the following ways. IO PEAK = 0 IO PEAK = gmSP × | VDAC | IO PEAK = ILIMSP ( | VDAC | < VDZSP ) ( gmSP × | VDAC | < ILIMSP ) ( gmSP × | VDAC | > ILIMSP ) Where VDZSP is input deadzone (single-sided) of 10mV (Typ). The gmSP is output/input gain and ILIMSP is output limit current, and they can be obtained respectively as follows. gmSP = 0.409 / RSPRNF [A/V] ILIMSP = 0.35 / RSPRNF [A] VDAC, the DAC output voltage, can be obtained from DAC register settings through the following equation. MSB=0 : 1 2 3 11 VDAC = 1.0×(bit[10]×0.5 +bit[9]×0.5 +bit[8]×0.5 +…+bit[0]×0.5 ) MSB=1 : 1 2 3 11 11 VDAC = (-1.0)×(^bit[10]×0.5 +^bit[9]×0.5 +^bit[8]×0.5 +…+^bit[0]×0.5 +0.5 ) DAC format (DSP) REG MSB Digital input (BIN) LSB Hex Dec VDAC [V] IO PEAK [A]※ 1000_0000_0000 800h -2048 -0.9995 -1.239 1000_0000_0001 801h -2047 -0.9995 -1.239 1111_1110_1011 FEBh -21 -0.0103 -0.013 1111_1110_1100 FECh -20 -0.0098 0 1111_1111_1111 FFFh -1 -0.0005 0 08h(DSP) 0000_0000_0000 000h 0 0 0 0000_0000_0001 001h +1 +0.0005 0 0000_0001_0100 014h +20 +0.0098 0 0000_0001_0101 015h +21 +0.0103 +0.013 0111_1111_1110 7FEh +2046 +0.9990 +1.238 0111_1111_1111 7FFh +2047 +0.9995 +1.239 *Output voltage saturation and limit current setting are not taken into account in the table. Condition:RSPRNF=0.33Ω IO PEAK [A] VDAC [V] +1.239 +1.06 =ILIMSP(Limit Current) +0.9995 1.24 A/V =gmSP(Input-output Gain) 800h FECh 0 014h 7FFh DAC code +/- 10mV =VDZSP(Input Deadzone) -1.06 -1.239 -0.9995 Figure 13. IO PEAK Characteristics (When set as RSPRNF=0.33 Ω). www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 21/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M ■ Description of Driver Operations ◆ LVDS for Spherical Aberration Driver (SA1, SA2) LVDS for Spherical Aberration Driver delivers output corresponding to data stored in DSA1 and DSA2, in accordance with the table below. SAO1+ and SAO1- correspond to DSA1, while SAO2+ and SAO2- to DSA2, and they can be controlled independently. Recommended operation frequency of each output is 10 kHz or less. DAC format (DSA1, DSA2) REG MSB 06h(DSA1), 07h(DSA2) DSA1 Digital input (BIN) LSB 0 - - -_- - - -_- - - 1 - - -_- - - -_- - - - 0 Hex 000h 800h Dec 0 -2048 1 SAO+ L H SAOH L 0 1 SAO1- SAO1+ VOD = |V(SAO1+)-V(SAO1-)| VOC= (V(SAO1+)+V(SAO1-))/2 0V(GND) DSA2 0 1 0 SAO2- SAO2+ VOD = |V(SAO2+)-V(SAO2-)| VOC= (V(SAO2+)+V(SAO2-))/2 0V(GND) Figure 14. Timing Chart of LVDS for Spherical Aberration Driver www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 22/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M ◆ Sled Motor Driver VCC AMP COMP SLRNF1,2 DAC LIMIT PWM Clock OSC M SLO1+, SLO2+ SLO1-, SLO2- PRE LOGIC Figure 15. Sled motor driver block State 1 State 2 VCC VCC IO SLRNF1 ON SLRNF1 reset OFF SLO1+ ON ON M M SLO1+ SLO1- OFF ON SLO1- OFF set OFF Figure 16. Current Paths in Set [State 1] and Reset [State 2] PWM Clock Current value proportional to driver input, or limit current value Motor Current set State 1 reset State 2 set State 1 reset State 2 set State 1 reset State 2 Figure 17. Sled Motor Driver Operation Timing Chart Set [State1] : Output turned ON at the rise of PWM clock --> Load current supplied from VCC. Reset [State2] : Output turned OFF when load current increases to reach current value proportional to input or limit current value --> Load current regenerated by L component of the motor through the path shown in State 2 diagram. www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 23/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M ◆ Spindle Driver 12000 12000 10000 10000 Speed of Rotation [rpm] Speed of Rotation [rpm] 1. Spindle Driver Input-Output Characteristics Figure 18 shows input-output characteristics of the average current detection control and the peak current detection control. This IC controls output by detecting peak current. Linearity of the input/output characteristics is improved compared with the one in the average current detection method. 8000 6000 4000 2000 0 8000 6000 4000 2000 0 0 0.1 0.2 0.3 0.4 Input voltage [V] 0.5 0.6 0 (a) Peak Current Control Method (BD8256EFV-M) 0.1 0.2 0.3 Input voltage [V] 0.4 0.5 0.6 (b) Average Current Control Method Figure 18. Spindle Driver Input-Output Characteristics Difference in input/output characteristics due to control method can be explained as below. Motor coil comprises not only pure inductance but also impedance component. Suppose that V O represents peak value of output pulse, IO, current which flows into the motor when output pulse is turned on, can be expressed in the following ways. VO,IO R IO VO VO IO ( t ) R L IO VO L dIO ( t ) dt R IO t VO (1 e L ) R t Figure 19. Current Waveform Including Impedance Component You can see from the above equation that motor current Io follows a curve of natural logarithm. If you try to express this as motor current characteristics as opposed to input voltage controlled by the respective methods, you will get Figure 20. Spindle motor speed is proportional to motor current. In case of PWM driver, motor current is roughly equivalent to peak current because it includes regenerative current. In the peak current control, therefore, motor current (rotation speed) becomes proportional to input voltage. In contrast, in the average current control, average value of supply current (integral of supply current) becomes proportional to input voltage. So motor current (rotation speed) as opposed to input voltage roughly follows a curve of natural logarithm (Figure 20. (b)). And therefore, you get higher gain in low speed range. www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 24/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M Vo,Io Vo Vo,Io Vo Io Io Constant increase in (integral of) current area Constant increase in peak current t t (a) Peak Current Control (b) Average Current Control Figure 20. Input Voltage vs. Motor Current 2. Current Limit Operation. Figure 21 shows the operation timing chart. In this IC, flip-flop is activated based on a clock signal generated by the built-in triangular wave generator to generate PWM pulse. The spindle driver starts operation at the rising edge of internal clock. Short brake mode is activated if peak current defined by limit current or gain is detected, and no output pulse is delivered until next clock input. Both during limit current detection and usual peak current detection, it operates at PWM oscillating frequency generated by the same internal clock. VCC Voltage, Current SPRNF Dotted line：BHLD(No Capa case) BHLD charge charge charge SPCNF Peak current detection by Limit current or gain. IO PEAK (Peak Load Current) IO (Load Current) Internal Clock (100kHz) Internal Clock Rise Output State Active Short brake Active Short brake Active Short brake Active Time Figure 21. Spindle Driver Operation Timing Chart www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 25/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M 3. Role of Capacitors of BHLD and SPCNF Terminals Figure 22 shows a block diagram of the spindle driver. In this IC, peak current control method is realized by monitoring Io, the load current flowing in the spindle motor, at SPRNF terminal, and holding the peak current in C BHLD, the capacitor connected to BHLD terminal. Charging time of BHLD terminal is a time constant defined by capacity of CBHLD and 200 kΩ (Typ) internal resistance. CSPCNF, the capacitor of SPCNF terminal, influences fc, the cut-off frequency, of the spindle driver control loop. f c can be expressed in the following formula. Where ROERR is internal error amplifier output impedance of approximately 700 kΩ (Typ). fc 1 2πCSPCNFROERR VCC VCC CBHLD (Outside) BHLD(Pin9) VCC BD8256EFV VCC Spindle motor current 200kΩ SPRNF amp. Output current wave Error Amp amp. D/A U_OUT Wave range CSPCNF(Outside) control SPCNF(Pin8) comp. Limit current Normal voltage H+ Limit detection signal amp. comp. Hole signal PWM Duty control、 Limit detection short brake control V_OUT W_OUT HTriangle wave (inside wave) Figure 22. Spindle Driver Block Diagram 4. Spindle Hall Signal Setting In this IC, as shown in Figure 22, low noise (silence) is realized by controlling output current into a sine wave. Hall signal amplified according to REG 08h DSP is used to control the output current. So, if amplitude of the hall signal is too small, amplitude of the output current will also be too small, and rotation speed will become too low. Therefore, make sure that input level of the hall signal be 50 mV (input level at hall amplifier: V HIM) or greater as shown in Figure 23. Also make sure that waveform of the hall signal be as close as possible to sine wave. HU+ HU+ 50mV 50mV 50mV HU50mV HU- Figure 23. Minimum Amplitude of Hall Input (Example of HU+ and HU- Input). www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 26/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M 5. Hall input (Pin 1 to Pin 6) / Hall bias (Pin 7) (Spindle) Hall elements can be connected either in series or in parallel as shown in Figure 24. Hall input voltage should be set within the range of 1.5 V to 3.8 V (In-phase input voltage range of hall amplifier: VHICM). If the Hall input range is not meeting the specification due to variation in characteristics of Hall elements, there is a setting to connect resistor parallel to a resistor. Additionally, they can also be connected to GND instead of hall bias (Pin 7). In this case, GND should be set as PREGND (Pin 30) and the hall bias (Pin 7) to open. For connection details, please refer to the page with Application Example. HVCC HVCC HU HU HV HW HV HW Pin7 <Parallel Connection> Pin7 <Series Connection> Figure 24. Example of Hall Elements Connection 6. FG Pulse 3FG is output to FG terminal. Pull-up resistor of FG is recommended to be 3.3 kΩ or less. If the resistance setting is higher than that, High logic of FG output can be reversed to become "Low" as soon as spindle output becomes Hi-Z. Since FG pulse is generated from hall output signal, it can become unstable if the hall signal catches noise. Radiation noise on circuit patterns or flexible cables should be avoided as much as possible. Against any remaining noise, it is recommended to insert a capacitor (around 0.01 µF) between positive and negative sides of the hall signal. 7. Reverse brake When reverse brake is done coming from high speed, take note of the counter-electromotive force. Also, consider the speed of motor rotation to ensure sufficient output current when using the reverse brake. 8.Capacitor between SPVM-SPGND There is change in voltage and current because of the steep drive PWM. The capacitor between SPVM-SPGND is placed in order to suppress the fluctuations due to the SPVM voltage. However, the effect is reduced if this capacitor is placed far from the IC due to the effect of line impedances. Therefore, this capacitor should be placed near the IC. www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 27/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M 9. Spindle Dricer Input-Output Timing Chart HU+ HUHVHV+ HW+ HWSource U_OUT Sink Source V_OUT Sink Source W_OUT Sink High FG Low State A B C D E F (a) Forward Mode (b) Short Brake Mode (DSP>000h) (DSP<000h, REG 74h[6]=0) HU+ HUHVHV+ HW+ HWSource U_OUT Sink Source V_OUT Sink Source W_OUT Sink High FG Low State G H I J K L (c) Reverse Brake Mode (b) Anti-reverse Mode (DSP<000h, REG 74h[6]=1) (DSP<000h, REG 74h[6]=1, after reverse detected) www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 28/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M Start-up Operation 1. Startup Signals ・5V Power supply ・8V Power supply ・3.3V Power supply ・MUTEB (Input terminal) ・XXX_PSB (SPI control signal) ・XXX_EN (SPI control signal) ・MUTEB_D (Internal signal) ・RESETB (Internal signal) ： ： ： ： ： ： ： PREVCC, FCTLRNF, TKRNF VCC, SPRNF, SLRNF1, SLRNF2 SHV Standby (Low) / Active (High) setting for whole IC Power save (0) / Active (1) setting for control circuits of 9ch blocks Open (0) / Active (1) setting for output of 9ch blocks Standby / active control for analog block There may be 15 µs (Max) delay from MUTEB. ： Reset /active control for SPI block and logic block 2. Start-up and Shut-down Sequences Make sure to turn on 5V power supply before 8V and 3.3V power supplys. Otherwise internal logic becomes indefinite and abnormal output may be produced. As long as 5V power is turned on first, either 8V or 3.3V may be turned on next. There are no special requirements on sequence of power shut down. . 5V Power Supply 8V 4.0V Turn on 8V and 3.3V power supply after 5V becomes 4.0V or greater. 4.0V 3.3V Input High on MUTEB after 8V becomes 4.0V or greater. MUTEB Input Signal High Low XXX_PSB 0 1 XXX_EN 0 1 MUTEB_DELAY 15μs (Max) MUTEB_D Internal Signal (Reference) Protect Circuit Active RESET_DELAY 30μs (Max) RESETB Start to Receive SPI Input OUTEN_DELAY 45μs (Max) Output OUTPUT Active OPEN Analog Block Active State Logic Block Active www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 29/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M Description of Functions 1. Output Voltage State (Spindle / Sled Motor) Spindle Hi-Z Short Brake Under Input Dead Zone Under Current Limit Operation Sled Motor Short Brake Short Brake 2. PWM Oscillation Frequency (Spindle / Sled Motor) PWM oscillation of the spindle and the sled motor is internally free-running. Oscillation frequency is 100 kHz (Typ). 3. UVLO If VCC or PREVCC terminal voltage becomes 3.8 V (Typ) or less, or VREG terminal voltage becomes 2.0 V (Typ) or less, output of all channels turns OFF (Hi-Z). * REG 77h[0] UVLO_VCC is set to "1" while UVLO is activated. And UVLO_VCC is reset to "0" if PREVCC terminal voltage becomes 2.0 V (Typ) or less, or VREG terminal voltage becomes 1.2 V (Typ) or less, but this is below the operational voltage range and some register state may be unsustainable depending on degree of voltage drop. 4. Thermal Shutdown Thermal shutdown (over temperature protection circuit) is built-in in order to prevent thermal breakage of IC. The package should be used within acceptable power dissipation, but in case where it is left beyond the acceptable power dissipation, junction temperature rises, and thermal shutdown is activated at 175℃ (Typ) and all the channel outputs are turned OFF (Hi-Z). Then, when the junction temperature falls down to 150℃ (Typ), the channel outputs are turn ON again. Note that even though the thermal shut down is operating, IC may be overheated and end up broken if heat is continuously applied from outside. * REG 77h[3] TSD is set to "1" while thermal shutdown is activated, but this condition is beyond the rated temperature and all register states may be unsustainable depending on degree of temperature rise. 5. Loading Supply/Ground-Fault Protection This is the function to prevent breakage of output POWER MOS when there exist the conditions that may break the output POWER MOS if loading output is supply/ground-faulted. ・Supply-fault occurs when SINK-side POWER MOS is ON, and the supply-fault protection is performed if output terminal voltage of (Power Supply - 1 Vf) or greater and supply-fault current are detected at the same time. Here, the output is OFF-latched. Note that 1 Vf = 0.7V (Typ). ・Ground-fault occurs when SOURCE-side POWER MOS is ON, and the ground-fault protection is performed if ground-fault current is detected. Here, the output is OFF-latched. Note that the ground-fault detection current is dependent on the output voltage. See Figure 25. * REG 77h[4] SHORT_LD is set to "1" if the loading supply/ground-fault protection is activated. * You can reset the protection mode by resetting REG 75h[2] SHORT_RESET if the protection mode is activated and the output is OFF-latched. * High frequency noise suppression filter is built in the supply/ground-fault protection circuit, but the supply/ground-fault protection may be activated against the noise of 10 μs (Typ) or greater. Ground short detection current (A) 2.0 1.8 1.6 1.4 VCC=8V Ta=RT 1.2 1.0 0 1 2 3 4 5 6 7 Output voltage (ground referenced) (V) 8 Figure 25. Output voltage vs Ground short detection current www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 30/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M 6. Packet Bit Counts Error Serial input signal of this IC consists of 16 bits in one packet. If counts of the SCLK rising during the period between falling and rising of SLV are anything but 16 times, it is determined as a erroneous packet and REG 77h[2] PKT_ERR is set to "1". Any data determined as an erroneous packet are nullified, and the registers maintain the state immediately before the error. Note that PKT_ERR remains at "1" even though the next 1 packet is sent and counts of the clock rising during the period between falling and rising of SLV are 16 times. But this error will not open (i.e. turn off) the output circuit. 7. Packet Watchdog Timer If REG 76h[5,4] PKTSTOP_TIME is preset to anything but "00" and there is no valid packet (16 bits) rising of SLV within this preset time period, REG 77h[1] PKT_STOP will be set to "1" and all outputs will be OFF-latched (Hi-Z). * You can reset the protection mode by resetting REG 75h[4] RST_PKTSTOP if the protection mode is activated and the output is OFF-latched. 8. ERROUT Terminal If either the packet bit counts error or the packet watchdog timer is activated, this terminal switches to High as an error flag. 9. PRTOUT Terminal Operational state of MUTEB, UVLO and actuator overcurrrent protection is output to PRTOUT terminal. Output conditions are as per the following table. MUTEB UVLO ON L OFF ON H OFF Overcurrent PRTOUT Protection ON OFF ON OFF H* ON OFF ON OFF L *When connected with pull-up resistor. 10. VREG Terminal VREG terminal is the regurator output for internal blocks. A 0.01μF compensating capacitor shall be connected across the VREG terminal. Any value less than 0.01μF, or no compensating capacitor will result in system instablity. www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 31/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M 11. Actuator Overcurrent Protection (OCP: Over Current Protection) This is the function to protect the actuator when overcurrent condition is detected over a preset time period. PRTT, PRTFT > 2.95V < 2.95V PRTOUT H L Actuator Output Hi-Z (Protection Enabled) Active Charges/discharges the capacitor with current proportional to load current based on the externally preset load current threshold as "0". Time period until the protection is activated is subject to the value of the capacitors connected to PRTT and PRTFT terminals and the resistors connected to TKRNF, FCTLRNF, TKCDET, FCTLCDET and PRTLIM terminals. Default value of PRTT and PRTFT terminals is 1.06 V (Typ). The protection is activated at 2.95 V (Typ). (Be aware that the protection will be activated even at start-up or when recovered from stand-by, as long as voltage of 2.95 V or greater remains at PRTT or PRTFT terminal.) The protection will be deactivated when voltage at PRTT and PRTFT terminals falls down to 1.1 V or less and REG 75h[3] RST_OCP is set to "1" at that timing. Protect Circuit Active OFF ON OFF Driver Active MUTE Active Drive Current OCP Mute discharge Voltage of capacitor PRTFT / PRTT Current of Capacitor charge Set Current Value Threshold voltage=2.95V(Typ) OCP_TK/ OCP_FCTL 1 RST_OCP PRTOUT 1.06V(Typ) 1 0 1 0 0 0 1 ←Self-Reset 0 0 Protection OFF Conditions: PRTFT and PRTT voltage equal to or less than 1.1 V, and RST_OCP(75h[3])=1 Figure 26. OCP Timing Chart www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 32/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M 12. Example of Constants Setting for Actuator Overcurrent Protection Circuit ( ) indicates processing in case of not using OCP function. 5V Power Supply IO R1(Delete) RNF(0Ω) VOFDET Ｖ TKRNF / FCTLRNF TKCDET / FCTLCDET VI Conversion 3.3V 33k TKO+ FCTLO1+ FCTLO2+ ISOURCE TKOFCTLO1FCTLO2- MUTE Signal PRTT/PRTFT PRTOUT ISINK Matrix VI Conversion C(Delete) Ｖ VPRTREF:1.06V(Typ) VPRTDET:2.95V(Typ) PRTLIM 2.95V or 1.1V Ｖ VPRTLIM:0.53V(Typ) R2 * The above voltmeters indicate where electric characteristics should be measured. Figure 27. Overcurrent Protection Circuit Constants Capacitor-recharging/discharging current ISINK and ISOURCE can be obtained respectively as follows. ISINK RNF IO VPRTLIM , ISOURCE R2 R1 Load current It (threshold current) which begins to detect overcurrent is the current where I SINK=ISOURCE, and can be obtained as follows. ISINK ISOURCE VPRTLIM RNF It R2 R1 It R1 VPRTLIM R2 RNF ISINK < ISOURCE, so td, the time period until error detection flag is output, should be the time period until PRTFT/PRTT voltage becomes 2.95 V (Typ) and can be obtained as follows. ( Vd VPRTDET VPRTREF 2.95 1.06 1.89V ) C Vd (ISOURCE ISINK ) t d td C Vd ISOURCE ISINK C Vd RNF IO VPRTLIM R1 R2 For example, suppose that td=100 ms, IO=200 mA, It=100 mA, RNF=0.5 Ω and R2=47 kΩ, R1 and C can be obtained respectively as follows. td R2 RNF 47k 0.5 It 100m 4.4(kΩ) VPRTLIM 0.53 RNF Io VPRTLIM 100m 0.5 200m 0.53 t C d 0.61(μF) 1.89 Vd R1 R2 4.4k 47k Also, tdc, the time period after activation of the protection until PRTFT/PRTT voltage goes down to the default voltage (1.06 V Typ) through discharge of C, can be obtained as follows. R1 C Vd Isink t dc tdc C Vd ISINK C ( VPRTDET VPRTREF) www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 ISINK 0.59 ( 2.95 1.06 ) 47k 33/49 0.53 102(ms) TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M Noise Suppression The following are possible causes of noise of the PWM driver. A. Noise from power line or ground B. Radiated noise - Countermeasures against A (1) Reduce impedance in wiring for the driver's 8 V power supply (SPRNF, SLRNF 1, SLRNF 2, VCC), 5V power supply (FCTLRNF, TKRNF) and power GND (SPGND, SLGND, ACTGND) lines where high current flows. Make sure that they be separated from power supply lines of other devices at the root so that they do not have common impedance. (Figure 28) 8V 47μF GND 0.1μF 47μF 5V Other Devices than Driver 0.1μF Driver IC (BD8256EFV-M) Separate at the root as much as possible. Figure 28. Pattern Example (2) Provide a low ESR electrolytic capacitor between the power terminal and the ground terminal of the driver to achieve strong stabilization. Provide a ceramic capacitor with good high frequency property next to the IC. Also provide a ceramic capacitor with good high frequency property between RNF and GND. (Figure 29) Then power supply ripple due to PWM switching and spindle motor rotation can be reduced. SPVM 0.1μF RSLRNF 0.1μF SPVM 0.1μF RSPRNF 0.1μF SLRNF1,2 SPVM: Strongly stabilize with electrolytic capacitor. SPGND (Pin15) SPRNF SLGND (Pin16) SPGND (Pin15) U_OUT V_OUT W_OUT Power supply 8V 47μF or greater 0.1μF SPGND (Pin15) RSPRNF 0.1μF SPGND (Pin15) SLGND (Pin16) SPGND (Pin15) (a) Send motor 10 SPRNF BD8256EFV-M (b)Spindle (c) Around Spindle Power Supply Figure 29. Position of Ceramic Capacitors www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 34/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M (3) If you could not improve the situation by (1) and (2), another way is to insert a LC filter in the power line or the ground line. Example: Vcc 120μH 47μF 0.1μF PWM DRIVER IC 0.1μF PWM DRIVER IC 0.1μF PWM DRIVER IC GND Vcc GND 120μH 47μF 120μH Vcc 120μH GND 47μF Figure 30. LC Filter Diagram (4) Or you can also add a capacitor of around 2200 pF between each output and the ground. In this case, ensure that the GND wiring should not have any common impedance with other signals. PWM OUTPUT+ M PWM OUTPUT2200pF Figure 31. Snubber Circuit www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 35/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M - Countermeasures against B - See Figure 32 (1) Ensure certain distance between RF signal line and PWM-driven output line. If they must be located inevitably too close, shield the RF signal line with GND except the stable GND. (2) Like in (1), flexible cable to the pickup should be shielded with GND in order to separate noise between the signal line and the actuator drive output line. (3) Connect the motor system and the actuator system to separate flexible cables. (4) As FG pulse is generated from hall signal, provide a shield with stable GND or other wire with low impedance between the PWM output and the hall signal so that noise is not radiated from the flexible cable and the board pattern. RF PICK UP (2) GND Shield (1) GND Shield GND (3) FLEX to PICKUP Actuator Output (3) Make sure to separate from GND of driver and motor board Sled output BD8256EFV-M (3) FLEX to Motor Spindle output (4) GND shield Hall Signal Figure 32. RF Noise Suppression www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 36/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M Power Supply and Ground *(○) is pin. PREVCC VCC VREG REG SPRNF U_OUT SP DAC SP HALL SP Predrive SP Output V_OUT W_OUT SPGND SLRNF1 SLRNF2 SLO1+ SL Predrive SL Output ~ SL DAC SLO2- SLGND LD DAC LD Predrive LDO+ LD Output FCTLRNF LDO- TKRNF FCTLO1+ ACT Predrive ACT Output ~ ACT DAC TKO- ACTGND SHV SAO1+ SDO SA LVDS ~ SPI SAO2- PREGND Figure 33. Power Supply and Ground www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 37/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M Application Example1 CSPRNF SPGND SPGND V_OUT W_OUT TKO+ SPCNF PREGND CSPCNF RTKRNF RTKCDET RFCTLRNF RFCTLCDET PREGND CPRTT CAVM SPRNF U_OUT ACTGND CPRTFT TKOTKRNF TKCDET FCTLO1+ FCTLRNF FCTLCDET FCTLO2+ FCTLO1- FCTLO2LDO+ PRTT PRTFT LDOSLO1+ PREGND Back side metal RSLRNF1 SLRNF1 SLVM SLRNF2 RSLRNF2 CSLVM CSLRNF1 SLGND CSLRNF2 SLO1SLO2+ SLO2- SLGND SHV μ-con CSHV SAO1+ SAO1SAO2+ SAO2- SHV SLV SCLK SDI SDO PREGND POWERGND VREG MUTEB RHVCC HVCC LDD CSPVM AVM PREGND BHLD RSPRNF SPVM CPREVCC PREVCC CBHLD CVCC VCC ACTGND PREGND CVREG RPRTLIM HU+ PRTLIM HALL1 PREGND PREGND HURFG HV+ FG HALL2 HV- FG RHALLVC ACTGND HALL_VC SLGND HW- SPGND HALL3 PREGND HW+ PRTOUT ERROUT RPRTOUT RERROUT PRTOUT ERROUT PREGND POWERGND Figure 34. Application Example www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 38/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M ▼Recommended values1 for Application Example1 Component name Component value 0.1μF Product name GCM188R11H Series Manufacturer murata 47μF 0.1μF UCD1E470MCL GCM188R11H Series Nichicon murata 470pF 0.1μF GCM188R11H Series GCM188R11H Series murata murata RSPRNF 47μF 0.33Ω UCD1E470MCL MCR100 Series Nichicon Rohm CSPRNF CSPCNF 0.1μF 0.01μF GCM188R11H Series GCM188R11H Series murata murata CAVM 0.1μF 47μF GCM188R11H Series UCD1E470MCL murata Nichicon RTKRNF RTKCDET 0.5Ω 10kΩ MCR100 Series MCR03 Series Rohm Rohm RFCTLRNF RFCTLCDET 0.5Ω 10kΩ MCR100 Series MCR03 Series Rohm Rohm CPRTT CPRTFT 0.1μF 0.1μF GCM188R11H Series GCM188R11H Series murata murata CSLVM 0.1μF 47μF GCM188R11H Series UCD1E470MCL murata Nichicon RSLRNF1 RSLRNF2 0.56Ω 0.56Ω MCR100 Series MCR100 Series Rohm Rohm CSLRNF1 CSLRNF2 0.1μF 0.1μF GCM188R11H Series GCM188R11H Series murata murata CSHV RHVCC 0.1μF 100Ω GCM188R11H Series MCR03 Series murata Rohm RHALLVC CVREG 100Ω 0.01μF MCR03 Series GCM188R11H Series Rohm murata RPRTLIM RFG 47kΩ 3.3kΩ MCR03 Series MCR03 Series Rohm Rohm RPRTOUT RERROUT 33kΩ 33kΩ MCR03 Series MCR03 Series Rohm Rohm CVCC CPREVCC CBHLD CSPVM www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 39/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M Application Example2 CSPRNF SPGND SPGND V_OUT W_OUT TKO+ SPCNF PREGND CSPCNF RTKRNF RTKCDET RFCTLRNF RFCTLCDET PREGND CPRTT CAVM SPRNF U_OUT ACTGND CPRTFT TKOTKRNF TKCDET FCTLO1+ FCTLRNF FCTLCDET FCTLO2+ FCTLO1- FCTLO2LDO+ PRTT PRTFT LDOSLO1+ PREGND Back side metal RSLRNF1 SLRNF1 SLVM SLRNF2 RSLRNF2 CSLVM CSLRNF1 SLGND CSLRNF2 SLO1SLO2+ SLO2- SLGND SHV SHV SLV SCLK SDI SDO μ-con CSHV SAO1+ SAO1SAO2+ SAO2- PREGND POWERGND VREG MUTEB RHVCC HVCC LDD CSPVM AVM PREGND BHLD RSPRNF SPVM CPREVCC PREVCC CBHLD CVCC VCC ACTGND PREGND CVREG HU+ PRTLIM HALL1 PREGND HURFG HV+ FG HALL2 HV- FG ACTGND OPEN HALL_VC SLGND HW- SPGND HALL3 PREGND HW+ RHALL PREGND RPRTLIM PRTOUT ERROUT RPRTOUT RERROUT PRTOUT ERROUT RHALLVC PREGND POWERGND Figure 34. Application Example www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 40/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M ▼Recommended values2 for Application Example2 Component name Component value 0.1μF Product name GCM188R11H Series Manufacturer murata 47μF 0.1μF UCD1E470MCL GCM188R11H Series Nichicon murata 470pF 0.1μF GCM188R11H Series GCM188R11H Series murata murata RSPRNF 47μF 0.33Ω UCD1E470MCL MCR100 Series Nichicon Rohm CSPRNF CSPCNF 0.1μF 0.01μF GCM188R11H Series GCM188R11H Series murata murata CAVM 0.1μF 47μF GCM188R11H Series UCD1E470MCL murata Nichicon RTKRNF RTKCDET 0.5Ω 10kΩ MCR100 Series MCR03 Series Rohm Rohm RFCTLRNF RFCTLCDET 0.5Ω 10kΩ MCR100 Series MCR03 Series Rohm Rohm CPRTT CPRTFT 0.1μF 0.1μF GCM188R11H Series GCM188R11H Series murata murata CSLVM 0.1μF 47μF GCM188R11H Series UCD1E470MCL murata Nichicon RSLRNF1 RSLRNF2 0.56Ω 0.56Ω MCR100 Series MCR100 Series Rohm Rohm CSLRNF1 CSLRNF2 0.1μF 0.1μF GCM188R11H Series GCM188R11H Series murata murata CSHV RHVCC 0.1μF (1) 10Ω GCM188R11H Series MCR03 Series murata Rohm RHALL RHALLVC 100Ω (1) 100Ω MCR03 Series MCR03 Series Rohm Rohm CVREG RPRTLIM 0.01μF 47kΩ GCM188R11H Series MCR03 Series murata Rohm RFG RPRTOUT 3.3kΩ 33kΩ MCR03 Series MCR03 Series Rohm Rohm RERROUT 33kΩ MCR03 Series Rohm CVCC CPREVCC CBHLD CSPVM (1) (1)at HVCC = 3.3V, Hall elements 25°C resistance = 250Ω~450Ω www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 41/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M Power Dissipation 7 (4) 6.2W 6 Power Dissipation [W] 5 (3) 4.5W 4 3 (2) 2.5W 2 (1) 2.0W 1 0 0 25 50 75 100 Ambient Temperature [C] 125 150 175 Figure 35. Power dissipation Note 1: Power dissipation calculated when mounted on 70mm X 70mm X 1.6mm glass epoxy substrate 1-layer platform. Note 2: Power dissipation changes with the copper foil density of the board. This value represents only observed values, not guaranteed values. The board and the back exposure heat radiation board are connected through solder. Board(1) : 1-layer board (backside copper thickness 0mm × 0mm) Board(2) : 2-layer board (backside copper thickness 20mm × 11mm) Board(3) : 2-layer board (backside copper thickness 70mm × 70mm) Board(4) : 4-layer board (backside copper thickness 70mm × 70mm) Board(1) : θja = 62.5 C/W Board(2) : θja = 50.0 C/W Board(3) : θja = 27.8 C/W Board(4) : θja = 20.2 C/W www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 42/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M Input-Output Equivalent Circuit (Number is pin number, the value of resistor and capacitor is typical value) 1.HU+, 2.HU-, 3.HV+, 4.HV-, 5.HW+, 6.HW7.HALL_VC 54 54 54 54 4pF 1 2 50kΩ 50kΩ 3 7 4 12kΩ 5 6 100kΩ 30 10kΩ 30 30 30 30 8.SPCNF 9.BHLD 33 33 33 33 6kΩ 500Ω 200kΩ 10kΩ 5kΩ 9 8 500Ω 10kΩ 500Ω 10kΩ 30 30 10kΩ 30 30 10.SPRNF 11.FG 33 33 2kΩ 1.03kΩ 5kΩ 11 10 30 30 15 30 12.W_OUT, 13.V_OUT, 14.U_OUT, 17.SLO1+, 18.SLO1-, 20.SLO2+, 21.SLO210 19 19.SLRNF1, 22.SLRNF2 22 33 10pF 12 17 20 19 18 21 22 30kΩ 13 14 16 15 16 30 16 23.ERROUT, 36.PRTOUT 24.SDO 29 33 29 1kΩ 23 24 36 30 30 30 30 www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 43/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M 25.SDI, 26.SCLK, 35.MUTEB 27.SLV 28 54 28 28 100kΩ 1kΩ 25 10kΩ 1kΩ 35 27 26 100kΩ 100kΩ 30 30 30 30 30 30 28.VREG 31.PRTT, 32.PRTFT 52 54 53 1kΩ 33 33 28 1kΩ 31 1kΩ 10kΩ 100kΩ 32 1kΩ 10kΩ 30 30 30 30 30 34.PRTLIM 37.LDO-, 38.LDO+ 33 54 33 37 1kΩ 38 1kΩ 34 30 30 39 40.TKO+, 41.TKO-, 42.FCTLO1+, 43.FCTLO1-, 44.FCTLO2+, 45.FCTLO253 46.SAO1+, 47.SAO1-, 48.SAO2+, 49.SAO254 52 42 40 43 41 44 30kΩ 46 30kΩ 47 48 49 45 30 39 30 39 30 50.TKCDET, 51.FCTLCDET 52.FCTLRNF, 53.TKRNF 54 54 54 1kΩ 10kΩ 52 10kΩ 50 53 51 1kΩ 31 39 32 30 30 www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 30 44/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M Operational Notes 1. Reverse Connection of Power Supply Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply terminals. 2. Power Supply Lines Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic capacitors. 3. Ground Voltage Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. However, pins that drive inductive loads (e.g. motor driver outputs, DC-DC converter outputs) may inevitably go below ground due to back EMF or electromotive force. In such cases, the user should make sure that such voltages going below ground will not cause the IC and the system to malfunction by examining carefully all relevant factors and conditions such as motor characteristics, supply voltage, operating frequency and PCB wiring to name a few. 4. Ground Wiring Pattern When using both small-signal and large-current ground traces, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal ground caused by large currents. Also ensure that the ground traces of external components do not cause variations on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance. 5. Thermal Consideration Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in deterioration of the properties of the chip. The absolute maximum rating of the Pd stated in this specification is when the IC is mounted on a 70mm x 70mm x 1.6mm glass epoxy board. In case of exceeding this absolute maximum rating, increase the board size and copper area to prevent exceeding the Pd rating. 6. Recommended Operating Conditions These conditions represent a range within which the expected characteristics of the IC can be approximately obtained. The electrical characteristics are guaranteed under the conditions of each parameter. 7. Rush Current When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of connections. 8. Operation Under Strong Electromagnetic Field Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction. 9. Testing on Application Boards When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be turned off completely before connecting or removing it from the test setup during the inspection process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage. 10. Inter-pin Short and Mounting Errors Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin. Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins during assembly to name a few. www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 45/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M Operational Notes – continued 11. Unused Input Terminals Input terminals of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause unexpected operation of the IC. So unless otherwise specified, unused input terminals should be connected to the power supply or ground line. 12. Regarding the Input Pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a parasitic diode or transistor. For example (refer to figure below): When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided. Resistor Transistor (NPN) Pin A Pin B C E Pin A N P+ P N N P+ N Pin B B Parasitic Elements N P+ N P N P+ B N C E Parasitic Elements P Substrate P Substrate GND GND Parasitic Elements GND Parasitic Elements GND N Region close-by Figure 36. Example of monolithic IC structure 13. Ceramic Capacitor When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with temperature and the decrease in nominal capacitance due to DC bias and others. 14. Area of Safe Operation (ASO) Operate the IC such that the output voltage, output current, and power dissipation are all within the Area of Safe Operation (ASO). 15. Thermal Shutdown Circuit(TSD) This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below the TSD threshold, the circuits are automatically restored to normal operation. Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat damage. www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 46/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M Ordering Information B D 8 2 5 Part Number 6 E F V - Package EFV : HTSSOP-B54 M E 2 Packaging and forming specification M: High relaiability E2: Embossed tape and reel (HTSSOP-B54) Marking Diagram HTSSOP-B54 (TOP VIEW) Part Number Marking BD8256EFV LOT Number 1PIN MARK www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 47/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M Physical Dimension, Tape and Reel Information Package Name www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 HTSSOP-B54 48/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 BD8256EFV-M Revision History Date Revision Changes 1.Aug.2013 25.Apr.2014 002 003 4.Apr.2016 004 New release P.1 Add the sentence of AEC-Q100 Qualified at the features P.2 Change : Pin3 HV+ V negative⇒V positive Pin4 HV- V positive⇒V negative P.3 Change : (2)FCCDET⇒FCTLCDET, (3)LDO⇒LDO-, (4)SAO2⇒SAO2P.4, 5 Add RL=8Ω at the conditions P.9 Change : **P9⇒P.15 P.18 Change : DACFCTL2 = DFCTL2 - DFCTL2⇒DACFCTL2 = DFCTL2 - DFCTL1 P.20 Add *Condition:RSLRNF=0.56Ω P.21 Add *Condition:RSPRNF=0.33Ω P.26 Change : Figure 22. CSPRNF⇒CSPCNF P.27 5.Update : Hall input voltage range from 1.0 ~ 3.8V to 1.5 ~ 3.8V Add : Explanation about Hall bias P.33 Change : VPRTDET:3.0V(Typ)⇒2.95V(Typ), Vd=VPRTLIM-VPRREF⇒Vd=VPRTDET-VPRTREF P.37 Change : FCTLO+, SA1O+, SA2O- ⇒FCTLO1+, SAO1+, SAO2P.38 Change : title : from Application Example to Application Example1, Change : FCRNF, FCCDET, RFCRNF, RFCCDET⇒FCTLRNF, FCTLCDET, RFCTLRNF, RFCTLCDET P.39 Change title : from Recommended values to Recommended values1 for Application Example1 Change : RFCRNF, RFCCDET⇒RFCTLRNF, RFCTLCDET P.40 New addition : Application Example2 P.41 New addition : Recommended values2 for Application Example2 P.43, P.44 Change : 12.U_OUT, 14.W_OUT⇒12.W_OUT, 14.U_OUT, Update : Figure about Pin10, 25, 26, 35, 27, 28, 34, 52, 53 www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 49/49 TSZ02201-0G1G0BK00030-1-2 4.Apr.2016 Rev.004 Notice Precaution on using ROHM Products 1. (Note 1) If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment , aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific Applications. (Note1) Medical Equipment Classification of the Specific Applications JAPAN USA EU CHINA CLASSⅢ CLASSⅡb CLASSⅢ CLASSⅢ CLASSⅣ CLASSⅢ 2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which a failure or malfunction of our Products may cause. The following are examples of safety measures: [a] Installation of protection circuits or other protective devices to improve system safety [b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our Products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents [b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust [c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves [e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items [f] Sealing or coating our Products with resin or other coating materials [g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] Use of the Products in places subject to dew condensation 4. The Products are not subject to radiation-proof design. 5. Please verify and confirm characteristics of the final or mounted products in using the Products. 6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied, confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability. 7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in the range that does not exceed the maximum junction temperature. 8. Confirm that operation temperature is within the specified range described in the product specification. 9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document. Precaution for Mounting / Circuit board design 1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products, please consult with the ROHM representative in advance. For details, please refer to ROHM Mounting specification Notice-PAA-E © 2015 ROHM Co., Ltd. All rights reserved. Rev.003 Precautions Regarding Application Examples and External Circuits 1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the characteristics of the Products and external components, including transient characteristics, as well as static characteristics. 2. You agree that application notes, reference designs, and associated data and information contained in this document are presented only as guidance for Products use. Therefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. Precaution for Electrostatic This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control). Precaution for Storage / Transportation 1. Product performance and soldered connections may deteriorate if the Products are stored in the places where: [a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [b] the temperature or humidity exceeds those recommended by ROHM [c] the Products are exposed to direct sunshine or condensation [d] the Products are exposed to high Electrostatic 2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is exceeding the recommended storage time period. 3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of which storage time is exceeding the recommended storage time period. Precaution for Product Label A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only. Precaution for Disposition When disposing Products please dispose them properly using an authorized industry waste company. Precaution for Foreign Exchange and Foreign Trade act Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign trade act, please consult with ROHM in case of export. Precaution Regarding Intellectual Property Rights 1. All information and data including but not limited to application example contained in this document is for reference only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. 2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the Products with other articles such as components, circuits, systems or external equipment (including software). 3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to manufacture or sell products containing the Products, subject to the terms and conditions herein. Other Precaution 1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM. 2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of ROHM. 3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the Products or this document for any military purposes, including but not limited to, the development of mass-destruction weapons. 4. The proper names of companies or products described in this document are trademarks or registered trademarks of ROHM, its affiliated companies or third parties. Notice-PAA-E © 2015 ROHM Co., Ltd. All rights reserved. Rev.003 Datasheet General Precaution 1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents. ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny ROHM’s Products against warning, caution or note contained in this document. 2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s representative. 3. The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or concerning such information. Notice – WE © 2015 ROHM Co., Ltd. All rights reserved. Rev.001 Datasheet BD8256EFV-M - Web Page Buy Distribution Inventory Part Number Package Unit Quantity Minimum Package Quantity Packing Type Constitution Materials List RoHS BD8256EFV-M HTSSOP-B54 1500 1500 Taping inquiry Yes