Numonyx M25P64-VME6TP 64 mbit, low voltage, serial flash memory with 50 mhz spi bus interface Datasheet

M25P64
64 Mbit, low voltage, Serial Flash memory
with 50 MHz SPI bus interface
Features
■
64 Mbit of Flash memory
■
2.7 V to 3.6 V single supply voltage
■
SPI bus compatible serial interface
■
50 MHz clock rate (maximum)
■
VPP = 9 V for Fast Program/Erase mode
(optional)
■
Page Program (up to 256 Bytes)
– in 1.4 ms (typical)
– in 0.35 ms (typical with VPP = 9 V)
■
Sector Erase (512 Kbit)
■
Bulk Erase (64 Mbit)
■
Electronic Signatures
– JEDEC standard two-Byte signature
(2017h)
– RES instruction, one-Byte, signature (16h),
for backward compatibility
■
Hardware Write Protection: protected area size
defined by three non-volatile bits (BP0, BP1
and BP2)
■
More than 100 000 Erase/Program cycles per
sector
■
More than 20-year data retention
■
Packages
– ECOPACK® (RoHS compliant)
December 2007
VDFPN8 (ME)
8 × 6 mm (MLP8)
SO16 (MF)
300 mils width
Rev 7
1/50
www.numonyx.com
1
Contents
M25P64
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6
Write Protect/Enhanced Program supply voltage (W/VPP) . . . . . . . . . . . . 10
2.7
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3
Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13
4.4
Fast Program/Erase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.8
Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4.1
2/50
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
M25P64
Contents
6.4.2
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4.3
BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4.4
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.5
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.6
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.7
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 31
6.8
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.9
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.10
Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.11
Read Electronic Signature (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7
Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3/50
List of tables
M25P64
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
4/50
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Power-Up timing and VWI threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SO16 wide – 16 lead Plastic Small Outline, 300 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
M25P64
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 25
Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 27
Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 30
Read Data Bytes at Higher Speed (FAST_READ) instruction and data-out sequence . . . 31
Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Read Electronic Signature (RES) instruction sequence and data-out sequence . . . . . . . . 36
Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Write Protect setup and hold timing during WRSR when SRWD = 1 . . . . . . . . . . . . . . . . . 43
Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
VPPH timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SO16 wide – 16 lead Plastic Small Outline, 300 mils body width . . . . . . . . . . . . . . . . . . . . 46
5/50
Description
1
M25P64
Description
The M25P64 is a 64 Mbit (8M x 8) Serial Flash Memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program
instruction.
An enhanced Fast Program/Erase mode is available to speed up operations in factory
environment. The device enters this mode whenever the VPPH voltage is applied to the Write
Protect/Enhanced Program Supply Voltage pin (W/VPP).
The memory is organized as 128 sectors, each containing 256 pages. Each page is 256
bytes wide. Thus, the whole memory can be viewed as consisting of 32768 pages, or
8388608 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,
using the Sector Erase instruction.
In order to meet environmental requirements, Numonyx offers the M25P64 in ECOPACK®
packages. ECOPACK® packages are Lead-free and RoHS compliant.
6/50
M25P64
Description
Figure 1.
Logic diagram
VCC
D
Q
C
S
M25P64
W/VPP
HOLD
VSS
AI07485B
Table 1.
Signal names
Signal name
Function
Direction
C
Serial Clock
Input
D
Serial Data Input
Input
Q
Serial Data Output
Output
S
Chip Select
Input
W/VPP
Write Protect/Enhanced Program Supply Voltage
Input
HOLD
Hold
Input
VCC
Supply Voltage
VSS
Ground
Figure 2.
VDFPN connections
M25P64
S
Q
W/VPP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
C
D
AI08595B
1. There is an exposed central pad on the underside of the VDFPN package. This is pulled, internally, to VSS,
and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See Section 11: Package mechanical for package dimensions, and how to identify pin-1.
7/50
Description
M25P64
Figure 3.
SO connections
M25P64
HOLD
VCC
DU
DU
DU
DU
S
Q
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C
D
DU
DU
DU
DU
VSS
W/VPP
AI07486C
1. DU = Don’t Use
2. See Section 11: Package mechanical for package dimensions, and how to identify pin-1.
8/50
M25P64
Signal description
2
Signal description
2.1
Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2
Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress,
the device will be in the Standby Power mode. Driving Chip Select (S) Low selects the
device, placing it in the Active Power mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
9/50
Signal description
2.6
M25P64
Write Protect/Enhanced Program supply voltage (W/VPP)
W/VPP is both a control input and a power supply pin. The two functions are selected by the
voltage range applied to the pin.
If the W/VPP input is kept in a low voltage range (0V to VCC) the pin is seen as a control
input. This input signal is used to freeze the size of the area of memory that is protected
against program or erase instructions (as specified by the values in the BP2, BP1 and BP0
bits of the Status Register).
If VPP is in the range of VPPH it acts as an additional power supply pin. In this case VPP must
be stable until the Program/Erase algorithm is completed.
2.7
VCC supply voltage
VCC is the supply voltage.
2.8
VSS ground
VSS is the reference for the VCC supply voltage.
10/50
M25P64
3
SPI modes
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
●
CPOL=0, CPHA=0
●
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●
C remains at 0 for (CPOL=0, CPHA=0)
●
C remains at 1 for (CPOL=1, CPHA=1)
Figure 4.
Bus master and memory devices on the SPI bus
VSS
VCC
R
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C Q D
VCC
VCC
VSS
SPI Bus Master
SPI Memory
Device
R
CS3
C Q D
C Q D
VCC
VSS
SPI Memory
Device
R
VSS
SPI Memory
Device
R
CS2 CS1
S
W/VPP HOLD
S
W/VPP HOLD
S
W/VPP HOLD
AI13792
1. The Write Protect (W/VPP) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 4 shows an example of three devices connected to an MCU, on an SPI bus. Only one
device is selected at a time, so only one device drives the Serial Data Output (Q) line at a
time, the other devices are high impedance. Resistors R (represented in Figure 4) ensure
that the M25P64 is not selected if the Bus Master leaves the S line in the high impedance
state. As the Bus Master may enter a state where all inputs/outputs are in high impedance
at the same time (for example, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and
C do not become High at the same time, and so, that the tSHCH requirement is met). The
typical value of R is 100 kΩ, assuming that the time constant R*Cp (Cp = parasitic
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.
11/50
SPI modes
M25P64
Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the Bus
Master never leaves the SPI bus in the high impedance state for a time period shorter than
5 µs.
Figure 5.
SPI modes supported
CPOL CPHA
0
0
C
1
1
C
D
Q
MSB
MSB
AI01438B
12/50
M25P64
Operating features
4
Operating features
4.1
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one
byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is
followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted Bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few Bytes (see Page Program (PP)
and Table 14: AC characteristics).
4.2
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be
achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the
entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of
duration tSE or tBE).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
4.3
Polling during a Write, Program or Erase cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase
(SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The
Write In Progress (WIP) bit is provided in the Status Register so that the application program
can monitor its value, polling it to establish when the previous Write cycle, Program cycle or
Erase cycle is complete.
4.4
Fast Program/Erase mode
The Fast Program/Erase mode is used to speed up programming/erasing. The device
enters the Fast Program/Erase mode during the Page Program, Sector Erase or Bulk Erase
instruction whenever a voltage equal to VPPH is applied to the W/VPP pin.
The use of the Fast Program/Erase mode requires specific operating conditions in addition
to the normal ones (VCC must be within the normal operating range):
●
the voltage applied to the W/VPP pin must be equal to VPPH (see Table 10)
●
ambient temperature, TA must be 25°C ±10°C,
●
the cumulated time during which W/VPP is at VPPH should be less than 80 hours
13/50
Operating features
4.5
M25P64
Active Power and Standby Power modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active Power
mode until all internal cycles have completed (Program, Erase, Write Status Register). The
device then goes in to the Standby Power mode. The device consumption drops to ICC1.
4.6
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. For a detailed description of the Status Register bits,
see Section 6.4: Read Status Register (RDSR).
14/50
M25P64
4.7
Operating features
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P64 features the following data protection mechanisms:
●
Power On Reset and an internal timer (tPUW) can provide protection against inadvertant
changes while the power supply is outside the operating specification.
●
Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
●
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
Power-up
–
Write Disable (WRDI) instruction completion
–
Write Status Register (WRSR) instruction completion
–
Page Program (PP) instruction completion
–
Sector Erase (SE) instruction completion
–
Bulk Erase (BE) instruction completion
●
The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as
read-only. This is the Software Protected Mode (SPM).
●
The Write Protect (W/VPP) signal allows the Block Protect (BP2, BP1, BP0) bits and
Status Register Write Disable (SRWD) bit to be protected. This is the Hardware
Protected Mode (HPM).
Table 2.
Protected area sizes
Status Register
content
Memory content
BP2 BP1 BP0
Bit
Bit
Bit
Protected area
Unprotected area
0
0
0
none
All sectors(1) (128 sectors: 0 to 127)
0
0
1
Upper 64th (2 sectors: 126 and 127)
Lower 63/64ths (126 sectors: 0 to 125)
0
1
0
Upper 32nd (4 sectors: 124 to 127)
Lower 31/32nds (124 sectors: 0 to 123)
0
1
1
Upper sixteenth (8 sectors: 120 to
127)
Lower 15/16ths (120 sectors: 0 to 119)
1
0
0
Upper eighth (16 sectors: 112 to 127)
Lower seven-eighths (112 sectors: 0 to
111)
1
0
1
Upper quarter (32 sectors: 96 to 127)
Lower three-quarters (96 sectors: 0 to
95)
1
1
0
Upper half (64 sectors: 64 to 127)
Lower half (64 sectors: 0 to 63)
1
1
1
All sectors (128 sectors: 0 to 127)
none
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are
0.
15/50
Operating features
4.8
M25P64
Hold Condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low (as shown in Figure 6).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low. (This is shown in Figure 6).
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration
of the Hold condition. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
Figure 6.
Hold condition activation
C
HOLD
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
AI02029D
16/50
M25P64
Memory organization
The memory is organized as:
●
8388608 bytes (8 bits each)
●
128 sectors (512 Kbits, 65536 bytes each)
●
32768 pages (256 bytes each).
Each page can be individually programmed (bits are programmed from 1 to 0). The device is
Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable.
Figure 7.
Block diagram
HOLD
W/VPP
High Voltage
Generator
Control Logic
S
C
D
I/O Shift Register
Q
Address Register
and Counter
Status
Register
256 Byte
Data Buffer
7FFFFFh
Size of the
read-only
memory area
Y Decoder
5
Memory organization
00000h
000FFh
256 Bytes (Page Size)
X Decoder
AI08520B
17/50
Memory organization
Table 3.
M25P64
Memory organization
Sector
18/50
Address range
127
7F0000h
7FFFFFh
126
7E0000h
7EFFFFh
125
7D0000h
7DFFFFh
124
7C0000h
7CFFFFh
123
7B0000h
7BFFFFh
122
7A0000h
7AFFFFh
121
790000h
79FFFFh
120
780000h
78FFFFh
119
770000h
77FFFFh
118
760000h
76FFFFh
117
750000h
75FFFFh
116
740000h
74FFFFh
115
730000h
73FFFFh
114
720000h
72FFFFh
113
710000h
71FFFFh
112
700000h
70FFFFh
111
6F0000h
6FFFFFh
110
6E0000h
6EFFFFh
109
6D0000h
6DFFFFh
108
6C0000h
6CFFFFh
107
6B0000h
6BFFFFh
106
6A0000h
6AFFFFh
105
690000h
69FFFFh
104
680000h
68FFFFh
103
670000h
67FFFFh
102
660000h
66FFFFh
101
650000h
65FFFFh
100
640000h
64FFFFh
99
630000h
63FFFFh
98
620000h
62FFFFh
97
610000h
61FFFFh
96
600000h
60FFFFh
95
5F0000h
5FFFFFh
94
5E0000h
5EFFFFh
93
5D0000h
5DFFFFh
M25P64
Memory organization
Table 3.
Memory organization (continued)
Sector
Address range
92
5C0000h
5CFFFFh
91
5B0000h
5BFFFFh
90
5A0000h
5AFFFFh
89
590000h
59FFFFh
88
580000h
58FFFFh
87
570000h
57FFFFh
86
560000h
56FFFFh
85
550000h
55FFFFh
84
540000h
54FFFFh
83
530000h
53FFFFh
82
520000h
52FFFFh
81
510000h
51FFFFh
80
500000h
50FFFFh
79
4F0000h
4FFFFFh
78
4E0000h
4EFFFFh
77
4D0000h
4DFFFFh
76
4C0000h
4CFFFFh
75
4B0000h
4BFFFFh
74
4A0000h
4AFFFFh
73
490000h
49FFFFh
72
480000h
48FFFFh
71
470000h
47FFFFh
70
460000h
46FFFFh
69
450000h
45FFFFh
68
440000h
44FFFFh
67
430000h
43FFFFh
66
420000h
42FFFFh
65
410000h
41FFFFh
64
400000h
40FFFFh
63
3F0000h
3FFFFFh
62
3E0000h
3EFFFFh
61
3D0000h
3DFFFFh
60
3C0000h
3CFFFFh
59
3B0000h
3BFFFFh
58
3A0000h
3AFFFFh
19/50
Memory organization
Table 3.
M25P64
Memory organization (continued)
Sector
20/50
Address range
57
390000h
39FFFFh
56
380000h
38FFFFh
55
370000h
37FFFFh
54
360000h
36FFFFh
53
350000h
35FFFFh
52
340000h
34FFFFh
51
330000h
33FFFFh
50
320000h
32FFFFh
49
310000h
31FFFFh
48
300000h
30FFFFh
47
2F0000h
2FFFFFh
46
2E0000h
2EFFFFh
45
2D0000h
2DFFFFh
44
2C0000h
2CFFFFh
43
2B0000h
2BFFFFh
42
2A0000h
2AFFFFh
41
290000h
29FFFFh
40
280000h
28FFFFh
39
270000h
27FFFFh
38
260000h
26FFFFh
37
250000h
25FFFFh
36
240000h
24FFFFh
35
230000h
23FFFFh
34
220000h
22FFFFh
33
210000h
21FFFFh
32
200000h
20FFFFh
31
1F0000h
1FFFFFh
30
1E0000h
1EFFFFh
29
1D0000h
1DFFFFh
28
1C0000h
1CFFFFh
27
1B0000h
1BFFFFh
26
1A0000h
1AFFFFh
25
190000h
19FFFFh
24
180000h
18FFFFh
23
170000h
17FFFFh
M25P64
Memory organization
Table 3.
Memory organization (continued)
Sector
Address range
22
160000h
16FFFFh
21
150000h
15FFFFh
20
140000h
14FFFFh
19
130000h
13FFFFh
18
120000h
12FFFFh
17
110000h
11FFFFh
16
100000h
10FFFFh
15
0F0000h
0FFFFFh
14
0E0000h
0EFFFFh
13
0D0000h
0DFFFFh
12
0C0000h
0CFFFFh
11
0B0000h
0BFFFFh
10
0A0000h
0AFFFFh
9
090000h
09FFFFh
8
080000h
08FFFFh
7
070000h
07FFFFh
6
060000h
06FFFFh
5
050000h
05FFFFh
4
040000h
04FFFFh
3
030000h
03FFFFh
2
020000h
02FFFFh
1
010000h
01FFFFh
0
000000h
00FFFFh
21/50
Instructions
6
M25P64
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select
(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most
significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed in Table 4.
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),
Read Status Register (RDSR), Read Identification (RDID) or Read Electronic Signature
(RES) instruction, the shifted-in instruction sequence is followed by a data-out sequence.
Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted
out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status
Register (WRSR), Write Enable (WREN) or Write Disable (WRDI), Chip Select (S) must be
driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not
executed. That is, Chip Select (S) must driven High when the number of clock pulses after
Chip Select (S) being driven Low is an exact multiple of eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
Table 4.
Instruction
Description
One-byte instruction
code
Address
bytes
Dummy
bytes
Data
bytes
WREN
Write Enable
0000 0110
06h
0
0
0
WRDI
Write Disable
0000 0100
04h
0
0
0
RDID
Read Identification
1001 1111
9Fh
0
0
1 to 3
RDSR
Read Status Register
0000 0101
05h
0
0
1 to ∞
WRSR
Write Status Register
0000 0001
01h
0
0
1
READ
Read Data Bytes
0000 0011
03h
3
0
1 to ∞
Read Data Bytes at
Higher Speed
0000 1011
0Bh
3
1
1 to ∞
PP
Page Program
0000 0010
02h
3
0
1 to
256
SE
Sector Erase
1101 1000
D8h
3
0
0
BE
Bulk Erase
1100 0111
C7h
0
0
0
Read Electronic Signature
1010 1011
ABh
0
3
1 to ∞
FAST_READ
RES
22/50
Instruction set
M25P64
6.1
Instructions
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector
Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 8.
Write Enable (WREN) instruction sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI02281E
23/50
Instructions
6.2
M25P64
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
●
Power-up
●
Write Disable (WRDI) instruction completion
●
Write Status Register (WRSR) instruction completion
●
Page Program (PP) instruction completion
●
Sector Erase (SE) instruction completion
●
Bulk Erase (BE) instruction completion
Figure 9.
Write Disable (WRDI) instruction sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI03750D
24/50
M25P64
6.3
Instructions
Read Identification (RDID)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be
read, followed by two bytes of device identification. The manufacturer identification is
assigned by JEDEC, and has the value 20h for Numonyx. The device identification is
assigned by the device manufacturer, and indicates the memory type in the first byte (20h),
and the memory capacity of the device in the second byte (17h).
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is
not decoded, and has no effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in. This is followed by the 24-bit device identification, stored in
the memory, being shifted out on Serial Data Output (Q), each bit being shifted out during
the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 10.
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Table 5.
Read Identification (RDID) data-out sequence
Device Identification
Manufacturer Identification
20h
Memory Type
Memory Capacity
20h
17h
Figure 10. Read Identification (RDID) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
C
Instruction
D
Manufacturer Identification
Device Identification
High Impedance
Q
15 14 13
MSB
3
2
1
0
MSB
AI06809b
25/50
Instructions
6.4
M25P64
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is
also possible to read the Status Register continuously, as shown in Figure 11.
Table 6.
Status Register format
b7
SRWD
b0
0
0
BP2
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
The status and control bits of the Status Register are as follows:
6.4.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to
0 no such cycle is in progress.
6.4.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
6.4.3
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes
protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect
(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,
BP1, BP0) bits are 0.
26/50
M25P64
6.4.4
Instructions
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write Protect
(W/VPP) signal allow the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W/VPP) is driven Low). In
this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become
read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for
execution.
Figure 11. Read Status Register (RDSR) instruction sequence and data-out
sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
D
Status Register Out
Status Register Out
High Impedance
Q
7
MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
AI02031E
27/50
Instructions
6.5
M25P64
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data Input (D).
The instruction sequence is shown in Figure 12.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the
Status Register. b6 and b5 are always read as 0.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in Table 2. The Write Status Register (WRSR) instruction also allows
the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the
Write Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write
Protect (W/VPP) signal allow the device to be put in the Hardware Protected Mode (HPM).
The Write Status Register (WRSR) instruction is not executed once the Hardware Protected
Mode (HPM) is entered.
Table 7.
Protection modes
W/VPP SRWD
signal
bit
1
0
0
0
1
1
0
1
Mode
Write Protection of the
Status Register
Memory content
Protected area(1)
Unprotected area(1)
Status Register is Writable
(if the WREN instruction
Software has set the WEL bit)
Protected
(SPM) The values in the SRWD,
BP2, BP1 and BP0 bits
can be changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
Status Register is
Hardware Hardware write protected
Protected The values in the SRWD,
(HPM) BP2, BP1 and BP0 bits
cannot be changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
Table 2.
The protection features of the device are summarized in Table 7.
28/50
M25P64
Instructions
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W/VPP) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W/VPP):
●
If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.
●
If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register
even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the Status Register are rejected, and are not
accepted for execution). As a consequence, all the data bytes in the memory area that
are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status
Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
●
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect
(W/VPP) Low
●
or by driving Write Protect (W/VPP) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect/ (W/VPP) High.
If Write Protect/ (W/VPP) is permanently tied High, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
Figure 12. Write Status Register (WRSR) instruction sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
Status
Register In
7
D
High Impedance
6
5
4
3
2
1
0
MSB
Q
AI02282D
29/50
Instructions
6.6
M25P64
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum
frequency fR, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-Bit Address
23 22 21
D
3
2
1
0
MSB
Data Out 1
High Impedance
Q
7
6
5
4
3
2
Data Out 2
1
0
7
MSB
AI03748D
1. Address bit A23 is Don’t Care.
30/50
M25P64
6.7
Instructions
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each
bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 14.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 14. Read Data Bytes at Higher Speed (FAST_READ) instruction and data-out
sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
C
Instruction
24 BIT ADDRESS
23 22 21
D
3
2
1
0
High Impedance
Q
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy Byte
D
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
Q
7
MSB
6
5
4
3
2
1
0
7
MSB
6
5
4
3
2
1
0
7
MSB
AI04006
1. Address bit A23 is Don’t Care.
31/50
Instructions
6.8
M25P64
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address bytes and at least one data byte on Serial Data Input (D).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 15.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 Data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted Bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few Bytes (see Table 14: AC
characteristics).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.
32/50
M25P64
Instructions
Figure 15. Page Program (PP) instruction sequence
S
0
1
2
3
4
5
6
7
8
28 29 30 31 32 33 34 35 36 37 38 39
9 10
C
Instruction
24-Bit Address
23 22 21
D
3
2
Data Byte 1
1
0
7
6
5
4
3
2
0
1
MSB
MSB
2078
2079
2077
2076
2075
2074
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
S
1
0
C
Data Byte 2
D
7
6
MSB
5
4
3
2
Data Byte 3
1
0
7
MSB
6
5
4
3
2
Data Byte 256
1
0
7
6
5
4
3
2
MSB
AI04082B
33/50
Instructions
6.9
M25P64
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on Serial Data Input (D). Any address inside the
Sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 16.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.
Figure 16. Sector Erase (SE) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
Instruction
D
24 Bit Address
23 22
2
1
0
MSB
AI03751D
1. Address bit A23 is Don’t Care.
34/50
M25P64
6.10
Instructions
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 17.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are
0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 17. Bulk Erase (BE) instruction sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
AI03752D
35/50
Instructions
6.11
M25P64
Read Electronic Signature (RES)
The instruction is used to read, on Serial Data Output (Q), the old-style 8-bit Electronic
Signature, whose value for the M25P64 is 16h.
Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic
Signature that is read by the Read Identifier (RDID) instruction. The old-style Electronic
Signature is supported for reasons of backward compatibility, only, and should not be used
for new designs. New designs should, instead, make use of the JEDEC 16-bit Electronic
Signature, and the Read Identifier (RDID) instruction.
The device is first selected by driving Chip Select (S) Low. The instruction code is followed
by 3 dummy bytes, each bit being latched-in on Serial Data Input (D) during the rising edge
of Serial Clock (C). Then, the old-style 8-bit Electronic Signature, stored in the memory, is
shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 18.
The Read Electronic Signature (RES) instruction is terminated by driving Chip Select (S)
High after the Electronic Signature has been read at least once. Sending additional clock
cycles on Serial Clock (C), while Chip Select (S) is driven Low, cause the Electronic
Signature to be output repeatedly.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device,
but before the whole of the 8-bit Electronic Signature has been transmitted for the first time,
still ensures that the device is put into Standby Power mode. Once in the Standby Power
mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
Figure 18. Read Electronic Signature (RES) instruction sequence and data-out
sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
C
Instruction
3 Dummy Bytes
23 22 21
D
3
2
1
0
MSB
Electronic Signature Out
High Impedance
Q
7
MSB
1. The value of the 8-bit Electronic Signature, for the M25P64, is 16h.
36/50
6
5
4
3
2
1
0
AI04047C
M25P64
7
Power-up and Power-down
Power-up and Power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on VCC) until VCC reaches the correct value:
●
VCC(min) at Power-up, and then for a further delay of tVSL
●
VSS at Power-down
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during Power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less
than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and
the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of
tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the
correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min).
No Write Status Register, Program or Erase instructions should be sent until the later of:
●
tPUW after VCC passed the VWI threshold
●
tVSL after VCC passed the VCC(min) level
These values are specified in Table 8.
If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be
selected for READ instructions even if the tPUW delay is not yet fully elapsed.
At Power-up, the device is in the following state:
●
The device is in the Standby Power mode
●
The Write Enable Latch (WEL) bit is reset
●
The Write In Progress (WIP) bit is reset
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply.
Each device in a system should have the VCC rail decoupled by a suitable capacitor close to
the package pins. (Generally, this capacitor is of the order of 100 nF).
At Power-down, when VCC drops from the operating voltage, to below the Power On Reset
(POR) threshold voltage, VWI, all operations are disabled and the device does not respond
to any instruction. (The designer needs to be aware that if a Power-down occurs while a
Write, Program or Erase cycle is in progress, some data corruption can result.).
Power up sequencing for Fast program/erase mode: VCC should attain VCCMIN before VPPH
is applied.
37/50
Power-up and Power-down
M25P64
Figure 19. Power-up timing
VCC
VCC(max)
Program, Erase and Write Commands are Rejected by the Device
Chip Selection Not Allowed
VCC(min)
tVSL
Reset State
of the
Device
Read Access allowed
Device fully
accessible
VWI
tPUW
time
AI04009C
Table 8.
Power-Up timing and VWI threshold
Symbol
Parameter
Max.
Unit
tVSL(1)
VCC(min) to S low
30
tPUW(1)
Time delay to Write instruction
1
10
ms
VWI(1)
Write Inhibit Voltage
1.5
2.5
V
1. These parameters are characterized only.
38/50
Min.
µs
M25P64
8
Initial delivery state
Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each byte
contains FFh). The Status Register contains 00h (all Status Register bits are 0).
9
Maximum rating
Stressing the device outside the ratings listed in Table 9 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the Operating sections of this specification, is not
implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability. Refer also to the Numonyx SURE Program and other relevant quality
documents.
Table 9.
Absolute maximum ratings
Symbol
Parameter
TSTG
Storage Temperature
TLEAD
Lead Temperature during Soldering
Min.
Max.
Unit
–65
150
°C
See note (1)
°C
VIO
Input and Output Voltage (with respect to Ground)
–0.5
VCC +
0.6
V
VCC
Supply Voltage
–0.2
4.0
V
VPP
Fast Program/Erase Voltage
–0.2
10.0
V
–2000
2000
V
VESD
Electrostatic Discharge Voltage (Human Body model)
(2)
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx
ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous
Substances (RoHS) 2002/95/EU
2. JEDEC Std JESD22-A114A (C1=100 pF, R1 = 1500 Ω, R2 = 500 Ω).
39/50
DC and AC parameters
10
M25P64
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 10.
Operating conditions
Symbol
Parameter
Min.
Typ
Max.
Unit
VCC
Supply Voltage
2.7
3.6
V
VPPH
Supply Voltage on W/VPP pin for Fast Program/Erase
mode
8.5
9.5
V
Ambient Operating Temperature
–40
85
°C
Ambient Operating Temperature for Fast
Program/Erase mode
15
35
°C
TA
TAVPP
Table 11.
AC measurement conditions
Symbol
CL
25
Parameter
Min.
Max.
Load Capacitance
30
Input Rise and Fall Times
Unit
pF
5
ns
Input Pulse Voltages
0.2VCC to 0.8VCC
V
Input Timing Reference Voltages
0.3VCC to 0.7VCC
V
VCC / 2
V
Output Timing Reference Voltages
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 20. AC measurement I/O waveform
Input Levels
Input and Output
Timing Reference Levels
0.8VCC
0.7VCC
0.5VCC
0.3VCC
0.2VCC
AI07455
Table 12.
Symbol
Capacitance
Parameter
COUT
Output Capacitance (Q)
CIN
Input Capacitance (other pins)
Test condition
Max.
Unit
VOUT = 0 V
8
pF
VIN = 0 V
6
pF
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 20 MHz.
40/50
Min.
M25P64
DC and AC parameters
Table 13.
DC characteristics
Symbol
Parameter
Test condition
(in addition to those in
Table 10)
Min.
Max.
Unit
ILI
Input Leakage Current
±2
µA
ILO
Output Leakage Current
±2
µA
ICC1
Standby Current
S = VCC, VIN = VSS or VCC
100
µA
C = 0.1VCC / 0.9.VCC at 50 MHz,
Q = open
8
mA
C = 0.1VCC / 0.9.VCC at 20 MHz,
Q = open
4
mA
ICC3
Operating Current (READ)
ICC4
Operating Current (PP)
S = VCC
15
mA
ICC5
Operating Current (WRSR)
S = VCC
20
mA
ICC6
Operating Current (SE)
S = VCC
20
mA
ICC7
Operating Current (BE)
S = VCC
20
mA
ICCPP
Operating current for Fast
Program/Erase mode
S = VCC, VPP = VPPH
20
mA
IPP
VPP Operating current in
Fast Program/Erase mode
S = VCC, VPP = VPPH
20
mA
VIL
Input Low Voltage
– 0.5
0.3VCC
V
VIH
Input High Voltage
0.7VCC
VCC+0.2
V
VOL
Output Low Voltage
IOL = 1.6 mA
0.4
V
VOH
Output High Voltage
IOH = –100 µA
VCC–0.2
V
41/50
DC and AC parameters
Table 14.
M25P64
AC characteristics
Test conditions specified in Table 10 and Table 11
Symbol
Alt.
fC
fC
fR
tCH (1)
tCL
(1)
tCLCH
Min.
Typ.
Max.
Unit
Clock Frequency for the following instructions: FAST_READ,
D.C.
PP, SE, BE, RES, WREN, WRDI, RDID, RDSR, WRSR
50
MHz
Clock Frequency for READ instructions
20
MHz
D.C.
tCLH Clock High Time
9
ns
tCLL Clock Low Time
9
ns
0.1
V/ns
0.1
V/ns
5
ns
(3)
(2)
Clock Rise Time
tCHCL (2)
tSLCH
Parameter
(peak to peak)
Clock Fall Time(3) (peak to peak)
tCSS S Active Setup Time (relative to C)
tCHSL
5
ns
tDVCH
tDSU Data In Setup Time
S Not Active Hold Time (relative to C)
2
ns
tCHDX
tDH
Data In Hold Time
5
ns
tCHSH
S Active Hold Time (relative to C)
5
ns
tSHCH
S Not Active Setup Time (relative to C)
5
ns
tSHSL
tCSH S Deselect Time
tSHQZ (2)
tDIS
tCLQV
tV
tCLQX
tHO
100
ns
Output Disable Time
8
ns
Clock Low to Output Valid
8
ns
Output Hold Time
0
ns
tHLCH
HOLD Setup Time (relative to C)
5
ns
tCHHH
HOLD Hold Time (relative to C)
5
ns
tHHCH
HOLD Setup Time (relative to C)
5
ns
tCHHL
HOLD Hold Time (relative to C)
5
ns
(2)
tLZ
HOLD to Output Low-Z
8
ns
tHLQZ (2)
tHZ
HOLD to Output High-Z
8
ns
tHHQX
tWHSL (4)
tSHWL
(4)
tVPPHSL(6)
tW
Write Protect Setup Time
100
ns
Enhanced Program Supply Voltage High to Chip Select Low
200
ns
Write Status Register Cycle Time
Page Program Cycle Time (n Bytes)
Page Program Cycle Time (VPP = VPPH) (256 Bytes)
tSE
tBE
ns
Write Protect Hold Time
Page Program Cycle Time (256 Bytes)
tPP (5)
20
Sector Erase Cycle Time
5
1.4
0.4+ n*1/256
15
ms
5
ms
0.35
1
ms
3
Sector Erase Cycle Time (VPP = VPPH)
0.5
s
Bulk Erase Cycle Time
68
160
s
Bulk Erase Cycle Time (VPP = VPPH)
35
160
s
1. tCH + tCL must be greater than or equal to 1/ fC(max)
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are obtained with one
sequence including all the Bytes versus several sequences of only a few Bytes. (1 ≤n ≤256).
6. VPPH should be kept at a valid level until the program or erase operation has completed and its result (success or failure) is
known.
42/50
s
M25P64
DC and AC parameters
Figure 21. Serial input timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
D
Q
MSB IN
tCLCH
LSB IN
High Impedance
AI01447C
Figure 22. Write Protect setup and hold timing during WRSR when SRWD = 1
W/VPP
tSHWL
tWHSL
S
C
D
High Impedance
Q
AI07439b
43/50
DC and AC parameters
M25P64
Figure 23. Hold timing
S
tHLCH
tCHHL
tHHCH
C
tCHHH
tHLQZ
tHHQX
Q
D
HOLD
AI02032
Figure 24. Output timing
S
tCH
C
tCLQV
tCLQX
tCLQV
tCL
tSHQZ
tCLQX
LSB OUT
Q
tQLQH
tQHQL
ADDR
LSB IN
D
AI01449e
Figure 25. VPPH timing
End of PP, SE or BE
(identified by WPI polling)
S
C
D
PP, SE, BE
VPPH
W/VPP
tVPPHSL
44/50
ai12092
M25P64
11
Package mechanical
Package mechanical
Figure 26. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm,
package outline
D
E
E2
e
b
D2
A
L
L1
K
ddd
A1
VDFPN-02
1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
Table 15.
VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm,
package mechanical data
millimeters
inches
Symbol
Typ
A
Min
0.85
A1
b
0.40
D
8.00
D2
5.16
Max
Typ
1.00
0.0335
0.00
0.05
0.35
0.48
0.0157
(1)
0.0000
0.0020
0.0138
0.0189
0.2031
0.0020
E
6.00
0.2362
E2
4.80
0.1890
e
1.27
–
–
0.0500
0.82
0.50
0.45
L1
N
0.0394
0.05
K
Max
0.3150
ddd
L
Min
–
0.0323
0.60
0.0197
0.0177
0.15
8
–
0.0236
0.0059
8
1. D2 Max must not exceed (D – K – 2 × L).
45/50
Package mechanical
M25P64
Figure 27. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width
D
16
h x 45˚
9
C
E
1
θ
8
A2
B
H
A1
A
L
ddd
e
SO-H
1. Drawing is not to scale.
Table 16.
SO16 wide – 16 lead Plastic Small Outline, 300 mils body width,
package mechanical data
millimeters
inches
Symbol
Typ
Min
Max
A
2.35
A1
Min
Max
2.65
0.093
0.104
0.10
0.30
0.004
0.012
B
0.33
0.51
0.013
0.020
C
0.23
0.32
0.009
0.013
D
10.10
10.50
0.398
0.413
E
7.40
7.60
0.291
0.299
–
–
–
–
H
10.00
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
L
0.40
1.27
0.016
0.050
θ
0°
8°
0°
8°
e
ddd
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1.27
0.10
Typ
0.050
0.004
M25P64
12
Part numbering
Part numbering
Table 17.
Ordering information scheme
Example:
M25P64
–
V MF 6
T P
Device Type
M25P = Serial Flash memory for Code Storage
Device Function
64 = 64 Mbit (8M x 8)
Operating Voltage
V = VCC = 2.7 V to 3.6 V
Package
MF = SO16 (300 mil width)
ME = VDFPN8 8 × 6 mm (MLP8)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
P or G = ECOPACK® (RoHS compliant)
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest Numonyx Sales Office.
The category of second-Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
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Revision history
13
Revision history
Table 18.
Document revision history
Date
Revision
28-Apr-2003
0.1
Target Specification Document written in brief form
15-May-2003
0.2
Target Specification Document written in full
20-Jun-2003
0.3
8x6 MLP8 and SO16(300 mil) packages added
18-Jul-2003
0.4
tPP, tSE and tBE revised
02-Sep-2003
0.5
Voltage supply range changed
19-Sep-2003
0.6
Table of contents, warning about exposed paddle on MLP8, and Pb-free
options added
17-Dec-2003
0.7
Value of tVSL(min) VWI, tPP(typ) and tBE(typ) changed. MLP8 package
removed.
15-Nov-2004
1.0
Document status promoted from Target Specification to Preliminary Data.
8x6 MLP8 package added. Minor wording changes.
2.0
Deep Power-Down mode removed from datasheet (Figure 18: Read
Electronic Signature (RES) instruction sequence and data-out sequence
modified and tRES1 and tRES2 removed from Table 14: AC
characteristics). SO16 Wide package specifications updated. End timing
line of tSHQZ modified in Figure 24: Output timing. Figures moved below
the corresponding instructions in the Instructions section.
23-Dec-2005
3.0
Updated Page Program (PP) instructions in Page Programming, Page
Program (PP) and Table 14: AC characteristics.
Fast Program/Erase mode added and Power-up specified for Fast
Program/Erase mode in Power-up and Power-down section. W pin
changed to W/VPP. (see Write Protect/Enhanced Program supply voltage
(W/VPP) description). Note 2 inserted below Figure 26 Blank option
removed under Plating Technology.
tVPPHSL added to Table 14: AC characteristics and Figure 25: VPPH timing
inserted.
All packages are ECOPACK® compliant.
Document status promoted from Preliminary Data to full Datasheet
status.
16-Feb-2006
4.0
VDFPN8 (MLP8) package specifications updated (see Section 11:
Package mechanical).
07-Sep-2006
5
24-Feb-2005
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M25P64
Changes
Figure 4: Bus master and memory devices on the SPI bus modified.
ICC1 maximum value updated in Table 13: DC characteristics.
M25P64
Revision history
Table 18.
Date
Document revision history
Revision
Changes
19-Jan-2007
6
Hardware Write Protection feature added to Features on page 1.
VCC supply voltage and VSS ground descriptions added.
Figure 4: Bus master and memory devices on the SPI bus updated and
explanatory paragraph added.
At Power-up The Write In Progress (WIP) bit is reset.
VIO max modified and TLEAD added in Table 9: Absolute maximum
ratings. Small text changes.
Note 1 added to Table 15: VDFPN8 (MLP8) 8-lead Very thin Dual Flat
Package No lead, 8 × 6 mm, package mechanical data.
10-Dec-2007
7
Applied Numonyx branding.
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M25P64
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