Holtek HT48R064G Enhanced i/o type mcu with opa Datasheet

Enhanced I/O Type MCU with OPA
HT48R064G/065G/066G/0662G
Revision: 1.00
Date: February 23, 2011
Contents
Table of Contents
Features ...............................................................................................6
CPU Features ........................................................................................................6
Peripheral Features ................................................................................................6
General Description ............................................................................7
Selection Table ....................................................................................7
Block Diagram .....................................................................................7
Pin Assignment ...................................................................................8
Pin Description ....................................................................................9
HT48R064G ...........................................................................................................9
HT48R065G .........................................................................................................10
HT48R066G .........................................................................................................11
HT48R0662G .......................................................................................................13
Absolute Maximum Ratings .............................................................16
D.C. Characteristics ..........................................................................16
A.C. Characteristics ..........................................................................18
Power-on Reset Characteristics ......................................................19
Comparator Amplifier Characteristics ............................................19
Operational Amplifier Characteristics.............................................20
System Architecture .........................................................................21
Clocking and Pipelining ........................................................................................21
Program Counter..................................................................................................22
Stack ....................................................................................................................23
Arithmetic and Logic Unit - ALU ...........................................................................23
Program Memory...............................................................................24
Structure...............................................................................................................24
Special Vectors.....................................................................................................24
Look-up Table.......................................................................................................25
Table Program Example .......................................................................................26
Data Memory......................................................................................27
Structure...............................................................................................................27
Special Purpose Data Memory.........................................................28
Special Function Registers ...................................................................................29
Wake-up Function Register - PAWK, PCWK........................................................35
Rev. 1.00
2
February 23, 2011
Contents
Pull-high Registers - PAPU, PBPU, PCPU, PDPU, PEPU, PFPU ........................35
Software COM Register - SCOMC.......................................................................35
Oscillator............................................................................................35
System Oscillator Overview..................................................................................35
System Clock Configurations................................................................................35
External Crystal/Resonator Oscillator - HXT ........................................................36
External RC Oscillator - ERC ...............................................................................36
Internal RC Oscillator - HIRC ...............................................................................37
External 32768Hz Crystal Oscillator - LXT ...........................................................37
LXT Oscillator Low Power Function ......................................................................38
Internal Low Speed Oscillator - LIRC ...................................................................38
Operating Modes ...............................................................................39
Mode Types and Selection ...................................................................................39
Mode Switching ....................................................................................................40
Standby Current Considerations...........................................................................41
Wake-up...............................................................................................................41
Watchdog Timer ................................................................................42
Watchdog Timer Operation...................................................................................42
Reset and Initialisation .....................................................................44
Reset Functions ...................................................................................................44
Reset Initial Conditions .........................................................................................46
Input/Output Ports.............................................................................49
Pull-high Resistors................................................................................................49
I/O Port Wake-up..................................................................................................49
I/O Port Control Registers.....................................................................................51
Pin-shared Functions............................................................................................52
Pin Remapping Configuration - HT48R0662G .....................................................52
I/O Pin Structures .................................................................................................53
Programming Considerations ...............................................................................53
Timer/Event Counters .......................................................................55
Configuring the Timer/Event Counter Input Clock Source .....................................55
Timer Registers - TMR0, TMR1 ...........................................................................55
Timer Control Registers - TMR0C, TMR1C..........................................................57
Timer Mode ..........................................................................................................58
Event Counter Mode.............................................................................................59
Pulse Width Capture Mode...................................................................................59
Prescaler ..............................................................................................................60
PFD Function .......................................................................................................60
I/O Interfacing.......................................................................................................61
Timer Program Example.......................................................................................62
Time Base ..........................................................................................62
Rev. 1.00
3
February 23, 2011
Contents
Pulse Width Modulator .....................................................................63
PWM Operation....................................................................................................63
6+2 PWM Mode ...................................................................................................64
7+1 PWM Mode ...................................................................................................65
PWM Output Control ............................................................................................66
PWM Programming Example ...............................................................................66
Operational Amplifiers......................................................................67
Comparator & Operational Amplifier Registers .....................................................67
Operational Amplifier Operation............................................................................67
Operational Amplifier Application Example ...........................................................71
Operational Amplifier Offset Cancellation Function ...............................................78
Comparator ........................................................................................79
Comparator Functions ..........................................................................................79
Interrupts............................................................................................81
Interrupt Register..................................................................................................81
Interrupt Operation ...............................................................................................85
Interrupt Priority.....................................................................................................85
External Interrupt ..................................................................................................86
Timer/Event Counter Interrupt ..............................................................................86
Time Base Interrupt ..............................................................................................86
Multi-function Interrupt ..........................................................................................87
Programming Considerations ...............................................................................87
SCOM Function for LCD ...................................................................87
LCD Operation .....................................................................................................87
LCD Bias Control..................................................................................................88
Configuration Options ......................................................................89
Application Circuits ..........................................................................89
Instruction Set ...................................................................................90
Introduction ..........................................................................................................90
Instruction Timing .................................................................................................90
Moving and Transferring Data ..............................................................................90
Arithmetic Operations ...........................................................................................90
Logical and Rotate Operations .............................................................................90
Branches and Control Transfer.............................................................................91
Bit Operations.......................................................................................................91
Table Read Operations.........................................................................................91
Other Operations..................................................................................................91
Instruction Set Summary ......................................................................................92
Instruction Definition ........................................................................94
Rev. 1.00
4
February 23, 2011
Contents
Package Information .......................................................................104
16-pin DIP (300mil) Outline Dimensions .............................................................104
16-pin NSOP (150mil) Outline Dimensions .........................................................107
20-pin DIP (300mil) Outline Dimensions .............................................................108
20-pin SOP (300mil) Outline Dimensions............................................................110
20-pin SSOP (150mil) Outline Dimensions..........................................................111
24-pin SKDIP (300mil) Outline Dimensions.........................................................112
24-pin SOP (300mil) Outline Dimensions............................................................115
24-pin SSOP (150mil) Outline Dimensions .........................................................116
28-pin SKDIP (300mil) Outline Dimensions.........................................................117
28-pin SOP (300mil) Outline Dimensions............................................................118
28-pin SSOP (150mil) Outline Dimensions .........................................................119
44-pin QFP (10mm´10mm) Outline Dimensions ................................................120
Reel Dimensions ................................................................................................121
Carrier Tape Dimensions ....................................................................................122
Rev. 1.00
5
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Features
CPU Features
·
Operating voltage:
fSYS= 4MHz: 2.2V~5.5V
fSYS= 8MHz: 3.3V~5.5V
fSYS= 12MHz: 4.5V~5.5V
·
Up to 0.33ms instruction cycle with 12MHz system clock at VDD= 5V
·
Oscillator types:
External high freuency Crystal -- HXT
External RC -- ERC
Internal RC -- HIRC
External low frequency crystal -- LXT
·
Four operational modes: Normal, Slow, Idle, Sleep
·
Fully integrated internal 4MHz, 8MHz and 12MHz oscillator requires no external components
·
Watchdog Timer function
·
LIRC oscillator function for watchdog timer
·
All instructions executed in one or two instruction cycles
·
Table read instructions
·
63 powerful instructions
·
Up to 6-level subroutine nesting
·
Bit manipulation instruction
·
Low voltage reset function
·
Wide range of available package types
Peripheral Features
Rev. 1.00
·
Program Memory: 1K x 14 ~ 4K x 15
·
Data Memory: 64 x 8 ~ 224 x 8
·
Up to 42 bidirectional I/O lines
·
Up to 2 channel 8-bit PWM
·
Software controlled 4-SCOM lines LCD driver with 1/2 bias
·
External interrupt input shared with an I/O line
·
Up to two 8-bit programmable Timer/Event Counter with overflow interrupt and prescaler
·
Time-Base function
·
Programmable Frequency Divider - PFD
·
Two integrated operational amplifiers with interrupt function - one with programmable gain
control
·
Single comparator with interrupt and low power consumption
6
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
General Description
The Enhanced I/O MCU devices are a series of 8-bit high performance, RISC architecture
microcontroller specifically designed for a wide range of applications. The usual Holtek
microcontroller features of low power consumption, I/O flexibility, timer functions, oscillator options,
power down and wake-up functions, watchdog timer and low voltage reset, combine to provide
devices with a huge range of functional options while still maintaining a high level of cost
effectiveness. The fully integrated system oscillator HIRC, which requires no external components
and which has three frequency selections, opens up a huge range of new application possibilities for
the device, some of which may include industrial control, consumer products, household appliances
subsystem controllers, etc.
Selection Table
Program
Memory
Data
Memory
I/O
8-bit
Timer
HIRC
(MHz)
RTC
(LXT)
LCD
SCOM
PWM
HT48R064G
1K´14
64´8
18
1
4/8/12
Ö
¾
¾
2
1
HT48R065G
2K´15
96´8
22
1
4/8/12
Ö
4
¾
2
HT48R066G
4K´15
128´8
26
2
4/8/12
Ö
4
8-bit´1
HT48R0662G
4K´15
224´8
42
2
4/8/12
Ö(*)
4
8-bit´2
Part No.
Note:
OPA Comp. PFD
Stack
Package
Ö
4
16DIP/NSOP
20DIP/SOP/SSOP
1
Ö
4
16DIP/NSOP
20DIP/SOP/SSOP
24SKDIP/SOP/SSOP
2
1
Ö
4
20DIP/SOP/SSOP
24/28SKDIP/SOP/SSOP
2
1
Ö
6
24/28SKDIP/SOP/SSOP
44QFP
²*² the oscillator is connected to the OSC3/OSC4 pins with TinyPower
TM
design.
Block Diagram
The following block diagram illustrates the main functional blocks.
L o w
V o lta g e
R e s e t
W a tc h d o g
T im e r
R e s e t
C ir c u it
P W M
D r iv e r
O T P
P ro g ra m
M e m o ry
R A M
D a ta
M e m o ry
P F D
D r iv e r
I/O
P o rts
8 - b it
R IS C
M C U
C o re
In te rru p t
C o n tr o lle r
E x te rn a l
C ry s ta l
O s c illa to r s
In te rn a l
O s c illa to r s
O p e r a tio n a l
A m p lifie r s
L C D
S C O M
8 - b it
T im e r s
T im e
B a s e
C o m p a ra to r
Rev. 1.00
7
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Pin Assignment
P A 4 /A 0 P
1
2 0
V S S
P A 3 /IN T /A 0 N
2
1 9
V D D
P A 3 /IN T /A 0 N
1
1 6
P A 4 /A 0 P
P A 2 /T C 0 /A 0 X
3
1 8
P A 5 /O S C 2
P A 3 /IN T /A 0 N
1
1 6
P A 4 /T C 1 P /A 0 P
P A 2 /T C 0 /A 0 X
2
1 5
V S S
P A 1 /P F D /A 1 X
4
1 7
P A 6 /O S C 1
P A 2 /T C 0 /A 0 X
2
1 5
V S S
P A 1 /P F D /A 1 X
3
1 4
V D D
P A 0 /A 1 N
5
1 6
P A 7 /R E S
P A 1 /P F D /A 1 X
3
1 4
V D D
P A 0 /A 1 N
4
1 3
P A 5 /O S C 2
P C 6 /A 1 P
6
1 5
P C 5
P A 0 /A 1 N
4
1 3
P A 5 /O S C 2
P C 6 /A 1 P
5
1 2
P A 6 /O S C 1
P C 7 /C P
7
1 4
P C 4
P C 6 /A 1 P
5
1 2
P A 6 /O S C 1
P C 7 /C P
6
1 1
P A 7 /R E S
P C 0 /C N
8
1 3
P B 3
P C 7 /C P
6
1 1
P A 7 /R E S
P C 0 /C N
7
1 0
P C 5
P C 1 /C X
9
1 2
P B 2
P C 0 /C N
7
1 0
P C 5
P C 1 /C X
8
9
P C 4
P B 0
1 0
1 1
P B 1
P C 1 /C X
8
9
P C 4
H T 4 8 R 0 6 4 G
1 6 D IP -A /N S O P -A
H T 4 8 R 0 6 4 G
2 0 D IP -A /S O P -A /S S O P -A
H T 4 8 R 0 6 5 G
1 6 D IP -A /N S O P -A
P A 4 /T C 1 /A 0 P
1
2 4
V S S
P A 3 /IN T /A 0 N
2
2 3
V D D
P A 4 /T C 1 /A 0 P
1
2 0
V S S
P A 2 /T C 0 /A 0 X
3
2 2
P A 5 /O S C 2
P A 3 /IN T /A 0 N
2
1 9
V D D
P A 1 /P F D /A 1 X
4
2 1
P A 6 /O S C 1
P A 2 /T C 0 /A 0 X
3
1 8
P A 5 /O S C 2
P A 0 /A 1 N
5
2 0
P A 7 /R E S
P A 1 /P F D /A 1 X
4
1 7
P A 6 /O S C 1
P C 6 /A 1 P
6
1 9
P C 5
P A 0 /A 1 N
5
1 6
P A 7 /R E S
P C 7 /C P
7
1 8
P C 4
P C 6 /A 1 P
6
1 5
P C 5
P C 0 /C N
8
1 7
P C 3
P C 7 /C P
7
1 4
P C 4
P C 1 /C X
9
1 6
P C 2
8
1 3
P B 3 /S C O M 3
P B 0 /S C O M 0
1 0
1 5
P B 5
9
1 2
P B 2 /S C O M 2
P B 1 /S C O M 1
1 1
1 4
P B 4
1 0
1 1
P B 1 /S C O M 1
P B 2 /S C O M 2
1 2
1 3
P B 3 /S C O M 3
P C 0 /C N
P C 1 /C X
P B 0 /S C O M 0
H T 4 6 R 0 6 5 G
2 0 D IP -A /S O P -A /S S O P -A
P A 4 /T C 1 /A 0 P
1
2 0
V S S
P A 3 /IN T /A 0 N
2
1 9
V D D
P A 2 /T C 0 /A 0 X
3
1 8
P A 5 /O S C 2
P A 1 /P F D /A 1 X
4
1 7
P A 6 /O S C 1
P A 0 /A 1 N
5
1 6
P A 7 /R E S
P C 6 /A 1 P
6
1 5
P C 5
P C 7 /C P
7
1 4
P C 4
P C 0 /C N
8
1 3
P B 3 /S C O M 3
P C 1 /C X
9
1 2
P B 2 /S C O M 2
1 0
1 1
P B 1 /S C O M 1
P B 0 /S C O M 0
H T 4 8 R 0 6 6 G
2 0 D IP -A /S O P -A /S S O P -A
H T 4 6 R 0 6 5 G
2 4 S K D IP -A /S O P -A /S S O P -A
P A 4 /T C 1 /A 0 P
1
2 8
V S S
P A 3 /IN T /A 0 N
2
2 7
V D D
P A 4 /T C 1 /A 0 P
1
2 4
V S S
P A 2 /T C 0 /A 0 X
3
P A 5 /O S C 2
P A 4 /T C 1 /A 0 P
1
2 4
V S S
P A 3 /IN T /A 0 N
2
2 6
2 3
V D D
P A 1 /P F D /A 1 X
4
P A 6 /O S C 1
P A 3 /IN T /A 0 N
2
2 3
V D D
P A 2 /T C 0 /A 0 X
3
2 5
2 2
P A 5 /O S C 2
P A 0 /A 1 N
5
P A 7 /R E S
P A 2 /T C 0 /A 0 X
3
2 2
P A 5 /O S C 2
P A 1 /P F D /A 1 X
4
2 4
2 1
P A 6 /O S C 1
P C 6 /A 1 P
6
P C 5
P A 1 /P F D /A 1 X
4
2 1
P A 6 /O S C 1
P A 0 /A 1 N
5
2 3
2 0
P A 7 /R E S
7
2 2
P C 4
P A 0 /A 1 N
5
2 0
P A 7 /R E S
P C 6 /A 1 P
6
P C 7 /C P
1 9
P C 5
8
2 1
P C 3
P C 6 /A 1 P
6
1 9
P C 5 /[P F D ]
P C 7 /C P
7
P C 0 /C N
1 8
P C 4
P C 1 /C X
9
2 0
P C 2
P C 7 /C P
7
1 8
P C 4 /[T C 0 ]
P C 0 /C N
8
1 7
P C 3
P D 0
1 0
1 9
P D 3
P C 0 /C N
8
1 7
P C 3 /[IN T ]
P C 1 /C X
9
1 6
P C 2
P D 1
1 1
1 8
P D 2
P C 1 /C X
9
1 6
P F 1 /O S C 3
P B 0 /S C O M 0
1 0
1 5
P B 5
1 2
1 7
P B 5
P D 0 /P W M 0
1 0
1 5
P F 0 /O S C 4
P B 1 /S C O M 1
1 1
P B 0 /S C O M 0
1 4
P B 4
1 3
1 6
P B 4
P B 0 /[P F D ]/S C O M 0
1 1
1 4
P B 3 /[T C 1 ]/S C O M 3
P B 2 /S C O M 2
1 2
P B 1 /S C O M 1
1 3
P B 3 /S C O M 3
P B 2 /S C O M 2
1 4
1 5
P B 3 /S C O M 3
P B 1 /[T C 0 ]/S C O M 1
1 2
1 3
P B 2 /[IN T ]/S C O M 2
H T 4 8 R 0 6 6 G
2 4 S K D IP -A /S O P -A /S S O P -A
H T 4 8 R 0 6 6 G
2 8 S K D IP -A /S O P -A /S S O P -A
H T 4 6 R 0 6 6 2 G
2 4 S K D IP -A /S O P -A /S S O P -A
P A
P A
P A
P A
V S S
2 7
V D D
P A 2 /T C 0 /A 0 X
3
2 6
P A 5 /O S C 2
P A 1 /P F D /A 1 X
4
2 5
P A 6 /O S C 1
P A 0 /A 1 N
5
2 4
P A 7 /R E S
P C 6 /A 1 P
6
2 3
P C 5 /[P F D ]
P C 7 /C P
7
2 2
P C 4 /[T C 0 ]
P C 0 /C N
8
2 1
P C 3 /[IN T ]
P C 1 /C X
9
2 0
P C 2 /[T C 1 ]
P D 0 /P W M 0
1 0
1 9
P D 7
P D 1 /P W M 1
1 1
1 8
P D 6
P B 0 /[P F D ]/S C O M 0
1 2
1 7
P F 1 /O S C 3
P B 1 /[T C 0 ]/S C O M 1
1 3
1 6
P F 0 /O S C 4
P B 2 /[IN T ]/S C O M 2
1 4
1 5
P B 3 /[T C 1 ]/S C O M 3
4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4
1
3 3
2
3 2
3
3 1
4
3 0
5
2 9
H T 4 6 R 0 6 6 2 G
4 4 Q F P -A
6
7
2 8
2 7
8
2 6
9
2 5
1 0
1 1
2 4
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
2 3
P C 5
P C 4
P C 3
P C 2
P D 7
P D 6
P D 5
P D 4
P D 3
P D 2
P F 1
/[P
/[T
/[IN
/[T
F D ]
C 0 ]
T ]
C 1 ]
/O S C 3
1 ]/S C
T ]/S C
0 ]/S C
D ]/S C
M 1
M 0
/O S C 4
/[T C
/[IN
/[T C
/[P F
/P W
/P W
H T 4 6 R 0 6 6 2 G
2 8 S K D IP -A /S O P -A /S S O P -A
P C 7 /C P
P C 0 /C N
P C 1 /A X
P E 0 /[P F D ]
P E 1 /[T C 0 ]
P E 2 /[IN T ]
P E 3 /[T C 1 ]
P E 4
P E 5
P E 6
P E 7
P F 0
P B 7
P B 6
P B 5
P B 4
P B 3
P B 2
P B 1
P B 0
P D 1
P D 0
2 8
2
E S
C 1
C 2
D D
S S
0 P
0 N
0 X
1 X
1 N
1 P
1
P A 3 /IN T /A 0 N
P A 7 /R
P A 6 /O S
P A 5 /O S
V
V
1 /A
T /A
0 /A
D /A
0 /A
6 /A
4 /T C
3 /IN
2 /T C
1 /P F
P A
P C
P A 4 /T C 1 /A 0 P
O M
O M
O M
O M
2
3
1
0
Note: Bracketed pin names indicate non-default pinout remapping locations.
Rev. 1.00
8
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Pin Description
The function of each pin is listed in the following tables, however the details behind how each pin is
configured is contained in the other individual peripheral function sections.
HT48R064G
Pin Name
Function
OPT
I/T
PA0
PAPU
PAWK
ST
A1N
COPA3C
OPAI
PA1
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PFD
CTRL0
¾
CMOS PFD output
A1X
COPA3C
¾
OPAO
PA2
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
TC0
TMR0C
ST
¾
A0X
COPA3C
¾
OPAO
PA3
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
INT
INTC0
CTRL1
ST
¾
External interrupt input
A0X
COPA3C
OPAI
¾
OPA0 inverting input pin
PA4
PAPU
PAWK
ST
A0P
COPA3C
OPAI
PA5
PAPU
PAWK
ST
OSC2
CO
¾
PA6
PAPU
PAWK
ST
OSC1
CO
OSC
PA7
PAWK
ST
RES
CO
ST
PBn
PBPU
ST
CMOS General purpose I/O. Register enabled pull-up.
PC0
PCPU
ST
CMOS General purpose I/O. Register enabled pull-up.
PA0/A1N
PA1/PFD/A1X
PA2/TC0/A0X
PA3/INT/A0N
PA4/A0P
PA5/OSC2
PA6/OSC1
PA7/RES
PB0~PB3
PC0/CN
CN
COPA3C CMPI
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
OPA1 inverting input pin
OPA1 output pin
External Timer 0 clock input
OPA0 output pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
OPA0 non-inverting input pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
OSC
Oscillator pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
Oscillator pin
NMOS General purpose I/O. Register enabled wake-up.
¾
¾
Reset input
Comparator inverting input pin
PCPU
ST
CMOS General purpose I/O. Register enabled pull-up.
CX
COPA2C
¾
CMPO Comparator output pin
PCn
PCPU
ST
CMOS General purpose I/O. Register enabled pull-up.
PC6
PCPU
ST
CMOS General purpose I/O. Register enabled pull-up.
A1P
COPA3C
OPAI
PC6/A1P
Rev. 1.00
Description
PC1
PC1/CX
PC4, PC5
O/T
¾
OPA1 non-inverting input pin
9
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Pin Name
Function
OPT
I/T
PC7
PCPU
ST
PC7/CP
CP
COPA3C CMPI
O/T
Description
CMOS General purpose I/O. Register enabled pull-up.
¾
Comparator non-inverting input pin
VDD
VDD
¾
PWR
¾
Power supply
VSS
VSS
¾
PWR
¾
Ground
Note:
OPT: Optional by configuration option (CO) or register option
I/T: Input type
O/T: Output type
PWR: Power
CO: Configuration option
ST: Schmitt Trigger input
CMOS: CMOS output
NMOS: NMOS output
OSC: Oscillator pin
OPAI: Operational Amplifier input
OPAO: Operational Amplifier output
CMPI: Comparator input
CMPO: Comparator output
HT48R065G
Pin Name
Function
OPT
I/T
PA0
PAPU
PAWK
ST
A1N
COPA3C
OPAI
PA1
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PFD
CTRL0
¾
CMOS PFD output
A1X
COPA3C
¾
OPAO
PA2
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
TC0
TMR0C
ST
¾
A0X
COPA3C
¾
OPAO
PA3
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
INT
INTC0
CTRL1
ST
¾
External interrupt input
A0X
COPA3C
OPAI
¾
OPA0 inverting input pin
PA4
PAPU
PAWK
ST
TC1
TMR1C
ST
¾
External Timer 1 clock input
A0P
COPA3C
OPAI
¾
OPA0 non-inverting input pin
PA5
PAPU
PAWK
ST
OSC2
CO
¾
PA0/A1N
PA1/PFD/A1X
PA2/TC0/A0X
PA3/INT/A0N
PA4/TC1/A0P
PA5/OSC2
Rev. 1.00
O/T
Description
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
OPA1 inverting input pin
OPA1 output pin
External Timer 0 clock input
OPA0 output pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CMOS General purpose I/O. Register enabled pull-up and wake-up.
OSC
Oscillator pin
10
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Pin Name
Function
OPT
I/T
PA6
PAPU
PAWK
ST
OSC1
CO
OSC
PA7
PAWK
ST
RES
CO
ST
PBn
PBPU
ST
CMOS General purpose I/O. Register enabled pull-up.
SCOMn
SCOMC
¾
SCOM Software controlled 1/2 bias LCD COM
PBn
PBPU
ST
CMOS General purpose I/O. Register enabled pull-up.
PCPU
ST
CMOS General purpose I/O. Register enabled pull-up.
PA6/OSC1
PA7/RES
PB0/SCOM0~
PB3/SCOM3
PB4~PB5
PC0
PC0/CN
CN
COPA3C CMPI
Description
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
Oscillator pin
NMOS General purpose I/O. Register enabled wake-up.
¾
¾
Reset input
Comparator inverting input pin
PC1
PCPU
ST
CMOS General purpose I/O. Register enabled pull-up.
CX
COPA2C
¾
CMPO Comparator output pin
PCn
PCPU
ST
CMOS General purpose I/O. Register enabled pull-up.
PC6
PCPU
ST
CMOS General purpose I/O. Register enabled pull-up.
A1P
COPA3C
OPAI
PC7
PCPU
ST
PC1/CX
PC2~PC5
O/T
PC6/A1P
PC7/CP
CP
COPA3C CMPI
¾
OPA1 non-inverting input pin
CMOS General purpose I/O. Register enabled pull-up.
¾
Comparator non-inverting input pin
VDD
VDD
¾
PWR
¾
Power supply
VSS
VSS
¾
PWR
¾
Ground
Note:
OPT: Optional by configuration option (CO) or register option
I/T: Input type; O/T: Output type; PWR: Power; CO: Configuration option
ST: Schmitt Trigger input; AN: analog input
CMOS: CMOS output; NMOS: NMOS output
OSC: Oscillator pin; SCOM: Software controlled LCD COM
CMPI: Comparator input; CMPO: Comparator output
OPAI: Operational Amplifier input; OPAO: Operational Amplifier output
HT48R066G
Pin Name
Function
OPT
I/T
PA0
PAPU
PAWK
ST
PA0/A1N
A1N
PA1/PFD/A1X
PA2/TC0/A0X
Rev. 1.00
COPA3C OPAI
O/T
Description
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
OPA1 inverting input pin
PA1
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PFD
CTRL0
¾
CMOS PFD output
A1X
COPA3C
¾
OPAO OPA1 output pin
PA2
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
TC0
TMR0C
ST
A0X
COPA3C
¾
¾
External Timer 0 clock input
OPAO OPA0 output pin
11
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Pin Name
PA3/INT/A0N
Function
OPT
I/T
PA3
PAPU
PAWK
ST
INT
INTC0
CTRL1
ST
A0X
PA4/TC1/A0P
COPA3C OPAI
PA4
PAPU
PAWK
ST
TC1
TMR1C
ST
A0P
COPA3C OPAI
PB3/[TC1]/SCOM3
PB4~PB5
¾
OPA0 inverting input pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
External Timer 1 clock input
¾
OPA0 non-inverting input pin
CO
¾
PA6
PAPU
PAWK
ST
OSC1
CO
OSC
PA7
PAWK
ST
RES
CO
ST
PB0
PBPU
ST
CMOS General purpose I/O. Register enabled pull-up.
PFD
CTRL0
¾
CMOS PFD output
SCOM0
SCOMC
¾
SCOM Software controlled 1/2 bias LCD COM
PB1
PBPU
ST
CMOS General purpose I/O. Register enabled pull-up.
TC0
TMR0C
ST
SCOM1
SCOMC
¾
SCOM Software controlled 1/2 bias LCD COM
PB2
PBPU
ST
CMOS General purpose I/O. Register enabled pull-up.
INT
INTC0
CTRL1
ST
SCOM2
SCOMC
¾
SCOM Software controlled 1/2 bias LCD COM
PB3
PBPU
ST
CMOS General purpose I/O. Register enabled pull-up.
TC1
TMR1C
ST
SCOM3
SCOMC
¾
SCOM Software controlled 1/2 bias LCD COM
PBn
PBPU
ST
CMOS General purpose I/O. Register enabled pull-up.
PC0
PCPU
PCWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CN
COPA3C CMPI
CMOS General purpose I/O. Register enabled pull-up and wake-up.
OSC
Oscillator pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
Oscillator pin
NMOS General purpose I/O. Register enabled wake-up.
¾
¾
¾
¾
¾
Reset input
External Timer 0 clock input
External interrupt input
External Timer 1 clock input
Comparator inverting input pin
PC1
PCPU
PCWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CX
COPA2C
¾
CMPO Comparator output pin
PCn
PCPU
PCWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PC6
PCPU
PCWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PC1/CX
PC6/A1P
A1P
Rev. 1.00
External interrupt input
OSC2
PC0/CN
PC2~PC5
¾
ST
PA7/RES
PB2/[INT]/SCOM2
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PAPU
PAWK
PA6/OSC1
PB1/[TC0]/SCOM1
Description
PA5
PA5/OSC2
PB0/[PFD]/SCOM0
O/T
COPA3C OPAI
¾
OPA1 non-inverting input pin
12
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Pin Name
Function
OPT
I/T
PC7
PCPU
PCWK
ST
PC7/CP
CP
COPA3C CMPI
O/T
Description
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
Comparator non-inverting input pin
PD0~PD3
PDn
PDPU
ST
VDD
VDD
¾
PWR
¾
Power supply
VSS
VSS
¾
PWR
¾
Ground
Note:
CMOS General purpose I/O. Register enabled pull-up.
OPT: Optional by configuration option (CO) or register option
I/T: Input type
O/T: Output type
PWR: Power
CO: Configuration option
ST: Schmitt Trigger input
CMOS: CMOS output
NMOS: NMOS output
HXT: High frequency crystal oscillator pin
LXT: Low frequency crystal oscillator pin
SCOM: Software controlled LCD COM
CMPI: Comparator input
CMPO: Comparator output
OPAI: Operational Amplifier input
OPAO: Operational Amplifier output
HT48R0662G
Pin Name
Function
OPT
I/T
PA0
PAPU
PAWK
ST
PA0/A1N
A1N
PA1/PFD/A1X
PA2/TC0/A0X
PA3/INT/A0N
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
OPA1 inverting input pin
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PFD
CTRL0
¾
CMOS PFD output
A1X
COPA3C
¾
OPAO OPA1 output pin
PA2
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
TC0
TMR0C
ST
A0X
COPA3C
¾
OPAO OPA0 output pin
PA3
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
INT
INTC0
CTRL1
ST
COPA3C OPAI
PA4
PAPU
PAWK
ST
TC1
TMR1C
ST
A0P
Rev. 1.00
Description
PA1
A0X
PA4/TC1/A0P
COPA3C OPAI
O/T
COPA3C OPAI
¾
External Timer 0 clock input
¾
External interrupt input
¾
OPA0 inverting input pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
External Timer 1 clock input
¾
OPA0 non-inverting input pin
13
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Pin Name
Function
OPT
I/T
PA5
PAPU
PAWK
ST
OSC2
CO
¾
PA6
PAPU
PAWK
ST
OSC1
CO
OSC
PA7
PAWK
ST
RES
CO
ST
PB0
PBPU
ST
CMOS General purpose I/O. Register enabled pull-up.
PFD
CTRL0
¾
CMOS PFD output
SCOM0
SCOMC
¾
SCOM Software controlled 1/2 bias LCD COM
PB1
PBPU
ST
CMOS General purpose I/O. Register enabled pull-up.
TC0
TMR0C
ST
SCOM1
SCOMC
¾
SCOM Software controlled 1/2 bias LCD COM
PB2
PBPU
ST
CMOS General purpose I/O. Register enabled pull-up.
INT
INTC0
CTRL1
ST
SCOM2
SCOMC
¾
SCOM Software controlled 1/2 bias LCD COM
PB3
PBPU
ST
CMOS General purpose I/O. Register enabled pull-up.
TC1
TMR1C
ST
SCOM3
SCOMC
¾
SCOM Software controlled 1/2 bias LCD COM
PBn
PBPU
ST
CMOS General purpose I/O. Register enabled pull-up.
PC0
PCPU
PCWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PA5/OSC2
PA6/OSC1
PA7/RES
PB0/[PFD]/SCOM0
PB1/[TC0]/SCOM1
PB2/[INT]/SCOM2
PB3/[TC1]/SCOM3
PB4~PB7
PC0/CN
CN
COPA3C CMPI
O/T
Description
CMOS General purpose I/O. Register enabled pull-up and wake-up.
OSC
Oscillator pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
Oscillator pin
NMOS General purpose I/O. Register enabled wake-up.
¾
¾
¾
¾
¾
Reset input
External Timer 0 clock input
External interrupt input
External Timer 1 clock input
Comparator inverting input pin
PC1
PCPU
PCWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CX
COPA2C
¾
CMPO Comparator output pin
PC2
PCPU
PCWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
TC1
TMR1C
ST
PC3
PCPU
PCWK
ST
INT
INTC0
CTRL1
ST
PC4
PCPU
PCWK
ST
TC0
TMR0C
ST
PC5
PCPU
PCWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PFD
CTRL0
¾
CMOS PFD output
PC1/CX
PC2/[TC1]
¾
External Timer 1 clock input
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PC3/[INT]
PC4/[TC0]
PC5/[PFD]
Rev. 1.00
¾
External interrupt input
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
External Timer 0 clock input
14
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Pin Name
Function
OPT
I/T
PC6
PCPU
PCWK
ST
PC6/A1P
A1P
PC7
PC7/CP
CP
COPA3C OPAI
PCPU
PCWK
COPA3C CMPI
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
OPA1 non-inverting input pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
Comparator non-inverting input pin
PDPU
ST
CMOS General purpose I/O. Register enabled pull-up.
PWM0
CTRL0
¾
CMOS PWM 0 output
PD1
PDPU
ST
CMOS General purpose I/O. Register enabled pull-up.
PWM1
CTRL0
¾
CMOS PWM 1 output
PDn
PDPU
ST
CMOS General purpose I/O. Register enabled pull-up.
PE0
PEPU
ST
CMOS General purpose I/O. Register enabled pull-up.
PFD
CTRL0
¾
CMOS PFD output
PE1
PEPU
ST
CMOS General purpose I/O. Register enabled pull-up.
TC0
TMR0C
¾
CMOS External Timer 0 clock input
PE2
PEPU
ST
CMOS General purpose I/O. Register enabled pull-up.
INT
INTC0
CTRL1
¾
CMOS External interrupt input
PE3
PEPU
ST
CMOS General purpose I/O. Register enabled pull-up.
TC1
TMR1C
¾
CMOS External Timer 1 clock input
PEn
PEPU
ST
CMOS General purpose I/O. Register enabled pull-up.
CMOS General purpose I/O. Register enabled pull-up.
PD1/PWM1
PE0/[PFD]
PE1/[TC0]
PE2/[INT]
PE3/[TC1]
PE4~PE7
Description
PD0
PD0/PWM0
PD2~PD7
ST
O/T
PF0
PFPU
ST
OSC4
CO
¾
PF1
PFPU
ST
OSC3
CO
LXT
¾
LXT Oscillator pin
VDD
VDD
¾
PWR
¾
Power supply
VSS
VSS
¾
PWR
¾
Ground
PF0/OSC4
PF1/OSC3
Note:
OSC
LXT Oscillator pin
CMOS General purpose I/O. Register enabled pull-up.
OPT: Optional by configuration option (CO) or register option
I/T: Input type
O/T: Output type
PWR: Power
CO: Configuration option
ST: Schmitt Trigger input
CMOS: CMOS output
NMOS: NMOS output
HXT: High frequency crystal oscillator pin
LXT: Low frequency crystal oscillator pin
SCOM: Software controlled LCD COM
CMPI: Comparator input
CMPO: Comparator output
OPAI: Operational Amplifier input
OPAO: Operational Amplifier output
Rev. 1.00
15
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Absolute Maximum Ratings
Supply Voltage ...............................................................................................VSS-0.3V to VSS+6.0V
Input Voltage .................................................................................................VSS-0.3V to VDD+0.3V
Storage Temperature .................................................................................................-50°C to 125°C
Operating Temperature................................................................................................-40°C to 85°C
IOL Total...................................................................................................................................100mA
IOH Total ................................................................................................................................-100mA
Total Power Dissipation .........................................................................................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme
conditions may affect device reliability.
D.C. Characteristics
Symbol
VDD
IDD1
IDD2
IDD3
IDD4
Parameter
Ta=25°C
Test Conditions
Operating Voltage
¾
Operating Current
(HXT, HIRC, ERC)
3V
Operating Current
(HXT, HIRC, ERC)
3V
Operating Current
(HXT, HIRC, ERC)
Operating Current
(HIRC + LXT, Slow Mode)
ISTB2
Standby Current
(LIRC On, LXT Off)
Standby Current
(LIRC Off, LXT Off)
Standby Current
(LIRC Off, LXT On, LXTLP=1)
Max.
Unit
fSYS=4MHz
2.2
¾
5.5
V
fSYS=8MHz
3.3
¾
5.5
V
fSYS=12MHz
4.5
¾
5.5
V
¾
0.8
1.2
mA
¾
1.5
2.25
mA
¾
1.4
2.1
mA
¾
2.8
4.2
mA
No load, fSYS=4MHz
No load, fSYS=8MHz
5V
5V
No load, fSYS=12MHz
¾
4
6
mA
3V
No load, fSYS=32768Hz
(LXT on OSC1/OSC2,
LVR disabled, LXTLP=1)
¾
5
10
mA
¾
12
24
mA
No load, fSYS=32768Hz
(LXT on XT1/XT2,
LVR disabled, LXTLP=1)
¾
5
10
mA
¾
10
20
mA
¾
¾
5
mA
¾
¾
10
mA
¾
¾
1
mA
¾
¾
2
mA
¾
¾
5
mA
¾
¾
10
mA
¾
¾
3
mA
¾
¾
5
mA
5V
3V
3V
No load, system HALT
5V
3V
No load, system HALT
5V
3V
ISTB3
Typ.
Conditions
5V
5V
ISTB1
Min.
VDD
5V
3V
5V
No load, system HALT
(LXT on OSC1/OSC2)
No load, system HALT
(LXT on XT1/XT2)
VIL1
Input Low Voltage for I/O,
TCn and INT
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O,
TCn and INT
¾
¾
0.7VDD
¾
VDD
V
Rev. 1.00
16
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Ta=25°C
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR1
Low Voltage Reset 1
¾
VLVR = 4.2V
3.98
4.2
4.42
V
VLVR2
Low Voltage Reset 2
¾
VLVR = 3.15V
2.98
3.15
3.32
V
VLVR3
Low Voltage Reset 3
¾
VLVR = 2.1V
1.98
2.1
2.22
V
IOL1
I/O Port Sink Current
(PA, PB, PC)
3V
4
8
¾
mA
5V
10
20
¾
mA
3V
-2
-4
¾
mA
-5
-10
¾
mA
2
3
¾
mA
IOH
I/O Port Source Current
VOL=0.1VDD
VOH=0.9VDD
5V
IOL2
PA7 Sink Current
RPH
Pull-high Resistance
ISCOM
SCOM Operating Current
5V
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
SCOMC, ISEL[1:0]=00
17.5
25.0
32.5
mA
SCOMC, ISEL[1:0]=01
35
50
65
mA
SCOMC, ISEL[1:0]=10
70
100
130
mA
SCOMC, ISEL[1:0]=11
140
200
260
mA
5V
VSCOM
VDD/2 Voltage for LCD COM
VOPBIAS
OPA/Comparator bias voltage
Deviation (Bias=0.7/0.5/0.1VDD
Selected by A1PS[2:0],
A0PS[2:0], CPS[2:0] Bits)
3V
OPA1 Gain Deviation (Software
Gain Controlled by A1G[2:0]
3V
GOP
VOL=0.1VDD
5V
No load
No load
No load
0.475
0.500
0.525
VDD
0.665
0.700
0.735
VDD
0.475
0.500
0.525
VDD
0.995
0.100
0.105
VDD
-5
¾
+5
%
Note: The standby current (ISTB1~ISTB3) and IDD4 are measured with all I/O pins in input mode and tied to VDD.
Rev. 1.00
17
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
A.C. Characteristics
Symbol
fSYS
Parameter
System Clock
Ta=25°C
Test Conditions
Min.
Typ.
Max.
Unit
2.2V~5.5V
32
¾
4000
kHz
3.0V~5.5V
32
¾
8000
kHz
4.5V~5.5V
32
¾
12000
kHz
3V/5V Ta=25°C
-2%
4
+2%
MHz
3V/5V Ta=25°C
-2%
8
+2%
MHz
-2%
12
+2%
MHz
3V/5V Ta=0~70°C
-5%
4
+5%
MHz
3V/5V Ta=0~70°C
-5%
8
+5%
MHz
VDD
¾
5V
fHIRC
fERC
System Clock
(ERC)
fLXT
System Clock (LXT)
fTIMER
Timer Input Frequency
(TCn)
fLIRC
Ta=0~70°C
-5%
12
+5%
MHz
-8%
4
+8%
MHz
3.0V~
Ta=0~70°C
5.5V
-8%
4
+8%
MHz
3.0V~
Ta=0~70°C
5.5V
-8%
8
+8%
MHz
4.5V~
Ta=0~70°C
5.5V
-8%
12
+8%
MHz
2.2V~
Ta= -40°C~85°C
3.6V
-12%
4
+12%
MHz
3.0V~
Ta= -40°C~85°C
5.5V
-12%
4
+12%
MHz
3.0V~
Ta= -40°C~85°C
5.5V
-12%
8
+12%
MHz
4.5V~
Ta= -40°C~85°C
5.5V
-12%
12
+12%
MHz
5V
Ta=25°C, R=120kW *
-2%
4
+2%
MHz
5V
Ta=0~70°C, R=120kW *
-5%
4
+5%
MHz
5V
Ta= -40°C~85°C,
R=120kW *
-7%
4
+7%
MHz
2.2V~ Ta= -40°C~85°C,
5.5V R=120kW *
-11%
4
+11%
MHz
¾
32768
¾
Hz
2.2V~5.5V
0
¾
4000
kHz
3.0V~5.5V
0
¾
8000
kHz
4.5V~5.5V
0
¾
12000
kHz
¾
¾
¾
3V
¾
5
10
15
kHz
5V
¾
6.5
13
19.5
kHz
¾
1
¾
¾
ms
For HXT/LXT
¾
128
¾
tSYS
For ERC/IRC
¾
2
¾
tSYS
LIRC Oscillator
tRES
External Reset Low Pulse Width
¾
tSST
System Start-up time Period
¾
Rev. 1.00
Ta=25°C
2.2V~
Ta=0~70°C
3.6V
5V
System Clock
(HIRC)
Conditions
18
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Ta=25°C
Symbol
Test Conditions
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tLVR
Low Voltage Width to Reset
¾
¾
0.25
1
2
ms
tRSTD
Reset Delay Time
¾
¾
¾
50
¾
ms
Note:
1. tSYS=1/fSYS
2. *For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended.
3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should
be connected between VDD and VSS and located as close to the device as possible.
Power-on Reset Characteristics
Symbol
Ta=25°C
Test Conditions
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VPOR
VDD Start Voltage to Ensure
Power-on Reset
¾
¾
¾
¾
100
mV
RRVDD
VDD Rise Rate to Ensure
Power-on Reset
¾
¾
0.035
¾
¾
V/ms
tPOR
Minimum Time for VDD to remain
at VPOR to Ensure Power-on Reset
¾
¾
1
¾
¾
ms
V
D D
tP
O R
R R
V D D
V
P O R
T im e
Comparator Amplifier Characteristics
Ta=25°C
Symbol
ICOMP
Parameter
Comparator Operating Current
Test Conditions
VDD
3V
Min.
Typ.
Max.
Unit
CPCS[1:0]=00B
¾
200
300
mA
CPCS[1:0]=01B
¾
5
10
mA
CPCS[1:0]=10B
¾
1
2
mA
Conditions
VOS
Comparator Input Offset Voltage
3V
¾
-10
¾
10
mV
VCM
Comparator Common Mode
Voltage Range
¾
¾
0
¾
VDD-1.4V
V
tPD
Comparator Response Time
(With 10mV overdrive)
Rev. 1.00
3V
CPCS[1:0]=00B
¾
¾
2
ms
3V
CPCS[1:0]=01B
¾
¾
60
ms
¾
CPCS[1:0]=10B
¾
¾
400
ms
19
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Operational Amplifier Characteristics
Symbol
Parameter
Power Down Current
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
3V
¾
¾
¾
0.1
mA
-15
¾
15
mV
-4
¾
4
mV
VOPOS1
Input Offset Voltage
3V
Without calibration,
OPOF[3:0]=1000B
VOPOS2
Input Offset Voltage
3V
By Calibration
VCM
Common Mode Voltage Range
¾
¾
VSS
¾
VDD-1.4V
V
PSRR
Power Supply Rejection Ratio
3V
¾
60
80
¾
dB
CMRR
Common Mode Rejection Ratio
3V
VCM=0~VDD-1.4V
60
80
¾
dB
SR
Slew Rate +, Slew Rate -
3V
No load
1.8
2.5
¾
V/ms
GBW
Gain Band Width
3V
RL=1M, CL=100p
500
¾
¾
kHz
Rev. 1.00
20
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to
the internal system architecture. The range of devices take advantage of the usual features found
within RISC microcontrollers providing increased speed of operation and enhanced performance. The
pipelining scheme is implemented in such a way that instruction fetching and instruction execution are
overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or
call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries
out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The
internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal
registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple
addressing methods of these registers along with additional architectural features ensure that a
minimum of external components is required to provide a functional I/O control system with
maximum reliability and flexibility.
Clocking and Pipelining
The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into
four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the
beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one
instruction cycle. Although the fetching and execution of instructions takes place in consecutive
instruction cycles, the pipelining structure of the microcontroller ensures that instructions are
effectively executed in one instruction cycle. The exception to this are instructions where the contents
of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction
will take one more instruction cycle to execute.
O s c illa to r C lo c k
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m
C o u n te r
P ip e lin in g
P C
P C + 1
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
P C + 2
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
Rev. 1.00
21
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
For instructions involving branches, such as jump or call instructions, two instruction cycles are
required to complete instruction execution. An extra cycle is required as the program takes one cycle to
first obtain the actual jump or call address and then another cycle to actually execute the branch. The
requirement for this extra cycle should be taken into account by programmers in timing sensitive
applications.
3
M O V A ,[1 2 H ]
C A L L D E L A Y
C P L [1 2 H ]
5
:
1
2
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
:
4
F e tc h In s t. 6
N O P
6
F lu s h P ip e lin e
E x e c u te In s t. 6
F e tc h In s t. 7
D E L A Y :
Instruction Fetching
Program Counter
During program execution, the Program Counter is used to keep track of the address of the next
instruction to be executed. It is automatically incremented by one each time an instruction is executed
except for instructions, such as ²JMP² or ²CALL² that demand a jump to a non-consecutive Program
Memory address. Note that the Program Counter width varies with the Program Memory capacity
depending upon which device is selected. However, it must be noted that only the lower 8 bits, known
as the Program Counter Low Register, are directly addressable by user.
When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition has
been met, the next instruction, which has already been fetched during the present instruction
execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
Program Counter
Device
Program Counter High Byte
HT48R064G
PC9, PC8
HT48R065G
PC10~PC8
HT48R066G
HT48R0662G
PC11~PC8
PCL Register
PCL7~PCL0
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writeable register. By transferring data directly
into this register, a short program jump can be executed directly, however, as only this low byte is
available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted.
The lower byte of the Program Counter is fully accessible under program control. Manipulating the
PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on
the PCL register can be found in the Special Function Register section.
Rev. 1.00
22
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Stack
This is a special part of the memory which is used to save the contents of the Program Counter only.
The stack is neither part of the Data or Program Memory space, and is neither readable nor writeable.
The activated level is indexed by the Stack Pointer, SP, and is neither readable nor writeable. At a
subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto
the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or
RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the
Stack Pointer will point to the top of the stack.
P ro g ra m
T o p o f S ta c k
C o u n te r
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k
P o in te r
B o tto m
P ro g ra m
M e m o ry
S ta c k L e v e l 3
o f S ta c k
S ta c k L e v e l N
Device
Stack Levels
HT48R064G/065G/066G
4
HT48R0662G
6
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but
the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI,
the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use
the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be
executed which will result in a stack overflow. Precautions should be taken to avoid such cases
which might cause unpredictable program branching.
Arithmetic and Logic Unit - ALU
The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and
logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specified register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated to
reflect these changes. The ALU supports the following functions:
Rev. 1.00
·
Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
·
Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
·
Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
·
Increment and Decrement INCA, INC, DECA, DEC
·
Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI
23
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Program Memory
The Program Memory is the location where the user code or program is stored. The device is supplied
with One-Time Programmable, OTP, memory where users can program their application code into the
device. By using the appropriate programming tools, OTP devices offer users the flexibility to freely
develop their applications which may be useful during debug or for products requiring frequent
upgrades or program changes.
Structure
The Program Memory has a capacity of 1K´14 to 4K´15. The Program Memory is addressed by the
Program Counter and also contains data, table information and interrupt entries. Table data, which can
be setup in any location within the Program Memory, is addressed by separate table pointer registers.
Device
Capacity
HT48R064G
1K´14
HT48R065G
2K´15
HT48R066G/0662G
4K´15
Special Vectors
Within the Program Memory, certain locations are reserved for special usage such as reset and
interrupts.
Reset Vector
This vector is reserved for use by the device reset for program initialisation. After a device reset is initiated,
the program will jump to this location and begin execution.
External Interrupt Vector
This vector is used by the external interrupt. If the external interrupt pin on the device receives an edge
transition, the program will jump to this location and begin execution if the external interrupt is
enabled and the stack is not full. The external interrupt active edge transition type, whether high to low,
low to high or both is specified in the CTRL1 register.
H T 4 8 R 0 6 4 G
H T 4 8 R 0 6 5 G
H T 4 8 R 0 6 6 G
H T 4 8 R 0 6 6 2 G
0 0 0 H
R e s e t
R e s e t
R e s e t
0 0 4 H
E x te rn a l
In te rru p t
E x te rn a l
In te rru p t
E x te rn a l
In te rru p t
0 0 8 H
T im e r 0
In te rru p t
T im e r 0
In te rru p t
T im e r 0
In te rru p t
T im e r 1
In te rru p t
T im e r 1
In te rru p t
0 0 C H
0 1 0 H
0 1 4 H
T im e B a s e
In te rru p t
T im e B a s e
In te rru p t
T im e B a s e
In te rru p t
0 1 8 H
M u lti- fu n c tio n
In te rru p t
M u lti- fu n c tio n
In te rru p t
M u lti- fu n c tio n
In te rru p t
3 F F H
1 4 b its
7 F F H
1 5 b its
F F F H
1 5 b its
Program Memory Structure
Rev. 1.00
24
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Timer/Event 0/1 Counter Interrupt Vector
This internal vector is used by the Timer/Event Counters. If a Timer/Event Counter overflow occurs,
the program will jump to its respective location and begin execution if the associated Timer/Event
Counter interrupt is enabled and the stack is not full.
Time Base Interrupt Vector
This vector is used by the OPA0, OPA1 and Comparator. When either an OPA or Comparator,
dependent upon which one is selected, requires interrupt servicing, the program will jump to this
location and begin execution if the output interrupt is enabled and the stack is not full.
Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers can
store fixed data. To use the look-up table, the table pointer must first be setup by placing the lower
order address of the look up data to be retrieved in the table pointer register, TBLP. This register
defines the lower 8-bit address of the look-up table.
After setting up the table pointer, the table data can be retrieved from the current Program Memory
page or last Program Memory page using the ²TABRDC[m]² or ²TABRDL [m]² instructions,
respectively. When these instructions are executed, the lower order table byte from the Program
Memory will be transferred to the user defined Data Memory register [m] as specified in the
instruction. The higher order table data byte from the Program Memory will be transferred to the
TBLH special register. Any unused bits in this transferred higher order byte will be read as ²0².
The following diagram illustrates the addressing/data flow of the look-up table:
L a s t p a g e o r
p re s e n t p a g e
P C x ~ P C 8
P ro g ra m
H ig h B y te
A d d re s s
P C
T B L P R e g is te r
M e m o ry
D a ta
1 4 ~ 1 5 b its
R e g is te r T B L H
U s e r S e le c te d
R e g is te r
H ig h B y te
Instruction
L o w
B y te
Table Location Bits
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
TABRDC [m]
PC11
PC10
PC9
PC8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
PC11~PC8: Current Program Counter bits
@7~@0: Table Pointer TBLP bits
For the HT48R064G, the Table address location is 10 bits, i.e. from b9~b0
For the HT48R065G, the Table address location is 11 bits, i.e. from b10~b0
For the HT48R066G/HT48R0662G, the Table address location is 12 bits, i.e. from b11~b0
Rev. 1.00
25
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Table Program Example
The accompanying example shows how the table pointer and table data is defined and retrieved from
the device. This example uses raw table data located in the last page which is stored there using the
ORG statement. The value at this ORG statement is ²300H² which refers to the start address of the last
page within the 1K Program Memory of the device. The table pointer is setup here to have an initial
value of ²06H². This will ensure that the first data read from the data table will be at the Program
Memory address ²306H² or 6 locations after the start of the last page. Note that the value for the table
pointer is referenced to the first address of the present page if the ²TABRDC [m]² instruction is being
used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH
register automatically when the ²TABRDL [m]² instruction is executed.
Because the TBLH register is a read-only register and cannot be restored, care should be taken to
ensure its protection if both the main routine and Interrupt Service Routine use the table read
instructions. If using the table read instructions, the Interrupt Service Routines may change the value
of TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended
that simultaneous use of the table read instructions should be avoided. However, in situations where
simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table related instructions require two instruction
cycles to complete their operation.
Table Read Program Example
tempreg1
tempreg2
:
:
db ?
db ?
; temporary register #1
; temporary register #2
mov
a,06h
; initialise table pointer - note that this address is referenced
mov
:
:
tblp,a
; to the last page or present page
tabrdl tempreg1
; transfers value in table referenced by table pointer
; to tempregl
; data at prog. memory address ²306H² transferred to
; tempreg1 and TBLH
dec
; reduce value of table pointer by one
tblp
Tabrdl tempreg2
; transfers value in table referenced by table pointer
; to tempreg2
; data at prog.memory address ²305H² transferred to
; tempreg2 and TBLH
; in this example the data ²1AH² is transferred to
; tempreg1 and data ²0FH² to register tempreg2
; the value ²00H² will be transferred to the high byte
; register TBLH
:
:
org
300h
dc
:
:
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
Rev. 1.00
; sets initial address of last page
26
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where
temporary information is stored.
Structure
Divided into two sections, the first of these is an area of RAM where special function registers are
located. These registers have fixed locations and are necessary for correct operation of the device. Many
of these registers can be read from and written to directly under program control, however, some remain
protected from user manipulation. The second area of Data Memory is reserved for general purpose use.
All locations within this area are read and write accessible under program control.
Capacity
Banks
HT48R064G
Device
64´8
¾
HT48R065G
96´8
¾
HT48R066G
128´8
¾
HT48R0662G
224´8
0, 1
The two sections of Data Memory, the Special Purpose and General Purpose Data Memory are located
at consecutive locations. All are implemented in RAM and are 8 bits wide but the length of each memory section is dictated by the type of microcontroller chosen. The start address of the Data Memory for
all devices is the address ²00H².
All microcontroller programs require an area of read/write memory where temporary data can be
stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data
Memory. This area of Data Memory is fully accessible by the user program for both read and write
operations. By using the ²SET [m].i² and ²CLR [m].i² instructions individual bits can be set or reset
under program control giving the user a large range of flexibility for bit manipulation in the Data
Memory.
H T 4 8 R 0 6 6 2 G
B a n k 0
B a n k 1
H T 4 8 R 0 6 4 G
H T 4 8 R 0 6 5 G
H T 4 8 R 0 6 6 G
0 0 H
IA R 0
IA R 0
IA R 0
IA R 0
IA R 0
0 1 H
M P 0
M P 0
M P 0
M P 0
M P 0
0 0 H
IA R 1
IA R 1
IA R 1
IA R 1
IA R 1
0 1 H
M P 1
M P 1
M P 1
M P 1
M P 1
S p e c ia l
P u rp o s e
R e g is te r s
3 F H
4 0 H
7 F H
6 4 b y te s
9 F H
9 6 b y te s
T o ta l 2 2 4 b y te s
1 2 8 b y te s
B F H
5 F H
G e n e ra l
P u rp o s e
R e g is te r s
F F H
Data Memory Structure
Note:
Rev. 1.00
Most of the Data Memory bits can be directly manipulated using the ²SET [m].i² and ²CLR
[m].i² with the exception of a few dedicated bits. The Data Memory can also be accessed
through the memory pointer registers.
27
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Special Purpose Data Memory
This area of Data Memory is where registers, necessary for the correct operation of the
microcontroller, are stored. Most of the registers are both readable and writeable but some are
protected and are readable only, the details of which are located under the relevant Special Function
Register section. Note that for locations that are unused, any read instruction to these addresses will
return the value ²00H².
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
HT48R064G
HT48R065G
HT48R066G
HT48R0662G
IAR0
MP0
IAR1
MP1
IAR0
MP0
IAR1
MP1
ACC
PCL
TBLP
TBLH
WDTS
STATUS
INTC0
TMR0
TMR0C
ACC
PCL
TBLP
TBLH
WDTS
STATUS
INTC0
TMR0
TMR0C
TMR1
TMR1C
PA
PAC
PAPU
PAWK
PB
PBC
PBPU
PC
PCC
PCPU
CTRL0
CTRL1
LCDC
MFIC
INTC1
IAR0
MP0
IAR1
MP1
BP
ACC
PCL
TBLP
TBLH
WDTS
STATUS
INTC0
TMR0
TMR0C
TMR1
TMR1C
PA
PAC
PAPU
PAWK
PB
PBC
PBPU
PC
PCC
PCPU
CTRL0
CTRL1
LCDC
IAR0
MP0
IAR1
MP1
BP
ACC
PCL
TBLP
TBLH
WDTS
STATUS
INTC0
TMR0
TMR0C
TMR1
TMR1C
PA
PAC
PAPU
PAWK
PB
PBC
PBPU
PC
PCC
PCPU
CTRL0
CTRL1
LCDC
PWM1
INTC1
PWM0
PA
PAC
PAPU
PAWK
PB
PBC
PBPU
PC
PCC
PCPU
CTRL0
CTRL1
INTC1
CMP0C
CMP1C
COPA0C
COPA1C
COPA2C
COPA3C
OPA0OC
OPA1OC
INTC1
MFIC
PD
PDC
PDPU
MFIC
PD
PDC
PDPU
PE
PEC
PEPU
PF
PFC
PFPU
CTRL2
CMP0C
CMP1C
COPA0C
COPA1C
COPA2C
COPA3C
OPA0OC
OPA1OC
CTRL2
CMP0C
CMP1C
COPA0C
COPA1C
COPA2C
COPA3C
OPA0OC
OPA1OC
PCWK
PCWK
CMP0C
CMP1C
COPA0C
COPA1C
COPA2C
COPA3C
OPA0OC
OPA1OC
3EH
3FH
: unused, read as 00H
Special Purpose Data Memory
Rev. 1.00
28
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HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Special Function Registers
To ensure successful operation of the microcontroller, certain internal registers are implemented in the
Data Memory area. These registers ensure correct operation of internal functions such as timers,
interrupts, etc., as well as external functions such as I/O data control. The location of these registers
within the Data Memory begins at the address ²00H² and are mapped into both Bank 0 and Bank 1.
Any unused Data Memory locations between these special function registers and the point where the
General Purpose Memory begins is reserved and attempting to read data from these locations will
return a value of ²00H².
Indirect Addressing Registers - IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM
register space, do not actually physically exist as normal registers. The method of indirect addressing
for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in
contrast to direct memory addressing, where the actual memory address is specified. Actions on the
IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to
the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as a pair,
IAR0 with MP0 and IAR1 with MP1 can together access data from the Data Memory. As the Indirect
Addressing Registers are not physically implemented, reading the Indirect Addressing Registers
indirectly will return a result of ²00H² and writing to the registers indirectly will result in no operation.
Memory Pointers - MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically
implemented in the Data Memory and can be manipulated in the same way as normal registers
providing a convenient way with which to indirectly address and track data. MP0 can only be used to
indirectly address data in Bank 0 while MP1 can be used to address data in Bank 0 and Bank1. When
any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the
microcontroller is directed to, is the address specified by the related Memory Pointer. Note that for the
HT48R064G device, bit 7 of the Memory Pointers is not required to address the full memory space.
When bit 7 of the Memory Pointers for these devices is read, a value of ²1² will be returned. Note that
indirect addressing using MP1 and IAR1 must be used to access any data in Bank 1. The following
example shows how to clear a section of four Data Memory locations already defined as locations adres1
to adres4.
·
Indirect Addressing Program Example
data .section ¢data¢
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 code
org 00h
start:
mov
mov
mov
mov
a,04h
block,a
a,offset adres1
mp0,a
; setup size of block
clr
inc
sdz
jmp
IAR0
mp0
block
loop
; clear the data at address defined by MP0
; increment memory pointer
; check if last memory location has been cleared
; Accumulator loaded with first RAM address
; setup memory pointer with first RAM address
loop:
continue:
The important point to note here is that in the example shown above, no reference is made to specific
Data Memory addresses.
Rev. 1.00
29
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HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Accumulator - ACC
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate results from
the ALU are stored. Without the Accumulator it would be necessary to write the result of each
calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting
in higher programming and timing overheads. Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when transferring data between one user defined
register and another, it is necessary to do this by passing the data through the Accumulator as no direct
transfer between two registers is permitted.
Program Counter Low Register - PCL
To provide additional program control functions, the low byte of the Program Counter is made
accessible to programmers by locating it within the Special Purpose area of the Data Memory. By
manipulating this register, direct jumps to other program locations are easily implemented. Loading a
value directly into this PCL register will cause a jump to the specified Program Memory location,
however, as the register is only 8-bit wide, only jumps within the current Program Memory page are
permitted. When such operations are used, note that a dummy cycle will be inserted.
Bank Pointer - BP
In the HT48R0662G device, the Data Memory is divided into two Banks, known as Bank 0 and Bank
1. A Bank Pointer, which is bit 0 of the Bank Pointer register is used to select the required Data
Memory bank. Only data in Bank 0 can be directly addressed as data in Bank 1 must be indirectly
addressed using Memory Pointer MP1 and Indirect Addressing Register IAR1. Using Memory
Pointer MP0 and Indirect Addressing Register IAR0 will always access data from Bank 0, irrespective
of the value of the Bank Pointer. Memory Pointer MP1 and Indirect Addressing Register IAR1 can
indirectly address data in either Bank 0 or Bank 1 depending upon the value of the Bank Pointer.
The Data Memory is initialised to Bank 0 after a reset, except for the WDT time-out reset in the
Idle/Sleep Mode, in which case, the Data Memory bank remains unaffected. It should be noted that
Special Function Data Memory is not affected by the bank selection, which means that the Special
Function Registers can be accessed from within either Bank 0 or Bank 1. Directly addressing the Data
Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer.
· BP Register - HT48R0662G
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
¾
¾
¾
DMBP0
R/W
¾
¾
¾
¾
¾
¾
¾
R/W
POR
¾
¾
¾
¾
¾
¾
¾
0
Bit 7~1 :
Bit 0
Rev. 1.00
unimplemented, read as ²0²
DMBP0: Data Memory bank point
0: Bank 0
1: Bank 1
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HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Status Register - STATUS
This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation
and system management flags are used to record the status and operation of the microcontroller.
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like
most other registers. Any data written into the status register will not change the TO or PDF flag. In
addition, operations related to the status register may give different results due to the different
instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by
executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system power-up.
The Z, OV, AC and C flags generally reflect the status of the latest operations.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not
be pushed onto the stack automatically. If the contents of the status registers are important and if the
interrupt routine can change the status register, precautions must be taken to correctly save it. Note that
bits 0~3 of the STATUS register are both readable and writeable bits.
· STATUS Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
TO
PDF
OV
Z
AC
C
R/W
¾
¾
R
R
R/W
R/W
R/W
R/W
POR
¾
¾
0
0
x
x
x
x
²x² unknown
Bit 7, 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
unimplemented, read as ²0²
TO: Watchdog Time-Out flag
0: After power up or executing the ²CLR WDT² or ²HALT² instruction
1: A watchdog time-out occurred.
PDF: Power down flag
0: After power up or executing the ²CLR WDT² instruction
1: By executing the ²HALT² instruction
OV: Overflow flag
0: no overflow
1: an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
AC: Auxiliary flag
0: no auxiliary carry
1: an operation results in a carry out of the low nibbles in addition, or no borrow from the
high nibble into the low nibble in subtraction
C: Carry flag
0: no carry-out
1: an operation results in a carry during an addition operation or if a borrow does not take place
during a subtraction operation
C is also affected by a rotate through carry instruction.
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HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Input/Output Ports and Control Registers
Within the area of Special Function Registers, the port PA, PB, etc data I/O registers and their associated
control register PAC, PBC, etc play a prominent role. These registers are mapped to specific addresses
within the Data Memory as shown in the Data Memory table. The data I/O registers, are used to transfer
the appropriate output or input data on the port. The control registers specifies which pins of the port are
set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the control
register must be set high, for an output it must be set low. During program initialisation, it is important to
first setup the control registers to specify which pins are outputs and which are inputs before reading data
from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly
program single bits using the ²SET [m].i² and ²CLR [m].i² instructions. The ability to change I/O pins
from output to input and vice versa by manipulating specific bits of the I/O control registers during
normal program operation is a useful feature of these devices.
System Control Registers - CTRL0, CTRL1, CTRL2
These registers are used to provide control over several internal functions. These functions include the
external Interrupt edge trigger type, the PWM function control, Time Base period selection and LXT
oscillator low power control,etc.
· CTRL0 Register - HT48R064G
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
¾
PFDC
LXTLP
CLKMOD
R/W
¾
¾
¾
¾
¾
R/W
R/W
R/W
POR
¾
¾
¾
¾
¾
0
0
0
· CTRL0 Register - HT48R065G
Bit
7
6
5
4
3
2
1
0
Name
¾
PFDCS
¾
¾
¾
PFDC
LXTLP
CLKMOD
R/W
¾
R/W
¾
¾
¾
R/W
R/W
R/W
POR
¾
0
¾
¾
¾
0
0
0
· CTRL0 Register - HT48R0662G
Bit
7
6
5
4
3
2
1
0
Name
¾
PFDCS
PWMSEL
PWMC1
PWMC0
PFDC
LXTLP
CLKMOD
R/W
¾
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
¾
0
0
0
0
0
0
0
unimplemented, read as ²0²
PFDCS: PFD clock source selection
0: timer0
1: timer1
For HT48R064G device, this bit is read as 0 and the PFD clock source always comes from the
timer.
PWMSEL: PWM type selection
0: 6+2 type
1: 7+1 type
PWMC1: I/O or PWM1 selection
0: I/O
1: PWM1
PWMC0: I/O or PWM0 selection
0: I/O or other pin-shared functions
1: PWM0
Rev. 1.00
32
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HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
PFDC: I/O or PFD selection
0: I/O
1: PFD
LXTLP: LXT oscillator low power control function
0: LXT Oscillator quick start-up mode
1: LXT Oscillator Low Power Mode
CLKMOD: system clock mode selection
0: High speed - HIRC oscillator used as system clock
1: Low speed - LXT oscillator used as system clock, HIRC oscillator stopped
For HT48R064G/HT48R065G devices, this bit is available if the oscillator configuration options
have selected the HIRC+LXT.
If the PWMn output is selected by the PWMCn bit, the PWM clock source fTP always comes from the system
clock source fSYS. The fTP clock is the clock source for timer0, timer 1, time base and PWM.
Note:
· CTRL0 Register - HT48R066G
Bit
7
6
5
4
3
2
1
0
Name
PCFG
PFDCS
¾
¾
PFDEN1
PFDEN0
LXTLP
CLKMOD
R/W
R/W
R/W
¾
¾
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5~4
Bit 3~2:
Bit 1
Bit 0
Rev. 1.00
PCFG: I/O configuration
0: INTB/TC0/PFD pin-shared with PA3/PA2/PA0
1: INTB/TC0/PFD pin-shared with PC5/PC4/PC3
PFDCS: PFD clock source
0: Timer 0
1: Timer 1
unimplemented, read as ²0²
PFDEN[1:0]: PFD/PFDB enable/ disable
00: Both disable
01: unimplemented, read as ²0²
10: PFD enable
11: PFD and PFDB enable
LXTLP: LXT oscillator low power control function
0: LXT oscillator quick start-up mode
1: LXT oscillator Low Power Mode
CLKMOD: System clock mode selection
0: High speed - HIRC used as system clock
1: Low speed - LXT used as system clock, HIRC oscillator stopped
This clock mode selection is only valid if the oscillator configuration option has selected the
HIRC+LXT.
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February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
· CTRL1 Register
Bit
7
6
5
4
3
2
1
0
Name
INTEG1
INTEG0
TBSEL1
TBSEL0
WDTEN3
WDTEN2
WDTEN1
WDTEN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
0
0
0
1
0
1
0
Bit 7, 6
Bit 5, 4
INTEG1, INTEG0: External interrupt edge type
00: disable
01: rising edge trigger
10: falling edge trigger
11: dual edge trigger
TBSEL1, TBSEL0: Time base period selection
10
00: 2 /fTP
11
01: 2 /fTP
12
10: 2 1/fTP
13
11: 2 1/fTP
Bit 3~0
Note:
WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT function enable
1010: WDT function disabled
Other values: WDT function enabled - Recommended value is 0101
If the ²watchdog timer enable configuration option² is selected, then the watchdog timer will
always be enabled and the WDTEN3~WDTEN0 control bits will have no effect.
The WDT is only disabled when both the WDT configuration option is disabled and when bits
WDTEN3~WDTEN0 is set to 1010. The WDT is enabled when either the WDT configuration option is enabled
or when bits WDTEN3~WDTEN0¹1010.
· CTRL2 Register - HT48R0662G
Bit
7
6
5
4
3
2
1
0
Name
PCFG1
PCFG0
¾
¾
¾
¾
¾
LXTEN
R/W
R/W
R/W
¾
¾
¾
¾
¾
R/W
POR
0
0
¾
¾
¾
¾
¾
1
Bit 7~6
PCFG1, PCFG0: Pin configuration
00: PFD/TC0/INT/TC1 pin-shared with PA1/PA2/PA3/PA4
01: PFD/TC0/INT/TC1 pin-shared with PC5/PC4/PC3/PC2
10: PFD/TC0/INT/TC1 pin-shared with PB0/PB1/PB2/PB3
11: PFD/TC0/INT/TC1 pin-shared with PE0/PE1/PE2/PE3
Bit 5~1
Bit 0
Unimplemented, read as ²0²
LXTEN: LXT Oscillator on/off control after execution of HALT instruction
0: LXT oscillator off after HALT instruction
1: LXT oscillator on after HALT instruction
Rev. 1.00
34
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Wake-up Function Register - PAWK, PCWK
When the microcontroller enters the Idle/Sleep Mode, various methods exist to wake the device up and
continue with normal operation. One method is to allow a falling edge on the I/O pins to have a
wake-up function. These register are used to selected which pins on I/O Port A or Port C are used to
have this wake-up function.
Pull-high Registers - PAPU, PBPU, PCPU, PDPU, PEPU, PFPU
The I/O pins, if configured as inputs, can have internal pull-high resistors connected, which eliminates
the need for external pull-high resistors. This register selects which I/O pins are connected to internal
pull-high resistors.
Software COM Register - SCOMC
For HT48R065G, HT48R066G and HT48R0662G devices, the pins PB0~PB3 on Port B can be used
as SCOM lines to drive an external LCD panel. To implement this function, the SCOMC register is
used to setup the correct bias voltages on these pins.
Oscillator
Various oscillator options offer the user a wide range of functions according to their various
application requirements. The flexible features of the oscillator functions ensure that the best optimisation
can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a
combination of configuration options and registers.
System Oscillator Overview
In addition to being the source of the main system clock the oscillators also provide clock sources for
the Watchdog Timer and Time Base functions. External oscillators requiring some external
components as well as a two fully integrated internal oscillators, requiring no external components, are
provided to form a wide range of both fast and slow system oscillators.
Type
Name
Freq.
Pins
External Crystal
HXT
400kHz~12MHz
OSC1/OSC2
External RC
ERC
400kHz~12MHz
OSC1
Internal High Speed RC
HIRC
4, 8 or 12MHz
¾
External Low Speed Crystal
LXT
32768Hz
OSC3/OSC4*
Internal Low Speed RC
LIRC
13kHz
¾
²*² For HT48R0662G only
System Clock Configurations
There are four system oscillators implemented in this device, three high speed oscillators and one low
speed oscillator. The high speed oscillators are the external crystal/ceramic oscillator -- HXT, the
external RC oscillator -- ERC and the internal RC oscillator -- HIRC. The low speed oscillator is the
external 32.768kHz crystal oscillator -- LXT. The LXT oscillator can be used as the system oscillator
only when the HIRC oscillator is selected as the high speed system oscillator for the HT48R0662G
device. Also there is an internal 13kHz RC oscillator named LIRC oscillator used as the clock source
for the WDT function. More details are described in the accompanying sections.
Rev. 1.00
35
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HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
External Crystal/Resonator Oscillator - HXT
The simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and
feedback for oscillation. However, for some crystals and most resonator types, to ensure oscillation
and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and
C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator
manufacturer¢s specification.
C 1
O S C 1
R p
R f
T o in te r n a l
c ir c u its
O S C 2
C 2
In te r n a l
O s c illa to r
C ir c u it
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d . C 1 a n d C 2 a r e r e q u ir e d .
2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic
c a p a c ita n c e o f a r o u n d 7 p F .
Crystal/Resonator Oscillator - HXT
Crystal Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
12MHz
¾
¾
8MHz
¾
¾
4MHz
¾
¾
1MHz
100pF
100pF
Note:
C1 and C2 values are for guidance only.
Crystal Recommended Capacitor Values
External RC Oscillator - ERC
Using the ERC oscillator only requires that a resistor, with a value between 24kW and 1.5MW, is
connected between OSC1 and VDD, and a capacitor is connected between OSC and ground,
providing a low cost oscillator configuration. It is only the external resistor that determines the
oscillation frequency; the external capacitor has no influence over the frequency and is connected for
stability purposes only. Device trimming during the manufacturing process and the inclusion of
internal frequency compensation circuits are used to ensure that the influence of the power supply
voltage, temperature and process variations on the oscillation frequency are minimised. Here only the
OSC1 pin is used, which is shared with I/O pin PA6, leaving pin PA5 free for use as a normal I/O pin.
V
R
D D
O S C
P A 6 /O S C 1
4 7 0 p F
P A 5 /O S C 2
External RC Oscillator - ERC
Rev. 1.00
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February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Internal RC Oscillator - HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components. The
internal RC oscillator has three fixed frequencies of either 4MHz, 8MHz or 12MHz. Device trimming
during the manufacturing process and the inclusion of internal frequency compensation circuits are
used to ensure that the influence of the power supply voltage, temperature and process variations on
the oscillation frequency are minimised. Refer to the A.C. Characteristics for more frequency accuracy
details. Note that if this internal system clock option is selected, as it requires no external pins for its
operation, I/O pins PA5 and PA6 are free for use as normal I/O pins or the LXT oscillator pins
depending upon the selected device.
P A 5 /O S C 2
P A 6 /O S C 1
In te rn a l R C
O s c illa to r
N o te : P A 5 /P A 6 u s e d a s n o rm a l I/O s
Internal RC Oscillator - HIRC
External 32768Hz Crystal Oscillator - LXT
When the microcontroller enters the Idle/Sleep Mode, the system clock is switched off to stop
microcontroller activity and to conserve power. However, in many microcontroller applications it may
be necessary to keep the internal timers operational even when the microcontroller is in the
Power-down Mode. To do this, another clock, independent of the system clock, must be provided. To
do this a configuration option exists to allow a high speed oscillator to be used in conjunction with a
low speed oscillator, known as the LXT oscillator. The LXT oscillator is implemented using a
32768Hz crystal connected to pins OSC1/OSC2 for the HT48R064G/HT48R065G or connected to
pins OSC3/OSC4 for the HT48R0662G. However, for some crystals, to ensure oscillation and
accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2.
The exact values of C1 and C2 should be selected in consultation with the crystal or resonator
manufacturers specification. The external parallel feedback resistor, Rp, is required. For the
HT48R064G/HT48R065G devices the LXT oscillator must be used together with the HIRC oscillator.
For the HT48R0662G device the LXT oscillator must be used together with the HXT, ERC or HIRC
register.
In te r n a l
O s c illa to r
C ir c u it
C 1
R p
3 2 7 6 8 H z
In te rn a l R C
O s c illa to r
T o in te r n a l
c ir c u its
C 2
N o te : 1 . R p , C 1 a n d C 2 a r e r e q u ir e d .
2 . A lth o u g h n o t s h o w n p in s h a v e a
p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F .
External LXT Oscillator - LXT
Rev. 1.00
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February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
LXT Oscillator C1 and C2 Values
Crystal Frequency
32768Hz
Note:
C1
C2
10pF
10pF
1. C1 and C2 values are for guidance only.
2. RP=5M~10MW is recommended.
32768 Hz Crystal Recommended Capacitor Values
For the HT48R0662G device, a configuration option determines if the OSC3/OSC4 pins are used for
the LXT oscillator or as I/O pins.
·
If the I/O option is selected then the OSC3/OSC4 pins can be used as normal I/O pins.
·
If the LXT oscillator is selected, then the 32.768kHz crystal should be connected to the
OSC3/OSC4 pins.
LXT Oscillator Low Power Function
The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode.
The mode selection is executed using the LXTLP bit in the CTRL0 register.
LXTLP Bit
LXT Mode
0
Quick Start
1
Low-power
After power on the LXTLP bit will be automatically cleared to zero ensuring that the LXT oscillator
is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up and
stabilise quickly. However, after the LXT oscillator has fully powered up it can be placed into the
Low-power mode by setting the LXTLP bit high. The oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the LXT oscillator start-up. In power sensitive applications, such as battery applications, where power
consumption must be kept to a minimum, it is therefore recommended that the application program
sets the LXTLP bit high about 2 seconds after power-on.
It should be noted that, no matter what condition the LXTLP bit is set to, the LXT oscillator will always
function normally, the only difference is that it will take more time to start up if in the Low-power
mode.
Internal Low Speed Oscillator - LIRC
The LIRC is a fully self-contained free running on-chip RC oscillator with a typical frequency of
13kHz at 5V requiring no external components. When the device enters the Idle/Sleep Mode, the
system clock will stop running but the LIRC oscillator continues to free-run and to keep the watchdog
active. However, to preserve power in certain applications the LIRC can be disabled via a
configuration option.
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
Operating Modes
By using the LXT low frequency oscillator in combination with a high frequency oscillator, the system
can be selected to operate in a number of different modes. These Modes are Normal, Slow, Idle and
Sleep.
Mode Types and Selection
HT48R064G/HT48R065G/HT48R066G
For these devices, if the LXT oscillator is used then the internal RC oscillator, HIRC, must be used as
the high frequency oscillator. If the HXT or the ERC oscillator is chosen as the high frequency system
clock then the LXT oscillator cannot be used as they share the same oscillator pins. The CLKMOD bit
in the CTRL0 register can be used to switch the system clock from the high speed HIRC oscillator to
the low speed LXT oscillator. When the HALT instruction is executed and the device enters the
Idle/Sleep Mode the LXT oscillator will always continue to run. For these devices the LXT crystal is
connected to the OSC1/OSC2 pins and LXT will always run (the LXTEN bit is not used). Note that
CLKMOD is only valid in HIRC+LXT oscillator configuration for HT48R064G/HT48R065G/
HT48R066G.
HT48R0662G
For the device the LXT oscillator can run together with any of the high speed oscillators, namely the
HXT, ERC or the HIRC. The CLKMOD bit in the CTRL0 register can be used to switch the system
clock from the selected high speed oscillator to the low speed LXT oscillator. When the HALT
instruction is executed the LXT oscillator can be chosen to run or not using the LXTEN bit in the
CTRL2 register.
Note that CLKMOD is only valid in HIRC+LXT oscillator configuration.
f
H X T
C L K M O D
( D e te r m in e N o r m a l/
S lo w M o d e )
H X T
C o n fig u r a tio n o p tio n
f
E R C
f
H IR C
E R C
M U X
H IR C
( N o r m a l)
M U X
(S L O W
f
f
S Y S
)
L X T
L X T
C o n fig u r a tio n o p tio n
L IR C
f
L IR C
f
M U X
S Y S
T o w a tc h d o g tim e r
/4
System Clock Configurations
For all devices, when the system enters the Sleep or Idle Mode, the high frequency system clock will
always stop running. The accompanying tables shows the relationship between the CLKMOD bit, the
HALT instruction and the high/low frequency oscillators. The CLMOD bit can change normal or Slow
Mode.
Rev. 1.00
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HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Operating Mode Control
·
HT48R064G/HT48R065G/HT48R066G
OSC1/OSC2 Configuration
Operating
Mode
Normal
HIRC + LXT
HXT
ERC
HIRC
HIRC
LXT
Run
Run
Run
Run
Run
Slow
¾
¾
¾
Stop
Run
Sleep
Stop
Stop
Stop
Stop
Run
²¾² unimplemented
·
HT48R0662G
OSC1/OSC2 Configuration
Operating
Mode
OSC3/OSC4 Configuration
LXT
HXT
ERC
HIRC
LXTEN=0
LXTEN=1
Normal
Run
Run
Run
Run
Run
Slow
Stop
Stop
Stop
Run
Run
Idle
Stop
Stop
Stop
Stop
Run
Sleep
Stop
Stop
Stop
Stop
Stop
Mode Switching
The devices are switched between one mode and another using a combination of the CLKMOD bit in
the CTRL0 register and the HALT instruction. The CLKMOD bit chooses whether the system runs in
either the Normal or Slow Mode by selecting the system clock to be sourced from either a high or low
frequency oscillator. The HALT instruction forces the system into either the Idle or Sleep Mode,
depending upon whether the LXT oscillator is running or not. The HALT instruction operates
independently of the CLKMOD bit condition.
When a HALT instruction is executed and the LXT oscillator is not running, the system enters the
Sleep mode the following conditions exist:
Rev. 1.00
·
The system oscillator will stop running and the application program will stop at the ²HALT²
instruction.
·
The Data Memory contents and registers will maintain their present condition.
·
The WDT will be cleared and resume counting if the WDT clock source is selected to come from the
LIRC or LXT oscillator. The WDT will stop if its clock source originates from the system clock.
·
The I/O ports will maintain their present condition.
·
In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
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Standby Current Considerations
As the main reason for entering the Idle/Sleep Mode is to keep the current consumption of the MCU to
as low a value as possible, perhaps only in the order of several micro-amps, there are other
considerations which must also be taken into account by the circuit designer if the power consumption
is to be minimised.
Special attention must be made to the I/O pins on the device. All high-impedance input pins must be
connected to either a fixed high or low level as any floating input pins could create internal oscillations
and result in increased current consumption. Care must also be taken with the loads, which are
connected to I/O pins, which are setup as outputs. These should be placed in a condition in which
minimum current is drawn or connected only to external circuits that do not draw current, such as other
CMOS inputs.
If the configuration options have enabled the LIRC oscillator, then this will continue to run when in the
Idle/Sleep Mode and will thus consume some power. For power sensitive applications it may be
therefore preferable to use the system clock source for the Watchdog Timer. The LXT, if configured for
use, will also consume a limited amount of power, as it continues to run when the device enters the
Idle/Sleep Mode. To keep the LXT power consumption to a minimum level the LXTLP bit in the
CTRL0 register, which controls the low power function, should be set high.
Wake-up
After the system enters the Idle/Sleep Mode, it can be woken up from one of various sources listed as
follows:
·
An external reset
·
An external falling edge on PA0~PA7 or PC0~PC7 (HT48R0662G only)
·
A system interrupt
·
A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the
wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the
²HALT² instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status.
Pins PA0 to PA7 or PC0 to PC7 can be setup via the PAWK or PCWK register to permit a negative
transition on the pin to wake-up the system. When a pin on PA0~PA7 or PC0~PC7 wake-up occurs, the
program will resume execution at the instruction following the ²HALT² instruction.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where the
related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program
will resume execution at the instruction following the ²HALT² instruction. In this situation, the
interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later
when the related interrupt is finally enabled or when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is not full, in which case the regular interrupt
response takes place. If an interrupt request flag is set to ²1² before entering the Idle/Sleep Mode, then
any future interrupt requests will not generate a wake-up function and the related interrupt will be
ignored.
Rev. 1.00
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HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
No matter what the source of the wake-up event is, once a wake-up event occurs, there will be a time
delay before normal program execution resumes. Consult the table for the related time.
Oscillator Type
Wake-up
Source
External RES
ERC, IRC
Crystal
tRSDT + tSST2
tRSDT + tSST2
tSST1
tSST2
PA or PC* Port
Interrupt
WDT Overflow
²*² Port C pin wake-up is only available for the HT48R0662G device.
Note: 1. tRSTD (reset delay time), tSYS (system clock)
2. tRSTD is power-on delay, typical time=50ms
3. tSST1= 2 tSYS
4. tSST2= 128 tSYS
Wake-up Delay Time
Watchdog Timer
The Watchdog Timer, also known as the WDT, is provided to inhibit program malfunctions caused by
the program jumping to unknown locations due to certain uncontrollable external events such as
electrical noise.
Watchdog Timer Operation
It operates by providing a device reset when the Watchdog Timer counter overflows. Note that if the
Watchdog Timer function is not enabled, then any instructions related to the Watchdog Timer will
result in no operation.
Setting up the various Watchdog Timer options are controlled via the configuration options and two
internal registers WDTS and CTRL1. Enabling the Watchdog Timer can be controlled by both a
configuration option and the WDTEN bits in the CTRL1 internal register in the Data Memory.
Configuration Option
CTRL1 Register
WDT Function
Disable
Disable
OFF
Disable
Enable
ON
Enable
x
ON
Watchdog Timer On/Off Control
The Watchdog Timer will be disabled if bits WDTEN3~WDTEN0 in the CTRL1 register are written
with the binary value 1010B and WDT configuration option is disable. This will be the condition
when the device is powered up. Although any other data written to WDTEN3~WDTEN0 will ensure
that the Watchdog Timer is enabled, for maximum protection it is recommended that the value
0101B is written to these bits.
Rev. 1.00
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HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
The Watchdog Timer clock can emanate from three different sources, selected by configuration option.
These are LXT, fSYS/4, or LIRC. It is important to note that when the system enters the Idle/Sleep Mode
the instruction clock is stopped, therefore if the configuration options have selected fSYS/4 as the
Watchdog Timer clock source, the Watchdog Timer will cease to function. For systems that operate in
noisy environments, using the LIRC or the LXT as the clock source is therefore the recommended
choice. The division ratio of the prescaler is determined by bits 0, 1 and 2 of the WDTS register, known
as WS0, WS1 and WS2. If the Watchdog Timer internal clock source is selected and with the WS0, WS1
and WS2 bits of the WDTS register all set high, the prescaler division ratio will give a maximum
time-out period.
C L R
W D T 1 F la g
C L R
W D T 2 F la g
C le a r W D T T y p e
C o n fig u r a tio n O p tio n
1 o r 2 In s tr u c tio n s
fS
C L R
/4
L X T
L IR C
C o n fig .
O p tio n
S e le c t
Y S
fW
D T C K
1 5 s ta g e c o u n te r
W D T C lo c k S o u r c e S e le c tio n
W D T T im e - o u t
W S 2 ~ W S 0
Watchdog Timer
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the
status bit TO. However, if the system is in the Idle/Sleep Mode, when a Watchdog Timer time-out
occurs, the device will be woken up, the TO bit in the status register will be set and only the Program
Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the
Watchdog Timer. The first is an external hardware reset, which means a low level on the external reset
pin, the second is using the Clear Watchdog Timer software instructions and the third is when a HALT
instruction is executed. There are two methods of using software instructions to clear the Watchdog
Timer, one of which must be chosen by configuration option. The first option is to use the single ²CLR
WDT² instruction while the second is to use the two commands ²CLR WDT1² and ²CLR WDT2². For
the first option, a simple execution of ²CLR WDT² will clear the Watchdog Timer while for the second
option, both ²CLR WDT1² and ²CLR WDT2² must both be executed to successfully clear the
Watchdog Timer. Note that for this second option, if ²CLR WDT1² is used to clear the Watchdog
Timer, successive executions of this instruction will have no effect, only the execution of a ²CLR
WDT2² instruction will clear the Watchdog Timer. Similarly after the ²CLR WDT2² instruction has
been executed, only a successive ²CLR WDT1² instruction can clear the Watchdog Timer.
WDTS Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
¾
WS2
WS1
WS0
R/W
¾
¾
¾
¾
¾
R/W
R/W
R/W
POR
¾
¾
¾
¾
¾
1
1
1
Bit 7~3 :
Bit 2~0
Rev. 1.00
unimplemented, read as ²0²
WS2, WS1, WS0: WDT time-out period selection
8
000: 2 tWDTCK
9
001: 2 tWDTCK
10
010: 2 tWDTCK
11
011: 2 tWDTCK
12
100: 2 tWDTCK
13
101: 2 tWDTCK
14
110: 2 tWDTCK
15
111: 2 tWDTCK
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Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside parameters. The most important reset condition
is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the
microcontroller, after a short delay, will be in a well defined state and ready to execute the first
program instruction. After this power-on reset, certain important internal registers will be set to
defined states before the program commences. One of these registers is the Program Counter, which
will be reset to zero forcing the microcontroller to begin program execution from the lowest Program
Memory address.
In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset
condition when the microcontroller is running. One example of this is where after power has been
applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a
case, known as a normal operation reset, some of the microcontroller registers remain unchanged
allowing the microcontroller to proceed with normal operation after the reset line is allowed to return
high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All
types of reset operations result in different register conditions being setup.
Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES
reset is implemented in situations where the power supply voltage falls below a certain threshold.
Reset Functions
There are five ways in which a microcontroller reset can occur, through events occurring both
internally and externally:
Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program Memory begins execution from the first
memory address, a power-on reset also ensures that certain other registers are preset to known
conditions. All the I/O port and port control registers will power up in a high condition ensuring that all
pins will be first set to inputs.
Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is
not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable
of providing proper reset operation. For this reason it is recommended that an external RC network is
connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an
extended period to allow the power supply to stabilise. During this time delay, normal operation of the
microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay
time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal
operation. The abbreviation SST in the figures stands for System Start-up Timer.
V D D
0 .9 V
R E S
D D
t RR
SS TT DD ++
t SS
SS TT
In te rn a l R e s e t
Note: tRSTD is power-on delay, typical time=50ms
Power-On Reset Timing Chart
Rev. 1.00
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February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
For most applications a resistor connected between VDD and the RES pin and a capacitor connected
between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to
the RES pin should be kept as short as possible to minimise any stray noise interference.
For applications that operate within an environment where more noise is present the Reset Circuit
shown is recommended.
V
D D
0 .0 1 m F * *
V D D
1 N 4 1 4 8 *
1 0 k W ~
1 0 0 k W
R E S /P A 7
3 0 0 W *
0 .1 ~ 1 m F
V S S
Note:
²*² It is recommended that this component is added for added ESD protection
²**² It is recommended that this component is added in environments where power line noise
is significant
External RES Circuit
More information regarding external reset circuits is located in Application Note HA0075E on the
Holtek website.
RES Pin Reset
This type of reset occurs when the microcontroller is already running and the RES pin is forcefully
pulled low by external hardware such as an external switch. In this case as in the case of other reset, the
Program Counter will reset to zero and program execution initiated from this point.
0 .4 V
R E S
0 .9 V
D D
D D
tR
S T D
+
tS
S T
In te rn a l R e s e t
Note: tRSTD is power-on delay, typical time=50ms
RES Reset Timing Chart
Low Voltage Reset - LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the
device. The LVR function is selected via a configuration option. If the supply voltage of the device
drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will
automatically reset the device internally. For a valid LVR signal, a low supply voltage, i.e., a voltage in
the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C.
characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low
supply voltage and will not perform a reset function. The actual VLVR value can be selected via
configuration options.
L V R
tR
S T D
+
tS
S T
In te rn a l R e s e t
Note: tRSTD is power-on delay, typical time=50ms
Low Voltage Reset Timing Chart
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except
that the Watchdog time-out flag TO will be set to ²1².
W D T T im e - o u t
tR
S T D
+
tS
S T
In te rn a l R e s e t
Note: tRSTD is power-on delay, typical time=50ms
WDT Time-out Reset during Normal Operation Timing Chart
Watchdog Time-out Reset during Idle/Sleep Mode
The Watchdog time-out Reset during Idle/Sleep mode is a little different from other kinds of reset.
Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will
be cleared to ²0² and the TO flag will be set to ²1². Refer to the A.C. Characteristics for tSST details.
W D T T im e - o u t
tS
S T
In te rn a l R e s e t
WDT Time-out Reset during Idle/Sleep Timing Chart
Note: The tSST can be chosen to be either 128 or 2 clock cycles via configuration option if the system clock
source is provided by ERC or HIRC. The SST is 128 for HXT or LXT.
Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. These flags, known as
PDF and TO are located in the status register and are controlled by various microcontroller operations,
such as the Idle/Sleep function or Watchdog Timer. The reset flags are shown in the table:
TO
PDF
0
0
Power-on reset
RESET Conditions
u
u
RES or LVR reset during Normal or Slow Mode operation
1
u
WDT time-out reset during Normal or Slow Mode operation
1
1
WDT time-out reset during Idle or Sleep Mode operation
Note: ²u² stands for unchanged
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
Item
Rev. 1.00
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins counting
Timer/Event Counter
Timer Counter will be turned off
Prescaler
The Timer Counter Prescaler will be cleared
Input/Output Ports
I/O ports will be setup as inputs
Stack Pointer
Stack Pointer will point to the top of the stack
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The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program executio n after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers.
HT46R0662G
MP1
HT46R066G
MP0
HT48R065G
PCL
HT48R064G
Register
Power-on
Reset
·
·
·
·
0000 0000
·
RES or LVR
Reset
WDT Time-out
(Normal
Operation)
WDT Time-out
(Idle/Sleep)
0000 0000
0000 0000
0000 0000
1xxx xxxx
1xxx xxxx
1xxx xxxx
1uuu uuuu
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
·
·
·
1xxx xxxx
1xxx xxxx
1xxx xxxx
1uuu uuuu
·
·
·
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
·
---- ---0
---- ---0
---- ---0
---- ---u
·
BP
ACC
·
·
·
·
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
·
·
·
·
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
TBLH
·
·
·
·
-xxx xxxx
WDTS
·
·
·
·
---- -111
---- -111
---- -111
---- -uuu
STATUS
·
·
·
·
--00 xxxx
--uu uuuu
--1u uuuu
--11 uuuu
--00 -000
--00 -000
--00 -000
--uu -uuu
·
-000 0000
-000 0000
-000 0000
-uuu uuuu
·
-000 -000
-000 -000
-000 -000
-uuu -uuu
-00- -00-
-00- -00-
-00- -00-
-uu- -uu-
INTC0
INTC1
·
·
·
·
·
·
MFIC
·
·
·
·
-000 -000
-000 -000
-000 -000
-uuu -uuu
TMR0
·
·
·
·
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
·
·
·
·
0000 1000
0000 1000
0000 1000
uuuu uuuu
·
·
·
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1
·
·
·
0000 1---
0000 1---
0000 1---
uuuu u---
PA
·
·
·
·
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
·
·
·
·
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAWK
·
·
·
·
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAPU
·
·
·
·
-000 0000
-000 0000
-000 0000
-uuu uuuu
---- 1111
---- 1111
---- 1111
---- uuuu
--11 1111
--11 1111
--11 1111
--uu uuuu
1111 1111
1111 1111
1111 1111
uuuu uuuu
---- 1111
---- 1111
---- 1111
---- uuuu
--11 1111
--11 1111
--11 1111
--uu uuuu
1111 1111
1111 1111
1111 1111
uuuu uuuu
TMR1C
·
·
PB
·
·
·
·
PBC
·
·
·
PBPU
·
·
·
Rev. 1.00
---- 0000
---- 0000
---- 0000
---- uuuu
--00 0000
--00 0000
--00 0000
--uu uuuu
0000 0000
0000 0000
0000 0000
uuuu uuuu
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Enhanced I/O Type 8-Bit OTP MCU with OPA
HT48R065G
HT46R066G
HT48R0662G
HT48R064G
Register
Power-on
Reset
·
·
·
1111 1111
·
PC
·
PCC
·
·
·
·
PCPU
·
·
·
·
PCWK
·
RES or LVR
Reset
WDT Time-out
(Normal
Operation)
WDT Time-out
(Idle/Sleep)
1111 --11
1111 --11
1111 --11
uuuu --uu
1111 1111
1111 1111
uuuu uuuu
1111 --11
1111 --11
1111 --11
uuuu --uu
1111 1111
1111 1111
1111 1111
uuuu uuuu
0000 --00
0000 --00
0000 --00
uuuu --uu
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
uuuu uuuu
---- 1111
---- 1111
---- 1111
---- uuuu
1111 1111
1111 1111
1111 1111
uuuu uuuu
---- 1111
---- 1111
---- 1111
---- uuuu
1111 1111
1111 1111
1111 1111
uuuu uuuu
---- 0000
---- 0000
---- 0000
---- uuuu
·
0000 0000
0000 0000
0000 0000
uuuu uuuu
PE
·
1111 1111
1111 1111
1111 1111
uuuu uuuu
PEC
·
1111 1111
1111 1111
1111 1111
uuuu uuuu
PEPU
·
0000 0000
0000 0000
0000 0000
uuuu uuuu
PF
·
---- --11
---- --11
---- --11
---- --uu
PFC
·
---- --11
---- --11
---- --11
---- --uu
PFPU
·
---- --00
---- --00
---- --00
---- --uu
--0- 0000
--0- 0000
--0- 0000
--u- uuuu
PD
·
·
PDC
·
·
PDPU
·
·
CTRL0
CTRL1
·
·
·
·
CTRL2
·
-00- 0000
-00- 0000
-uu- uuuu
-000 0000
-000 0000
-000 0000
-uuu uuuu
·
1000 1010
1000 1010
1000 1010
uuuu uuuu
·
00-- ---1
00-- ---1
00-- ---1
uu-- ---u
·
0000 0000
0000 0000
0000 0000
uuuu uuuu
PWM0
·
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM1
·
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
SCOMC
·
-00- 0000
·
CMP0C
·
·
·
·
-000 0000
-000 0000
-000 0000
-uuu uuuu
CMP1C
·
·
·
·
000- 0-00
000- 0-00
000- 0-00
uuu- u-uu
COPA0C
·
·
·
·
0000 0000
0000 0000
0000 0000
uuuu uuuu
COPA1C
·
·
·
·
0000 0000
0000 0000
0000 0000
uuuu uuuu
COPA2C
·
·
·
·
0000 0000
0000 0000
0000 0000
uuuu uuuu
COPA3C
·
·
·
·
0000 0000
0000 0000
0000 0000
uuuu uuuu
OPA0OC
·
·
·
·
0x00 1000
0x00 1000
0x00 1000
uuuu uuuu
OPA1OC
·
·
·
·
0x00 1000
0x00 1000
0x00 1000
uuuu uuuu
Note:
²-² not implemented
²u² means ²unchanged²
²x² means ²unknown²
Rev. 1.00
48
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. Most pins can have either an
input or output designation under user program control. Additionally, as there are pull-high resistors
and wake-up software configurations, the user is provided with an I/O structure to meet the needs of a
wide range of application possibilities.
For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising
edge of instruction ²MOV A,[m]², where m denotes the port address. For output operation, all the data
is latched and remains unchanged until the output latch is rewritten.
Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the use
of an external resistor. To eliminate the need for these external resistors, when configured as an input
have the capability of being connected to an internal pull-high resistor. These pull-high resistors are
selectable via a register known as PAPU, PBPU, PCPU, PDPU, PEPU and PFPU located in the Data
Memory. The pull-high resistors are implemented using weak PMOS transistors. Note that pin PA7
does not have a pull-high resistor selection.
I/O Port Wake-up
If the HALT instruction is executed, the device will enter the Idle/Sleep Mode, where the system clock
will stop resulting in power being conserved, a feature that is important for battery and other
low-power applications. Various methods exist to wake-up the microcontroller, one of which is to
change the logic condition on one of the PA0~PA7 pins from high to low. For the HT48R0662G
device, a logic transition from high to low on one of the PC0~PC7 pins can also wake up the
microcontroller if the corresponding wake-up function control is enabled. After a HALT instruction
forces the microcontroller into entering the Idle/Sleep Mode, the processor will remain idle or in a
low-power state until the logic condition of the selected wake-up pin on Port A or Port C changes from
high to low. This function is especially suitable for applications that can be woken up via external
switches. Note that pins PA0~PA7 or PC0~PC7 can be selected individually to have this wake-up
feature using an internal register known as PAWK or PCWK, located in the Data Memory.
PAWK, PAC~PCC, PAPU~PCPU Registers - HT48R064G
Register
Name
POR
Bit
7
6
5
4
3
2
1
0
PAWK
00H
PAWK7
PAWK6
PAWK5
PAWK4
PAWK3
PAWK2
PAWK1
PAWK0
PAC
FFH
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
PAPU
00H
¾
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
PBC
0FH
¾
¾
¾
¾
PBC3
PBC2
PBC1
PBC0
PBPU
00H
¾
¾
¾
¾
PBPU3
PBPU2
PBPU1
PBPU0
PCC
F3H
PCC7
PCC6
PCC5
PCC4
¾
¾
PCC1
PCC0
PCPU
00H
PCPU7
PCPU6
PCPU5
PCPU4
¾
¾
PCPU1
PCPU0
²¾² Unimplemented, read as ²0²
PAWKn: PA wake-up function enable
0: disable
1: enable
PACn/PBCn/PCCn: I/O type selection
0: output
1: input
PAPUn/PBPUn/PCPUn: Pull-high function enable
0: disable
1: enable
Rev. 1.00
49
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
PAWK, PAC~PCC, PAPU~PCPU Registers - HT48R065G
Register
Name
POR
Bit
7
6
5
4
3
2
1
0
PAWK0
PAWK
00H
PAWK7
PAWK6
PAWK5
PAWK4
PAWK3
PAWK2
PAWK1
PAC
FFH
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
PAPU
00H
¾
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
PBC
3FH
¾
¾
PBC5
PBC4
PBC3
PBC2
PBC1
PBC0
PBPU0
PBPU
00H
¾
¾
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
PCC
FFH
PCC7
PCC6
PCC5
PCC4
PCC3
PCC2
PCC1
PCC0
PCPU
00H
PCPU7
PCPU6
PCPU5
PCPU4
PCPU3
PCPU2
PCPU1
PCPU0
²¾² Unimplemented, read as ²0²
PAWKn: PA wake-up function enable
0: disable
1: enable
PACn/PBCn/PCCn: I/O type selection
0: output
1: input
PAPUn/PBPUn/PCPUn: Pull-high function enable
0: disable
1: enable
PAWK, PAC~PDC, PAPU~PDPU, PCWK Registers - HT48R066G
Register
Name
POR
Bit
7
6
5
4
3
2
1
0
PAWK0
PAWK
00H
PAWK7
PAWK6
PAWK5
PAWK4
PAWK3
PAWK2
PAWK1
PAC
FFH
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
PAPU
00H
¾
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
PBC
3FH
¾
¾
PBC5
PBC4
PBC3
PBC2
PBC1
PBC0
PBPU
00H
¾
¾
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
PBPU0
PCWK
00H
PCWK7
PCWK6
PCWK5
PCWK4
PCWK3
PCWK2
PCWK1
PCWK0
PCC
FFH
PCC7
PCC6
PCC5
PCC4
PCC3
PCC2
PCC1
PCC0
PCPU
00H
PCPU7
PCPU6
PCPU5
PCPU4
PCPU3
PCPU2
PCPU1
PCPU0
PDC
0FH
¾
¾
¾
¾
PDC3
PDC2
PDC1
PDC0
PDPU
00H
¾
¾
¾
¾
PDPU3
PDPU2
PDPU1
PDPU0
²¾² Unimplemented, read as ²0²
PAWKn, PCWKn: PA, PC wake-up function enable
0: disable
1: enable
PACn/PBCn/PCCn/PDCn: I/O type selection
0: output
1: input
PAPUn/PBPUn/PCPUn/PDPUn: Pull-high function enable
0: disable
1: enable
Rev. 1.00
50
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
PAWK, PCWK, PAC~PFC, PAPU~PFPU Registers - HT48R0662G
Register
Name
POR
Bit
7
6
5
4
3
2
1
0
PAWK0
PAWK
00H
PAWK7
PAWK6
PAWK5
PAWK4
PAWK3
PAWK2
PAWK1
PAC
FFH
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
PAPU
00H
¾
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
PBC
FFH
PBC7
PBC6
PBC5
PBC4
PBC3
PBC2
PBC1
PBC0
PBPU
00H
PBPU7
PBPU6
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
PBPU0
PCWK
00H
PCWK7
PCWK6
PCWK5
PCWK4
PCWK3
PCWK2
PCWK1
PCWK0
PCC
FFH
PCC7
PCC6
PCC5
PCC4
PCC3
PCC2
PCC1
PCC0
PCPU
00H
PCPU7
PCPU6
PCPU5
PCPU4
PCPU3
PCPU2
PCPU1
PCPU0
PDC
FFH
PDC7
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
PDPU
00H
PDPU7
PDPU6
PDPU5
PDPU4
PDPU3
PDPU2
PDPU1
PDPU0
PEC
FFH
PEC7
PEC6
PEC5
PEC4
PEC3
PEC2
PEC1
PEC0
PEPU
00H
PEPU7
PEPU6
PEPU5
PEPU4
PEPU3
PEPU2
PEPU1
PEPU0
PFC
03H
¾
¾
¾
¾
¾
¾
PFC1
PFC0
PFPU
00H
¾
¾
¾
¾
¾
¾
PFPU1
PFPU0
²¾² Unimplemented, read as ²0²
PAWKn/PCWKn: PA/PC wake-up function enable
0: disable
1: enable
PACn/PBCn/PCCn/PDCn/PECn/PFCn: I/O type selection
0: output
1: input
PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn: Pull-high function enable
0: disable
1: enable
I/O Port Control Registers
Each Port has its own control register, known as PAC, PBC, PCC, PDC, PEC, PFC which controls the
input/output configuration. With this control register, each I/O pin with or without pull-high resistors
can be reconfigured dynamically under software control. For the I/O pin to function as an input, the
corresponding bit of the control register must be written as a ²1². This will then allow the logic state of
the input pin to be directly read by instructions. When the corresponding bit of the control register is
written as a ²0², the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output,
instructions can still be used to read the output register. However, it should be noted that the program
will in fact only read the status of the output data latch and not the actual logic status of the output pin.
Rev. 1.00
51
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Pin-shared Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than
one function. Limited numbers of pins can force serious design constraints on designers but by
supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the
chosen function of the multi-function I/O pins is set by configuration options while for others the
function is set by application program control.
External Interrupt Input
The external interrupt pin, INT, is pin-shared with an I/O pin. To use the pin as an external interrupt
input the correct bits in the INTC register must be programmed. The pin must also be setup as an input
by setting the PAC3 bit in the Port Control Register. An internal pull-high resistor can be selected to be
connected to this pin by the corresponding pull-high function enable control bit. Note that even if the
pin is setup as an external interrupt input the I/O function still remains.
External Timer/Event Counter Input
The Timer/Event Counter pin TCn is pin-shared with I/O pins. For the shared pin to be used as the
Timer/Event Counter input, the Timer/Event Counter n must be configured to be in the Event Counter
or Pulse Width Capture Mode. This is achieved by setting the appropriate bits in the Timer/Event
Counter Control Register. The pins must also be setup as inputs by setting the appropriate bit in the
Port Control Register. Pull-high resistor function for the TCn pin can also be selected using the port
pull-high resistor register. Note that even if the pin is setup as an external timer input the I/O function
still remains.
PFD Output
The PFD function output is pin-shared with an I/O pin. The output function of this pin is chosen using
the CTRL0 register. Note that the corresponding bit of the port control register, must setup the pin
as an output to enable the PFD output. If the port control register has setup the pin as an input, then the
pin will function as a normal logic input with the usual pull-high selection, even if the PFD function
has been selected.
PWM Outputs
The PWM function whose outputs are pin-shared with I/O pins. The PWM output functions are chosen
using the CTRL0 register. Note that the corresponding bit of the port control registers, for the output
pin, must setup the pin as an output to enable the PWM output. If the pins are setup as inputs, then the
pin will function as a normal logic input with the usual pull-high selections, even if the PWM registers
have enabled the PWM function.
SCOM Driver Pins
Pins PB0~PB3 on Port B for the HT48R065G, HT48R066G and HT48R0662G devices can be used as
LCD COM driver pins. This function is controlled using the register which will generate the necessary
1/2 bias signals on these four pins.
Pin Remapping Configuration - HT48R0662G
The pin remapping function for the HT48R0662G device enables the function pins INT, TC0, TC1 and
PFD to be located on different port pins. It is important not to confuse the Pin Remapping function with
the Pin-shared function; these two functions have no interdependence.
The PCFG1 and PCFG0 bits in the CTRL2 register allow the four function pins INT, TC0, TC1 and
PFD to be remapped to different port pins. After power up, this bit will be reset to zero, which will
define the default port pins to which these functions will be mapped. Changing these bits will move the
functions to other port pins.
Rev. 1.00
52
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Examination of the pin names on the package diagrams will reveal that some pin function names are
repeated, this indicates a function pin that can be remapped to other port pins. If the pin name is
bracketed, then this indicates its alternative location. Pin name without brackets indicates its default
location which is the condition after Power-on.
PCFG [1:0] Bits Status
PCFG [1:0] Bit
00
01
10
11
Pin Mapping
PFD/PA1
TC0/PA2
INT/PA3
TC1/PA4
PFD/PC5
TC0/PC4
INT/PC3
TC1/PC2
PFD/PB0
TC0/PB1
INT/PB2
TC1/PB3
PFD/PE0
TC0/PE1
INT/PE2
TC1/PE3
Pin Remapping
I/O Pin Structures
The diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin
may differ from these drawings, they are supplied as a guide only to assist with the functional
understanding of the I/O pins.
Programming Considerations
Within the user program, one of the first things to consider is port initialisation. After a reset, the I/O
data register and I/O port control register will be set high. This means that all I/O pins will default to an
input state, the level of which depends on the other connected circuitry and whether pull-high options
have been selected. If the port control registers, are then programmed to setup some pins as outputs,
these output pins will have an initial high output value unless the associated port data register is first
programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by
loading the correct value into the port control register or by programming individual bits in the port
control register using the ²SET [m].i² and ²CLR [m].i² instructions. Note that when using these bit
control instructions, a read-modify-write operation takes place. The microcontroller must first read in
the data on the entire port, modify it to the required new bit values and then rewrite this data back to the
output ports.
T 1
S y s te m
T 2
T 3
T 4
T 1
T 2
T 3
T 4
C lo c k
P o rt D a ta
R e a d fro m
P o rt
W r ite to P o r t
Read Modify Write Timing
Pins on PA0 to PA7 for all the devices or PC0 to PC7 for only the HT48R0662G device each have a
wake-up function, selected via the PAWK or PCWK register. When the device is in the Idle/Sleep
Mode, various methods are available to wake the device up. One of these is a high to low transition of
any of these pins. Single or multiple pins on Port A or Port C can be setup to have this function.
Rev. 1.00
53
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
V
P u ll- H ig h
S e le c t
C o n tr o l B it
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
W e a k
P u ll- u p
Q
C K
S
C h ip R e s e t
I/O
R e a d C o n tr o l R e g is te r
p in
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
Q
S
M
R e a d D a ta R e g is te r
S y s te m
D D
U
X
W a k e - u p fu n c tio n p in o n ly
W a k e -u p
W a k e - u p S e le c t
Generic Input/Output Ports
C o n tr o l B it
Q
D
D a ta B u s
W r ite C o n tr o l R e g is te r
C K
Q
S
C h ip R e s e t
IO /R E S
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
S
Q
M
R e a d D a ta R e g is te r
S y s te m
U
X
W a k e -u p
W a k e - u p fu n c tio n
R E S
RES NMOS Input/Output Port
V
P u ll- H ig h
S e le c t
D a ta B u s
W r ite C o n tr o l R e g is te r
C o n tr o l B it
Q
D
D D
W e a k
P u ll- u p
Q
C K
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P B 0 /S C O M 0 ~
P B 3 /S C O M 3
P B 4 ~ P B 7
D a ta B it
Q
D
Q
C K
S
M
R e a d D a ta R e g is te r
U
X
V
D D
/2
C O M n E N
S C O M E N
PB Input/Output Port
Rev. 1.00
54
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Timer/Event Counters
The provision of timers form an important part of any microcontroller, giving the designer a means of
carrying out time related functions. The devices contain from one to three count-up timer of 8-bit
capacity. As the timers have three different operating modes, they can be configured to operate as a
general timer, an external event counter or as a pulse width capture device. The provision of an internal
prescaler to the clock circuitry on gives added range to the timers.
There are two types of registers related to the Timer/Event Counters. The first is the register that
contains the actual value of the timer and into which an initial value can be preloaded. Reading from
this register retrieves the contents of the Timer/Event Counter. The second type of associated register
is the Timer Control Register which defines the timer options and determines how the timer is to be
used. The device can have the timer clock configured to come from the internal clock source. In
addition, the timer clock source can also be configured to come from an external timer pin.
Configuring the Timer/Event Counter Input Clock Source
The Timer/Event Counter clock source can originate from various sources, an internal clock or an
external pin. The internal clock source is used when the timer is in the timer mode or in the pulse width
capture mode. For the Timer/Event Counter 0, this internal clock source is first divided by a prescaler,
the division ratio of which is conditioned by the Timer Control Register bits T0PSC0~T0PSC2. The
internal clock source can be derived from the system clock fSYS or the LXT oscillator for Timer/Event
Counter 0 or from the instruction clock fSYS/4 or the LXT oscillator for Timer/Event Counter 1 selected
by the clock selection bit TnS in the control register TMRnC.
An external clock source is used when the Timer/Event Counter is in the event counting mode, the
clock source being provided on an external timer pin TCn. Depending upon the condition of the TnEG
bit, each high to low, or low to high transition on the external timer pin will increment the counter by
one.
Timer Registers - TMR0, TMR1
The timer register is a special function register located in the Special Purpose Data Memory and is the
place where the actual timer value is stored and the register is known as TMRn. The value in the timer
register increases by one each time an internal clock pulse is received or an external transition occurs
on the external timer pin. The timer will count from the initial value loaded by the preload register to
the full count of FFH at which point the timer overflows and an internal interrupt signal is generated.
The timer value will be reset with the initial preload register value and continue counting.
To achieve a maximum full range count of FFH, the preload register must first be cleared to all zeros. It
should be noted that after power-on, the preload register will be in an unknown condition. Note that if
the Timer/Event Counter is switched off and data is written to its preload register, this data will be
immediately written into the actual timer register. However, if the Timer/Event Counter is enabled and
counting, any new data written into the preload data register during this period will remain in the
preload register and will only be written into the timer register the next time an overflow occurs.
Rev. 1.00
55
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
P W M
P W M C 0
P W M C 1
C o n tro l
P W M 0 , P W M 1
T im e - B a s e e v e n t in te r r u p t P e r io d
1
(2 10 ~ 2 13 ) *
fT P
T im e - B a s e C o n tr o l
T 0 S
fS
Y S
fL
X T
0
M U X
1
fT
T 0 P S C
[2 :0 ]
P
7 S ta g e C o u n te r
7
T o T im e r 0 in te r n a l c lo c k
(fT 0 C K = fT P ~ fT P /1 2 8 )
8 -1 M U X
7
T 2 P S C
T o T im e r 2 in te r n a l c lo c k
(fT 2 C K = fT P ~ fT P /1 2 8 )
8 -1 M U X
[2 :0 ]
T im e r P r e s c a le r
Clock Structure for Timer/PWM/Time Base
D a ta B u s
T 0 M 1 , T 0 M 0
T im e r 0 In te r n a l C lo c k
(fT P )
T C 0
C X
P r e lo a d R e g is te r
M o d e C o n tro l
T 0 O V
O v e r flo w
to In te rru p t
U p C o u n te r
M U X
T 0 O N
T 0 E G
T M R 0 S
¸
2
P F D 0
8-bit Timer/Event Counter 0 Structure
D a ta B u s
T 1 M 1 , T 1 M 0
fS Y S /4
L X T O s c illa to r
M
U
X
P r e lo a d R e g is te r
M o d e C o n tro l
T 1 O V
T 1 S
O v e r flo w
to In te rru p t
U p C o u n te r
T C 1
T 1 O N
T 1 E G
¸
2
P F D 1
8-bit Timer/Event Counter 1 Structure
P F D C S
P F D 0
0
P F D 1
1
M U X
P F D
o u tp u t
HT48R0662G PFD Clock Source
Note: If PWM0/PWM1 is enabled, then fTP comes from fSYS and the T0S bit will have no effect.
Rev. 1.00
56
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Timer Control Registers - TMR0C, TMR1C
The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in
three different modes, the options of which are determined by the contents of their respective control
register.
The Timer Control Register is known as TMRnC. It is the Timer Control Register together with its
corresponding timer register that control the full operation of the Timer/Event Counter. Before the
timer can be used, it is essential that the Timer Control Register is fully programmed with the right data
to ensure its correct operation, a process that is normally carried out during program initialisation.
To choose which of the three modes the timer is to operate in, either in the timer mode, the event
counting mode or the pulse width capture mode, bits 7 and 6 of the Timer Control Register, which are
known as the bit pair TnM1/TnM0, must be set to the required logic levels. The timer-on bit, which is
bit 4 of the Timer Control Register and known as TnON, provides the basic on/off control of the
respective timer. Setting the bit high allows the counter to run, clearing the bit stops the counter. Bits
0~2 of the Timer Control Register determine the division ratio of the input clock prescaler. The
prescaler bit settings have no effect if an external clock source is used. If the timer is in the event count
or pulse width capture mode, the active transition edge level type is selected by the logic level of bit 3
of the Timer Control Register which is known as TnEG. The TnS bit selects the internal clock source if
used.
TMR0C Register
Bit
7
6
5
4
3
2
1
0
Name
T0M1
T0M0
T0S
T0ON
T0EG
T0PSC2
T0PSC1
T0PSC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
1
0
0
0
Bit 7,6
Bit 5
Bit 4
Bit 3
Bit 2~0
Rev. 1.00
T0M1, T0M0: Timer0 operation mode selection
00: no mode available
01: event counter mode
10: timer mode
11: pulse width capture mode
T0S: timer clock source
0: fSYS
1: LXT oscillator
T0S selects the clock source for fTP which is provided for Timer 0, the Time-Base and
the PWM. If the PWM is enabled, then fSYS will be selected, overriding the T0S selection.
T0ON: Timer/event counter counting enable
0: disable
1: enable
T0EG:
Event counter active edge selection
0: count on raising edge
1: count on falling edge
Pulse Width Capture active edge selection
0: start counting on falling edge, stop on rasing edge
1: start counting on raising edge, stop on falling edge
T0PSC2, T0PSC1, T0PSC0: Timer prescaler rate selection
Timer internal clock=
000: fTP
001: fTP/2
010: fTP/4
011: fTP/8
100: fTP/16
101: fTP/32
110: fTP/64
111: fTP/128
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Enhanced I/O Type 8-Bit OTP MCU with OPA
TMR1C Register
Bit
7
6
5
4
3
2
1
0
Name
T1M1
T1M0
T1S
T1ON
T1EG
¾
¾
¾
R/W
R/W
R/W
R/W
R/W
R/W
¾
¾
¾
POR
0
0
0
0
1
¾
¾
¾
Bit 7,6
Bit 5
Bit 4
Bit 3
Bit 2~0
T1M1, T1M0: Timer 1 Operation mode selection
00: no mode available
01: event counter mode
10: timer mode
11: pulse width capture mode
T1S: timer clock source
0: fSYS/4
1: LXT oscillator
T1ON: Timer/event counter counting enable
0: disable
1: enable
T1EG:
Event counter active edge selection
0: count on raising edge
1: count on falling edge
Pulse Width Capture active edge selection
0: start counting on falling edge, stop on rasing edge
1: start counting on raising edge, stop on falling edge
unimplemented, read as ²0²
Timer Mode
In this mode, the Timer/Event Counter can be utilised to measure fixed time intervals, providing an
internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode, the
Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the correct
value as shown.
Control Register Operating Mode
Select Bits for the Timer Mode
Bit7
Bit6
1
0
In this mode the internal clock is used as the timer clock. The timer input clock source is fSYS, fSYS/4 or
the LXT oscillator depending upon whether the Timer/Event Counter 0 or Timer/Event Counter 1 is
selected. For Timer/Event Counter 0, the timer clock source is further divided by a prescaler, the value
of which is determined by the bits T0PSC2~T0PSC0 in the Timer Control Register TMR0C. The
timer-on bit, TnON must be set high to enable the timer to run. Each time an internal clock high to low
transition occurs, the timer increments by one; when the timer is full and overflows, an interrupt signal
is generated and the timer will reload the value already loaded into the preload register and continue
counting. A timer overflow condition and corresponding internal interrupt is one of the wake-up
sources, however, the internal interrupts can be disabled by ensuring that the TnE bits of the INTC0
register are reset to zero.
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N + 1
Timer Mode Timing Chart
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
Event Counter Mode
In this mode, a number of externally changing logic events, occurring on the external timer TCn pin,
can be recorded by the Timer/Event Counter. To operate in this mode, the Operating Mode Select bit
pair, TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown.
Control Register Operating Mode
Select Bits for the Event Counter Mode
Bit7
Bit6
0
1
In this mode, the external timer TCn pin, is used as the Timer/Event Counter clock source, however it
is not divided by the internal prescaler. After the other bits in the Timer Control Register have been
setup, the enable bit TnON, which is bit 4 of the Timer Control Register, can be set high to enable the
Timer/Event Counter to run. If the Active Edge Select bit, TnEG, which is bit 3 of the Timer Control
Register, is low, the Timer/Event Counter will increment each time the external timer pin receives a
low to high transition. If the TnEG is high, the counter will increment each time the external timer pin
receives a high to low transition. When it is full and overflows, an interrupt signal is generated and the
Timer/Event Counter will reload the value already loaded into the preload register and continue
counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit
in the corresponding Interrupt Control Register, is reset to zero.
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as an
event counter input pin, two things have to happen. The first is to ensure that the Operating Mode
Select bits in the Timer Control Register place the Timer/Event Counter in the Event Counting Mode,
the second is to ensure that the port control register configures the pin as an input. It should be noted
that in the event counting mode, even if the microcontroller is in the Idle/Sleep Mode, the Timer/Event
Counter will continue to record externally changing logic events on the timer input TCn pin. As a
result when the timer overflows it will generate a timer interrupt and corresponding wake-up source.
E x te rn a l E v e n t
In c re m e n t
T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Chart (TnEG=1)
Pulse Width Capture Mode
In this mode, the Timer/Event Counter can be utilised to measure the width of external pulses applied
to the external timer pin. To operate in this mode, the Operating Mode Select bit pair, TnM1/TnM0, in
the Timer Control Register must be set to the correct value as shown.
Control Register Operating Mode
Select Bits for the Pulse Width Capture Mode
Bit7
Bit6
1
1
In this mode the internal clock, fSYS, fSYS/4 or the LXT oscillator, is used as the internal clock
determined by which Timer/Event Counter is selected to be used. The internal clock source for the
Timer/Event Counter 0 is further divided by a prescaler, the value of which is determined by the
Prescaler Rate Select bits named T0PSC2~T0PSC0, which are bits 2~0 in the Timer Control Register.
After other bits in the Timer Control Register have been setup, the enable bit TnON, which is bit 4 of
the Timer Control Register, can be set high to enable the Timer/Event Counter, however it will not
actually start counting until an active edge is received on the external timer pin.
If the Active Edge Select bit TnEG, which is bit 3 of the Timer Control Register, is low, once a high to
low transition has been received on the external timer pin, the Timer/Event Counter will start counting
until the external timer pin returns to its original high level. At this point the enable bit will be
automatically reset to zero and the Timer/Event Counter will stop counting. If the Active Edge Select
bit is high, the Timer/Event Counter will begin counting once a low to high transition has been
received on the external timer pin and stop counting when the external timer pin returns to its original
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
low level. As before, the enable bit will be automatically reset to zero and the Timer/Event Counter
will stop counting. It is important to note that in the pulse width capture Mode, the enable bit is
automatically reset to zero when the external control signal on the external timer pin returns to its
original level, whereas in the other two modes the enable bit can only be reset to zero under program
control.
The residual value in the Timer/Event Counter, which can now be read by the program, therefore
represents the length of the pulse received on the TCn pin. As the enable bit has now been reset, any
further transitions on the external timer pin will be ignored. The timer cannot begin further pulse width
capture until the enable bit is set high again by the program. In this way, single shot pulse
measurements can be easily made.
It should be noted that in this mode the Timer/Event Counter is controlled by logical transitions on the
external timer pin and not by the logic level. When the Timer/Event Counter is full and overflows, an
interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the
preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event
Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is reset to zero.
As the TCn pin is shared with an I/O pin, to ensure that the pin is configured to operate as a pulse width
capture pin, two things have to happen. The first is to ensure that the Operating Mode Select bits in the
Timer Control Register place the Timer/Event Counter in the pulse width capture Mode, the second is
to ensure that the port control register configures the pin as an input.
E x te rn a l T C n
P in In p u t
T n O N
- w ith T n E G = 0
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o u n te r
+ 1
T im e r
+ 2
+ 3
+ 4
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Capture Mode Timing Chart (TnEG=0)
Prescaler
Bits T0PSC0~T0PSC2 of the TMR0C register can be used to define a division ratio for the internal
clock source of the Timer/Event Counter enabling longer time out periods to be setup.
PFD Function
The Programmable Frequency Divider provides a means of producing a variable frequency output
suitable for applications, such as piezo-buzzer driving or other interfaces requiring a precise frequency
generator.
The Timer/Event Counter overflow signal is the clock source for the PFD function, which is controlled
by PFDCS bit in CTRL0. For applicable devices the clock source can come from either Timer/Event
Counter 0 or Timer/Event Counter 1. The output frequency is controlled by loading the required values
into the timer prescaler and timer registers to give the required division ratio. The counter will begin to
count-up from this preload register value until full, at which point an overflow signal is generated,
causing both the PFD outputs to change state. The counter will then be automatically reloaded with the
preload register value and continue counting-up.
If the CTRL0 register has selected the PFD function, then for PFD output to operate, it is essential for
the corresponding Port control register, to setup the PFD pins as outputs. The corresponding I/O pin
data bit must be set high to activate the PFD. The output data bits can be used as the on/off control bit
for the PFD outputs. Note that the PFD outputs will all be low if the output data bit is cleared to zero.
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
Using this method of frequency generation, and if a crystal oscillator is used for the system clock, very
precise values of frequency can be generated.
T im e r O v e r flo w
P F D
I/O
P F D
C lo c k
P in D a ta
O u tp u t a t I/O
P in
PFD Function
I/O Interfacing
The Timer/Event Counter, when configured to run in the event counter or pulse width capture mode,
requires the use of an external timer pin for its operation. As this pin is a shared pin it must be configured
correctly to ensure that it is setup for use as a Timer/Event Counter input pin. This is achieved by
ensuring that the mode select bits in the Timer/Event Counter control register, select either the event
counter or pulse width capture mode. Additionally the corresponding Port Control Register bit must be
set high to ensure that the pin is setup as an input. Any pull-high resistor connected to this pin will remain
valid even if the pin is used as a Timer/Event Counter input.
Programming Considerations
When configured to run in the timer mode, the internal system clock is used as the timer clock source and
is therefore synchronised with the overall operation of the microcontroller. In this mode when the
appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing
the program flow to the respective internal interrupt vector. For the pulse width capture mode, the
internal system clock is also used as the timer clock source but the timer will only run when the correct
logic condition appears on the external timer input pin. As this is an external event and not synchronised
with the internal timer clock, the microcontroller will only see this external event when the next timer
clock pulse arrives. As a result, there may be small differences in measured values requiring
programmers to take this into account during programming. The same applies if the timer is configured
to be in the event counting mode, which again is an external event and not synchronised with the internal
system or timer clock.
When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to
avoid errors, however as this may result in a counting error, this should be taken into account by the
programmer. Care must be taken to ensure that the timers are properly initialised before using them for
the first time. The associated timer enable bits in the interrupt control register must be properly set
otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer
mode and clock source control bits in timer control register must also be correctly set to ensure the timer
is properly configured for the required application. It is also important to ensure that an initial value is
first loaded into the timer registers before the timer is switched on; this is because after power-on the
initial values of the timer registers are unknown. After the timer has been initialised the timer can be
turned on and off by controlling the enable bit in the timer control register.
When the Timer/Event Counter overflows, its corresponding interrupt request flag in the interrupt
control register will be set. If the Timer/Event Counter interrupt is enabled this will in turn generate an
interrupt signal. However irrespective of whether the interrupts are enabled or not, a Timer/Event
Counter overflow will also generate a wake-up signal if the device is in a Power-down condition. This
situation may occur if the Timer/Event Counter is in the Event Counting Mode and if the external
signal continues to change state. In such a case, the Timer/Event Counter will continue to count these
external events and if an overflow occurs the device will be woken up from its Power-down condition.
To prevent such a wake-up from occurring, the timer interrupt request flag should first be set high
before issuing the ²HALT² instruction to enter the Idle/Sleep Mode.
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
Timer Program Example
The program shows how the Timer/Event Counter registers are setup along with how the interrupts are
enabled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the Timer
Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the same bit.
This example program sets the Timer/Event Counters to be in the timer mode, which uses the internal
system clock as their clock source.
Timer Programming Example
org
04h
; external interrupt vector
org
08h
; Timer Counter 0 interrupt vector
jmp
tmr0int
; jump here when Timer 0 overflows
:
:
org
20h
; main program
:
:
;internal Timer 0 interrupt routine
tmr0int:
:
; Timer 0 main program placed here
:
:
begin:
;setup Timer 0 registers
mov
a,09bh
mov
tmr0,a
mov
a,081h
mov
tmr0c,a
;setup interrupt register
mov
a,00dh
mov
intc0,a
:
:
set tmr0c.4
:
:
; setup Timer 0 preload value
; setup Timer 0 control register
; timer mode and prescaler set to /2
; enable master interrupt and both timer interrupts
; start Timer 0
Time Base
The device includes a Time Base function which is used to generate a regular time interval signal.
The Time Base time interval magnitude is determined using an internal 13 stage counter sets the
division ratio of the clock source. This division ratio is controlled by both the TBSEL0 and TBSEL1
bits in the CTRL1 register. The clock source is selected using the T0S bit in the TMR0C register.
When the Time Base time out, a Time Base interrupt signal will be generated. It should be noted that as
the Time Base clock source is the same as the Timer/Event Counter clock source, care should be taken
when programming.
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
Pulse Width Modulator
The series of devices includes up to 2 8-bit PWM outputs. Useful for the applications such as motor
speed control, the PWM function provides outputs with a fixed frequency but with a duty cycle that
can be varied by setting particular values into the corresponding PWM register.
P W M 0 R e g is te r
P M W 0
8 - b it C o m p a r a to r 0
P W M 1 R e g is te r
8 - b it C o m p a r a to r 1
P M W 1
8 - b it/( 7 + 1 ) /( 6 + 2 )
P W M C o u n te r
PWM Block Diagram
Device
Channels
Mode
Pins
Registers
HT48R0662G
2
6+2
7+1
PD0
PD1
PWM0
PWM1
PWM Operation
The register, known as PWMn and located in the Data Memory, is assigned to each Pulse Width
Modulator channel. It is here that the 8-bit value, which represents the overall duty cycle of one
modulation cycle of the output waveform, should be placed. To increase the PWM modulation
frequency, each modulation cycle is subdivided into two or four individual modulation subsections,
known as the 7+1 mode or 6+2 mode respectively. The required mode and the on/off control for each
PWM channel is selected using the CTRL0 register. Note that when using the PWM, it is only
necessary to write the required value into the PWMn register and select the required mode setup and
on/off control using the CTRL0 register, the subdivision of the waveform into its sub-modulation
cycles is implemented automatically within the microcontroller hardware. The PWM clock source is
the system clock fSYS. This method of dividing the original modulation cycle into a further 2 or 4
sub-cycles enable the generation of higher PWM frequencies which allow a wider range of
applications to be served. The difference between what is known as the PWM cycle frequency and the
PWM modulation frequency should be understood. As the PWM clock is the system clock, fSYS, and as
the PWM value is 8-bits wide, the overall PWM cycle frequency is fSYS/256. However, when in the 7+1
mode of operation the PWM modulation frequency will be fSYS/128, while the PWM modulation
frequency for the 6+2 mode of operation will be fSYS/64.
PWM Modulation
fSYS/64 for (6+2) bits mode
fSYS/128for (7+1) bits mode
Rev. 1.00
63
PWM Cycle Frequency
PWM Cycle Duty
fSYS/256
[PWM]/256
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HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
6+2 PWM Mode
Each full PWM cycle, as it is controlled by an 8-bit PWM register, has 256 clock periods. However, in
the 6+2 PWM mode, each PWM cycle is subdivided into four individual sub-cycles known as
modulation cycle 0 ~ modulation cycle 3, denoted as i in the table. Each one of these four sub-cycles
contains 64 clock cycles. In this mode, a modulation frequency increase of four is achieved. The 8-bit
PWM register value, which represents the overall duty cycle of the PWM waveform, is divided into
two groups. The first group which consists of bit2~bit7 is denoted here as the DC value. The second
group which consists of bit0~bit1 is known as the AC value. In the 6+2 PWM mode, the duty cycle
value of each of the four modulation sub-cycles is shown in the following table.
Parameter
AC (0~3)
DC (Duty Cycle)
i<AC
DC+1
64
i³AC
DC
64
Modulation cycle i
(i=0~3)
6+2 Mode Modulation Cycle Values
The following diagram illustrates the waveforms associated with the 6+2 mode of PWM operation.
It is important to note how the single PWM cycle is subdivided into 4 individual modulation cycles,
numbered from 0~3 and how the AC value is related to the PWM value.
fS
Y S
/2
[P W M ] = 1 0 0
P W M
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 6 /6 4
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
P W M
m o d u la tio n p e r io d : 6 4 /fS
M o d u la tio n c y c le 0
Y S
M o d u la tio n c y c le 1
P W M
M o d u la tio n c y c le 2
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 3
M o d u la tio n c y c le 0
Y S
6+2 PWM Mode
b 7
b 0
P W M
R e g is te r
A C
v a lu e
D C
v a lu e
(6 + 2 ) M o d e
PWM Register for 6+2 Mode
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
7+1 PWM Mode
Each full PWM cycle, as it is controlled by an 8-bit PWM register, has 256 clock periods. However, in
the 7+1 PWM mode, each PWM cycle is subdivided into two individual sub-cycles known as
modulation cycle 0 ~ modulation cycle 1, denoted as i in the table. Each one of these two sub-cycles
contains 128 clock cycles. In this mode, a modulation frequency increase of two is achieved. The 8-bit
PWM register value, which represents the overall duty cycle of the PWM waveform, is divided into two
groups. The first group which consists of bit1~bit7 is denoted here as the DC value. The second group
which consists of bit0 is known as the AC value. In the 7+1 PWM mode, the duty cycle value of each of
the two modulation sub-cycles is shown in the following table.
Parameter
AC (0~1)
DC (Duty Cycle)
i<AC
DC+1
128
i³AC
DC
128
Modulation cycle i
(i=0~1)
7+1 Mode Modulation Cycle Values
The following diagram illustrates the waveforms associated with the 7+1 mode PWM operation. It is
important to note how the single PWM cycle is subdivided into 2 individual modulation cycles,
numbered 0 and 1 and how the AC value is related to the PWM value.
fS
Y S
/2
[P W M ] = 1 0 0
P W M
5 0 /1 2 8
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
5 2 /1 2 8
P W M
m o d u la tio n p e r io d : 1 2 8 /fS
Y S
M o d u la tio n c y c le 0
M o d u la tio n c y c le 1
P W M
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 0
Y S
7+1 PWM Mode
b 7
b 0
P W M
R e g is te r
A C
v a lu e
D C
v a lu e
(7 + 1 ) M o d e
PWM Register for 7+1 Mode
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
PWM Output Control
The PWM outputs are pin-shared with the I/O pins PA4, PD0 and PD3 respectively depending upon
the selected device. To operate as a PWM output and not as an I/O pin, the correct bits must be set in
the CTRL0 register. A zero value must also be written to the corresponding I/O Port Control bit to
ensure that the corresponding PWM output pin is setup as an output. After these two initial steps have
been carried out, and of course after the required PWM value has been written into the PWMn register,
writing a high value to the corresponding I/O Output Data bit will enable the PWM data to appear on
the pin. Writing a zero value will disable the PWM output function and force the output low. In this
way, the Port data output registers can be used as an on/off control for the PWM function. Note that if
the CTRL0 register has selected the PWM function, but a high value has been written to its
corresponding I/O Port Control bit to configure the pin as an input, then the pin can still function as a
normal input line, with pull-high resistor options.
PWM Programming Example
The following sample program shows how the PWM0 output is setup and controlled.
mov
mov
set
set
clr
set
:
clr
Rev. 1.00
a,64h
pwm0,a
ctrl0.5
ctrl0.3
pac.7
pa.7
:
pa.7
; setup PWM value of decimal 100
; select the 7+1 PWM mode
; select pin PA7 to have a PWM function
; setup pin PA7 as an output
; enable the PWM output
; disable the PWM output_ pin
; PA7 forced low
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Operational Amplifiers
There are two fully integrated Operational Amplifiers in these devices, OPA0 and OPA1. These OPAs
can be used for user specified analog signal processing. The OPAs can be disabled or enabled entirely
under software control using internal registers. With specific control registers, some OPA related
applications can be easily implemented, such as Unity Gain Buffer, Non-Inverting Amplifier,
Inverting Amplifier and various kinds of filters, etc.
Comparator & Operational Amplifier Registers
The internal Operational Amplifiers are fully under the control of internal registers, COPA0C,
COPA1C, COPA2C, COPA3C, OPA0OC and OPA1OC. These registers control the enable/disable
function, input path selection, gain control, polarity and calibration function.
Operational Amplifier Operation
The advantages of multiple switches and input path options, various reference voltage selection, up to 8
kinds of internal software gain control, output with interrupt function, offset reference voltage calibration
function and power down control for low power consumption enhance the flexibility of these two OPAs
to suit a wide range of application possibilities.
Note that the EA0I, EA1I interrupt control bits should be set to ²0² before entering halt mode for
power saving.
The following block diagram illustrates the main functional blocks of the OPAs and Comparator in this
device.
S12
EA0I
S11
A0N
A0X
A0
To OPA0 interrupt
A0P
0.7VDD
0.5VDD
0.1VDD
MUX
S13
A0PS[2:0]
MA0P
A0X
A1NS[1:0]
S21
MUX
A1N
MA1N
R1
10K
S22
R2
S23
500K
EA1I
A1
A1P
0.7VDD
0.5VDD
0.1VDD
A1X
To OPA1 interrupt
MA1P
MUX
CINTS[1:0]
A1PS[2:0]
S24
=00: rasing edge
=01: falling edge
=10: both edge
Edge
control
CNS[1:0]
to interrupt
A1X
MUX
MCN
POL
TC0 pin
CN
mux
C
CP
0.7VDD
0.5VDD
0.1VDD
debounce
CX
(COUT)
MCP
To timer 0 external
clock input
TMR0S
MUX
CPS[2:0]
CX
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
COPA0C Register
Bit
7
6
5
4
3
2
1
0
Name
A0PS2
A0PS1
A0PS0
CPS2
CPS1
CPS0
CNS1
CNS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~5
A0PS2~A0PS0: OPA0 Non-inverting input signal selection bits
000: A0P pin
001: 0.7VDD
010: 0.5VDD
011: 0.1VDD
100: VSS
101~111: undefined
CPS2~CPS0: Comparator Non-inverting input signal selection bits
000: CP pin
001: 0.7VDD
010: 0.5VDD
011: 0.1VDD
100: VSS
101~111: undefined
CNS1~CNS0: Comparator Inverting input signal selection bits
00: CN pin
01: A1X
10: VSS
11: undefined
Bit 4~2
Bit 1~0
COPA1C Register
Bit
7
6
5
4
3
2
1
0
Name
A1G2
A1G1
A1G0
A1PS2
A1PS1
A1PS0
A1NS1
A1NS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~5
Bit 4~2
Bit 1~0
Rev. 1.00
A1G2~A1G0: OPA1 Gain control bits
000: 6.25
001: 12.50
010: 18.75
011: 25.00
100: 31.25
101: 37.50
110: 43.75
111: 50.00
A1PS2~A1PS0: OPA1 Non-inverting input signal selection bits
000: A1P pin
001: 0.7VDD
010: 0.5VDD
011: 0.1VDD
100: VSS
101: A0X, the OPA0 internal output
110~111: undefined
A1NS1~A1NS0: OPA1 Inverting input signal selection bits
00: A1N pin
01: A0X, the OPA0 internal output
10: VSS
11: undefined
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COPA2C Register
Bit
7
6
5
4
3
2
1
0
Name
S24
S23
S22
S21
S13
S12
S11
CXC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
S24: Switch S24 on/off control bit
0: Off
1: On
S23: Switch S23 on/off control bit
0: Off
1: On
S22: Switch S22 on/off control bit
0: Off
1: On
S21: Switch S21 on/off control bit
0: Off
1: On
S13: Switch S13 on/off control bit
0: Off
1: On
S12: Switch S12 on/off control bit
0: Off
1: On
S11: Switch S11 on/off control bit
0: Off
1: On
CXC: Comparator output pin CX enable control bit
0: I/O pin or other pin-shared functional pin
1: CX output pin (I/O pull-high disabled)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
COPA3C Register
Bit
7
6
5
4
3
2
1
0
Name
A1XC
A1PC
A1NC
A0XC
A0PC
A0NC
CPC
CNC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
A1XC: OPA1 output pin A1X enable control bit
0: I/O pin or other pin-shared functional pin
1: A1X output pin (I/O pull-high disabled)
A1PC: OPA1 non-inverting input pin A1P enable control bit
0: I/O pin or other pin-shared functional pin
1: A1P input pin (I/O pull-high disabled)
A1NC: OPA1 inverting input pin A1N enable control bit
0: I/O pin or other pin-shared functional pin
1: A1N input pin (I/O pull-high disabled)
A0XC: OPA0 output pin A0X enable control bit
0: I/O pin or other pin-shared functional pin
1: A0X output pin (I/O pull-high disabled)
Bit 3
A0PC: OPA0 non-inverting input pin A0P enable control bit
0: I/O pin or other pin-shared functional pin
1: A0P input pin (I/O pull-high disabled)
Bit 2
A0NC: OPA0 inverting input pin A0N enable control bit
0: I/O pin or other pin-shared functional pin
1: A0N input pin (I/O pull-high disabled)
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
Bit 1
CPC: Comparator non-inverting input pin CP enable control bit
0: I/O pin or other pin-shared functional pin
1: CP input pin (I/O pull-high disabled)
CNC: Comparator inverting input pin CN enable control bit
0: I/O pin or other pin-shared functional pin
1: CN input pin (I/O pull-high disabled)
Bit 0
OPA0OC Register
Bit
7
6
5
4
3
2
1
0
Name
A0EN
A0OP
A0OFM
A0RS
A0OF3
A0OF2
A0OF1
A0OF0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
A0EN: Operational Amplifier 0 enable control bit
0: disable
1: enable
A0OP: Operational Amplifier 0 output; positive logic. This bit is read only bit.
Bit 6
Bit 5
A0OFM: Operational Amplifier 0 normal mode or input offset voltage cancellation mode
selection bit
0: Operational Amplifier 0 normal mode
1: input offset voltage cancellation mode
A0RS: Operational Amplifier 0 input offset voltage cancellation reference input selection bit
0: Operational Amplifier A0N as the reference input
1: Operational Amplifier A0P as the reference input
A0OF3~A0OF0: Operational Amplifier 0 input offset voltage cancellation control bits
Bit 4
Bit 3~0
OPA1OC Register
Bit
7
6
5
4
3
2
1
0
Name
A1EN
A1OP
A1OFM
A1RS
A1OF3
A1OF2
A1OF1
A1OF0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3~0
Rev. 1.00
A1EN: Operational Amplifier 1 enable control bit
0: disable
1: enable
A1OP: Operational Amplifier 1 output; positive logic. This bit is read only bit.
A1OFM: Operational Amplifier 1 normal mode or input offset voltage cancellation mode
selection bit
0: Operational Amplifier 1 normal mode
1: input offset voltage cancellation mode
A1RS: Operational Amplifier 1 input offset voltage cancellation reference input selection bit
0: Operational Amplifier A1N as the reference input
1: Operational Amplifier A1P as the reference input
A1OF3~A1OF0: Operational Amplifier 1 input offset voltage cancellation control bits
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Enhanced I/O Type 8-Bit OTP MCU with OPA
Operational Amplifier Application Example
The OPAs can be connected to work with each other or standalone as shown in the block diagram.
With the software controlled Switch and MUX, the OPAs can be connected to form various OPA
related applications, such as, Unity Gain Buffer, Non-Inverting Amplifier, Inverting Amplifier,
Integrators, Differential Amplifier, Low-Pass filter, High-Pass filter and Band-Pass filter,etc. The
following diagrams show the interconnection and settings between the OPAs to implement these
applications. The following examples are however only for reference.
Unity Gain Buffer
·
Example
A 0
V IN
·
V O U T
Implementation connection
S 1 2 O N
S 1 1 O F F
A 0 N
0 .7 V
0 .5 V
0 .1 V
D D
M A 0 P
D D
M U X
D D
A 0 P S 2 ~ A 0 P S 0
A 0 X
·
T o O P A 0 In te rru p t o r
C o m p a ra to r In p u t
A 0
A 0 P
S 1 3 O N
Unity Gain Buffer Switch Setup
Bit
7
6
5
4
3
2
1
0
OPA2C
S24
S23
S22
S21
S13
S12
S11
CXC
Setup value
x
x
x
x
1
1
0
x
²x² don¢t care
Bit
7
6
5
4
3
2
1
0
OPA0C
A0PS2
A0PS1
A0PS0
CPS2
CPS1
CPS0
CNS1
CNS0
Setup value
0
0
0
0
0
0
0
0
Switch control bits options:
S11: OFF
S12: ON
S13: ON
A0PS[2:0]: 000
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
Non-Inverting Amplifier
·
Example
R 2
R 1
·
Implementation connection
R 1
S 1 2 O F F
S 1 1 O N
A 0 N
0 .7 V
0 .5 V
0 .1 V
R 2
T o O P A 0 In te rru p t o r
C o m p a ra to r In p u t
A 0
A 0 P
V IN
·
V O U T
A 0
V IN
D D
M A 0 P
D D
M U X
D D
A 0 P S 2 ~ A 0 P S 0
A 0 X
S 1 3 O N
Non-Inverting Amplifier Switch Setup
Bit
7
6
5
4
3
2
1
0
OPA2C
S24
S23
S22
S21
S13
S12
S11
CXC
Setup value
x
x
x
x
1
0
1
x
²x² don¢t care
Bit
7
6
5
4
3
2
1
0
OPA0C
A0PS2
A0PS1
A0PS0
CPS2
CPS1
CPS0
CNS1
CNS0
Setup value
0
0
0
0
0
0
0
0
Switch control bits options:
S11: ON
S12: OFF
S13: ON
A0PS[2:0]: 000
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
Inverting Amplifier
·
Example
V IN
·
R 2
R 1
A 0
Implementation connection
V IN
R 1
R 2
S 1 2 O F F
S 1 1 O N
A 0 N
A 0 P
0 .7 V D D
0 .5 V D D
0 .1 V D D
·
V O U T
T o O P A 0 In te rru p t o r
C o m p a ra to r In p u t
A 0
M U X
M A 0 P
A 0 P S 2 ~ A 0 P S 0
A 0 X
S 1 3 O N
Inverting Amplifier Switch Setup
Bit
7
6
5
4
3
2
1
0
OPA2C
S24
S23
S22
S21
S13
S12
S11
CXC
Setup value
x
x
x
x
1
0
1
x
²x² don¢t care
Bit
7
6
5
4
3
2
1
0
OPA0C
A0PS2
A0PS1
A0PS0
CPS2
CPS1
CPS0
CNS1
CNS0
Setup value
1
0
0
0
0
0
0
0
Switch control bits options:
S11: ON
S12: OFF
S13: ON
A0PS[2:0]: 100
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
Two-Stage Non-Inverting Amplifier
·
Example
R 1
R 2
V O U T
A 0
R 3
R 4
A 0
V IN
·
Implementation connection
R3
A0N
EA0I
S12 OFF
S11 ON
A0X
VIN
A0
A0P
0.7VDD
0.5VDD
0.1VDD
R4
A0X
To OPA0 Interrupt
or Comparator input
MA0P
MUX
A0PS[2:0]
S13 ON
A1NS[1:0]
S21 OFF
MUX MA1N
A1N
R1
10K
S23
ON
EA1I
A1
0.7VDD
0.5VDD
0.1VDD
·
R2
500K
A1X
A1P
A1X
S22 OFF
To OPA1 Interrupt
or Comparator input
MA1P
MUX
A1PS[2:0]
S24 ON
Two-Stage Non-Inverting Amplifier Switch Setup
Bit
7
6
5
4
3
2
1
0
OPA2C
S24
S23
S22
S21
S13
S12
S11
CXC
Setup value
1
1
0
0
1
0
1
x
²x² don¢t care
Bit
7
6
5
4
3
2
1
0
OPA0C
A0PS2
A0PS1
A0PS0
CPS2
CPS1
CPS0
CNS1
CNS0
Setup value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
OPA1C
A1G2
A1G1
A1G0
A1PS2
A1PS1
A1PS0
A1NS1
A1NS0
Setup value
0
0
0
1
0
1
1
0
Switch control bits options:
S11: ON
S12: OFF
S13: ON
S21: OFF
S22: OFF
S23: ON
S24: ON
A0PS[2:0]: 000
A1PS[2:0]: 101
A1NS[1:0]: 10
A1G[2:0]: User define OPA1 Gain control
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
Two-Stage Inverting Amplifier
·
Example
V IN
R 3
R 1
R 4
R 2
A 0
·
Implementation connection
EA0I
S12 OFF
R3
VIN
V O U T
A 0
A0N
S11 ON
A0X
A0
A0P
0.7VDD
0.5VDD
0.1VDD
R4
A0X
S13 ON
To OPA0 Interrupt
or Comparator input
MUX MA0P
A0PS[2:0]
A1NS[1:0]
A1N
S21 OFF
S22 OFF
R1
10K
R2
500K
MA1N
MUX
S23
ON
EA1I
A1X
A1P
MUX
MA1P
A1PS[2:0]
A1X
·
To OPA1 Interrupt
or Comparator input
A1
0.7VDD
0.5VDD
0.1VDD
S24 ON
Two-Stage Inverting Amplifier Switch Setup
Bit
7
6
5
4
3
2
1
0
OPA2C
S24
S23
S22
S21
S13
S12
S11
CXC
Setup value
1
1
0
0
1
0
1
x
²x² don¢t care
Bit
7
6
5
4
3
2
1
0
OPA0C
A0PS2
A0PS1
A0PS0
CPS2
CPS1
CPS0
CNS1
CNS0
Setup value
1
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
OPA1C
A1G2
A1G1
A1G0
A1PS2
A1PS1
A1PS0
A1NS1
A1NS0
Setup value
0
0
0
1
0
0
0
1
Switch control bits options:
S11: ON
S12: OFF
S13: ON
S21: OFF
S22: OFF
S23: ON
S24: ON
A0PS[2:0]: 100
A1PS[2:0]: 100
A1NS[1:0]: 01
A1G[2:0]: User define OPA1 Gain control
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
Integrator
·
Example
V IN
R 1
C
V O U T
A 0
·
Implementation connection
A1NS[1:0]
S21 ON
VIN
A1N
R1
MA1N
MUX
10K
0.7VDD
0.5VDD
0.1VDD
500K
A1
A1P
C
S22 OFF
A0X
MUX
S23
OFF
EA1I
A1X
To OPA1 Interrupt
or Comparator input
MA1P
A1PS[2:0]
A1X
·
S24 ON
Integrator Switch Setup
Bit
7
6
5
4
3
2
1
0
OPA2C
S24
S23
S22
S21
S13
S12
S11
CXC
Setup value
1
0
0
1
x
x
x
x
²x² don¢t care
Bit
7
6
5
4
3
2
1
0
OPA0C
A0PS2
A0PS1
A0PS0
CPS2
CPS1
CPS0
CNS1
CNS0
Setup value
0
0
0
1
0
0
0
0
Switch control bits options:
S21: ON
S22: OFF
S23: OFF
S24: ON
A1PS[2:0]: 100
A1NS[1:0]: 00
A1G[2:0]: User define OPA1 Gain control
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
Low Pass Filter
·
Example
C
V IN
R 1
R 2
V O U T
A 0
·
VIN
Implementation connection
R1
A0N
S12 OFF
S11 ON
A0
To OPA0 Interrupt
or Comparator input
MUX MA0P
0.7VDD
0.5VDD
0.1VDD
A0PS[2:0]
R2
A0X
S13 ON
C
·
Low Pass Filter Switch Setup
Bit
7
6
5
4
3
2
1
0
OPA2C
S24
S23
S22
S21
S13
S12
S11
CXC
Setup value
x
x
x
x
1
0
1
x
²x² don¢t care
Bit
7
6
5
4
3
2
1
0
OPA0C
A0PS2
A0PS1
A0PS0
CPS2
CPS1
CPS0
CNS1
CNS0
Setup value
1
0
0
0
0
0
0
0
Switch control bits options:
S11: ON
S12: OFF
S13: ON
A0PS[2:0]: 100
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
Operational Amplifier Offset Cancellation Function
Each of the internal OPAs allows for a common mode adjustment method of its input offset voltage.
A0RS
A0OFM
S1A
S2A
S3A
0
0
ON
ON
OFF
0
1
OFF
ON
ON
1
0
ON
ON
OFF
1
1
ON
OFF
ON
S 1 A
A 0 P
A 0 O P
S 3 A
S 2 A
A 0 N
A 0 O F 0 ~ A 0 O F 3
A 0 E N
A 0 X
A1RS
A1OFM
S1B
S2B
S3B
0
0
ON
ON
OFF
0
1
OFF
ON
ON
1
0
ON
ON
OFF
1
1
ON
OFF
ON
S 1 B
A 1 P
A 1 N
S 2 B
1 .5 k W
A 1 O P
S 3 B
A 1 O F 0 ~ A 1 O F 3
A 1 E N
A 1 X
The calibration steps are as following:
1. Set A0OFM=1 to setup the offset cancellation mode, here S3A is closed.
2. Set A0RS to select which input pin is to be used as the reference voltage - S1 or S2 is closed
3. Adjust A0OF0~A0OF3 until the output status changes
4. Set A0OFM = 0 to restore the normal OPA mode
5. Repeat the same procedure from steps 1 to 4 for OPA1.
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
Comparator
These devices contain a fully integrated Comparator whose operation is controlled by the Comparator
control registers, known as the CMP0C, CMP1C, COPA0C, COPA2C and COPA3C registers. The
CEN bit within CMP0C register is used as the enable or disable bit for the comparator function. The
advantages of multiple input resources, multiple reference voltage options, output polarity control,
output to Timer counter, multiple output interrupt triggers, comparator output wakeup MCU function,
comparator output with de-bounce options, comparator operating current selection and power down
control for low power consumption enhance the flexibility of this comparator to suit a wide range of
application possibilities.
Comparator Functions
The Comparator can work with OPAs or standalone as shown in the main functional blocks of the OPAs
and Comparator in this device. This comparator provides three operating current options, which are
200mA, 5mA and 1mA. The purpose of this design is to provide the suitable comparator power
consumption for different operating modes of the device. The higher the operating current, the shorter the
comparator response time, therefore, the designer can select the higher operating current for the device
working at normal mode and a lower one for the device entering power down mode. By this way, this
comparator can operate under very low power consumption and perform as a wakeup resource when the
device enters power down mode. In addition, this device provides different comparator output de-bounce
time options for different input signal. If the input signal is noise sensitive, then the better choice will be
the longer de-bounce time. The designer could select the suitable de-bounce time according to the input
signal.
CMP0C Register
Bit
7
6
5
4
3
2
1
0
Name
¾
CEN
CPOL
COUT
DBC1
DBC0
CPCS1
CPCS0
R/W
¾
R/W
R/W
R
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3~2
Bit 1~0
Rev. 1.00
unimplemented, read as ²0²
CEN: comparator on/off bit
0: off
1: on
Note that the designer should enable the comparator first before enabling the comparator
interrupt, in order to prevent an unexpected interrupt.
CPOL: comparator output polarity control bit
0: not inverted
1: inverted
COUT: comparator output bit.
CPOL=0: If the CP pin input voltage is less than CN pin, then the COUT is ²0².
If the CP pin input voltage is greater than CN pin, then the COUT is ²1².
CPOL=1: If the CP pin input voltage is less than CN pin, then the COUT is ²1².
If the CP pin input voltage is greater than CN pin, then the COUT is ²0².
DBC1, DBC0: De-bounce time selection, up to application signal
00: no de-bounce
01: de-bounce time= 1 system clock
10: de-bounce time= 4 system clock
11: de-bounce time= 16 system clock
CPCS1, CPCS0]: Comparator operating current selection for low power consumption
00: 200mA
01: 5mA
10: 1mA
11: not implemented
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Enhanced I/O Type 8-Bit OTP MCU with OPA
CMP1C Register
Bit
7
6
5
4
3
2
1
0
Name
A0VRC
A1VRC
CPVRC
¾
TMR0S
¾
CINTS1
CINTS0
R/W
R/W
R/W
R/W
¾
R/W
¾
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit7
Bit6
A0VRC: OPA0 non-inverting input connection control bit
0: connected to internal reference voltage only
1: connected to both internal reference voltage and external I/O (A0P) pin
A1VRC: OPA1 non-inverting input connection control bit
0: connected to internal reference voltage only
1: connected to both internal reference voltage and external I/O (A1P) pin
Bit5
CPVRC: Comparator non-inverting input connection control bit
0: connected to internal reference voltage only
1: connected to both internal reference voltage and external I/O (CP) pin
Note that the above setting of these three bits, which are A0VRC, A1VRC and CPVRC, is valid
when the non inverting input pins are selected to be connected to the internal reference voltage
by A0PS[2:0],A1PS[2:0] and CPS[2:0] control bits respectively.
Bit 4, 2
unimplemented, read as ²0²
Bit 3
TMR0S: signal input path selection for Timer 0 Event counter
0: from TC0 pin
1: from comparator output
CINTS1, CINTS0: comparator interrupt trigger type selection
00: falling edge
01: rising edge
10: both edge
11: reserved
Bit 1~0
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an internal
function such as a Timer/Event Counter or Time Base requires microcontroller attention, their
corresponding interrupt will enforce a temporary suspension of the main program allowing the
microcontroller to direct attention to their respective needs.
The devices contain a single external interrupt and multiple internal interrupts. The external interrupt
is controlled by the action of the external interrupt pin, while the internal interrupts are controlled by
the various functions such as Timer/Event Counters and Time Base overflow, etc.
Interrupt Register
Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by
using the registers, INTC0 and INTC1. By controlling the appropriate enable bits in the registers each
individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding
request flag will be set by the microcontroller. The global enable control bit if cleared to zero will
disable all interrupts.
INTC0 Register - HT48R064G
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
T0F
INTF
¾
T0E
INTE
EMI
R/W
¾
¾
R/W
R/W
¾
R/W
R/W
R/W
POR
¾
¾
0
0
¾
0
0
0
Bit 7~6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
unimplemented, read as ²0²
T0F: Timer/Event Counter 0 interrupt request flag
0: inactive
1: active
INTF: External interrupt request flag
0: inactive
1: active
unimplemented, read as ²0²
T0E: Timer/Event Counter 0 interrupt enable
0: disable
1: enable
INTE: external interrupt enable
0: disable
1: enable
EMI: Master interrupt global enable
0: disable
1: enable
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INTC0 Register - HT48R065G/HT48R0662G
Bit
7
6
5
4
3
2
1
0
Name
¾
T1F
T0F
INTF
T1E
T0E
INTE
EMI
R/W
¾
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
¾
0
0
0
0
0
0
0
unimplemented, read as ²0²
T1F: Timer/Event Counter 1 interrupt request flag
0: inactive
1: active
T0F: Timer/Event Counter 0 interrupt request flag
0: inactive
1: active
INTF: External interrupt request flag
0: inactive
1: active
T1E: Timer/Event Counter 1 interrupt enable
0: disable
1: enable
T0E: Timer/Event Counter 0 interrupt enable
0: disable
1: enable
INTE: external interrupt enable
0: disable
1: enable
EMI: Master interrupt global enable
0: disable
1: enable
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTC0 Register - HT48R066G
Bit
7
6
5
4
3
2
1
0
Name
¾
T1F
T0F
EIF
ET1I
ET0I
EEI
EMI
R/W
¾
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
¾
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
unimplemented, read as ²0²
T1F: Timer/Event Counter 1 interrupt request flag
0: inactive
1: active
T0F: Timer/Event Counter 0 interrupt request flag
0: inactive
1: active
EIF: External interrupt request flag
0: inactive
1: active
ET1I: Timer/Event Counter 1 interrupt enable
0: disable
1: enable
ET0I: Timer/Event Counter 0 interrupt enable
0: disable
1: enable
EEI: External interrupt enable
0: disable
1: enable
EMI: Master interrupt global enable
0: disable
1: enable
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INTC1 Register - All devices
Bit
7
6
5
4
3
2
1
0
Name
¾
MFF
TBF
¾
¾
MFE
TBE
¾
R/W
¾
R/W
R/W
¾
¾
R/W
R/W
¾
POR
¾
0
0
¾
¾
0
0
¾
4
3
2
1
0
Bit 7
Bit 6
unimplemented, read as ²0²
MFF: Multi-function interrupt request flag
0: inactive
1: active
Bit 5
TBF: Time Base event interrupt request flag
0: inactive
1: active
Bit 4~3
Bit 2
unimplemented, read as ²0²
MFE: Multi-function interrupt enable
0: disable
1: enable
Bit 1
TBE: Time base event interrupt enable
0: disable
1: enable
Bit 0
unimplemented, read as ²0²
MFIC Register - All devices
Bit
7
Name
¾
A1F
A0F
CF
¾
EA1I
EA0I
ECI
R/W
¾
R/W
R/W
R/W
¾
R/W
R/W
R/W
POR
¾
0
0
0
¾
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
6
5
unimplemented, read as ²0²
A1F: OPA1 interrupt request flag
0: inactive
1: active
A0F: OPA0 interrupt request flag
0: inactive
1: active
CF: Comparator interrupt request flag
0: inactive
1: active
Bit 3
Bit 2
unimplemented, read as ²0²
EA1I: OPA1 interrupt enable
0: disable
1: enable
Bit 1
EA0I: OPA0 interrupt enable
0: disable
1: enable
Bit 0
ECI: Comparator interrupt enable
0: disable
1: enable
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
A u to m a tic a lly D is a b le d b y IS R
C a n b e E n a b le d M a n u a lly
A u to m a tic a lly C le a r e d b y IS R
M a n u a lly S e t o r C le a r e d b y S o ftw a r e
P r io r ity
E x te rn a l In te rru p t
R e q u e s t F la g IN T F
IN T E
E M I
T im e r /E v e n t C o u n te r 0
In te r r u p t R e q u e s t F la g T 0 F
T 0 E
E M I
T im e r /E v e n t C o u n te r 1 *
In te r r u p t R e q u e s t F la g T 1 F
T 1 E
E M I
T im e B a s e In te r r u p t
R e q u e s t F la g T B F
T B E
E M I
M u lti- F u n c tio n In te r r u p t
R e q u e s t F la g M F F
M F E
E M I
C o m p a ra to r In te rru p t
R e q u e s t F la g C F
E C I
O P A 0 In te rru p t
R e q u e s t F la g A 0 F
E A 0 I
O P A 1 In te rru p t
R e q u e s t F la g A 1 F
E A 1 I
H ig h
In te rru p t
P o llin g
L o w
* : T im e r /E v e n t C o u n te r 1 in te r r u p t is fo r
H T 4 8 R 0 6 5 G /H T 4 8 R 0 6 6 2 G o n ly .
Interrupt Scheme
Main
Program
Interrupt Request or
Interrupt Flag Set by Instruction
N
Enable Bit Set ?
Y
Main
Program
Automatically Disable Interrupt
Clear EMI & Request Flag
Wait for 2 ~ 3 Instruction Cycles
ISR Entry
RETI
(it will set EMI automatically)
Interrupt Flow
Rev. 1.00
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Interrupt Operation
A Timer/Event Counter overflow, an active edge on the external interrupt pin, a comparator output
transition, an OPA output falling edge or a Time Base event will all generate an interrupt request by
setting their corresponding request flag. When this happens, the Program Counter, which stores the
address of the next instruction to be executed, will be transferred onto the stack. The Program Counter
will then be loaded with a new address which will be the value of the corresponding interrupt vector.
The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this
vector will usually be a JMP statement which will jump to another section of program which is known
as the interrupt service routine. Here is located the code to control the appropriate interrupt. The
interrupt service routine must be terminated with a RETI instruction, which retrieves the original
Program Counter address from the stack and allows the microcontroller to continue with normal
execution at the point where the interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
following diagram with their order of priority.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be
cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other
interrupt requests occur during this interval, although the interrupt will not be immediately serviced,
the request flag will still be recorded. If an interrupt requires immediate servicing while the program is
already in another interrupt service routine, the EMI bit should be set after entering the routine, to
allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the
stack must be prevented from becoming full.
When an interrupt request is generated it takes 2 or 3 instruction cycle before the program jumps to the
interrupt vector. If the device is in the Sleep or Idle Mode and is woken up by an interrupt request then
it will take 3 cycles before the program jumps to the interrupt vector.
Interrupt Priority
Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be
serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of
simultaneous requests, the following table shows the priority that is applied. These can be masked by
resetting the EMI bit.
HT48R064G
Interrupt Source
Priority
Vector
External Interrupt
1
04H
Timer/Event Counter 0 Overflow
2
08H
Time Base Overflow
3
14H
Multi-function interrupt
(Comparator, OPA0, OPA1)
4
18H
HT48R065G/HT48R066G/HT48R0662G
Rev. 1.00
Interrupt Source
Priority
Vector
External Interrupt
1
04H
Timer/Event Counter 0 Overflow
2
08H
Timer/Event Counter 1 Overflow
3
0CH
Time Base Overflow
4
14H
Multi-function interrupt
(Comparator, OPA0, OPA1)
5
18H
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In cases where both external and internal interrupts are enabled and where an external and internal interrupt occurs simultaneously, the external interrupt will always have priority and will therefore be
serviced first. Suitable masking of the individual interrupts using the interrupt registers can prevent
simultaneous occurrences.
External Interrupt
For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bit,
INTE, must first be set. An actual external interrupt will take place when the external interrupt request
flag, INTF, is set, a situation that will occur when an edge transition appears on the external INT line.
The type of transition that will trigger an external interrupt, whether high to low, low to high or both is
determined by the INTEG0 and INTEG1 bits, which are bits 6 and 7 respectively, in the CTRL1
control register. These two bits can also disable the external interrupt function.
INTEG1
INTEG0
0
0
External interrupt disable
Edge Trigger Type
0
1
Rising edge Trigger
1
0
Falling edge Trigger
1
1
Both edge Trigger
The external interrupt pin is pin-shared with the I/O pin PA3 and can only be configured as an external interrupt pin if the corresponding external interrupt enable bit in the INTC register has been set
and the edge trigger type has been selected using the CTRL1 register. The pin must also be setup as
an input by setting the corresponding PAC.3 bit in the port control register. When the interrupt is enabled, the stack is not full and an active transition appears on the external interrupt pin, a subroutine
call to the external interrupt vector at location 04H, will take place. When the interrupt is serviced,
the external interrupt request flag, INTF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor connections on this pin will
remain valid even if the pin is used as an external interrupt input.
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and the
corresponding timer interrupt enable bit, TnE, must first be set. An actual Timer/Event Counter
interrupt will take place when the Timer/Event Counter request flag, TnF, is set, a situation that will
occur when the relevant Timer/Event Counter overflows. When the interrupt is enabled, the stack is
not full and a Timer/Event Counter n overflow occurs, a subroutine call to the relevant timer interrupt
vector, will take place. When the interrupt is serviced, the timer interrupt request flag, TnF, will be
automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
Time Base Interrupt
For a time base interrupt to occur the global interrupt enable bit EMI and the corresponding interrupt
enable bit TBE, must first be set. An actual Time Base interrupt will take place when the time base
request flag TBF is set, a situation that will occur when the Time Base overflows. When the interrupt is
enabled, the stack is not full and a time base overflow occurs a subroutine call to time base vector will
take place. When the interrupt is serviced, the time base interrupt flag. TBF will be automatically reset
and the EMI bit will be automatically cleared to disable other interrupts.
Rev. 1.00
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Enhanced I/O Type 8-Bit OTP MCU with OPA
Multi-function Interrupt
For a Multi-function interrupt to occur, the global interrupt enable bit, EMI, and the corresponding
multi-function interrupt enable bit, MFE, must first be set. An actual Multi-function interrupt will take
place when the Multi-function interrupt request flag, MFF, is set, a situation that will occur when
OPA0 or OPA1 output has a falling edge, or a Comparator output transition occurs. When the interrupt
is enabled, the stack is not full and a Multi-function interrupt request occurs, a subroutine call to the
Multi-function interrupt vector at location 18H, will take place. When the interrupt is serviced, the
Multi-function interrupt request flag, MFF, will be automatically reset and the EMI bit will be
automatically cleared to disable other interrupts. After the Multi-function took place, the programmer
can check what the interrupt source was by interrogating the request flags, A0F, A1F or CF within the
MFIC register.
Programming Considerations
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced,
however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until
the corresponding interrupt is serviced or until the request flag is cleared by a software instruction.
It is recommended that programs do not use the ²CALL subroutine² instruction within the interrupt
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in
some applications. If only one stack is left and the interrupt is not well controlled, the original control
sequence will be damaged once a ²CALL subroutine² is executed in the interrupt subroutine.
All of these interrupts have the capability of waking up the processor when in the Idle/Sleep Mode.
Only the Program Counter is pushed onto the stack. If the contents of the register or status register are
altered by the interrupt service program, which may corrupt the desired control sequence, then the
contents should be saved in advance.
SCOM Function for LCD
The HT48R065G, HT48R066G and HT48R0662G devices have the capability of driving external
LCD panels. The common pins for LCD driving, SCOM0~SCOM3, are pin shared with certain pin on
the PB0~PB3 port. The LCD signals (COM and SEG) are generated using the application program.
LCD Operation
An external LCD panel can be driven using this device by configuring the PB0~PB3 pins as common
pins and using other output ports lines as segment pins. The LCD driver function is controlled using
the SCOMC register which in addition to controlling the overall on/off function also controls the bias
voltage setup function. This enables the LCD COM driver to generate the necessary VDD/2 voltage
levels for LCD 1/2 bias operation.
V
D D
S C O M
V
D D
o p e r a tin g c u r r e n t
/2
S C O M 0 ~
S C O M 3
C O M n E N
S C O M E N
LCD COM Bias
Rev. 1.00
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The SCOMEN bit in the SCOMC register is the overall master control for the LCD Driver, however
this bit is used in conjunction with the COMnEN bits to select which Port B and Port C pins are used
for LCD driving. Note that the Port Control register does not need to first setup the pins as outputs to
enable the LCD driver operation.
SCOMEN
COMnEN
Pin Function
O/P Level
0
X
I/O
0 or 1
1
0
I/O
0 or 1
1
1
SCOMN
VDD/2
Output Control
LCD Bias Control
The LCD COM driver enables a range of selections to be provided to suit the requirement of the LCD
panel which is being used. The bias resistor choice is implemented using the ISEL1 and ISEL0 bits in
the SCOMC register.
SCOMC Register
Bit
7
6
5
4
3
2
1
0
Name
¾
ISEL1
ISEL0
SCOMEN
COM3EN
COM2EN
COM1EN
COM0EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 6,5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
Reserved Bit
1: Unpredictable operation - bit must NOT be set high
0: Correct level - bit must be reset to zero for correct operation
ISEL1, ISEL0: SCOM operating current selection (VDD=5V)
00: 25mA
01: 50mA
10: 100mA
11: 200mA
SCOMEN: SCOM module on/off control
0: disable
1: enable
SCOMn can be enable by COMnEN if SCOMEN=1
COM3EN: PC6 or SCOM3 selection
0: GPIO
1: SCOM3
COM2EN: PC7 or SCOM2 selection
0: GPIO
1: SCOM2
COM1EN: PB7 or SCOM1 selection
0: GPIO
1: SCOM1
COM0EN: PB6 or SCOM0 selection
0: GPIO
1: SCOM0
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Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the OTP
Program Memory device during the programming process. During the development process, these
options are selected using the HT-IDE software development tools. As these options are programmed
into the device using the hardware programming tools, once they are selected they cannot be changed
later by the application software. All options must be defined for proper system function, the details of
which are shown in the table.
No.
Options
1
Watchdog Timer: enable or disable
2
Watchdog Timer clock source: LXT, LIRC or fSYS/4
Note: LXT oscillator must be selected by OSC configuration option if WDT clock source is from LXT.
3
CLRWDT instructions: 1 or 2 instructions
4
For HT48R064G/HT48R065G/HT48R066G
System oscillator configuration: HXT, HIRC, ERC, HIRC+LXT
For HT48R0662G
System oscillator configuration: HXT, HIRC, ERC, HXT+LXT, HIRC+LXT, ERC+LXT
5
LVR function: enable or disable
6
LVR voltage: 2.1V, 3.15V or 4.2V
7
RES or PA7 pin function
8
HIRC oscillator frequency: 4MHz, 8MHz or 12MHz
Application Circuits
V
D D
0 .0 1 m F
0 .1 m F
V D D
R e s e t
C ir c u it
1 0 k W ~
1 0 0 k W
1 N 4 1 4 8
0 .1 ~ 1 m F
3 0 0 W
P A 7 /R E S
P A
P A 1 /P F
P A 2 /T C
P A 3 /IN
P A 4 /T C 1 /P W M
0 /A
D /A
0 /A
T /A
0 /A
1 N
1 A
0 X
0 N
0 P
P B 0 /S C O M 0 ~ P B 3 /S C O M 3
P B 4 ~ P B 7
V S S
O S C
C ir c u it
P A 6 /O S C 1
P A 5 /O S C 2
S e e O s c illa to r
S e c tio n
O S C
C ir c u it
P C
P C
P C 2 /A N 0 ~ P C 5
P C 6
P C
0 /C
1 /C
/A N
/A 1
7 /C
N
X
P
P
3
P D 2 ~ P D 3
P D 4 /A N 7 ~ P D 7 /A N 4
P F 0 /O S C 4
P E 0 ~ P E 7
P F 1 /O S C 3
S e e O s c illa to r
S e c tio n
H T 4 8 R 0 6 6 2 G
Rev. 1.00
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Instruction Set
Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set of
program instruction codes that directs the microcontroller to perform certain operations. In the case of
Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable
programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call,
or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4
system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be
implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although
instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET,
RETI and table read instructions, it is important to realize that any other instructions which involve
manipulation of the Program Counter Low register or PCL will also take one more cycle to implement.
As instructions which change the contents of the PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A².
For the case of skip instructions, it must be noted that if the result of the comparison involves a skip
operation then this will also take one more cycle, if no skip is involved then only one cycle is required.
Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used operations.
Making use of three kinds of MOV instructions, data can be transferred from registers to the
Accumulator and vice-versa as well as being able to move specific immediate data directly into the
Accumulator. One of the most important data transfer applications is to receive data from the input
ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of
most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add
and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be
taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less
than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA
provide a simple means of increasing or decreasing by a value of one of the values in the destination
specified.
Logical and Rotate Operations
The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within
the Holtek microcontroller instruction set. As with the case of most instructions involving data
manipulation, data must pass through the Accumulator which may involve additional programming
steps. In all logical data operations, the zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC
and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions
exist depending on program requirements. Rotate instructions are useful for serial port programming
applications where data can be rotated from an internal register into the Carry bit from where it can be
examined and the necessary serial bit set high or low. Another application where rotate data operations
are used is to implement multiplication and division calculations.
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Branches and Control Transfer
Program branching takes the form of either jumps to specified locations using the JMP instruction or to
a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call,
the program must return to the instruction immediately when the subroutine has been carried out. This
is done by placing a return instruction RET in the subroutine which will cause the program to jump
back to the address right after the CALL instruction. In the case of a JMP instruction, the program
simply jumps to the desired location. There is no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special and extremely useful set of branch
instructions are the conditional branches. Here a decision is first made regarding the condition of a
certain data memory or individual bits. Depending upon the conditions, the program will continue with
the next instruction or skip over it and jump to the following instruction. These instructions are the key
to decision making and branching within the program perhaps determined by the condition of certain
input switches or by the condition of internal data bits.
Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port bit programming where
individual bits or port pins can be directly set high or low using either the ²SET [m].i² or ²CLR [m].i²
instructions respectively. The feature removes the need for programmers to first read the 8-bit output
port, manipulate the input data to ensure that other bits are not changed and then output the port with
the correct new data. This read-modify-write process is taken care of automatically when these bit
operation instructions are used.
Table Read Operations
Data storage is normally implemented by using registers. However, when working with large amounts
of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data
Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be
setup as a table where data can be directly stored. A set of easy to use instructions provides the means
by which this fixed data can be referenced and retrieved from the Program Memory.
Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as the
²HALT² instruction for Power-down operations and instructions to control the operation of the
Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.
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Instruction Set Summary
The following table depicts a summary of the instruction set categorised according to function and can
be consulted as a basic instruction reference using the following listed conventions.
Table conventions:
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
1
1Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
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Mnemonic
Description
Cycles
Flag Affected
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by the
execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and ²CLR WDT2² instructions
are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result
is stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical
AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then
increments by 1 to obtain the address of the next instruction which is then pushed onto
the stack. The specified address is then loaded and the program continues execution
from this new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2
will have no effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1
will have no effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement).
Bits which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement).
Bits which previously contained a 1 are changed to 0 and vice versa. The complemented
result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater
than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the
low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set,
then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is
performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag
conditions. Only the C flag may be affected by this instruction which indicates that if the
original BCD sum is greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared.
The power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a
dummy instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR
operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be
processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into
bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into
bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit
7 replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated
into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0
rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the
Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit.
Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
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SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if
the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result
is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Data Memory. Note that if
the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result
is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0
the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0
the program proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0,
the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a
dummy instruction while the next instruction is fetched, it is a two cycle instruction. If
the result is not 0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
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SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0,
the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0
the program proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0,
the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a
dummy instruction while the next instruction is fetched, it is a two cycle instruction. If
the result is not 0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C
flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to
1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C
flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to
1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag
will be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
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SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped.
As this requires the insertion of a dummy instruction while the next instruction is
fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the
following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is
not 0 the program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP)
is moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.00
102
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR
operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical
XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.00
103
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Package Information
16-pin DIP (300mil) Outline Dimensions
A
B
A
1 6
9
1
8
B
1 6
9
1
8
H
H
C
C
D
D
G
E
G
E
I
F
I
F
Fig1. Full Lead Packages
Fig2. 1/2 Lead Packages
MS-001d (see fig1)
Symbol
Nom.
Max.
A
0.780
¾
0.880
B
0.240
¾
0.280
C
0.115
¾
0.195
D
0.115
¾
0.150
E
0.014
¾
0.022
0.070
F
0.045
¾
G
¾
0.100
¾
H
0.300
¾
0.325
I
¾
0.430
¾
Symbol
Rev. 1.00
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
19.81
¾
22.35
B
6.10
¾
7.11
C
2.92
¾
4.95
D
2.92
¾
3.81
E
0.36
¾
0.56
F
1.14
¾
1.78
G
¾
2.54
¾
H
7.62
¾
8.26
I
¾
10.92
¾
104
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
MS-001d (see fig2)
Symbol
Nom.
Max.
A
0.735
¾
0.775
B
0.240
¾
0.280
C
0.115
¾
0.195
D
0.115
¾
0.150
E
0.014
¾
0.022
F
0.045
¾
0.070
G
¾
0.100
¾
H
0.300
¾
0.325
I
¾
0.430
¾
Symbol
A
Rev. 1.00
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
18.67
¾
19.69
B
6.10
¾
7.11
C
2.92
¾
4.95
D
2.92
¾
3.81
E
0.36
¾
0.56
F
1.14
¾
1.78
G
¾
2.54
¾
H
7.62
¾
8.26
I
¾
10.92
¾
105
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
MO-095a (see fig2)
Symbol
Nom.
Max.
A
0.745
¾
0.785
B
0.275
¾
0.295
C
0.120
¾
0.150
D
0.110
¾
0.150
E
0.014
¾
0.022
F
0.045
¾
0.060
G
¾
0.100
¾
H
0.300
¾
0.325
I
¾
0.430
¾
Symbol
A
Rev. 1.00
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
18.92
¾
19.94
B
6.99
¾
7.49
C
3.05
¾
3.81
D
2.79
¾
3.81
E
0.36
¾
0.56
F
1.14
¾
1.52
G
¾
2.54
¾
H
7.62
¾
8.26
I
¾
10.92
¾
106
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
16-pin NSOP (150mil) Outline Dimensions
A
1 6
9
1
B
8
C
C '
G
H
D
E
a
F
MS-012
Symbol
A
Min.
Nom.
Max.
0.228
¾
0.244
B
0.150
¾
0.157
C
0.012
¾
0.020
C¢
0.386
¾
0.402
D
¾
¾
0.069
E
¾
0.050
¾
F
0.004
¾
0.010
G
0.016
¾
0.050
H
0.007
¾
0.010
a
0°
¾
8°
Symbol
Rev. 1.00
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
5.79
¾
6.20
B
3.81
¾
3.99
C
0.30
¾
0.51
C¢
9.80
¾
10.21
D
¾
¾
1.75
E
¾
1.27
¾
F
0.10
¾
0.25
G
0.41
¾
1.27
H
0.18
¾
0.25
a
0°
¾
8°
107
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
20-pin DIP (300mil) Outline Dimensions
A
B
A
2 0
1 1
1
1 0
B
2 0
1 1
1 0
1
H
H
C
C
D
D
E
F
I
G
E
F
Fig1. Full Lead Packages
I
G
Fig2. 1/2 Lead Packages
MS-001d (see fig1)
Symbol
Nom.
Max.
A
0.980
¾
1.060
B
0.240
¾
0.280
C
0.115
¾
0.195
D
0.115
¾
0.150
E
0.014
¾
0.022
F
0.045
¾
0.070
G
¾
0.100
¾
H
0.300
¾
0.325
I
¾
0.430
¾
Symbol
A
Rev. 1.00
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
24.89
¾
26.92
B
6.10
¾
7.11
C
2.92
¾
4.95
D
2.92
¾
3.81
E
0.36
¾
0.56
F
1.14
¾
1.78
G
¾
2.54
¾
H
7.62
¾
8.26
I
¾
10.92
¾
108
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
MO-095a (see fig2)
Symbol
Nom.
Max.
A
0.945
¾
0.985
B
0.275
¾
0.295
C
0.120
¾
0.150
D
0.110
¾
0.150
E
0.014
¾
0.022
F
0.045
¾
0.060
G
¾
0.100
¾
H
0.300
¾
0.325
I
¾
0.430
¾
Symbol
A
Rev. 1.00
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
24.00
¾
25.02
B
6.99
¾
7.49
C
3.05
¾
3.81
D
2.79
¾
3.81
E
0.36
¾
0.56
F
1.14
¾
1.52
G
¾
2.54
¾
H
7.62
¾
8.26
I
¾
10.92
¾
109
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
20-pin SOP (300mil) Outline Dimensions
1 1
2 0
A
B
1
1 0
C
C '
G
H
D
E
a
F
MS-013
Symbol
Nom.
Max.
A
0.393
¾
0.419
B
0.256
¾
0.300
C
0.012
¾
0.020
C¢
0.496
¾
0.512
D
¾
¾
0.104
E
¾
0.050
¾
F
0.004
¾
0.012
G
0.016
¾
0.050
H
0.008
¾
0.013
a
0°
¾
8°
Symbol
Rev. 1.00
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
9.98
¾
10.64
B
6.50
¾
7.62
C
0.30
¾
0.51
C¢
12.60
¾
13.00
D
¾
¾
2.64
E
¾
1.27
¾
F
0.10
¾
0.30
G
0.41
¾
1.27
H
0.20
¾
0.33
a
0°
¾
8°
110
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
20-pin SSOP (150mil) Outline Dimensions
1 1
2 0
A
B
1
1 0
C
C '
G
H
D
E
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.228
¾
0.244
B
0.150
¾
0.158
C
0.008
¾
0.012
C¢
0.335
¾
0.347
D
0.049
¾
0.065
E
¾
0.025
¾
F
0.004
¾
0.010
G
0.015
¾
0.050
H
0.007
¾
0.010
a
0°
¾
8°
Symbol
Rev. 1.00
a
F
Dimensions in mm
Min.
Nom.
Max.
A
5.79
¾
6.20
B
3.81
¾
4.01
C
0.20
¾
0.30
C¢
8.51
¾
8.81
D
1.24
¾
1.65
E
¾
0.64
¾
F
0.10
¾
0.25
G
0.38
¾
1.27
H
0.18
¾
0.25
a
0°
¾
8°
111
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
24-pin SKDIP (300mil) Outline Dimensions
A
A
1 3
2 4
B
1 3
2 4
B
1 2
1
1 2
1
H
H
C
C
D
D
E
F
I
G
E
F
I
G
Fig2. 1/2 Lead Packages
Fig1. Full Lead Packages
MS-001d (see fig1)
Symbol
Nom.
Max.
A
1.230
¾
1.280
B
0.240
¾
0.280
C
0.115
¾
0.195
D
0.115
¾
0.150
E
0.014
¾
0.022
F
0.045
¾
0.070
G
¾
0.100
¾
H
0.300
¾
0.325
I
¾
0.430
¾
Symbol
A
Rev. 1.00
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
31.24
¾
32.51
B
6.10
¾
7.11
C
2.92
¾
4.95
D
2.92
¾
3.81
E
0.36
¾
0.56
F
1.14
¾
1.78
G
¾
2.54
¾
H
7.62
¾
8.26
I
¾
10.92
¾
112
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
MS-001d (see fig2)
Symbol
Nom.
Max.
A
1.160
¾
1.195
B
0.240
¾
0.280
C
0.115
¾
0.195
D
0.115
¾
0.150
E
0.014
¾
0.022
F
0.045
¾
0.070
G
¾
0.100
¾
H
0.300
¾
0.325
I
¾
0.430
¾
Symbol
A
Rev. 1.00
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
29.46
¾
30.35
B
6.10
¾
7.11
C
2.92
¾
4.95
D
2.92
¾
3.81
E
0.36
¾
0.56
F
1.14
¾
1.78
G
¾
2.54
¾
H
7.62
¾
8.26
I
¾
10.92
¾
113
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
MO-095a (see fig2)
Symbol
Nom.
Max.
A
1.145
¾
1.185
B
0.275
¾
0.295
C
0.120
¾
0.150
D
0.110
¾
0.150
E
0.014
¾
0.022
F
0.045
¾
0.060
G
¾
0.100
¾
H
0.300
¾
0.325
I
¾
0.430
¾
Symbol
A
Rev. 1.00
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
29.08
¾
30.10
B
6.99
¾
7.49
C
3.05
¾
3.81
D
2.79
¾
3.81
E
0.36
¾
0.56
F
1.14
¾
1.52
G
¾
2.54
¾
H
7.62
¾
8.26
I
¾
10.92
¾
114
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
24-pin SOP (300mil) Outline Dimensions
1 3
2 4
A
B
1
1 2
C
C '
G
H
D
E
a
F
MS-013
Symbol
Nom.
Max.
A
0.393
¾
0.419
B
0.256
¾
0.300
C
0.012
¾
0.020
C¢
0.598
¾
0.613
D
¾
¾
0.104
E
¾
0.050
¾
F
0.004
¾
0.012
G
0.016
¾
0.050
H
0.008
¾
0.013
a
0°
¾
8°
Symbol
Rev. 1.00
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
9.98
¾
10.64
B
6.50
¾
7.62
C
0.30
¾
0.51
C¢
15.19
¾
15.57
D
¾
¾
2.64
E
¾
1.27
¾
F
0.10
¾
0.30
G
0.41
¾
1.27
H
0.20
¾
0.33
a
0°
¾
8°
115
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
24-pin SSOP (150mil) Outline Dimensions
1 3
2 4
A
B
1
1 2
C
C '
G
H
D
E
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.228
¾
0.244
B
0.150
¾
0.157
C
0.008
¾
0.012
C¢
0.335
¾
0.346
D
0.054
¾
0.060
E
¾
0.025
¾
F
0.004
¾
0.010
G
0.022
¾
0.028
H
0.007
¾
0.010
a
0°
¾
8°
Symbol
Rev. 1.00
a
F
Dimensions in mm
Min.
Nom.
Max.
A
5.79
¾
6.20
B
3.81
¾
3.99
C
0.20
¾
0.30
C¢
8.51
¾
8.79
D
1.37
¾
1.52
E
¾
0.64
¾
F
0.10
¾
0.25
G
0.56
¾
0.71
H
0.18
¾
0.25
a
0°
¾
8°
116
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
28-pin SKDIP (300mil) Outline Dimensions
A
B
2 8
1 5
1
1 4
H
C
D
E
Symbol
I
G
Dimensions in inch
Min.
Nom.
Max.
A
1.375
¾
1.395
B
0.278
¾
0.298
C
0.125
¾
0.135
D
0.125
¾
0.145
E
0.016
¾
0.020
0.070
F
0.050
¾
G
¾
0.100
¾
H
0.295
¾
0.315
I
¾
0.375
¾
Symbol
Rev. 1.00
F
Dimensions in mm
Min.
Nom.
Max.
A
34.93
¾
35.43
B
7.06
¾
7.57
C
3.18
¾
3.43
D
3.18
¾
3.68
E
0.41
¾
0.51
F
1.27
¾
1.78
G
¾
2.54
¾
H
7.49
¾
8.00
I
¾
9.53
¾
117
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
a
F
MS-013
Symbol
Nom.
Max.
A
0.393
¾
0.419
B
0.256
¾
0.300
C
0.012
¾
0.020
C¢
0.697
¾
0.713
D
¾
¾
0.104
E
¾
0.050
¾
F
0.004
¾
0.012
G
0.016
¾
0.050
H
0.008
¾
0.013
a
0°
¾
8°
Symbol
Rev. 1.00
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
9.98
¾
10.64
B
6.50
¾
7.62
C
0.30
¾
0.51
C¢
17.70
¾
18.11
D
¾
¾
2.64
E
¾
1.27
¾
F
0.10
¾
0.30
G
0.41
¾
1.27
H
0.20
¾
0.33
a
0°
¾
8°
118
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
28-pin SSOP (150mil) Outline Dimensions
1 5
2 8
A
B
1
1 4
C
C '
G
H
D
E
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.228
¾
0.244
B
0.150
¾
0.157
C
0.008
¾
0.012
C¢
0.386
¾
0.394
D
0.054
¾
0.060
E
¾
0.025
¾
F
0.004
¾
0.010
G
0.022
¾
0.028
H
0.007
¾
0.010
a
0°
¾
8°
Symbol
Rev. 1.00
a
F
Dimensions in mm
Min.
Nom.
Max.
A
5.79
¾
6.20
B
3.81
¾
3.99
C
0.20
¾
0.30
C¢
9.80
¾
10.01
D
1.37
¾
1.52
E
¾
0.64
¾
F
0.10
¾
0.25
G
0.56
¾
0.71
H
0.18
¾
0.25
a
0°
¾
8°
119
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
44-pin QFP (10mm´10mm) Outline Dimensions
H
C
D
G
2 3
3 3
I
3 4
2 2
L
F
A
B
E
1 2
4 4
K
a
J
1
Symbol
A
Dimensions in inch
Min.
Nom.
Max.
0.512
¾
0.528
B
0.390
¾
0.398
C
0.512
¾
0.528
D
0.390
¾
0.398
E
¾
0.031
¾
F
¾
0.012
¾
G
0.075
¾
0.087
H
¾
¾
0.106
I
0.010
¾
0.020
J
0.029
¾
0.037
K
0.004
¾
0.008
L
¾
0.004
¾
a
0°
¾
7°
Symbol
Rev. 1.00
1 1
Dimensions in mm
Min.
Nom.
Max.
A
13.00
¾
13.40
B
9.90
¾
10.10
C
13.00
¾
13.40
D
9.90
¾
10.10
E
¾
0.80
¾
F
¾
0.30
¾
G
1.90
¾
2.20
H
¾
¾
2.70
I
0.25
¾
0.50
J
0.73
¾
0.93
K
0.10
¾
0.20
L
¾
0.10
¾
a
0°
¾
7°
120
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 16N (150mil)
Symbol
Description
A
Reel Outer Diameter
B
Reel Inner Diameter
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Dimensions in mm
330.0±1.0
100.0±1.5
13.0
+0.5/-0.2
2.0±0.5
16.8
+0.3/-0.2
22.2±0.2
SOP 20W, SOP 24W, SOP 28W (300mil)
Symbol
Description
A
Reel Outer Diameter
B
Reel Inner Diameter
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Dimensions in mm
330.0±1.0
100.0±1.5
13.0
+0.5/-0.2
2.0±0.5
24.8
+0.3/-0.2
30.2±0.2
SSOP 20S (150mil), SSOP 24S (150mil), SSOP 28S (150mil)
Symbol
Description
A
Reel Outer Diameter
B
Reel Inner Diameter
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev. 1.00
Dimensions in mm
330.0±1.0
100.0±1.5
13.0
+0.5/-0.2
2.0±0.5
16.8
+0.3/-0.2
22.2±0.2
121
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
B 0
C
D 1
P
K 0
A 0
R e e l H o le
IC p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SOP 16N (150mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
16.0±0.3
P
Cavity Pitch
8.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
1.55
+0.10/-0.00
D1
Cavity Hole Diameter
1.50
+0.25/-0.00
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
10.3±0.1
K0
Cavity Depth
2.1±0.1
7.5±0.1
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
Rev. 1.00
122
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
SOP 20W
Symbol
Description
Dimensions in mm
24.0
+0.3/-0.1
W
Carrier Tape Width
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
11.5±0.1
1.5
1.50
+0.1/-0.0
+0.25/-0.00
D1
Cavity Hole Diameter
P0
Perforation Pitch
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.8±0.1
B0
Cavity Width
13.3±0.1
K0
Cavity Depth
3.2±0.1
4.0±0.1
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
21.3±0.1
SOP 24W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
1.55
+0.10/-0.00
D1
Cavity Hole Diameter
1.50
+0.25/-0.00
P0
Perforation Pitch
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.9±0.1
B0
Cavity Width
15.9±0.1
K0
Cavity Depth
11.5±0.1
4.0±0.1
3.1±0.1
t
Carrier Tape Thickness
0.35±0.05
C
Cover Tape Width
21.3±0.1
Rev. 1.00
123
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5
D1
Cavity Hole Diameter
1.50
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.85±0.10
B0
Cavity Width
18.34±0.10
K0
Cavity Depth
2.97±0.10
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
21.3±0.1
+0.1/-0.0
+0.25/-0.00
SSOP 20S (150mil)
Symbol
Description
Dimensions in mm
16.0
+0.3/-0.1
W
Carrier Tape Width
P
Cavity Pitch
E
Perforation Position
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
1.5
D1
Cavity Hole Diameter
1.50
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
9.0±0.1
K0
Cavity Depth
2.3±0.1
8.0±0.1
1.75±0.10
7.5±0.1
+0.1/-0.0
+0.25/-0.00
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
Rev. 1.00
124
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
SSOP 24S (150mil)
Symbol
Description
Dimensions in mm
16.0
+0.3/-0.1
W
Carrier Tape Width
P
Cavity Pitch
E
Perforation Position
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
1.5
D1
Cavity Hole Diameter
1.50
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
9.5±0.1
K0
Cavity Depth
2.1±0.1
8.0±0.1
1.75±0.10
7.5±0.1
+0.1/-0.0
+0.25/-0.00
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
SSOP 28S (150mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
16.0±0.3
P
Cavity Pitch
8.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
7.5±0.1
D
Perforation Diameter
1.55
+0.10/-0.00
D1
Cavity Hole Diameter
1.50
+0.25/-0.00
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
10.3±0.1
K0
Cavity Depth
2.1±0.1
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
Rev. 1.00
125
February 23, 2011
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
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February 23, 2011