MP2007 3A, 1.3V–6.0V DDR Memory Termination Regulator The Future of Analog IC Technology DESCRIPTION FEATURES The MP2007 integrates the DDR memory termination regulator with the output voltage (VTT) and a buffered VTTREF outputs is a half of VREF. • • • The VTT-LDO is a 3A sink/source tracking termination regulator. It is specifically designed for low-cost/low-external component count systems, where space is a premium. • • The MP2007 maintains a fast transient response only requiring 20uF (2x10uF) of ceramic output capacitance. The MP2007 supports Kelvin sensing functions. • • • • • The MP2007 is available in the 8-pin MSOP with Exposed PAD package and is specified from −40oC to 85oC. VDDQ Voltage Range: 1.3V to 6.0 V Up to 3A Integrated Sink/Source Linear Regulator with Accurate VREF/2 Divider Reference for DDR Termination Requires Only 20uF Ceramic Output Capacitance Drive Voltage Range: 4.5 V to 5.5 V 1.3V Input (VDDQ) Helps Reduce Total Power Dissipation Integrated Divider Tracks VREF for VTT and VTTREF Kelvin Sensing (VTTSEN) ±20mV Accuracy for VTT and VTTREF Built-In Soft-Start, UVLO and OCL Thermal Shutdown APPLICATIONS • • Notebook DDR2/3 Memory Supply and Termination Voltage in ACPI Compliant Active Termination Busses “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION VDDQ R3 20 C1 10uF 1206 6 C4 0.1uF DDQ VTTREF REF R2 100k C7 4.7uF 7 VDRV VTTSEN VTT VTTEN GND GND MP2007 Rev. 0.9 7/23/2009 8 3 VTTREF C6 0.1uF MP2007DH 5 5V EN 1 4 GND 2 VTT C2 10uF 1206 C3 10uF 1206 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. C9 NC 1 MP2007 – 3A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR ORDERING INFORMATION Part Number* Package Top Marking Temperature MP2007DH MSOP8E 2007D –40°C to +85°C * For Tape & Reel, add suffix –Z (e.g. MP2007DH–Z); For RoHS Compliant Packaging, add suffix –LF (e.g. MP2007DH–LF–Z) PACKAGE REFERENCE TOP VIEW DDQ 1 8 VTTREF VTT 2 7 EN GND 3 6 REF VTTSEN 4 5 VDRV ABSOLUTE MAXIMUM RATINGS (1) Supply Voltage VDDQ......................... -0.3V to 6.0V Drive Voltage VDRV..................... -0.3V to 6.0V All Other Pins................................ -0.3V to 6.0V Continuous Power Dissipation (TA = +25°C)(2) ........................................................... 1.56W Junction Temperature...............................150oC Lead Temperature ....................................260oC Storage Temperature .............. -50oC to +150oC Recommended Operating Conditions (3) Drive Voltage VDRV....................... 4.5V to 5.5V Operating Temperature .............–40oC to +85oC MP2007 Rev. 0.9 7/23/2009 Thermal Resistance (4) θJA θJC MSOP8E.................................. 80...... 12... oC/W Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7 4-layer board. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 2 MP2007 – 3A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR ELECTRICAL CHARACTERISTICS VDRV = 5V, TA = +25oC, unless otherwise noted. Parameters Symbol VDRV Operating Voltage VDRV VDRV Shut down current IDRV_SD VDRV Operation Current VDRV UVLO Upper Threshold VDRV UVLO Hysteresis Thermal Trip Point Hysteresis VDDQ UVLO Upper Threshold VTT with Respect to 1/2VREF Test Condition Min Typ Max Unit - 4.5 5.0 5.5 V - 0.2 1.0 - 1.3 4.1 0.35 150 25 3 4.4 - μA mA V V o C o C - 0.9 1.3 V -30 - - - - 30 -30 - - - - 30 40 55 75 kΩ VDRV = 5.0 V, VDDQ=0V IDRV VEN_H, VTT=0.75V VDRVUV+ Rising Edge VDRVUVHYS TSD TSDHYS VDDQUV+ dVTT0 Rising Edge; hysteresis = 55mV 1/2VREF – VTT, VREF = 1.8 V, IVTT = 0 to 3 A (Sink Current) IVTT = 0 to –3 A (Source Current) 1/2VREF – VTT, VREF = 1.5 V, IVTT = 0 to 3 A (Sink Current) IVTT = 0 to –3 A (Source Current) mV REF Input Resistance REF_R Source Current Limit ILIMVTsrc - - 3.5 - A Sink Current Limit ILIMVTsnk - - 3.5 - A Soft−Start Source Current Limit ILIMVTSS - - 1.0 - A Maximum Soft−Start Time tssvttmax VREF=1.8V, VDRV=5V - 9 - VREF=1.5V, VDRV=5V - 7 - VREF = 1.8 V or 1.5 V 1/2VREF – VTTR, VREF = 1.8 V, IVTTR = 0 mA to 15 mA 1/2VREF – VTTR, VREF = 1.5 V, IVTTR = 0 mA to 15 mA 15 - - mA -18 - 18 mV -15 - 15 mV VTTREF Source Current VTTREF Accuracy Referred to 1/2VREF IVTTR dVTTR VREF = 1.8 V mV us VEN Pin Threshold High VEN_H - 1.4 - - V VEN Pin Threshold Low VEN_L - - - 0.5 V VEN = 5.0 V - - 1.0 μA VEN Pin Input Current MP2007 Rev. 0.9 7/23/2009 IIN_VEN www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 3 MP2007 – 3A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR PIN FUNCTIONS Pin # Name 1 DDQ 2 VTT GND Exposed Pad 3 Description Power input for VTT regulator. Connect to GND through 10uF ceramic capacitor. It is normally connected to the VDDQ of DDR memory rail. Power output for the VTT LDO. The exposed pad and GND pin must be connected to the same ground plane. Kelvin sensed feedback signal. 4 VTTSEN 5 VDRV 6 REF LDO signal input for generating VDDQ/2 reference. 7 EN VTT regulator enable input. High to enable the chip. 8 VTTREF MP2007 Rev. 0.9 7/23/2009 Chip bias Voltage. Buffered output for the system. The receiving end of the DDR memory cells needs this signal for their input comparator. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 4 MP2007 – 3A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR TYPICAL PERFORMANCE CHARACTERISTICS C1=C2=C3=10uF, C4 =C6=0.1uF, C7=4.7uF, VDRV=5V, TA=25ºC unless otherwise noted. 1.37 1.02 0.87 1.33 0.98 0.83 1.29 0.94 0.79 1.25 1.21 VDDQ=2.5V 0.9 0.86 VDDQ=1.8V 1.17 VDDQ=2.5V 0.75 0.71 VDDQ=1.8V 1 2 3 4 5 -5 -4 -3 -2 -1 0 Source Load Transient VDDQ=VREF=1.8V, V TT=0.9V 1 2 3 4 -5 -4 -3 -2 -1 0 5 ITT 1A/div. ITT 2A/div. VTTREF 2V/div. VTTREF 2V/div. VTT 0.5V/div. ITT 1A/div. MP2007 Rev. 0.9 7/23/2009 Startup Through Down Sink Over Current Protection VDDQ=VREF=1.8V, V TT=0.9V VDDQ=VREF=2.5V, V TT=1.25V,VSINK=2.5V VDDQ 2V/div VTTREF 1V/div. VTT 1V/div. ITT 2A/div. VTT 0.5V/div. ITT 1A/div. 4ms/div 5 400ms/div 400us/div VDDQ 2V/div 4 VDDQ=VREF=2.5V, V TT=1.25V ITT 1A/div. VDDQ 2V/div 3 Source Over Current Protection VIN 2V/div. VTTREF 1V/div. VTT 1V/div. VDDQ=VREF=1.8V, V TT=0.9V 2 VDDQ=VREF=2.5V, V TT=0.9V, VSINK=1.8V VTT 10mV/div. Power Ramp Up 1 Sink Load Transient VTT 10mV/div. 20us/div VDDQ=1.5V 0.67 0.82 -5 -4 -3 -2 -1 0 VDDQ=1.8V 10ms/div 1s/div www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 5 MP2007 – 3A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR TYPICAL PERFORMANCE CHARACTERISTICS (continued) C1=C2=C3=10uF, C4 =C6=0.1uF, C7=4.7uF, VDRV=5V, TA=25ºC unless otherwise noted. Enable On Enable Off VDDQ=VREF=2.5V, VTT=1.25V VDDQ=VREF=2.5V, VTT=1.25V Input Supply Current vs. Temp VDDQ=VREF=1.8V, VTT=0.9V VDDQ 2V/div. VEN 2V/div. VDDQ 2V/div. VEN 2V/div. VTT 10V/div. VTT 10V/div. ITT 1A/div. ITT 1A/div. INPUT CURRENT ( mA ) 2.0 1.6 1.2 0.8 0.4 0.0 200us/div 20us/div Short Circuit Short Circuit Recovery VDDQ=VREF=2.5V, VTT=1.25V VDDQ=VREF=2.5V, VTT=1.25V -40 -10 20 50 80 110 140 Shut Down Input Current vs. Temp VDDQ=VREF=.8V, VTT=0V 0.45 0.40 0.35 0.30 VTT 0.5V/div. 0.25 VTT 0.5V/div. 0.20 0.15 ITT 2A/div. 0.10 ITT 2A/div. 0.05 . 20us/div MP2007 Rev. 0.9 7/23/2009 100us/div 0.00 -40 -10 20 50 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 80 110 140 6 MP2007 – 3A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR DETAILED OPERATING DESCRIPTION VREF VDDQ DDQ REF Soft-Start 5V VDRV VDRV UVLO DDQ DDQ UVLO VTT Regulation & Deadband Control Current Limiter VTT VTT Current Limiter GND VTTSEN VTTSEN VTTREF VEN VTTREF EN Figure 1—Functional Block Diagram Control Logic The internal control logic is powered by VDRV. The IC is enabled whenever both VDDQ UVLO and VDRV UVLO are pulled low. VTTREF output begins to track VREF/2. When the VTTEN pin is high, the VTT regulator is activated. VTTREF Output The VTTREF output tracks VREF/2 with ±2% accuracy. It has source current capability of up to 15 mA. VTTREF should be bypassed to analog ground of the device by 1.0μF ceramic capacitor for stable operation. The VTTREF is turned on as long as both VDDQ and VDRV are higher the UVLO threshold. VTTREF features a soft-start and tracks VREF/2. of the VTT local bypass capacitor for load. VDDQ UVLO Protection For VDDQ undervoltage lockout (UVLO) protection, the MP2007 monitors VDDQ voltage. When the VDDQ voltage is lower than UVLO threshold voltage, the VTT regulator is shut off. Current Protection of VTT Active Terminator To provide protection for the internal FETs, over current limit(OCL) of 3A is implemented. The LDO has a constant overcurrent limit (OCL) at 3.5 A. This trip point is reduced to 1.0 A if the output voltage drops below 1/3 of the target voltage. Output Voltages Sensing The VTT output voltage is sensed across the VTTSEN and GND pins. The VTTSEN should be connected to the VTT regulation point, which is usually the VTT local bypass capacitor, via a direct sense trace. The GND should be connected via a direct sense trace to the ground MP2007 Rev. 0.9 7/23/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 7 MP2007 – 3A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR Thermal Consideration of VTT Active Terminator The VTT terminator is designed to handle large transient output currents. If large currents are required for very long duration, then care should be taken to ensure the maximum junction temperature is not exceeded. The 8-pin MSOP with ExposedPAD has a thermal resistance of 50oC/W (dependent on air flow, and PCB design). In order to take full advantage of the thermal capability of this package, the exposed pad should be soldered directly onto the PCB ground layer to allow good thermal contact. It is recommended that the PCB should have 10 to 15 vias with 0.3mm drill size underneath the exposed thermal pad connecting all the ground layers MP2007 Rev. 0.9 7/23/2009 Supply Voltage Undervoltage Monitor The IC continuously monitors VDRV. If VDRV is set higher than its preset threshold and VTTEN is high too, the IC will start up. Thermal Shutdown When the chip junction temperature exceeds 150oC, the entire IC is shutdown. The IC resumes normal operation only after the junction temperature dropping below 125oC. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 8 MP2007 – 3A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR APPLICATION INFORMATION Input Capacitor Depending on the trace impedance from the power supply to the part, transient increase of source current is supplied mostly by the charge from the VDDQ input capacitor. Use a 10μF (or more) ceramic capacitor to supply this transient charge. Provide more input capacitance as more output capacitance is used at VTT. In general, use 1/2 COUT for input. Output Capacitor For stable operation, total capacitance of the VTT output terminal can be equal or greater than 20μF. Attach two 10μF ceramic capacitors in parallel to minimize the effect of ESR and ESL. If the ESR is greater than 10mΩ, insert an R-C filter between the output and the VTTSEN input to achieve loop stability. The R-C filter time constant should be almost the same or slightly lower than the time constant of the output capacitor and its ESR. VDRV Capacitor Add a ceramic capacitor with a value between 1.0μF and 4.7μF placed close to the VDRV pin, to stabilize 5V from any parasitic impedance from the supply. Thermal design As the MP2007 is a linear regulator, the VTT current flow in both source and sink directions generate power dissipation from the device. In the source phase, the potential difference between VDDQ and VTT times VTT current becomes the power dissipation, Psource=(VDDQ-VTT) x Isource In this case, if VDDQ is connected to an alternative power supply lower than VDDQ voltage, power loss can be decreased. For the sink phase, VTT voltage is applied across the internal LDO regulator, and the power dissipation Psink is: Psink=VTT x Isink The device does not sink and source the current at the same time and source/sink current varies rapidly with time. The actual power dissipation to be considered for thermal design is an average of the above values over time. MP2007 Rev. 0.2 7/23/2009 Another power consumption is the current used for internal control circuitry from VDDQ supply. This power needs to be effectively dissipated from the package. PCB Layout Guidelines Good PCB layout design is critical to ensure high performance and stable operation of the DDR power controller. The following items must be considered when preparing PCB layout: 1. All high−current traces must be kept as short and wide as possible to reduce power loss. High−current traces are the trace from the input voltage terminal to VDDQ pin, the trace from the VTT output terminal to the load, the trace from the input ground terminal to the VTT output ground terminal, and the trace from VTT output ground terminal to the GND pin. Power handling and heaksinking of high−current traces can be improved by also routing the same high−current traces in the other layers by the same path and joining them together with multiple vias. 2. To ensure the proper function of the device, separated ground connections should be used for different parts of the application circuit according to their functions. The VTT output capacitor ground should be connected to the GND pin first with a short trace, it is then connected to the ground plane of GND. The input capacitor ground, the VTT output capacitor ground, the VDDQ decoupling capacitor ground should be connected to the GND plane. 3. The thermal pad of the 8-pin MSOP package should to be connected to GND for better thermal performance. It is recommended to use a PCB with 1 oz or 2oz copper foil. 4. A separate sense trace should be used to connect the VTT point of regulation, which is usually the local bypass capacitor for load, to the VTTSEN pin. 5. Separate sense trace should be used to connect the VREF point of regulation to the VTTREF pin to ensure the accuracy of the reference voltage to VTT. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 9 MP2007 – 3A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR 6. VDDQ should be connected to VREF Input with wide and short trace if VDDQ is used as the sourcing supply for VTT. An input capacitor of at least 10μF should be added close to the VDDQ MP2007 Rev. 0.2 7/23/2009 pin and bypassed to GND if external voltage supply is used as the VTT sourcing supply. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 10 MP2007 – 3A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR PACKAGE INFORMATION MSOP8E (EXPOSED PAD) 0.087(2.20) 0.099(2.50) 0.114(2.90) 0.122(3.10) 5 8 0.114(2.90) 0.122(3.10) PIN 1 ID (NOTE 5) 0.187(4.75) 0.199(5.05) 0.062(1.58) 0.074(1.88) Exposed Pad 0.010(0.25) 0.014(0.35) 4 1 0.0256(0.65)BSC BOTTOM VIEW TOP VIEW GAUGE PLANE 0.010(0.25) 0.030(0.75) 0.037(0.95) 0.043(1.10)MAX SEATING PLANE 0.002(0.05) 0.006(0.15) FRONT VIEW NOTE: 0.181(4.60) 0.040(1.00) 0.016(0.40) 0.016(0.40) 0.026(0.65) SIDE VIEW 0.100(2.54) 0.075(1.90) 0o-6o 0.004(0.10) 0.008(0.20) 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.004" INCHES MAX. 5) PIN 1 IDENTIFICATION HAS HALF OR FULL CIRCLE OPTION. 6) DRAWING MEETS JEDEC MO-187, VARIATION AA-T. 7) DRAWING IS NOT TO SCALE. 0.0256(0.65)BSC RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2007 Rev. 0.9 7/23/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 11