Spec. No. : C447C3 Issued Date : 2011.09.19 Revised Date : Page No. : 1/6 CYStech Electronics Corp. ESD protected N-CHANNEL MOSFET MTNK3C3 BVDSS ID RDSON 20V 100mA 3Ω Description • Low voltage drive, 1.8V. • Easy to use in parallel. • High speed switching. • ESD protected device. • Pb-free package. Symbol Outline MTNK3C3 SOT-523 D G G：Gate S：Source D：Drain S Absolute Maximum Ratings (Ta=25°C) Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Total Power Dissipation ESD susceptibility Operating Junction and Storage Temperature Range Thermal Resistance, Junction-to-Ambient Symbol BVDSS VGS ID IDM PD Tj Rth,ja Limits 20 ±8 100 400 *1 150 *2 350 *3 -55~+150 833 Unit V V mA mA mW V °C °C/W Note : *1. Pulse Width ≤ 300μs, Duty cycle ≤2%. *2. When device mounted on recommended land pattern. *3. Human body model, 1.5kΩ in series with 100pF. MTNK3C3 CYStek Product Specification Spec. No. : C447C3 Issued Date : 2011.09.19 Revised Date : Page No. : 2/6 CYStech Electronics Corp. Electrical Characteristics (Ta=25°C) Symbol Static BVDSS VGS(th) IGSS IDSS Min. Typ. Max. Unit 20 0.5 100 1.7 3.5 - 1.0 ±1 500 3 6 - V V μA nA 23 7.7 5.8 - RDS(ON) GFS Dynamic Ciss Coss Crss Source-Drain Diode *VSD - Test Conditions mS VGS=0, ID=100μA VDS=VGS, ID=250μA VGS=±8V, VDS=0 VDS=20V, VGS=0 VGS=4.5V, ID=100mA VGS=1.8V, ID=20mA VDS=5V, ID=100mA 50 25 5 pF VDS=10V, VGS=0, f=1MHz 1 V VGS=0V, IS=10mA Ω *Pulse Test : Pulse Width ≤300μs, Duty Cycle≤2% Ordering Information Device MTNK3C3 MTNK3C3 Package SOT-523 (Pb-free) Shipping Marking 3000 pcs / Tape & Reel K3 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C447C3 Issued Date : 2011.09.19 Revised Date : Page No. : 3/6 Typical Characteristics Typical Output Characteristics Typical Transfer Characteristics 0.8 0.7 Drain Current - ID(A) 0.5 4.5V 0.7 4.0V 3.5V 0.6 Drain Current -ID(A) 5V 0.6 3V 0.4 2.5V 0.3 2.0V 0.2 1.8V VGS=1.5V 0.1 VDS=3V 0.5 0.4 0.3 0.2 0.1 0 0 0 1 2 3 Drain-Source Voltage -VDS(V) 0 4 1 5 6 Static Drain-Source On-State Resistance vs Gate-Source Voltage Static Drain-Source On-State resistance vs Drain Current 10 Static Drain-Source On-State Resistance-RDS(ON)(Ω) Static Drain-Source On-State Resistance-RDS(on)(Ω) 7 VGS=1.8V VGS=4.5V 1 0.001 6 5 ID=100mA 4 3 2 ID=20mA 1 0 0.01 0.1 Drain Current-ID(A) 0 1 Reverse Drain Current vs Source-Drain Voltage 2 4 6 8 Gate-Source Voltage-VGS(V) 10 Capacitance vs Drain-to-Source Voltage 1 100 0.9 0.8 Capacitance---(pF) Source-Drain Voltage-VSD(V) 2 3 4 Gate-Source Voltage-VGS(V) 0.7 0.6 0.5 0.4 Ciss C oss 10 Crss 0.3 0.2 1 0.1 0 MTNK3C3 0.1 0.2 0.3 Reverse Drain Current -IDR(A) 0.4 0.1 1 10 Drain-Source Voltage -VDS(V) 100 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C447C3 Issued Date : 2011.09.19 Revised Date : Page No. : 4/6 Reel Dimension Carrier Tape Dimension MTNK3C3 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C447C3 Issued Date : 2011.09.19 Revised Date : Page No. : 5/6 Recommended wave soldering condition Product Pb-free devices Peak Temperature 260 +0/-5 °C Soldering Time 5 +1/-1 seconds Recommended temperature profile for IR reflow Profile feature Average ramp-up rate (Tsmax to Tp) Preheat −Temperature Min(TS min) −Temperature Max(TS max) −Time(ts min to ts max) Time maintained above: −Temperature (TL) − Time (tL) Peak Temperature(TP) Time within 5°C of actual peak temperature(tp) Ramp down rate Time 25 °C to peak temperature Sn-Pb eutectic Assembly Pb-free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 240 +0/-5 °C 217°C 60-150 seconds 260 +0/-5 °C 10-30 seconds 20-40 seconds 6°C/second max. 6 minutes max. 6°C/second max. 8 minutes max. Note : All temperatures refer to topside of the package, measured on the package body surface. MTNK3C3 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C447C3 Issued Date : 2011.09.19 Revised Date : Page No. : 6/6 SOT-523 Dimension Marking: C A 3 D 1 B K3 Date Code □□ Device Code 2 G F H I E 3-Lead SOT-523 Plastic Surface Mounted Package CYStek Package Code: C3 J K Style: Pin 1.Gate 2.Source 3.Drain L N M O *: Typical Inches Min. Max. 0.0079 0.0157 0.0591 0.0669 0.0118 0.0197 0.0295 0.0335 0.0118 0.0197 0.0039 0.0118 0.0039 0.0118 *0.0197 - DIM A B C D E F G H Millimeters Min. Max. 0.20 0.40 1.50 1.70 0.30 0.50 0.75 0.85 0.30 0.50 0.10 0.30 0.10 0.30 *0.50 - DIM I J K L M N O Inches Min. Max. *0.0197 0.0610 0.0650 0.0276 0.0315 0.0224 0.0248 0.0020 0.0059 0.0039 0.0118 0 0.0031 Millimeters Min. Max. *0.50 1.55 1.65 0.70 0.80 0.57 0.63 0.05 0.15 0.10 0.30 0 0.08 Notes: 1.Controlling dimension: millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYStek sales office. Material: • Lead: Pure tin plated. • Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0 Important Notice: • All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek. • CYStek reserves the right to make changes to its products without notice. • CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems. • CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. MTNK3C3 CYStek Product Specification