PD-95114
SMPS MOSFET
IRF730AS/LPbF
HEXFET® Power MOSFET
Applications
l Switch Mode Power Supply (SMPS)
l Uninterruptable Power Supply
l High speed power switching
l Lead-Free
Benefits
l Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
l Effective Coss Specified (See AN1001)
VDSS
Rds(on) max
ID
1.0Ω
5.5A
400V
D 2 Pak
TO-262
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
dv/dt
TJ
TSTG
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
5.5
3.5
22
74
0.6
± 30
4.6
-55 to + 150
Units
A
W
W/°C
V
V/ns
°C
300 (1.6mm from case )
Typical SMPS Topologies:
l
l
Single Transistor Flyback Xfmr. Reset
Single Transistor Forward Xfmr. Reset
(Both US Line input only).
Notes
through are on page 10
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1
3/16/04
IRF730AS/LPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
V(BR)DSS
IDSS
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Min. Typ. Max. Units
Conditions
400 ––– –––
V
VGS = 0V, ID = 250µA
–––
0.5 ––– V/°C Reference to 25°C, ID = 1mA
––– ––– 1.0
Ω
VGS = 10V, ID = 3.3A
2.0
––– 4.5
V
VDS = VGS, ID = 250µA
––– ––– 25
VDS = 400V, VGS = 0V
µA
––– ––– 250
VDS = 320V, VGS = 0V, TJ = 125°C
––– ––– 100
VGS = 30V
nA
––– ––– -100
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
Min.
3.1
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
–––
–––
–––
10
22
20
16
600
103
4.0
890
30
45
Max. Units
Conditions
–––
S
VDS = 50V, ID = 3.3A
22
ID = 3.5A
5.8
nC
VDS = 320V
9.3
VGS = 10V, See Fig. 6 and 13
–––
VDD = 200V
–––
ID = 3.5A
ns
–––
R G = 12Ω
–––
R D = 57Ω,See Fig. 10
–––
VGS = 0V
–––
VDS = 25V
–––
pF
ƒ = 1.0MHz, See Fig. 5
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 320V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 320V
Avalanche Characteristics
Parameter
EAS
IAR
EAR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Typ.
Max.
Units
–––
–––
–––
290
5.5
7.4
mJ
A
mJ
Typ.
Max.
Units
–––
–––
1.7
40
°C/W
Thermal Resistance
Parameter
RθJC
RθJA
Junction-to-Case
Junction-to-Ambient ( PCB Mounted, steady-state)*
Diode Characteristics
IS
ISM
VSD
trr
Qrr
ton
2
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 5.5
showing the
A
G
integral reverse
––– –––
22
S
p-n junction diode.
––– ––– 1.6
V
TJ = 25°C, IS = 5.5A, VGS = 0V
––– 370 550
ns
TJ = 25°C, IF = 3.5A
––– 1.6 2.4
µC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRF730AS/LPbF
100
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
10
1
0.1
4.5V
20µs PULSE WIDTH
TJ = 25 °C
0.01
0.1
1
10
10
1
4.5V
0.1
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TJ = 150 ° C
TJ = 25 ° C
V DS = 50V
20µs PULSE WIDTH
5.0
6.0
7.0
8.0
9.0
10.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
100
Fig 2. Typical Output Characteristics
100
0.1
4.0
1
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1
20µs PULSE WIDTH
TJ = 150 °C
0.01
0.1
100
VDS , Drain-to-Source Voltage (V)
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
TOP
5.9A
ID = 5.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF730AS/LPbF
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
C, Capacitance(pF)
10000
Coss = Cds + Cgd
1000
Ciss
Coss
100
10
VGS , Gate-to-Source Voltage (V)
20
100000
ID =5.5
5.9A
16
VDS = 320V
VDS = 200V
VDS = 80V
12
8
4
Crss
0
1
1
10
100
FOR TEST CIRCUIT
SEE FIGURE 13
0
5
1000
10
15
20
25
QG , Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
OPERATION IN THIS AREA LIMITED
BY RDS(on)
10us
10
TJ = 150 ° C
TJ = 25 ° C
1
0.1
0.4
I D , Drain Current (A)
ISD , Reverse Drain Current (A)
100
V GS = 0 V
0.6
0.8
1.0
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10
100us
1ms
1
10ms
0.1
1.2
TC = 25 °C
TJ = 150 °C
Single Pulse
10
100
1000
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF730AS/LPbF
6.0
VGS
5.0
ID , Drain Current (A)
RD
V DS
D.U.T.
RG
+
- VDD
4.0
10V
3.0
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
2.0
Fig 10a. Switching Time Test Circuit
1.0
VDS
90%
0.0
25
50
75
100
125
150
TC , Case Temperature ( °C)
Fig 9. Maximum Drain Current Vs.
Case Temperature
10%
VGS
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
1 D = 0.50
0.20
0.10
0.1
PDM
0.05
0.02
0.01
0.01
0.00001
t1
t2
SINGLE PULSE
(THERMAL RESPONSE)
0.0001
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF730AS/LPbF
700
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
EAS , Single Pulse Avalanche Energy (mJ)
15V
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
600
BOTTOM
400
300
200
100
0
QG
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
V DSav , Avalanche Voltage ( V )
QGD
Charge
75
100
125
150
600
590
580
570
560
550
.3µF
D.U.T.
+
V
- DS
540
0.0
VGS
1.0
2.0
3.0
4.0
5.0
6.0
IAV , Avalanche Current ( A)
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
50
Starting TJ , Junction Temperature ( °C)
610
VG
12V
25
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QGS
ID
2.5A
3.5A
5.5A
500
I AS
10 V
TOP
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
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IRF730AS/LPbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
RG
•
•
•
•
Driver Gate Drive
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Period
D=
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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7
IRF730AS/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information (Lead-Free)
T H IS IS AN IR F 5 3 0 S W IT H
L OT CODE 80 2 4
AS S E M B L E D ON W W 0 2, 20 00
IN T H E AS S E M B L Y L IN E "L "
IN T E R N AT IO N AL
R E C T IF IE R
L OGO
N ote: "P " in as s em bly lin e
po s itio n in dicates "L ead-F r ee"
P AR T N U M B E R
F 5 30 S
AS S E M B L Y
L O T CO D E
D AT E C O D E
Y E AR 0 = 2 0 0 0
W E E K 02
L IN E L
OR
IN T E R N AT IO N AL
R E C T IF IE R
L O GO
AS S E M B L Y
L OT COD E
8
P AR T N U M B E R
F 530S
D AT E CO D E
P = D E S IG N AT E S L E AD -F R E E
P R O D U C T (O P T IO N AL )
Y E AR 0 = 2 0 0 0
W E E K 02
A = AS S E M B L Y S IT E CO D E
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IRF730AS/LPbF
TO-262 Package Outline
IGBT
1- GATE
2- COLLECTOR
3- EMITTER
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789
AS SEMBLED ON WW 19, 1997
IN T HE ASS EMBLY LINE "C"
Note: "P" in as s embly line
pos ition indicates "Lead-Free"
INT ERNAT IONAL
RECT IFIER
LOGO
ASS EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
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PART NUMBER
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
WEEK 19
A = AS S EMBLY S ITE CODE
9
IRF730AS/LPbF
D2Pak Tape & Reel Infomation
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
1.65 (.065)
0.368 (.0145)
0.342 (.0135)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Starting TJ = 25°C, L = 19mH
RG = 25Ω, IAS = 5.5A. (See Figure 12)
ISD ≤ 5.5A, di/dt ≤ 90A/µs, VDD ≤ V(BR)DSS,
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Uses IRF730A data and test conditions
TJ ≤ 150°C
* When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
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10
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