APW7120A 5V to 12V Supply Voltage, 8-PIN, Synchronous Buck PWM Controller Features General Description • Operating with Single 5~12V Supply Voltage or The APW7120A is a fixed 300kHz frequency, voltage mode, Two Supply Voltages and synchronous PWM controller. The device drives two low cost N-channel MOSFETs and is designed to work • Drive Dual Low Cost N-Channel MOSFETs with single 5~12V or two supply voltage(s), providing excellent regulation for load transients. - Adaptive Shoot-Through Protection • Built-in Feedback Compensation The APW7120A integrates controls, monitoring and protection functions into a single 8-pin package to provide a - Voltage-Mode PWM Control - 0~100% Duty Ratio low cost and perfect power solution. A power-on-reset (POR) circuit monitors the VCC supply - Fast Transient Response • ±2% 0.8V Reference voltage to prevent wrong logic controls. An internal 0.8V reference provides low output voltage down to 0.8V for - Over Line, Load Regulation, and Operating further applications. An built-in digital soft-start with fixed soft-start interval prevents the output voltage from over- Temperature • • • • • Programmable Over-Current Protection shoot as well as limiting the input current. The controller’s over-current protection monitors the output current by - Using RDS(ON) of Low-Side MOSFET Hiccup-Mode Under-Voltage Protection using the voltage drop across the low-side MOSFET’s RDS(ON), eliminating the need of a current sensing resistor. 118% Over-Voltage Protection Adjustable Output Voltage Additional under voltage and over voltage protections monitor the voltage on FB pin for short-circuit and over- Small Converter Size - 300kHz Constant Switching Frequency voltage protections. The over-current protection cycles the soft-start function until 4 over-current events are counted. - Small SOP-8 Package • • • Pulling and holding the voltage on OCSET pin below 0.15V with an open drain device shuts down the controller. Built-In Digital Soft-Start Shutdown Control Using an External MOSFET Lead Free and Green Devices Available Pin Cinfiguration (RoHS Compliant) Applications • • • Motherboard Graphics Card High Current, Up to 20A, DC-DC Converters BOOT 1 8 PHASE UGATE 2 7 OCSET GND 3 LGATE 4 5 VCC 6 FB SOP-8 (Top View) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 1 www.anpec.com.tw APW7120A Ordering and Marking Information APW7120A Package Code K : SOP-8 Operating Ambient Temperature Range E : -20 to 70 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device Assembly Material Handling Code Temperature Range Package Code APW7120A K : APW7120A XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VCC VBOOT (Note 1) Parameter Rating Unit VCC Supply Voltage (VCC to GND) -0.3 ~ 16 V BOOT Voltage (BOOT to PHASE) -0.3 ~ 16 V <400ns pulse width >400ns pulse width -5 ~ VBOOT+0.3 -0.3 ~ VBOOT+0.3 V <400ns pulse width >400ns pulse width -5 ~ VCC+0.3 -0.3 ~ VCC+0.3 V <400ns pulse width >400ns pulse width -10 ~ 30 -3 ~ 16 V UGATE Voltage (UGATE to PHASE) LGATE Voltage (LGATE to GND) PHASE Voltage (PHASE to GND) VI/O Input Voltage (OCSET, FB to GND) -0.3 ~ 7 Maximum Junction Temperature TSTG TSDR Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds V 150 o -65 ~ 150 o 260 o C C C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Typical Value Junction-to-Ambient Resistance in Free Air (Note 2) SOP-8 160 Unit o C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 2 www.anpec.com.tw APW7120A Recommended Operating Conditions (Note 3) Symbol Parameter VCC VCC Supply Voltage VOUT Converter Output Voltage VIN Converter Input Voltage IOUT Converter Output Current TA Ambient Temperature TJ Range Unit 4.5 ~ 13.2 V 0.8 ~ 70%VIN V 2.2 ~ 13.2 V 0 ~ 20 Junction Temperature A -20 ~ 70 o -20 ~ 125 o C C Note 3: Please refer to the typical application circuit. Electrical Characteristics Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V and TA = -20 ~ 70oC. Typical values are at TA = 25oC. Symbol Parameter Test Conditions APW7120A Unit Min. Typ. Max. - 2.1 6 mA - 1.5 4 mA SUPPLY CURRENT IVCC VCC Nominal Supply Current UGATE and LGATE Open VCC Shutdown Supply Current POWER-ON-RESET Rising VCC Threshold 3.8 4.1 4.4 V Hysteresis 0.1 0.45 0.6 V 250 300 350 kHz - 1.5 - VP-P - 0.8 - V OSCILLATOR FOSC ∆VOSC Free Running Frequency Ramp Amplitude REFERENCE VOLTAGE VREF Reference Voltage Measured at FB Pin Accuracy TA =-20~70°C -2.0 - +2.0 % Line Regulation VCC=12 ~ 5V - 0.05 0.5 % - 86 - dB ERROR AMPLIFIER DC Gain FP1 First Pole Frequency - 0.4 - Hz FZ Zero Frequency - 0.4 - kHz FP2 Second Pole Frequency - 430 - kHz Average UGATE Duty Range 0 - 70 % FB Input Current - - 0.1 µA 1.0 2.0 - A PWM CONTROLLER GATE DRIVERS UGATE Source TD VBOOT-PHASE =12V, VUGATE-PHASE =6V UGATE Sink VBOOT-PHASE =12V, VUGATE-PHASE=1V - 3.5 7 Ω LGATE Source VCC=12V, VLGATE=6V 1.0 1.9 - A LGATE Sink VCC=12V, VLGATE=1V - 2.6 5 Ω Dead-Time Guaranteed by Design - 40 100 ns Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 3 www.anpec.com.tw APW7120A Electrical Characteristics (Cont.) Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V and TA = -20 ~ 70oC. Typical values are at TA = 25oC. Symbol Parameter Test Conditions APW7120A Min. Typ. Max. 35 40 45 Unit PROTECTIONS IOCSET UVFB OCSET Current Source VPHASE=0V, Normal Operation µA Over-Current Reference Voltage TA =-20~70°C 0.37 0.4 0.43 V FB Under-Voltage Threshold VFB Falling 62 67 72 % - 45 - mV VFB Rising 114 118 122 % 2 3.8 5 ms Falling VOCSET 0.1 0.15 0.3 V - 40 - mV FB Under-Voltage Hysteresis Over-Voltage Threshold SOFT-START AND SHUTDOWN TSS Soft-Start Interval OCSET Shutdown Threshold OCSET Shutdown Hysteresis Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 4 www.anpec.com.tw APW7120A Typical Operating Characteristics Reference Voltage vs. Junction 350 Switching Frequency, FOSC (kHz) Reference Voltage, VREF (V) Temperature 0.812 0.810 0.808 0.806 0.804 0.802 0.800 0.798 0.796 0.794 0.792 0.790 0.788 -50 -25 0 25 50 75 100 Junction Temperature (oC) 340 330 320 310 300 290 280 270 260 250 -50 125 150 Switching Frequency vs. Junction Temperature -25 0 25 50 75 100 125 150 Junction Temperature (oC) VCC POR Threshold Voltage vs. Junction Temperature 45 4.4 44 4.3 VCC POR Threshold Voltage (V) OCSET Current, IOCSET (µA) OCSET Current vs. Junction Temperature 43 42 41 40 39 38 37 36 35 -50 -25 4.2 4.0 3.9 3.8 Falling VCC 3.7 3.6 3.5 3.4 -50 0 25 50 75 100 125 150 Junction Temperature (oC) Rising VCC 4.1 -25 0 25 50 75 100 125 150 Junction Temperature (oC) OCSET Shutdown Threshold Voltage (V) OCSET Shutdown Threshold Voltage vs. Junction Temperature 0.20 Falling VOCSET 0.18 0.16 0.14 0.12 0.10 -50 -25 0 25 50 75 100 125 150 Junction Temperature (oC) Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 5 www.anpec.com.tw APW7120A Operating Waveforms (Refer to the typical application circuit, VBAIS=VIN=+12V supplied by an ATX Power Supply) 1. Load Transient Response : IOUT = 0A -> 15A -> 0A - IOUT slew rate = ±7.5A/µs IOUT = 0A -> 15A IOUT = 0A -> 15A -> 0A IOUT = 15A -> 0A VOUT=1.8V VOUT VOUT 1 1 1 VOUT VUGATE VUGATE 3 3 VUGATE 3 15A IOUT Ch1 : VOUT, 100mV/Div, AC, Ch2 : IOUT, 10A/Div Ch3 : VUGATE, 20V/Div, DC Time : 5µs/Div BW = 20 MHz IOUT 0A 2 2 Ch1 : VOUT, 100mV/Div, AC, Ch2 : IOUT, 10A/Div Ch3 : VUGATE, 20V/Div, DC Time : 40µs/Div BW = 20 MHz IOUT 2 Ch1 : VOUT, 100mV/Div, AC, Ch2 : IOUT, 10A/Div Ch3 : VUGATE, 20V/Div, DC Time : 5µs/Div BW = 20 MHz 2. UGATE and LGATE Switching Waveforms Rising VUGATE Falling VUGATE IOUT = 15A VLGATE VUGATE VLGATE VUGATE 1,2 1,2 Ch1 : VUGATE, 5V/Div, DC Time : 20ns/Div Ch2 : VLGATE, 2V/Div, DC BW = 500 MHz Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 Ch1 : VUGATE, 5V/Div, DC Ch2 : VLGATE, 2V/Div, DC Time : 20ns/Div BW = 500 MHz 6 www.anpec.com.tw APW7120A Operating Waveforms (Cont.) (Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply) 3. Powering ON / OFF Powering ON VCC=VIN=5V RL=0.12Ω Powering OFF VCC VCC=VIN=5V RL=0.12Ω VCC 1 1 IL IL 3 3 VOUT 2 VOUT 2 Ch1 : VCC, 2V/Div, DC Ch3 : IL, 10A/Div, DC BW = 20 MHz Ch2 : VOUT, 1V/Div, DC Time : 5ms/Div Ch1 : VCC, 2V/Div, DC Ch3 : IL, 10A/Div, DC BW = 20 MHz Powering ON VCC=VIN=12V RL=0.12Ω Ch2 : VOUT, 1V/Div, DC Time : 10ms/Div Powering OFF VCC=VIN=12V RL=0.12Ω VCC VCC 1 1 IL IL 3 3 VOUT VOUT 2 2 Ch1 : VCC, 5V/Div, DC Ch3 : IL, 10A/Div, DC BW = 20 MHz Ch1 : VCC, 5V/Div, DC Ch3 : IL, 10A/Div, DC BW = 20 MHz Ch2 : VOUT, 1V/Div, DC Time : 5ms/Div Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 7 Ch2 : VOUT, 1V/Div, DC Time : 10ms/Div www.anpec.com.tw APW7120A Operating Waveforms (Cont.) (Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply) 4. Enabling and Shutting Down Enabling by Releasing OCSET Pin 3 Shutting Down by Pulling OCSET Low VOCSET 3 VOCSET 2 VUGATE 2 VUGATE VOUT 1 VOUT 1 IOUT=2A Ch1 : VOUT, 1V/Div, DC Ch2 : VUGATE, 20V/Div, DC Ch3 : VOCSET, 2V/Div, DC Time : 2ms/Div BW = 20 MHz Ch1 : VOUT, 1V/Div, DC Ch3 : VOCSET, 2V/Div, DC BW = 20 MHz Ch2 : VUGATE, 20V/Div, DC Time : 2ms/Div 5. Over-Current Protection No Connecting a shutdown MOSFET at OCSET Pin Connecting a shutdown MOSFET (2N7002) at OCSET Pin ROCSET=15k APM2512 ROCSET=15k APM2512 VOUT 1 IL 2 Ch1 : VOUT, 1V/Div, DC Time : 5ms/Div IL 2 Ch2 : IL, 10A/Div, DC BW = 20 MHz Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 VOUT 1 Ch1 : VOUT, 1V/Div, DC Time : 5ms/Div 8 Ch2 : IL, 10A/Div, DC BW = 20 MHz www.anpec.com.tw APW7120A Operating Waveforms (Cont.) (Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply) 6. OCSET Voltage RC Delay No Connecting a shutdown MOSFET at OCSET Pin Connecting a shutdown MOSFET (2N7002) at OCSET Pin VOCSET VOCSET IL IL OCP 1,2 1,2 CProber=8pF Ch1 : VOCSET, 0.5V/Div, DC Time : 2µS/Div Ch2 : IL, 10A/Div, DC BW = 20 MHz OCP CProber=8pF C2N7002=44pF (measured) Ch1 : VOCSET, 0.5V/Div, DC Time : 2µ S/Div Ch2 : IL, 10A/Div, DC BW = 20 MHz 7. Short-Circuit Test 6. OCSET Voltage RC Delay Connecting a shutdown MOSFET (APM2322) at OCSET Pin Shorted by a wire IL OCP OCP OCP OCP VOUT 1 UVP VOCSET 1,2 CProber=8pF CAPM2322 =89pF (measured) IL OCP 2 Ch1 : VOCSET, 0.5V/Div, DC Ch2 : IL, 10A/Div, DC BW = 20 MHz Time : 2µS/Div Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 Ch1 : VOUT, 1V/Div, DC Time : 5ms/Div 9 Ch2 : IL, 10A/Div, DC BW = 20 MHz www.anpec.com.tw APW7120A Pin Description PIN FUNCTION NO. NAME 1 BOOT This pin provides ground referenced bias voltage to the high-side MOSFET driver. A bootstrap circuit with a diode connected to 5~12V is used to create a voltage suitable to drive a logic-level N-channel MOSFET. 2 UGATE Connect this pin to the high-side N-channel MOSFET gate. This pin provides gate drive for the high-side MOSFET. 3 GND The GND terminal provides return path for the IC bias current and the low-side MOSFET driver pull-low current. Connect the pin to the system ground via very low impedance layout on PCBs. 4 LGATE Connect this pin to the low-side N-channel MOSFET gate. This pin provides gate drive for the low-side MOSFET. 5 VCC Connect this pin to a 5~12V supply voltage. This pin provides bias supply for the control circuitry and the low-side MOSFET driver. The voltage at this pin is monitored for the Power-On-Reset (POR) purpose. FB This pin is the inverting input of the internal Gm amplifier. Connect this pin to the output (VOUT) of the converter via an external resistor divider for closed-loop operation. The output voltage set by the resistor divider is determined using the following formula: R1 VOUT = 0.8V ⋅ ( 1 + ) (V) R2 where R1 is the resistor connected from VOUT to FB , and R2 is the resistor connected from FB to GND. The FB pin is also monitored for under and over-voltage events. 6 The OCSET is a dual-function input pin for over-current protection and shutdown control. Connect a resistor (ROCSET) from this pin to the Drain of the low-side MOSFET. This resistor, an internal 40µA current source (IOCSET), and the MOSFET on-resistance (RDSON) set the converter over-current trip level (IPEAK) according to the following formula: 7 OCSET IPEAK = 40µA ⋅ ROCSET - 0.4V RDSON (A) Pulling and holding this pin below 0.15V with an open drain device, with very low parasitic capacitor, shuts down the IC with floating output and also resets the over-current counter. Releasing OCSET pin initiates a new soft-start and the converter works again. 8 PHASE The pin provides return path for the high-side MOSFET driver pull-low current. Connect this pin to the high-side MOSFET source. Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 10 www.anpec.com.tw APW7120A Block Diagram VCC 3VCC 40µA OCSET Power-OnReset Regulator POR 3VCC 67%VREF 0.4V OC 2.5V Enable 0.15V Soft-Start and Fault Logic UV BOOT OV UGATE 118%VREF Inhibit Soft-Start PHASE Gate Control COMP FB PWM VREF 0.8V VCC Gm Amplifier LGATE FOSC 300kHz GND Oscillator Typical Application Circuit L1 1µH D1 1N4148 VBIAS VIN +5V/12V C5 1µF C2 0.1µF 1 C3, C4 820µF x2 +5/12V BOOT R4 2.2 UGATE 5 C1 1µF PHASE VCC U1 OCSET APW7120A 6 LGATE FB Q1 APM2512 2 8 7 L2 1.5µH R5 VOUT C6, C7 1000µF x2 1.8V/15A Q2 APM2512 4 GND 3 Shutdown R1 1.5k Q3 2N7002 R2 1.2k C8 0.1µF R3 200 C3, C4 : 820µF/16V , ESR=25mΩ C6, C7 : 1000µF/6.3V, ESR=30mΩ Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 11 www.anpec.com.tw APW7120A Function Description Power-On-Reset (POR) at low operating duty, but very much at high operating duty, like the RC delay curve. Due to load regulation or The APW7120A monitors the VCC voltage (VCC) for PowerOn-Reset function, preventing wrong logic operation dur- current-limit, heavy load normally reduces converter’s input voltage and increases the power loses. During heavy ing powering on. When the VCC voltage is ready, the APW7120A starts a start-up process and then ramps the load, the APW7120A regulates the output voltage by expending the duty. This rises up the OCP trip level at the output voltage up to the target voltage. same time. Soft-Start Under-Voltage Protection (UVP) The APW7120A has a built-in digital soft-start to control The under-voltage function monitors the FB voltage (VFB) to protect the converter against short-circuit conditions. the output voltage rise and limit the current surge at the start-up. During soft-start, an internal ramp connected to When the VFB falls below the falling UVP threshold (67% VREF), the APW7120A shuts off the converter. After a pre- the one of the positive inputs of the Gm amplifier rises up from 0V to 2V to replace the reference voltage (0.8V) until ceding delay, which starts at the beginning of the undervoltage shutdown, the APW7120A initiates a new soft- the ramp voltage reaches the reference voltage. The softstart interval is about 3.2ms typical, independent of the start to resume regulating. The under-voltage protection shuts off and then re-starts the converter repeatedly with- converter’s input and output voltages. Over-Current Protection (OCP) out latching. The function is disabled during soft-start process. The over-current function protects the switching converter against over-current or short-circuit conditions. The controller senses the inductor current by detecting the drain- Over-Voltage Protection (OVP) The over-voltage protection monitors the FB voltage to prevent the output from over-voltage. When the output to-source voltage, product of the inductor’s current and the on-resistance, of the low-side MOSFET during it’s on- voltage rises to 118% of the nominal output voltage, the APW7120A turns on the low-side MOSFET until the out- state. This method enhances the converter’s efficiency and reduces cost by eliminating a current sensing put voltage falls below the OVP threshold, regulating the output voltage around the OVP thresholds. resistor. A resistor (ROCSET), connected from the OCSET to the lowside MOSFET’s drain, programs the over-current trip level. An internal 40µA (typical) current source flowing through Adaptive Shoot-Through Protection The gate driver incorporates adaptive shoot-through pro- the ROCSET develops a voltage (VROCSET) across the ROCSET. When the VOCSET (VROCSET+ VDS of the low-side MOSFET) is tection to high-side and low-side MOSFETs from conducting simultaneously and shorting the input supply. This less than the internal over-current reference voltage (0. 4V, typical), the IC shuts off the converter and then ini- is accomplished by ensuring the falling gate has turned off one MOSFET before the other is allowed to rise. tiates a new soft-start process. After 4 over-current events are counted, the device turns off both high-side and low- During turn-off of the low-side MOSFET, the LGATE voltage is monitored until it reaches a 1.5V threshold, at which side MOSFETs and the converter’s output is latched to be floating. time the UGATE is released to rise after a constant delay. During turn-off of the high-side MOSFET, the UGATE-to- Please pay attention to the RC delay effect. It causes the OCP trip level to be the function of the operating PHASE voltage is also monitored until it reaches a 1.5V threshold, at which time the LGATE is released to rise duty. The parasitic capacitance (including the capacitance inside the OCSET, external PCB trace capacitance and after a constant delay. the COSS of the shutdown MOSFET) must be minimized, especially selecting a shutdown MOSFET with very small COSS. The OCP trip level follows the duty to increase a little Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 12 www.anpec.com.tw APW7120A Function Description (Cont.) Shutdown Control Pulling the OCSET voltage below 0.15V by an open drain transistor, shown in typical application circuit, shuts down the APW7120A PWM controller. In shutdown mode, the UGATE and LGATE are pulled to PHASE and GND respectively, the output is floating. Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 13 www.anpec.com.tw APW7120A Application Information T=1/FOSC Input Capacitor Selection Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge cur- VUGATE rent needed each time high-side MOSFET(Q1) turns on. Place the small ceramic capacitors physically close to the DT I IOUT MOSFETs and between the drain of Q1 and the source of low-side MOSFET(Q2). IL IOUT The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable IQ1 operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and larg- ICOUT I VOUT est RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current of the bulk VOUT Figure 1. Buck Converter Waveforms input capacitor is calculated as the following equation : IRMS = IOUT ⋅ D ⋅ (1- D) (A) Output Capacitor Selection An output capacitor is required to filter the output and sup- For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tanta- ply the load transient current. The filtering requirements are a function of the switching frequency and the ripple lum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. current. The output ripple is the sum of the voltages, having phase shift, across the ESR and the ideal output VIN IQ1 UGATE Q1 IL Q2 VOUT = D ⋅ VIN VOUT ⋅ (1 - D) ∆I = FOSC ⋅ L VESR = ∆ I ⋅ ESR IOUT VOUT L LGATE capacitor. The peak-to-peak voltage of the ESR is calculated as the following equations : CIN ICOUT ESR (V) .......... . (1) (A) .......... .(2) (V) .......... ..(3) The peak-to-peak voltage of the ideal output capacitor is COUT calculated as the following equation : ∆VCOUT = ∆I (V) ....... (4) 8 ⋅ FOSC ⋅ COUT For general applications using bulk capacitors, the ∆VCOUT is much smaller than the V ESR and can be ignored. Therefore, the AC peak-to-peak output voltage is shown below: ∆VOUT = ∆ I ⋅ ESR (V) ...........(5) The load transient requirements are the function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern components and loads are capable of producing transient load rates Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 14 www.anpec.com.tw APW7120A Application Information (Cont.) Output Capacitor Selection (Cont.) tions give the approximate response time interval for application and removal of a transient load: above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the tRISE = L ⋅ ITRAN L ⋅ ITRAN , tFALL = VIN − VOUT VOUT bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) where and voltage rating requirements rather than actual capacitance requirements. ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response High frequency decoupling capacitors should be placed as close to the power pins of the load as physically time to the removal of load. The worst case response time can be either at the application or removal of load. possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these Be sure to check both of these equations at the transient load current. These requirements are minimum and low inductance components. An aluminum electrolytic capacitor’s ESR value is related maximum output levels for the worst case response time. MOSFET Selection to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) In high-current applications, the MOSFET power dissipation, package selection and heatsink are the domi- of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate nant design factors. The power dissipation includes two loss components, conduction loss and switching loss. transient loading. In most cases, multiple electrolytic capacitors of small case size perform better than a single The conduction losses are the largest component of power dissipation for both the high-side and the low-side large case capacitor. MOSFETs. These losses are distributed between the two Output Inductor Selection The output inductor is selected to meet the output voltage MOSFETs according to duty factor (see the equations below). Only the high-side MOSFET has switching losses, ripple requirements and minimize the converter’s response time to the load transient. The inductor value de- since the low-side MOSFETs body diode or an external Schottky rectifier across the lower MOSFET clamps the termines the converter’s ripple current and the ripple voltage, see equations (2) and (5). Increasing the value of switching node before the synchronous rectifier turns on. These equations assume linear voltage-current transi- inductance reduces the ripple current and voltage. However, the large inductance values reduce the tions and do not adequately model power loss due the reverse-recovery of the low-side MOSFET’s body diode. converter’s response time to a load transient. One of the parameters limiting the converter’s response The gate-charge losses are dissipated by the APW7120A and don’t heat the MOSFETs. However, large gate-charge to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, increases the switching interval, tSW which increases the high-side MOSFET switching losses. Ensure that both the APW7120A will provide either 0% or 85%(Average) duty cycle in response to a load transient. The response MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the tem- time is the time required to slew the inductor current from an initial current value to the transient current level. Dur- perature rise according to package thermal-resistance specifications. A separate heatsink may be necessary ing this interval the difference between the inductor current and the transient current level must be supplied by depending upon MOSFET power, package type, ambient temperature and air flow. PHigh - Side = IOUT 2 ⋅ RDSON ⋅ D + the output capacitor. Minimizing the response time can minimize the output capacitance required. PLow - Side = IOUT 2 ⋅ RDSON ⋅ (1 - D) The response time to a transient is different for the application of load and the removal of load. The following equa- Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 1 ⋅ IOUT ⋅ VIN ⋅ tSW ⋅ FOSC 2 Where tSW is the switching interval 15 www.anpec.com.tw APW7120A Application Information (Cont.) Feedback Compensation quencies of the A1(S), A2(S), A3(S), and ACL(S) are shown or calculated as the following equations: The figure 2 shows the control system of the APW7120, which consists of an internal voltage-mode PW M FZA21 = 0.4kHz FPA21 = 430kHz (FP2) 1 F PA41,2 = 2 π x LC modulator, an output L-C filter, a resistor-divider and an internal compensation network. The R and C are the equivalent series resistance (ESR) and capacitance of the output capacitor; the L is the inductance of the output F ZA41 = inductor. VIN APW7120 L the input voltage of the PWM converter and the load resistance of the converter is very large. For good converter R VO Driver LGATE FB Internal Compensation Network Zero frequencies of the A2(S), the FPA41,2 and FZA41 are the double-Pole and Zero frequencies of the A4(S), the VIN is VOUT VPHASE VCOMP stability, the values of the L, C, and R must be selected to meet the following criteria: C VFB 1 2 π xRxC where the FPA21 (or FP2) and FZA21 (or Fz) are the Pole and UGATE VOSC=1.6V (FZ) 1. Make sure the double-pole frequency (FPA41,2) of the output filter is bigger than the zero frequency (FZA21) of R1 the internal compensation network. 2. The following equation must be true: R2 0.8V log( Figure 2. APW7120 Control System 3. The converter crossover frequency (FCO) must be in the range of 10%~30% of minimum FOSC of the converter. The FCO is calculated by using the following equations: The transfer functions are defined as following: A1(S) = VFB(S) R2 = VO(S) R1 + R2 A2(S) = VCOMP(S) (Internal Compensation) VFB(S) VIN R2 1 L ) + log( ) − 2 ⋅ log( ⋅ ) + 1.2 > 0 ∆VOSC R1 + R2 R C Gain at FZA41 20 10% FOSC_MIN ≤ FCO = 10 ⋅ FZA41 ≤ 30% FOSC_MIN VIN R2 Gain at FZA41 = 20 ⋅ log( ) + 20 ⋅ log( ) ∆VOSC R1 + R2 VPHASE(S) VIN = VCOMP(S) ∆VOSC VOUT(S) R ⋅C⋅S +1 A4(S) = = VPHASE(S) L ⋅ C ⋅ S2 + R ⋅ C ⋅ S + 1 A3(S) = − 40 ⋅ log( 1 L ⋅ ) + 27 R C 4. The values of L, C, and R selected must meet the VOUT(S) VO(S) VFB(S) VCOMP(S) VPHASE(S) VOUT (S) = ⋅ ⋅ ⋅ VO(S) VFB(S) VCOMP(S) VPHASE(S) = A1(S) ⋅ A2(S) ⋅ A3(S) ⋅ A4(S) ACL(S) = equations above over the operaing temperature, voltage, and current ranges. where A1(S) is the transfer function of the resistor-divider, A2(S) is the transfer function of the feedback compensation network, A3(S) is the transfer function of the PWM modulator, A4(S) is the transfer function of the output LC filter, and ACL(S) is the transfer function of the closed-loop control system. Refer to figure 3. The Pole and Zero freCopyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 16 www.anpec.com.tw APW7120A Application Information (Cont.) 6. Keep the switching nodes (UGATE, LGATE, and PHASE) away from sensitive small signal nodes since these Feedback Compensation (Cont.) 100 nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. 80 Gain (dB) 60 FZA21 7. Place the decoupling ceramic capacitor CHF near the Drain of the high-side MOSFET as close as possible. Compensation Gain 40 20 0 FPA41,2 -20 FCO FZA41 The bulk capacitors CIN are also placed near the Drain. 8. Place the Source of the high-side MOSFET and the FPA21 Converter Gain Drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane be- -40 -60 100 PWM &Filter Gain 1K 10K 100K 1M tween the two pads reduces the voltage bounce of the node. 10M Frequency (f, Hz) 9. Use a wide power ground plane, with low impedance, to connects the CHF, CIN, COUT, Schottky diode and the Figure 3. Converter Gain vs. Frequency Source of the low-side MOSFET to provide a low impedance path between the components for large and Layout Consideration high frequency switching currents. In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. CHF In general, interconnecting impedances should be minimized by using short, wide printed circuit traces. Signal and power grounds are to be kept separate and finally combined using ground plane construction or single point VCC grounding. Figure 4 illustrates the layout, with bold lines indicating high current paths. Components along the bold BOOT lines should be placed close together. Below is a checklist for your layout: LGATE PHASE 8 path. If possible, make all the connections on one side of the PCB with wide, copper filled areas. + 4 APW7120A U 2 1 UGATE 1. Begin the layout by placing the power components first. Orient the power circuitry to chieve a clean power flow CIN 5 1 VIN Q1 Q2 + L1 COUT VOUT Figure 4. Recommended Layout Digram 2. Connect the ground of feedback divider directly to the GND pin of the IC using a dedicated ground trace. 3. The VCC decoupling capacitor should be right next to the VCC and GND pins. Capacitor CBOOT should be connected as close to the BOOT and PHASE pins as possible. 4. Minimize the length and increase the width of the trace between UGATE/LGATE and the gates of the MOSFETs to reduce the impedance driving the MOSFETs. 5. Use an dedicated trace to connect the ROCSET and the Drain pad of the low-side MOSFET, Kevin connection, for accurate current sensing. Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 17 www.anpec.com.tw APW7120A Package Information SOP-8 D E E1 SEE VIEW A h X 45 ° c A 0.25 b GAUGE PLANE SEATING PLANE A1 A2 e L VIEW A S Y M B O L SOP-8 INCHES MILLIMETERS MIN. MAX. MIN. MAX. 1.75 A 0.069 0.010 0.004 0.25 A1 0.10 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 e 0.049 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0 0° 8° 0° 8° Note: 1. Follow JEDEC MS-012 AA. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension “E” does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 18 www.anpec.com.tw APW7120A Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.40±0.20 5.20±0.20 2.10±0.20 SOP-8 4.0±0.10 8.0±0.10 (mm) Devices Per Unit Package Type Unit Quantity SOP-8 Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 19 www.anpec.com.tw APW7120A Taping Direction Information SOP-8 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 20 www.anpec.com.tw APW7120A Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 21 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW7120A Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2009 22 www.anpec.com.tw