TI CD74ACT258 Quad 2-input multiplexer with three-state output Datasheet

CD54/74AC257, CD54/74ACT257,
CD74ACT258
Data sheet acquired from Harris Semiconductor
SCHS248A
Quad 2-Input Multiplexer
with Three-State Outputs
August 1998 - Revised May 2000
Features
Description
• ’AC257, ’ACT257. . . . . . . . . . . . . Non-Inverting Outputs
The ’AC257, ’ACT257 and CD74ACT258 are quad 2-input
multiplexers with three-state outputs that utilize Advanced
CMOS Logic technology. Each of these devices selects four
bits of data from two sources under the control of a common
Select input (S). The Output Enable (OE) is active LOW.
When OE is HIGH, all of the outputs (Y or Y) are in the highimpedance state regardless of all other input conditions.
• CD74ACT258 . . . . . . . . . . . . . . . . . . . Inverting Outputs
• Buffered Inputs
• Typical Propagation Delay
- 4.4ns at VCC = 5V, TA = 25oC, CL = 50pF
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
Moving data from two groups of registers to four common
output buses is a common use of the ’AC257, ’ACT257, and
CD74ACT258. The state of the Select input determines the
particular register from which the data comes. The ’AC257,
’ACT257 and CD74ACT258 can also be used as function
generators.
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
• Balanced Propagation Delays
Ordering Information
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
PART
NUMBER
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
TEMP.
RANGE (oC)
CD54AC257F3A
0 to 70oC, -40 to 85, 16 Ld PDIP
-55 to 125
CD74AC257M
0 to 70oC, -40 to 85, 16 Ld SOIC
-55 to 125
CD54ACT257F3A
CD54AC257, CD54ACT257
(CERDIP)
CD74AC257, CD74ACT257, CD74ACT258
(PDIP, SOIC)
TOP VIEW
ACT258
S
AC/ACT257
S 1
1I0
CD74ACT257E
-55 to 125
0 to 70oC, -40 to 85,
16 Ld CERDIP
16 Ld PDIP
-55 to 125
AC/ACT257
16 VCC
ACT258
VCC
1I0 2
15 OE
OE
1I1
1I1 3
14 4I0
4I0
1Y
1Y 4
13 4I1
4I1
2I0
2I0 5
12 4Y
4Y
2I1
2I1 6
11 3I0
3I0
2Y
2Y 7
10 3I1
3I1
GND
GND 8
9 3Y
3Y
CD74ACT257M
0 to 70oC, -40 to 85, 16 Ld SOIC
-55 to 125
CD74ACT258E
0 to 70oC, -40 to 85, 16 Ld PDIP
-55 to 125
CD74ACT258M
0 to 70oC, -40 to 85, 16 Ld SOIC
-55 to 125
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local TI sales office or
customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © 2000, Texas Instruments Incorporated
16 Ld CERDIP
CD74AC257E
Drives 50Ω Transmission Lines
Pinout
-55 to 125
PACKAGE
1
CD54/74AC257, CD54/74ACT257, CD74ACT258
Functional Diagram
AC/ACT AC/ACT
257
258
1I0
2I0
3I0
4I0
1I1
2I1
3I1
4I1
2
4
5
1Y
1Y
2Y
2Y
3Y
3Y
4Y
4Y
11
7
14
3
9
6
10
12
13
1
15
S
OE
TRUTH TABLE
OUTPUT
ENABLE
SELECT
INPUT
257
OUTPUTS
258
OUTPUTS
OE
S
I0
I1
Y
Y
H
X
X
X
Z
Z
L
L
L
X
L
H
L
L
H
X
H
L
L
H
X
L
L
H
L
H
X
H
H
L
DATA INPUTS
H = High level voltage, L = Low level voltage, Z = High impedance (off) state, X = Don’t Care
2
CD54/74AC257, CD54/74ACT257, CD74ACT258
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA
Thermal Resistance (Typical, Note 5)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
___
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
___
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC (Note 4)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
VIH
-
-
1.5
1.2
-
1.2
-
1.2
-
V
3
2.1
-
2.1
-
2.1
-
V
AC TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
VIL
VOH
-
VIH or VIL
5.5
3.85
-
3.85
-
3.85
-
V
1.5
-
0.3
-
0.3
-
0.3
V
3
-
0.9
-
0.9
-
0.9
V
5.5
-
1.65
-
1.65
-
1.65
V
-0.05
1.5
1.4
-
1.4
-
1.4
-
V
-0.05
3
2.9
-
2.9
-
2.9
-
V
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-4
3
2.58
-
2.48
-
2.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
-
3
CD54/74AC257, CD54/74ACT257, CD74ACT258
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Low Level Output Voltage
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
VOL
VIH or VIL
0.05
1.5
-
0.1
-
0.1
-
0.1
V
0.05
3
-
0.1
-
0.1
-
0.1
V
0.05
4.5
-
0.1
-
0.1
-
0.1
V
12
3
-
0.36
-
0.44
-
0.5
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
Input Leakage Current
II
VCC or
GND
-
5.5
-
±0.1
-
±1
-
±1
µA
Three-State Leakage
Current
IOZ
VIH or VIL
VO = VCC
or GND
-
5.5
-
±0.5
-
±5
-
±10
µA
Quiescent Supply Current
MSI
ICC
VCC or
GND
0
5.5
-
8
-
80
-
160
µA
High Level Input Voltage
VIH
-
-
4.5 to
5.5
2
-
2
-
2
-
V
Low Level Input Voltage
VIL
-
-
4.5 to
5.5
-
0.8
-
0.8
-
0.8
V
High Level Output Voltage
VOH
VIH or VIL
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
0.05
4.5
-
0.1
-
0.1
-
0.1
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
ACT TYPES
Low Level Output Voltage
VOL
VIH or VIL
II
VCC or
GND
-
5.5
-
±0.1
-
±1
-
±1
µA
Three-State or Leakage
Current
IOZ
VIH or VIL
VO = VCC
or GND
-
5.5
-
±0.5
-
±5
-
±10
µA
Quiescent Supply Current
MSI
ICC
VCC or
GND
0
5.5
-
8
-
80
-
160
µA
∆ICC
VCC
-2.1
-
4.5 to
5.5
-
2.4
-
2.8
-
3
mA
Input Leakage Current
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC.
4
CD54/74AC257, CD54/74ACT257, CD74ACT258
ACT Input Load Table
INPUT
UNIT LOAD
Data
0.83
S
1.27
OE
1.27
NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
-40oC TO 85oC
PARAMETER
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tPLH, tPHL
1.5
-
-
106
-
-
117
ns
3.3
(Note 9)
3.3
-
11.8
3.3
-
13
ns
5
(Note 10)
2.4
-
8.5
2.3
-
9.3
ns
1.5
-
-
153
-
-
168
ns
3.3
4.8
-
17.1
4.7
-
18.8
ns
5
3.5
-
12.2
3.4
-
13.4
ns
1.5
-
-
167
-
-
184
ns
3.3
5.3
-
18.7
5.2
-
20.6
ns
5
3.8
-
13.4
3.7
-
14.7
ns
1.5
-
-
91
-
-
100
ns
3.3
2.9
-
10.2
2.8
-
11.2
ns
5
2.1
-
7.3
2
-
8
ns
1.5
-
-
153
-
-
168
ns
3.3
4.8
-
17.1
4.7
-
18.8
ns
5
3.5
-
12.2
3.4
-
13.4
ns
1.5
-
-
167
-
-
184
ns
3.3
5.3
-
18.7
5.2
-
20.6
ns
5
3.8
-
13.4
3.7
-
14.7
ns
AC TYPES
Propagation Delay,
In to Y
AC/ACT257
Propagation Delay,
S to Y
AC/ACT257
Propagation Delay,
OE to Y
AC/ACT257
Propagation Delay,
In to Y
’AC/CD74ACT258
Propagation Delay,
S to Y
’AC/CD74ACT258
Propagation Delay,
OE to Y
’AC/CD74ACT258
tPLH, tPHL
tPLZ, tPHZ,
tPZL, tPZH
tPLH, tPHL
tPLH, tPHL
tPLZ, tPHZ,
tPZL, tPZH
Three-State Output
Capacitance
CO
-
-
-
15
-
-
15
pF
Input Capacitance
CI
-
-
-
10
-
-
10
pF
CPD
(Note 11)
-
-
130
-
-
130
-
pF
Propagation Delay,
In to Y
AC/ACT257
tPLH, tPHL
5
(Note 10)
2.8
-
9.7
2.7
-
10.7
ns
Propagation Delay,
S to Y
AC/ACT257
tPLH, tPHL
5
4
-
14
3.9
-
15.4
ns
Power Dissipation Capacitance
ACT TYPES
5
CD54/74AC257, CD54/74ACT257, CD74ACT258
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
(Continued)
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Propagation Delay,
OE to Y
AC/ACT257
tPLZ, tPHZ,
tPZL, tPZH
5
4.1
-
14.6
4
-
16.1
ns
Propagation Delay,
In to Y
’AC/CD74ACT258
tPLH, tPHL
5
2.4
-
8.5
2.3
-
9.3
ns
Propagation Delay,
S to Y
’AC/CD74ACT258
tPLH, tPHL
5
4
-
14
3.9
-
15.4
ns
Propagation Delay,
OE to Y
’AC/CD74ACT258
tPLZ, tPHZ,
tPZL, tPZH
5
4.1
-
14.6
4
-
16.1
ns
Three-State Output
Capacitance
CO
-
-
-
15
-
-
15
pF
Input Capacitance
CI
-
-
-
10
-
-
10
pF
CPD
(Note 11)
-
-
130
-
-
130
-
pF
PARAMETER
Power Dissipation Capacitance
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. CPD is used to determine the dynamic power consumption per multiplexer.
AC: PD = CPD VCC2 fi + ∑ (CL VCC2 fo)
ACT: PD = CPD VCC2 fi + ∑ (CL VCC2 fo) + VCC ∆ICC where fi = input frequency, fo = output frequency, CL = output load capacitance,
VCC = supply voltage.
tr = 3ns
tf = 3ns
INPUT LEVEL
90%
OUTPUT
DISABLE
VS
10%
GND
tPZL
tPLZ
VS
0.2VCC
OUTPUT: LOW
TO OFF TO LOW
tPHZ
tPZH
0.8 VCC
VS
OUTPUT: HIGH
TO OFF TO HIGH
OUTPUTS
ENABLED
OTHER
INPUTS
(TIED HIGH
OR LOW)
OUTPUT
DISABLE
OUTPUTS
DISABLED
500Ω†
RL
DUT
WITH
THREESTATE
OUTPUT
CL
50pF
VOL (≠GND)
VOH (≠VCC)
OUTPUTS
ENABLED
GND (tPHZ, tPZH)
OPEN (tPHL, tPLH)
2 VCC (tPLZ, tPZL)
(OPEN DRAIN)
OUT
500Ω†
RL
†FOR AC SERIES ONLY: WHEN VCC = 1.5V, RL = 1kΩ
FIGURE 1. THREE-STATE PROPAGATION DELAY TIMES AND TEST CIRCUIT
6
CD54/74AC257, CD54/74ACT257, CD74ACT258
tr = 3ns
tf = 3ns
INPUT
LEVEL
nI0, nI1, S
VS
tPLH
INPUT LEVEL
90%
10%
tPLH
tPHL
GND
Y
Y
VS
S
tPHL
VS
VS
FIGURE 2. INPUTS OR SELECT TO OUTPUT PROPAGATION
DELAYS (AC/ACT257)
FIGURE 3. SELECT TO OUTPUT PROPAGATION DELAYS
(CD74ACT258)
OUTPUT
RL (NOTE)
500Ω
DUT
OUTPUT
LOAD
CL
50pF
NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.
AC
ACT
VCC
3V
Input Switching Voltage, VS
0.5 VCC
1.5V
Output Switching Voltage, VS
0.5 VCC
0.5 VCC
Input Level
FIGURE 4. PROPAGATION DELAY TIMES
7
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
CD54AC257F3A
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
CD54ACT257F3A
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
CD74AC257E
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74AC257EE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74AC257M
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74AC257M96
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74AC257M96E4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74AC257ME4
ACTIVE
SOIC
D
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74AC257SM
OBSOLETE
SSOP
DB
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74ACT257E
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74ACT257EE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74ACT257M
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74ACT257M96
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74ACT257M96E4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74ACT257ME4
ACTIVE
SOIC
D
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74ACT257SM
OBSOLETE
SSOP
DB
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74ACT258M
ACTIVE
SOIC
D
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
CD74ACT258M96
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
CD74ACT258M96E4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
CD74ACT258ME4
ACTIVE
SOIC
D
16
CU NIPDAU
Level-2-260C-1YEAR
40
40
40
40
Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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