LODEV LF3304 Dual line buffer/fifo Datasheet

LF3304
LF3304
DEVICES INCORPORATED
Dual Line Buffer/FIFO
Dual Line Buffer/FIFO
DEVICES INCORPORATED
FEATURES
DESCRIPTION
❑ 100 MHz Data Rate for Video and
other High-Speed Applications
❑ One 24-bit, Two 12-bit, Three
8-bit Data Paths, or One Double
Depth 12-bit
❑ Dual Modes: Line Buffer or FIFO
❑ User-Programmable FIFO Flags
❑ User-Resettable Read and Write
Pointers
❑ Single 3.3 V Power Supply,
5 V Tolerant I/O
❑ 100-lead PQFP
The LF3304 is a dual line buffer/
FIFO, designed to operate at HDTV
rates. The LF3304 will operate in
two distinct modes: Line Buffer and
FIFO. In these modes the two memories can operate independently or
with common control.
The LF3304 comprises two 12-bit 4K
memories configurable in a variety of
ways including: Two 12-bit 4K deep
line buffers (independent lengths),
Three 8-bit 4K deep line buffers
(common lengths), One 12-bit 8K
deep line buffer, or Two 12-bit 4K
FIFOs (independent operation).
In FIFO mode, independent Read
and Write Resets give the designer
control over the internal pointers
providing flexibility not commonly
found in ordinary FIFOs.
The LF3304 operatates at a maximum
data rate of 100 MHz and is available
in a 100-lead PQFP package.
LF3304 BLOCK DIAGRAM
WCLKA
RCLKA
WENA
RENA
RRA
RWA
FFA
EFA
PAFA
PAEA
FLAG
GENERATOR
RAM ARRAY 1
CONTROL
OEA
VARIABLE LENGTH RAM ARRAY A
12
AIN11-0
12
AOUT11-0
4K x 12-bit
ADDRA
LDA
12
LENGTH11-0
MASTER
CONTROL
ADDRB
LDB
VARIABLE LENGTH RAM ARRAY B
12
BOUT11-0
4K x 12-bit
BIN11-0
12
OEB
2
MODE1-0
WCLKB
RCLKB
WENB
RENB
RRB
RWB
FLAG
GENERATOR
RAM ARRAY 2
CONTROL
FFB
EFB
PAFB
PAEB
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LF3304
DEVICES INCORPORATED
LINE BUFFER MODE
SIGNAL DEFINITIONS
Power
VCC and GND
+3.3 V power supply. All pins must
be connected.
Clocks
WCLKA — Write Clock A
WCLKA and RCLKA must be tied
together for RAM Array A to properly
operate as a Line Buffer. The rising edge
of xCLKA strobes all appropriate
enabled registers.
Dual Line Buffer/FIFO
the data presented on LENGTH11-0 is
loaded into the device on the active edge of
WCLKA in conjunction with LDA being
driven LOW. To set the length of RAM
Array B the data presented on
LENGTH11-0 is loaded into the device
on the active edge of WCLKB in
conjunction with LDB being driven
LOW. If an equal length is desired for
both RAM Arrays, the data presented
on LENGTH11-0 is loaded into the
device on the active edge of WCLK
(WCLKA and WCLKB tied together) in
conjuction with LDx (LDA and LDB
tied together) being driven LOW.
MODE1-0 — Mode Select
TABLE 1. DEVICE CONFIGURATION
MODE1-0
Mode Select
0
0
Dual Line Buffer
0
1
Cascaded Line Buffer
1
0
Dual FIFO
1
1
Reserved
delay mode, RWA and RRA should be
brought LOW to properly reset the Write
and Read pointers.
RENA — Read Enable B
In Line Buffer mode, RENA must be
kept LOW.
WCLKB and RCLKB must be tied
together for RAM Array B to properly
operate as a Line Buffer. The rising
edge of xCLKB strobes all appropriate
enabled registers.
The mode select inputs determine the
operating mode of the LF3304 (Table 1) for
data being input on the next clock cycle.
When switching between modes, the
internal pipeline latencies of the device
must be observed. After switching
operating modes, either the user must
allow enough clock clycles to pass to flush
the internal RAM Array or RWx and RRx
must be driven LOW together before valid
data will appear on the outputs.
RCLKB — Read Clock B
Controls
Driving WENB LOW places the device in
programmable delay mode and driving
WENB HIGH places RAM Array B in
recirculate mode (programmable circular
buffer). When in recirculate mode, the
write pointer position remains fixed
while data on BIN11-0 is ignored. When
switching back from recirculate mode to
delay mode, RWB and RRB should be
brought LOW to properly reset the Write
and Read pointers.
LDA — RAM Array A Load
RENB — Read Enable B
When LDA is LOW, data on
LENGTH11-0 is latched in the length
register on the rising edge of xCLKA.
In Line Buffer mode, RENB must be
kept LOW.
RCLKA — Read Clock A
See WCLKA description.
WCLKB — Write Clock B
See WCLKB description.
Inputs
AIN11-0 — Data Input A
AIN11-0 is the 12-bit registered data
input port.
BIN11-0 — Data Input B
BIN11-0 is the 12-bit registered data
input port.
RWA — Reset Write A
LDB — RAM Array B Load
When LDB is LOW, data on
LENGTH11-0 is latched in the length
register on the rising edge of xCLKB.
WENA — Write Enable A
LENGTH11-0 — Line Buffer Length
The 12-bit value is used to specify the
length of each of the RAM Arrays. An
integer value ranging from 0 to 4095 is
used to select a delay ranging from 2 to
4097 clock cycles. The value placed on
LENGTH11-0 is equal to the desired delay
minus 8. To set the length of RAM Array A
WENB — Write Enable B
Driving WENA LOW places the device in
programmable delay mode and driving
WENA HIGH places RAM Array A in
recirculate mode (programmable circular
buffer). When in recirculate mode, the
write pointer position remains fixed while
data on AIN11-0 is ignored. When
switching back from recirculate mode to
The write address pointer is reset to the
first physical location when RWA is set
LOW. After power up, the LF3304
requires a Reset Write for initialization
because the write address pointer is not
defined at that time.
RRA — Reset Read A
The read address pointer is reset to the
first physical location when RRA is set
LOW. After power up, the LF3304
requires a Reset Read for initialization
because the read address pointer is not
defined at that time.
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LF3304
DEVICES INCORPORATED
Dual Line Buffer/FIFO
RWB — Reset Write B
Clocks
BIN11-0 — Data Input B
See RWA Description.
WCLKA — Write Clock A
BIN11-0 is the 12-bit registered data
input port.
Data present on AIN11-0 is written
into the LF3304 on the rising edge of
WCLKA when the device is configured
for writing.
RRB — Reset Read B
See RRA description.
OEA — Output Enable A
When OEA is LOW, AOUT11-0 is
enabled for output. When OEA is
HIGH, AOUT11-0 is placed in a highimpedence state.
OEB — Output Enable B
When OEB is LOW, BOUT11-0 is
enabled for output. When OEB is
HIGH, BOUT11-0 is placed in a highimpedence state.
RCLKA — Read Clock A
Data is read from the LF3304 and
presented on the output port (AOUT11-0)
after tD has elapsed from the rising
edge of RCLKA when the device is
configured for reading and the output
port is enabled. WCLKA and RCLKA
can be tied together and driven by the
same external clock or they may be
controlled by separate external clocks.
WCLKB — Write Clock B
Outputs
Data present on BIN11-0 is written into
the LF3304 on the rising edge of
WCLKB when the device is configured
for writing.
AOUT11-0 — Data Output A
AOUT11-0 is the 12-bit registered
data output port.
Data is read from the LF3304 and
presented on the output port (BOUT11-0)
after tD has elapsed from the rising
edge of RCLKB when the device is
configured for reading and the output
port is enabled. WCLKB and RCLKB
can be tied together and driven by the
same external clock or they may be
controlled by separate external clocks.
BOUT11-0 is the 12-bit registered
data output port.
FIFO MODE
SIGNAL DEFINITIONS
Power
If LDA is LOW, on the rising edge of
WCLKA data present on AIN11-0 is
written into the PAFA or PAEA register
depending on ADDRA (see Table 2).
The LSB, AIN0, corresponds to the LSB
of PAFA and PAEA registers. The MSB,
AIN11, corresponds to the MSB of PAFA
and PAEA registers.
ADDRB — Address B
If LDB is LOW, on the rising edge of
WCLKB data present on BIN11-0 is
written into the PAFB or PAEB register
depending on ADDRB (see Table 2).
The LSB, BIN0, corresponds to the LSB
of PAFB and PAEB registers. The MSB,
BIN11, corresponds to the MSB of PAFB
and PAEB registers.
MODE1-0 — Mode Select
RCLKB — Read Clock B
BOUT11-0 — Data Output B
ADDRA — Address A
The mode select inputs determine the
operating mode of the LF3304 (Table 1) for
data being input on the next clock cycle.
When switching between modes, the
internal pipeline latencies of the device
must be observed. After switching
operating modes, either the user must
allow enough clock clycles to pass to flush
the internal RAM Array or RWx and RRx
must be driven LOW together before valid
data will appear on the outputs.
VCC and GND
Inputs
+3.3 V power supply. All pins must be
connected.
AIN11-0 — Data Input A
LENGTH — Non-Flag Pins
AIN11-0 is the 12-bit registered data
input port.
In FIFO Mode, the unused LENGTH pins
(LENGTH11, LENGTH10, LENGTH5,
LENGTH4) must be tied LOW.
TABLE 2. LOADING PROGRAMMABLE FLAG REGISTERS
WCLKA
Controls
ADDRA
ADDRB
LDA
LDB
WCLKB
Operation
0
x
0
x
x
PAEA Register
1
x
0
x
x
PAFA Register
x
0
x
0
x
PAEB Register
x
1
x
0
x
PAFB Register
LDA — RAM Array A Load
When LDA is LOW, data on AIN11-0 is
latched in the LF3304 on the rising edge
of WCLKA.
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LF3304
DEVICES INCORPORATED
Dual Line Buffer/FIFO
LDB — RAM Array B Load
RRA — Reset Read A
When LDB is LOW, data on BIN11-0 is
latched in the LF3304 on the rising
edge of WCLKB.
The read address pointer is reset to the first
physical location when RRA is set LOW.
After power up, the LF3304 requires a Reset
Read for initialization because the read
address pointer is not defined at that time.
WENA — Write Enable A
If WENA is LOW, data on AIN11-0 is
written to the device on the rising edge
of WCLKA. When RAM Array A is
full, WENA is ignored.
RWB — Reset Write B
RENA — Read Enable A
See RRA description.
If RENA is LOW, data from RAM Array
A is read and presented on AOUT11-0
after tD has elapsed from the rising
edge of RCLKA if the output port is
enabled. If RENA goes HIGH, the last
value loaded in the RAM Array A
output register will remain unchanged.
When RAM Array A is empty, RENA is
ignored.
OEA — Output Enable A
WENB — Write Enable B
If WENB is LOW, data on BIN11-0 is
written to the device on the rising edgle
of WCLKB. When RAM Array B is full,
WENB is ignored.
See RWA Description.
RRB — Reset Read B
When OEA is LOW, AOUT11-0 is
enabled for output. When OEA is
HIGH, AOUT11-0 is placed in a highimpedence state. The flag outputs are
not affected by OEA.
OEB — Output Enable B
When OEB is LOW, BOUT11-0 is
enabled for output. When OEB is
HIGH, BOUT11-0 is placed in a highimpedence state. The flag outputs are
not affected by OEB.
Outputs
AOUT11-0 — Data Output A
RENB — Read Enable B
If RENB is LOW, data from RAM Array
B is read and presented on BOUT11-0
after tD has elapsed from the rising
edge of RCLKB if the output port is
enabled. If RENB goes HIGH, the last
value loaded in the RAM Array B
output register will remain unchanged.
When RAM Array B is empty, RENB is
ignored.
RWA — Reset Write A
The write address pointer is reset to the
first physical location when RWA is set
LOW. After power up, the LF3304
requires a Reset Write for initialization
because the write address pointer is not
defined at that time.
AOUT11-0 is the 12-bit registered data
output port.
BOUT11-0 — Data Output B
BOUT11-0 is the 12-bit registered data
output port.
FFA — Full Flag A
FFA goes LOW when RAM Array A is
full of data. When FFA is LOW, RAM
Array A can not be written to. The Full
Flag is synchronized to the rising edge
of WCLKA.
EFA — Empty Flag A
EFA goes LOW when the read pointer is
equal to the write pointer, indicating that
RAM Array A is empty. When EFA is
LOW, read operations can not be
performed. The Empty Flag is synchronized to the rising edge of RCLKA.
FFB — Full Flag B
FFB goes LOW when RAM Array B is full
of data. When FFB is LOW, RAM Array B
can not be written to. The Full Flag is
synchronized to the rising edge of WCLKB.
EFB — Empty Flag B
EFB goes LOW when the read pointer
is equal to the write pointer, indicating
that RAM Array B is empty. When EFB
is LOW, read operations can not be
performed. The Empty Flag is synchronized to the rising edge of RCLKB.
PAFA—ProgrammableAlmost-FullFlagA
PAFA goes LOW when the write
pointer is (Full – N) locations ahead of
the read pointer. N is the value stored
in the PAFA register and has no default
value. PAFA is synchronized to the
rising edge of WCLKA.
PAEA—ProgrammableAlmost-EmptyFlagA
PAEA goes HIGH when the write
pointer is (N + 1) location ahead of the
read pointer. N is the value stored in
the PAEA register and has no default
value. PAEA is synchronized to the
rising edge of RCLKA.
PAFB—ProgrammableAlmost-FullFlagB
PAFB goes LOW when the write pointer
is (Full – N) locations ahead of the read
pointer. N is the value stored in the
PAFB register and has no default value.
PAFB is synchronized to the rising
edge of WCLKB.
PAEB—ProgrammableAlmost-EmptyFlagB
PAEB goes HIGH when the write
pointer is (N + 1) location ahead of the
read pointer. N is the value stored in
the PAEB register and has no default
value. PAEB is synchronized to the
rising edge of RCLKB.
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LF3304
DEVICES INCORPORATED
FIFO MODE
OPERATION
Initialization
Upon power-up, the LF3304 requires
the initialization of the internal read
and write address pointers. This
initialization sequence can be done
by either a Flag Enable Reset or a
Flag Disable Reset.
Dual Line Buffer/FIFO
should be disregarded. For example,
as the 4096th data word is written
into the FIFO, assuming that no
preceding read cycles have occured,
FFx will be driven LOW thus indicating a ‘full’state. While the FIFO is
still in this ‘full’ state, the next
enabled write will access address
000H, thus writing over data that
has not yet been read out.
A Flag Enable Reset will force the
FIFO to operate in a ‘Flag Enabled’
mode. In this mode, writing will be
disabled when FFx is LOW and
reading is disabled when EFx is
LOW. Any ‘write beyond full’ event
or ‘read beyond empty’ event will be
disabled. Note: in an ‘empty’ state,
the last data word read from the
FIFO is held on the output bus until
the next valid read cycle.
Flag Enable Reset
1.
RWA/RWB must be LOW for at
least one WCLKA/WCLKB cycle.
A Flag Disable Reset will force the
FIFO to operate in a ‘Flag Disabled’
mode. In this mode, the user is
allowed to write over previously unread data and read out previously
read data. Consequently, any
enabled write or read is valid thus
allowing the write and read pointers
to ‘wrap-around’. Note: due to the
nature of this mode, the flag status
2.
RRA/RRB must be LOW for at
least one RCLKA/RCLKB cycle.
3.
WENx and RENx must be HIGH
during the above two conditions
plus one addition write or read
cycle (which ever is longer).
A Flag Enable Reset resets the read
and write pointers and enables the
flags to control the reading and
writing of data according to the Full
Flag and Empty Flag conditions. A
Flag Enable Reset occurs when the
following conditions are met:
The Flag Enable Reset condition can
be disabled if one of the two Flag
Disable Reset conditions are applied.
Flag Disable Reset
A Flag Disable Reset resets the read
and write pointers and disables the
flags from controlling the reading
and writing of data. A Flag Disable
Reset occurs when the following
conditions are met:
1.
RWA/RWB must be LOW for at
least one WCLKA/WCLKB cycle
while WENx is LOW.
2.
RRA/RRB must be LOW for at
least one RCLKA/RCLKB cycle
while RENx is LOW.
Configuration of Programmable Flags
In order to load a FIFO A Programmable Flag Register, a rising edge of
WCLKA, while WENA is LOW,
latches AIN11-0 into either the PAFA
or PAEA Register - depending on the
states of ADDRA and LDA (See
Table 2).
In order to load a FIFO B Programmable Flag Register, a rising edge of
WCLKB, while WENB is LOW,
latches BIN11-0 into either the PAFB
or PAEB Register - depending on the
states of ADDRB and LDB (See Table
2). See the Figure labeled “Programmable Flag Load Timing.”
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LF3304
DEVICES INCORPORATED
Dual Line Buffer/FIFO
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ............................................................................................................. –65°C to +150°C
Operating ambient temperature ............................................................................................. –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +4.5 V
Input signal with respect to ground ........................................................................................... –0.5 V to 5.5 V
Signal applied to high impedance output .................................................................................. –0.5 V to 5.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ................................................................................................................................ > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Active Operation, Commercial
Temperature Range (Ambient)
0°C to +70°C
Supply Voltage
3.00 V ≤ VCC ≤ 3.60 V
–55°C to +125°C
3.00 V ≤ VCC ≤ 3.60 V
Active Operation, Military
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol
Parameter
Test Condition
Min
VOH
Output High Voltage
VCC = Min., IOH = –4 mA
2.4
VOL
Output Low Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input High Voltage
VIL
Input Low Voltage
(Note 3)
IIX
Input Current
I OZ
Typ
Max
Unit
V
0.4
V
2.0
5.5
V
0.0
0.8
V
Ground ≤ VIN ≤ VCC (Note 12)
±10
µA
Output Leakage Current
Ground ≤ VOUT ≤ VCC (Note 12)
±10
µA
ICC1
VCC Current, Dynamic
(Notes 5, 6)
50
mA
ICC2
VCC Current, Quiescent
(Note 7)
2
mA
CIN
Input Capacitance
TA = 25°C, f = 1 MHz
10
pF
COUT
Output Capacitance
TA = 25°C, f = 1 MHz
10
pF
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LF3304
DEVICES INCORPORATED
Dual Line Buffer/FIFO
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
LF3304–
12
15
Max
Min
Max
10
Symbol
Parameter
Min
Min
Max
tCYC
Cycle Time
15
12
10
tPWH
Clock Pulse Width High
5
4
3
tPWL
Clock Pulse Width Low
5
4
3
tDS
Data Setup Time
6
5
4
tDH
Data Hold Time
0
0
0
tWES
Write Enable Setup Time
6
5
4
tWEH
Write Enable Hold Time
0
0
0
tRES
Read Enable Setup Time
6
5
4
tREH
Read Enable Hold Time
0
0
0
tLDS
Load Setup Time
6
5
4
tLDH
Load Hold Time
0
0
0
tRS
Read/Write Reset Setup Time
6
5
4
tRH
Read/Write Reset Hold Time
0
0
0
tAC
Access Time
8
7
6
tWFF
Write Clock to Full Flag
8
7
6
tREF
Read Clock to Empty Flag
8
7
6
tPAF
Write Clock to Programmable Almost-Full Flag
8
7
6
tPAE
Read Clock to Programmable Almost-Empty Flag
8
7
6
tOHZ
Output Enable to Output in Low Impedance
8
7
6
tOLZ
Output Enable to Output in High Impedance
8
7
6
tSKEW1
Skew Time Between Read and Write Clocks for EF and FF
6
5
4
tSKEW2
Skew Time Between Read and Write Clocks for PAEx and PAFx
6
5
4
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LF3304
DEVICES INCORPORATED
Dual Line Buffer/FIFO
WRITE CYCLE TIMING
WCLKA
WCLKB
tPWH
tWES
tPWL
tWEH
tCYC
WENA
WENB
tDS
AIN11–0
BIN11–0
tDH
(n)
(n+1)
(n+2)
(n+3)
tWFF
tWFF
FF
tSKEW1
RCLKA
RCLKB
RWA = RWB = HIGH
READ CYCLE TIMING
RCLKA
RCLKB
tPWH
RENA
RENB
AOUT11–0
BOUT11–0
tRES
tPWL
tREH
tCYC
tAC
(n–2)
(n–1)
(n)
(n+1)
tREF
(n+2)
(n+3)
tREF
EF
tSKEW1
WCLKA
WCLKB
RRA = RRB = HIGH
OEA = OEB = LOW
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LF3304
DEVICES INCORPORATED
Dual Line Buffer/FIFO
WRITE RESET TIMING
WCLKA
WCLKB
tRS
tRH
RWA
RWB
tDS
AIN11–0
BIN11–0
(n-1)
(n)
(n+1)
tDH
(n+2)
(0)
(1)
WENA = WENB = LOW
READ RESET TIMING
RCLKA
RCLKB
tRS
tRH
RRA
RRB
tAC
AOUT11–0
(n–2)
BOUT11–0
(n–1)
(n)
(n+1)
(n+2)
(0)
(0)
(1)
RENA = RENB = LOW
OEA = OEB = LOW
PROGRAMMABLE FLAG LOAD TIMING
WCLKA
WCLKB
tDS
AIN11–0
BIN11–0
tDH
PAEx
PAFx
ADDRA
ADDRB
tLDS
tLDH
LDA
LDB
WENA
WENB
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LF3304
DEVICES INCORPORATED
Dual Line Buffer/FIFO
PROGRAMMABLE ALMOST FULL FLAG
WCLKA
WCLKB
tPAF
tPAF
PAFA
PAFB
tSKEW2
RCLKA
RCLKB
PROGRAMMABLE ALMOST EMPTY FLAG
WCLKA
WCLKB
PAEA
PAEB
tPAE
tSKEW2
tPAE
RCLKA
RCLKB
OUTPUT ENABLE AND DISABLE
OEA
OEB
tOHZ
tOLZ
AOUT11–0
BOUT11–0
HIGH IMPEDANCE
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LF3304
DEVICES INCORPORATED
Dual Line Buffer/FIFO
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
respectively. Alternatively, a diode
2. The products described by this spec- bridge with upper and lower current
ification include internal circuitry desources of I OH and I OL respectively,
signedto protect the chipfrom damaging and a balancing voltage of 1.5 V may be
substrate injection currents and accu- used. Parasitic capacitance is 30 pF
mulations of static charge. Neverthe- minimum, and may be distributed.
less, conventional precautions should
be observed during storage, handling, This device has high-speed outputs caand use of these circuits in order to avoid pable of large instantaneous current
exposure to excessive electrical stress pulses and fast turn-on/turn-off times.
values.
As a result, care must be exercised in the
testing of this device. The following
3. This device provides hard clamping measures are recommended:
of transient undershoot. Input levels
below ground will be clamped begin- a. A 0.1 µF ceramic capacitor should be
ning at –0.6 V. The device can withstand installed between VCC and Ground
indefinite operation with inputs or out- leads as close to the Device Under Test
puts in the range of –0.5 V to +5.5 V. (DUT) as possible. Similar capacitors
Device operation will not be adversely should be installed between device VCC
affected, however, input current levels and the tester common, and device
will be well in excess of 100 mA.
ground and tester common.
4. Actual test conditions may vary from b. Ground and VCC supply planes must
those designated but operation is guar- be brought directly to the DUT socket or
anteed as specified.
contactor fingers.
measured to the 1.5 V crossing point with
datasheet loads. For the tDIS test, the
transition is measured to the ±200mV
level from the measured steady-state
output voltage with ±10mA loads.
The balancing voltage, V TH , is set at
3.0 V for Z-to-0 and 0-to-Z tests, and
set at 0 V for Z-to-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
IOL
where
4
c. Input voltages on a test fixture should
be adjusted to compensate for inductive
ground and VCC noise to maintain required DUT input levels relative to the
DUT ground pin.
VTH
CL
IOH
FIGURE B. THRESHOLD LEVELS
tENA
OE
Z
tDIS
1.5 V
1.5 V
3.0V Vth
0
1.5 V
1.5 V
Z
5. Supply current for a given application can be accurately approximated
by:
NCV2 F
S1
DUT
1
VOL*
0.2 V
VOH*
0.2 V
0
Z
1
Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view
of the external system driving the chip.
Setup time, for example, is specified as a
minimum since the external system must
6. Tested with outputs changing every supply at least that much time to meet the
cycle and no load, at a 40 MHz clock rate. worst-case requirements of all parts.
Responses from the internal circuitry are
7. Tested with all inputs within 0.1 V of specified from the point of view of the
VCC or Ground, no load.
device. Output delay, for example, is
8. These parameters are guaranteed but specified as a maximum since worstcase operation of any device always pronot 100% tested.
vides data within that time.
9. AC specifications are tested with
11. For the tENA test, the transition is
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
Video Imaging Products
11
08/16/2000–LDS.3304-F
LF3304
DEVICES INCORPORATED
Dual Line Buffer/FIFO
WENA
RWA
WCLKA
RCLKA
RRA
RENA
VCC
GND
MODE0
LDA
ADDRA
OEA
VCC
GND
LENGTH5
LENGTH4
FFA/LENGTH3
EFA/LENGTH2
PAFA/LENGTH1
PAEA/LENGTH0
ORDERING INFORMATION
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100-pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Top
View
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VCC
GND
AOUT0
AOUT1
AOUT2
AOUT3
AOUT4
AOUT5
AOUT6
AOUT7
AOUT8
AOUT9
AOUT10
AOUT11
VCC
GND
BOUT0
BOUT1
BOUT2
BOUT3
BOUT4
BOUT5
BOUT6
BOUT7
BOUT8
BOUT9
BOUT10
BOUT11
VCC
GND
WENB
RWB
WCLKB
RCLKB
RRB
RENB
GND
VCC
MODE1
LDB
ADDRB
OEB
GND
VCC
LENGTH11
LENGTH10
LENGTH9/FFB
LENGTH8/EFB
LENGTH7/PAFB
LENGTH6/PAEB
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
VCC
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
GND
VCC
BIN0
BIN1
BIN2
BIN3
BIN4
BIN5
BIN6
BIN7
BIN8
BIN9
BIN10
BIN11
GND
VCC
Plastic Quad Flatpack
(Q2)
Speed
0°C to +70°C — COMMERCIAL SCREENING
15 ns
12 ns
10 ns
LF3304QC15
LF3304QC12
LF3304QC10
Video Imaging Products
12
08/16/2000–LDS.3304-F