TI1 LM77CIMX-3/NOPB 9-bit sign digital temperature sensor Datasheet

LM77
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LM77 9-Bit + Sign Digital Temperature Sensor and Thermal Window Comparator with
Two-Wire Interface
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FEATURES
DESCRIPTION
•
The LM77 is a digital temperature sensor and thermal
window comparator with an I2C Serial Bus interface.
The window-comparator architecture of the LM77
eases the design of temperature control systems
conforming to the ACPI (Advanced Configuration and
Power
Interface)
specification
for
personal
computers. The open-drain Interrupt (INT) output
becomes active whenever temperature goes outside
a programmable window, while a separate Critical
Temperature Alarm (T_CRIT_A) output becomes
active
when
the
temperature
exceeds
a
programmable critical limit. The INT output can
operate in either a comparator or event mode, while
the T_CRIT_A output operates in comparator mode
only.
1
2
•
•
•
•
•
•
Window Comparison Simplifies Design of
ACPI Compatible Temperature Monitoring and
Control.
Serial Bus Interface
Separate Open-Drain Outputs for Interrupt and
Critical Temperature Shutdown
Shutdown Mode to Minimize Power
Consumption
Up to 4 LM77s Can be Connected to a Single
Bus
9-bit + Sign Output; Full-Scale Reading of Over
128°C
SOIC and VSSOP 8-lead Packages
APPLICATIONS
•
•
•
•
•
•
System Thermal Management
Personal Computers
Office Electronics
Electronic Test Equipment
Automotive
HVAC
KEY SPECIFICATIONS
•
•
•
Supply Voltage 3.0V to 5.5V
Supply Current
– Operating
– 250 μA (typ)
– 500 μA (max)
– Shutdown
– 5 μA (typ)
Temperature Accuracy
– −10°C to 65°C, ±1.5°C(max)
– −25°C to 100°C, ±2°C(max)
– −55°C to 125°C, ±3°C(max)
The host can program both the upper and lower limits
of the window as well as the critical temperature limit.
Programmable hysterisis as well as a fault queue are
available to minimize false tripping. Two pins (A0, A1)
are available for address selection. The sensor
powers up with default thresholds of 2°C THYST, 10°C
TLOW, 64°C THIGH, and 80°C T_CRIT.
The LM77's 3.0V to 5.5V supply voltage range, Serial
Bus interface, 9-bit + sign output, and full-scale range
of over 128°C make it ideal for a wide range of
applications. These include thermal management and
protection applications in personal computers,
electronic test equipment, office electronics,
automotive, and HVAC applications.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Simplified Block Diagram
Figure 1.
Connection Diagram
Figure 2. SOIC-8 or VSSOP Package
See Package Number D0008A or DGK0008A
PIN DESCRIPTIONS
Pin Name
Pin No.
Description
Typical Connection
SDA
1
Serial Bi-Directional Data Line. Open Drain Output
From Controller
SCL
2
Serial Bus Clock Input
From Controller
T_CRIT_A
3
Critical Temperature Alarm Open Drain Output
Pull Up Resistor, Controller Interrupt Line or
System Hardware Shutdown
GND
4
Power Supply Ground
Ground
INT
5
Interrupt Open Drain Output
Pull Up Resistor, Controller Interrupt Line
+VS
8
Positive Supply Voltage Input
DC Voltage from 3V to 5.5V
User-Set Address Inputs
Ground (Low, “0”) or +VS (High, “1”)
A0–A1
2
7,6
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Typical Application
Figure 3. Typical Application
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
−0.3V to 6.5V
Supply Voltage
−0.3V to (+VS + 0.3V )
Voltage at any Pin
Input Current at any Pin
5 mA
Package Input Current (2)
20 mA
T_CRIT_A and INT Output Sink Current
10 mA
T_CRIT_A and INT Output Voltage
6.5V
−65°C to +125°C
Storage Temperature
Soldering Information, Lead Temperature
ESD Susceptibility (3)
Human Body Model
2500V
Machine Model
250V
For soldering specifications: http://www.ti.com/lit/SNOA549
(1)
(2)
(3)
(4)
(4)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not
apply when operating the device beyond its rated operating conditions.
When the input voltage (VI) at any pin exceeds the power supplies (VI < GND or VI > +VS) the current at that pin should be limited to 5
mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input
current of 5 mA to four.
Human body model, 100 pF discharged through a 1.5 kΩ resistor. Machine model, 200 pF discharged directly into each pin.
Reflow temperature profiles are different for lead-free and non-lead-free packages.
Operating Ratings (1) (2)
Specified Temperature Range
See
T MIN to TMAX
(3)
−55°C to +125°C
Supply Voltage Range (+VS) (4)
(1)
(2)
(3)
(4)
+3.0V to +5.5V
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not
apply when operating the device beyond its rated operating conditions.
LM77 θJA (thermal resistance, junction-to-ambient) when attached to a printed circuit board with 2 oz. foil is: 200°C/W for the SOIC-8
(D0008A) package, 250°C/W for the VSSOP-8 (DGK0008A) package.
While the LM77 has a full-scale-range in excess of 128°C, prolonged operation at temperatures above 125°C is not recommended.
Both part numbers of the LM77 will operate properly over the +VS supply voltage range of 3V to 5.5V . The devices are tested and
specified for rated accuracy at their nominal supply voltage. Accuracy will typically degrade 1°C/V of variation in +VS as it varies from
the nominal value.
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Temperature-to-Digital Converter Characteristics
Unless otherwise noted, these specifications apply for +VS=+5 Vdc ±10% for LM77CIM-5, LM77CIMM-5 and +VS=+3.3 Vdc
±10% for LM77CIM-3, LM77CIMM-3 (1). Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA= TJ=+25°C,
unless otherwise noted.
Parameter
Accuracy
Test Conditions
Typical (2)
Limits (3)
TA = −10°C to +65°C
±1.5
TA = −25°C to +100°C
±2.0
TA = −55°C to +125°C
±3.0
Units
(Limit)
°C (max)
Resolution
See (4)
Temperature Conversion Time
See (5)
Quiescent Current
I2C Inactive
0.25
I2C Active
0.25
0.5
mA (max)
10
μA
10
0.5
70
Bits
°C
125
ms
mA
Shutdown Mode
5
THYST Default Temperature
See (6) (7)
2
°C
TLOW Default Temperature
See (7)
10
°C
THIGH Default Temperature
See
(7)
64
°C
TC Default Temperature
See (7)
80
°C
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Both part numbers of the LM77 will operate properly over the +VS supply voltage range of 3V to 5.5V . The devices are tested and
specified for rated accuracy at their nominal supply voltage. Accuracy will typically degrade 1°C/V of variation in +VS as it varies from
the nominal value.
Typicals are at TA = 25°C and represent most likely parametric norm.
Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).
9 bits + sign, two's complement
This specification is provided only to indicate how often temperature data is updated. The LM77 can be read at any time without regard
to conversion state (and will yield last conversion result). If a conversion is in process it will be interrupted and restarted after the end of
the read.
Hysteresis value adds to the TLOW setpoint value (e.g.: if TLOW setpoint = 10°C, and hysteresis = 2°C, then actual hysteresis point is
10+2 = 12°C); and subtracts from the THIGH and T_CRIT setpoints (e.g.: if THIGH setpoint = 64°C, and hysteresis = 2°C, then actual
hysteresis point is 64−2 = 62°C). For a detailed discussion of the function of hysteresis refer to Section 1.1, TEMPERATURE
COMPARISON, and Figure 7.
Default values set at power up.
Logic Electrical Characteristics Digital DC Characteristics
Unless otherwise noted, these specifications apply for +VS=+5 Vdc ±10% for LM77CIM-5, LM77CIMM-5 and +VS=+3.3 Vdc
±10% for LM77CIM-3, LM77CIMM-3. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA= TJ=+25°C, unless
otherwise noted.
Parameter
VIN(1)
VIN(0)
VIN(1)
VIN(0)
Test Conditions
Typical (1)
SDA and SCL Logical “1” Input Voltage
SDA and SCL Logical “0” Input Voltage
A0 and A1 Logical “1” Input Voltage
A0 and A1 Logical “0” Input Voltage
Limits (2)
Units
(Limit)
+VS × 0.7
V (min)
+VS+0.3
V (max)
−0.3
V (min)
+VS × 0.3
V (max)
2.0
V (min)
+VS+0.3
V (max)
−0.3
V (min)
0.8
V (max)
IIN(1)
Logical “1” Input Current
VIN = + VS
0.005
1.0
μA (max)
IIN(0)
Logical “0” Input Current
VIN = 0V
−0.005
−1.0
μA (max)
CIN
Capacitance of All Digital Inputs
IOH
Logic “1” Output Leakage Current
10
μA (max)
(1)
(2)
4
20
VOH = + VS
pF
Typicals are at TA = 25°C and represent most likely parametric norm.
Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).
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Logic Electrical Characteristics Digital DC Characteristics (continued)
Unless otherwise noted, these specifications apply for +VS=+5 Vdc ±10% for LM77CIM-5, LM77CIMM-5 and +VS=+3.3 Vdc
±10% for LM77CIM-3, LM77CIMM-3. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA= TJ=+25°C, unless
otherwise noted.
Parameter
VOL
Low Level Output Voltage
T_CRIT_A Output Saturation Voltage
Test Conditions
Typical (1)
IOL = 3 mA
IOUT = 4.0 mA
(3)
T_CRIT_A Delay
tOF
Output Fall Time
CL = 400 pF
Limits (2)
Units
(Limit)
0.4
V (max)
0.8
V (max)
1
Conversions
(max)
250
ns (max)
IO = 3 mA
(3)
For best accuracy, minimize output loading. Higher sink currents can affect sensor accuracy with internal heating. This can cause an
error of 0.64°C at full rated sink current and saturation voltage based on junction-to-ambient thermal resistance.
Logic Electrical Characteristics Serial Bus Digital Switching Characteristics
Unless otherwise noted, these specifications apply for +VS=+5 Vdc ±10% for LM77CIM-5 and LM77CIMM-5, +VS=+3.3 Vdc
±10% for LM77CIM-3 and LM77CIMM-3, CL (load capacitance) on output lines = 80 pF unless otherwise specified. Boldface
limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C, unless otherwise noted.
Parameter
Test Conditions
Typical (1)
Limits (2) (3)
Units
(Limit)
t1
SCL (Clock) Period
2.5
μs(min)
t2
Data in Set-Up Time to SCL High
100
ns(min)
t3
Data Out Stable after SCL Low
0
ns(min)
t4
SDA Low Set-Up Time to SCL Low (Start Condition)
100
ns(min)
t5
SDA High Hold Time after SCL High (Stop Condition)
100
ns(min)
(1)
(2)
(3)
Typicals are at TA = 25°C and represent most likely parametric norm.
Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).
Timing specifications are tested at the bus input logic levels (Vin(0)=0.3xVA for a falling edge and Vin(1)=0.7xVA for a rising edge) when
the SCL and SDA edge rates are similar.
Figure 4.
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Figure 5. Temperature-to-Digital Transfer Function (Non-linear scale for clarity)
6
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FUNCTIONAL DESCRIPTION
The LM77 temperature sensor incorporates a band-gap type temperature sensor, 10-bit ADC, and a digital
comparator with user-programmable upper and lower limit values. The comparator activates either the INT line
for temperatures outside the TLOW and THIGH window, or the T_CRIT_A line for temperatures which exceed
T_CRIT. The lines are programmable for mode and polarity.
TEMPERATURE COMPARISON
LM77 provides a window comparison against a lower (TLOW) and upper (THIGH) trip point. A second upper trip
point (T_CRIT) functions as a critical alarm shutdown. Figure 7 depicts the comparison function as well as the
modes of operation.
Status Bits
The internal Status bits operate as follows:
“True”: Temperature above a THIGH or T_CRIT is “true” for those respective bits. A “true” for TLOW is
temperature below TLOW.
“False”: Assuming temperature has previously crossed above THIGH or T_CRIT, then the temperature must
drop below the points corresponding THYST(THIGH − THYST or T_CRIT − THYST) in order for the condition to be
false. For TLOW, assuming temperature has previously crossed below TLOW, a “false” occurs when temperature
goes above TLOW + THYST.
The Status bits are not affected by reads or any other actions, and always represent the state of temperature vs.
setpoints.
Hardwire Outputs
The T_CRIT_A hardwire output mirrors the T_CRIT_A flag unless the part is read. When the flag is true, the
T_CRIT_A output is asserted regardless of Interrupt Mode. Reading the LM77 resets the T_CRIT_A output until
the internal conversion is completed. In a typical system, T_CRIT_A is used to immediately shutdown or reset
the system. Thus, once T_CRIT_A asserts the system normally would not be reading the LM77 via the I2C bus.
The behavior of the INT hardwire output is as follows:
Comparator Interrupt Mode (Default): User reading part resets output until next measurement completes. If
condition is still true, output is set again at end of next conversion cycle. For example, if a user never reads the
part, and temperature goes below TLOW then INT becomes active. It would stay that way until temperature goes
above TLOW + THYST. However if the user reads the part, the output would be reset. At the end of the next
conversion cycle, if the condition is true, it is set again. If not, it remains reset.
Event Interrupt Mode: User reading part resets output until next condition "event" occurs (in other words,
output is only set once for a true condition, if reset by a read, it remains reset until the next triggering threshold
has been crossed). Conversely, if a user never read the part, the output would stay set indefinitely after the first
event that set the output. An “event” for Event Interrupt Mode is defined as:
1. Transitioning upward (downward) across a setpoint, or
2. Transitioning downward (upward) across a setpoint's corresponding hysteresis (after having exceeded that
setpoint).
For example, if a user never read the part, and temperature went below TLOW then INT would become active. It
would stay that way forever if a user never read the part.
However if the user read the part, the output would be reset. Even if the condition is true, it will remain reset. The
temperature must cross above TLOW + THYST to set the output again.
In either mode, reading any register in the LM77 restarts the conversion. This allows a designer to know exactly
when the LM77 begins a comparison. This prevents unnecessary Interrupts just after reprogramming setpoints.
Typically, system Interrupt inputs are masked prior to reprogramming trip points. By doing a read just after
resetting trip points, but prior to unmasking, unexpected Interrupts are prevented.
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Avoid programming setpoints so close that their hysteresis values overlap. An example would be that with a
THYST value of 2°C then setting THIGH and TLOW to within 4°C of each other will violate this restriction. To be more
specific, with THYST set to 2°C assume THIGH set to 64°C. If TLOW is set equal to, or higher than 60°C this
restriction is violated.
DEFAULT SETTINGS
The LM77 always powers up in a known state. LM77 power up default conditions are:
1. Comparator Interrupt Mode
2. TLOW set to 10°C
3. THIGH set to 64°C
4. T_CRIT set to 80°C
5. THYST set to 2°C
6. INT and T_CRIT_A active low
7. Pointer set to “00”; Temperature Register
The LM77 registers will always reset to these default values when the power supply voltage is brought up from
zero volts as the supply crosses the voltage level plotted in the following curve. The LM77 registers will reset
again when the power supply drops below the voltage plotted in this curve.
Average Power on Reset Voltage vs Temperature
Figure 6.
SERIAL BUS INTERFACE
The LM77 operates as a slave on the Serial Bus, so the SCL line is an input (no clock is generated by the LM77)
and the SDA line is a bi-directional serial data line. According to Serial Bus specifications, the LM77 has a 7-bit
slave address. The five most significant bits of the slave address are hard wired inside the LM77 and are
“10010”. The two least significant bits of the address are assigned to pins A1–A0, and are set by connecting
these pins to ground for a low, (0); or to +VS for a high, (1).
Therefore, the complete slave address is:
1
0
0
1
MSB
8
0
A1
A0
LSB
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Note: Event Interrupt mode is drawn as if the user is reading the part. If the user doesn't read, the outputs would go
low and stay that way until the LM77 is read.
Figure 7. Temperature Response Diagram
TEMPERATURE DATA FORMAT
Temperature data can be read from the Temperature and Set Point registers; and written to the Set Point
registers. Temperature data can be read at any time, although reading faster than the conversion time of the
LM77 will prevent data from being updated. Temperature data is represented by a 10-bit, two's complement word
with an LSB (Least Significant Bit) equal to 0.5°C:
Temperature
Digital Output
Binary
Hex
+130°C
01 0000 0100
104h
+125°C
00 1111 1010
0FAh
+25°C
00 0011 0010
032h
+0.5°C
00 0000 0001
001h
0°C
00 0000 0000
000h
−0.5°C
11 1111 1111
3FFh
−25°C
11 1100 1110
3CEh
−55°C
11 1001 0010
392h
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SHUTDOWN MODE
Shutdown mode is enabled by setting the shutdown bit in the Configuration register via the Serial Bus. Shutdown
mode reduces power supply current to 5 μA typical. T_CRIT_A is reset if previously set. Since conversions are
stoped during shutdown, T_CRIT_A and INT will not be operational. The Serial Bus interface remains active.
Activity on the clock and data lines of the Serial Bus may slightly increase shutdown mode quiescent current.
Registers can be read from and written to in shutdown mode. The LM77 takes miliseconds to respond to the
shutdown command.
INT AND T_CRIT_A OUTPUT
The INT and T_CRIT_A outputs are open-drain outputs and do not have internal pull-ups. A "high" level will not
be observed on these pins until pull-up current is provided from some external source, typically a pull-up resistor.
Choice of resistor value depends on many system factors but, in general, the pull-up resistor should be as large
as possible. This will minimize any errors due to internal heating of the LM77. The maximum allowable resistance
of the pull up resistor is 90K Ohms based on the Logic “1” Output Leakage Current and a 2 volt high output level.
FAULT QUEUE
A fault queue of up to 4 faults is provided to prevent false tripping when the LM77 is used in noisy environments.
The 4 faults must occur consecutively to set flags as well as INT and T_CRIT_A outputs. The fault queue is
enabled by setting bit 4 of the Configuration Register high (see Table 3).
INTERNAL REGISTER STRUCTURE
Figure 8.
The data registers in the LM77 are selected by the Pointer register. At power-up the Pointer is set to “00”; the
location for the Temperature Register. The Pointer register latches the last location it was set to. In Comparator
Interrupt Mode, a read from the LM77 resets the INT output. Placing the device in Shutdown mode resets the
INT and T_CRIT_A outputs. All registers are read and write, except the Temperature register which is read only.
A write to the LM77 will always include the address byte and the Pointer byte. A write to the Configuration
register requires one data byte, while the TLOW, THIGH, and T_CRIT registers require two data bytes.
10
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Reading the LM77 can take place either of two ways: If the location latched in the Pointer is correct (most of the
time it is expected that the Pointer will point to the Temperature register because it will be the data most
frequently read from the LM77), then the read can simply consist of an address byte, followed by retrieving the
corresponding number of data bytes. If the Pointer needs to be set, then an address byte, pointer byte, repeat
start, and another address byte plus required number of data bytes will accomplish a read.
The first data byte is the most significant byte with most significant bit first, permitting only as much data as
necessary to be read to determine the temperature condition. For instance, if the first four bits of the temperature
data indicates a critical condition, the host processor could immediately take action to remedy the excessive
temperature. At the end of a read, the LM77 can accept either Acknowledge or No Acknowledge from the Master
(No Acknowledge is typically used as a signal for the slave that the Master has read its last byte).
An inadvertent 8-bit read from a 16-bit register, with the D7 bit low, can cause the LM77 to stop in a state where
the SDA line is held low as shown in Figure 9. This can prevent any further bus communication until at least 9
additional clock cycles have occurred. Alternatively, the master can issue clock cycles until SDA goes high, at
which time issuing a “Stop” condition will reset the LM77.
Figure 9. Inadvertent 8-Bit Read from 16-Bit Register where D7 is Zero (“0”)
(Selects which registers will be read from or written to):
Table 1. POINTER REGISTER
P7
P6
P5
P4
P3
0
0
0
0
0
P2
P1
P0
Register Select
P0–P2: Register Select:
P2
P1
P0
Register
0
0
0
Temperature (Read only) (Power-up default)
0
0
1
Configuration (Read/Write)
0
1
0
THYST (Read/Write)
0
1
1
T_CRIT (Read/Write)
1
0
0
TLOW (Read/Write)
1
0
1
THIGH (Read/Write)
P3–P7: Must be kept zero.
Table 2. TEMPERATURE REGISTER (Read Only):
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Sign
Sign
Sign
Sign
MSB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CRIT
HIGH
LOW
Status Bits
D0–D2: Status Bits
D3–D15: Temperature Data. One LSB = 0.5°C. Two's complement format.
Table 3. CONFIGURATION REGISTER (Read/Write):
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
Fault Queue
INT Polarity
T_CRIT_A
Polarity
INT Mode
Shutdown
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D0: Shutdown - When set to 1 the LM77 goes to low power shutdown mode. Power up default of “0”.
D1: Interrupt mode - 0 is Comparator Interrupt mode, 1 is Event Interrupt mode. Power up default of “0”.
D2, D3: T_CRIT_A and INT Polarity - 0 is active low, 1 is active high. Outputs are open-drain. Power up default
of “0”
D4: Fault Queue - When set to 1 the Fault Queue is enabled, see FAULT QUEUE. Power up default of “0”.
D5–D7: These bits are used for production testing and must be kept zero for normal operation.
Table 4. THYST, TLOW, THIGH AND T_CRIT_A REGISTERS (Read/Write):
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Sign
Sign
Sign
Sign
MSB
Bit7
Bit6
Bit5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
D0–D2: Undefined
D3–D15: THYST, TLOW, THIGH or T_CRIT Trip Temperature Data. Power up default is TLOW = 10°C, THIGH = 64°C,
T_CRIT = 80°C, THYST = 2°C.
THYST is subtracted from THIGH, and T_CRIT, and added to TLOW.
Avoid programming setpoints so close that their hysteresis values overlap. See TEMPERATURE COMPARISON.
TEST CIRCUIT DIAGRAMS
I2C Timing Diagrams
Figure 10. Typical 2-Byte Read From Preset Pointer Location Such as Temp or Comparison Registers
Figure 11. Typical Pointer Set Followed by Immediate Read for 2-Byte Register such as Temp or
Comparison Registers
Figure 12. Typical 1-Byte Read from Configuration Register with Preset Pointer
12
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SNIS103F – JUNE 1999 – REVISED MARCH 2013
Figure 13. Typical Pointer Set Followed by Immediate Read from Configuration Register
Figure 14. Configuration Register Write
Comparison Register Write
Figure 15. Timing Diagrams
Application Hints
The temperature response graph in Figure 16 depicts a typical application designed to meet ACPI requirements.
In this type of application, the temperature scale is given an arbitrary value of "granularity", or the window within
which temperature notification events should occur. The LM77 can be programmed to the window size chosen by
the designer, and will issue interrupts to the processor whenever the window limits have been crossed. The
internal flags permit quick determination of whether the temperature is rising or falling.
The T_CRIT limit would typically use its separate output to activate hardware shutdown circuitry separate from
the processor. This is done because it is expected that if temperature has gotten this high that the processor may
not be responding. The separate circuitry can then shut down the system, usually by shutting down the power
supply.
Note that the INT and T_CRIT_A outputs are separate, but can be wire-or'd together. Alternatively the T_CRIT_A
can be diode or'd to the INT line in such a way that a T_CRIT_A event activates the INT line, but an INT event
does not activate the T_CRIT_A line. This may be useful in the event that it is desirable to notify both the
processor and separate T_CRIT_A shutdown circuitry of a critical temperature alarm at the same time (maybe
the processor is still working and can coordinate a graceful shutdown with the separate shutdown circuit).
To implement ACPI compatible sensing it is necessary to sense whenever the temperature goes outside the
window, issue an interrupt, service the interrupt, and reprogram the window according to the desired granularity
of the temperature scale. The reprogrammed window will now have the current temperature inside it, ready to
issue an interrupt whenever the temperature deviates from the current window.
To understand this graph, assume that at the left hand side the system is at some nominal temperature. For the
1st event temperature rises above the upper window limit, THIGH, causing INT to go active. The system responds
to the interrupt by querying the LM77's status bits and determines that THIGH was exceeded, indicating that
temperature is rising. The system then reprograms the temperature limits to a value higher by an amount equal
to the desired granularity. Note that in Event Interrupt Mode, reprogramming the limits has caused a second,
known, interrupt to be issued since temperature has been returned within the window. In Comparator Interrupt
Mode, the LM77 simply stops issuing interrupts.
The 2nd event is another identical rise in temperature. The 3rd event is typical of a drop in temperature. This is
one of the conditions that demonstrates the power of the LM77, as the user receives notification that a lower limit
is exceeded in such a way that temperature is dropping.
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The Critical Alarm Event activates the separate T_CRIT_A output. Typically, this would feed circuitry separate
from the processor on the assumption that if the system reached this temperature, the processor might not be
responding.
Note: Event Interrupt mode is drawn as if the user is reading the part. If the user doesn't read, the outputs would go
low and stay that way until the LM77 is read.
Figure 16. Temperature Response Diagram for ACPI Implementation
Typical Applications
Figure 17. Typical Application
14
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Figure 18. Remote HVAC temperature sensor communicates via 3 wires including thermostat signals
By powering the LM77 from auxilary output of the power supply, a non-functioning overheated computer can be
powered down to preserve as much of the system as possible.
Figure 19. ACPI Compatible Terminal Alarm Shutdown
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REVISION HISTORY
Changes from Revision E (March 2013) to Revision F
•
16
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM77CIM-3
NRND
SOIC
D
8
95
TBD
Call TI
Call TI
-55 to 125
LM77
CIM-3
LM77CIM-3/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 125
LM77
CIM-3
LM77CIM-5/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 125
LM77
CIM-5
LM77CIMM-3/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 125
T06C
LM77CIMM-5/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 125
T07C
LM77CIMMX-3/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 125
T06C
LM77CIMMX-5/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 125
T07C
LM77CIMX-3
NRND
SOIC
D
8
2500
TBD
Call TI
Call TI
-55 to 125
LM77
CIM-3
LM77CIMX-3/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 125
LM77
CIM-3
LM77CIMX-5/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 125
LM77
CIM-5
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM77CIMM-3/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM77CIMM-5/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM77CIMMX-3/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM77CIMMX-5/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM77CIMX-3
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM77CIMX-3/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM77CIMX-5/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM77CIMM-3/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LM77CIMM-5/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LM77CIMMX-3/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LM77CIMMX-5/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LM77CIMX-3
SOIC
D
8
2500
367.0
367.0
35.0
LM77CIMX-3/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LM77CIMX-5/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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