LINER LTC1864L Ultra-tiny, differential, 16-bit adc with spi interface spi interface Datasheet

LTC2452
Ultra-Tiny, Differential, 16-Bit
ΔΣ ADC with SPI Interface
DESCRIPTION
FEATURES
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±VCC Differential Input Range
16-Bit Resolution (Including Sign), No Missing
Codes
2LSB Offset Error
4LSB Full-Scale Error
60 Conversions Per Second
Single Conversion Settling Time for Multiplexed
Applications
Single-Cycle Operation with Auto Shutdown
800µA Supply Current
0.2µA Sleep Current
Internal Oscillator—No External Components
Required
SPI Interface
Ultra-Tiny 3mm × 2mm DFN and TSOT-23 Packages
APPLICATIONS
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System Monitoring
Environmental Monitoring
Direct Temperature Measurements
Instrumentation
Industrial Process Control
Data Acquisition
Embedded ADC Upgrades
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and No
Latency ∆Σ is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 6208279, 6411242,
7088280, 7164378.
The LTC®2452 is an ultra-tiny, fully differential, 16-bit,
analog-to-digital converter. The LTC2452 uses a single
2.7V to 5.5V supply and communicates through an SPI
interface. The ADC is available in an 8-pin, 3mm × 2mm
DFN package or TSOT-23 package. It includes an integrated
oscillator that does not require any external components.
It uses a delta-sigma modulator as a converter core and
has no latency for multiplexed applications. The LTC2452
includes a proprietary input sampling scheme that reduces
the average input sampling current several orders of
magnitude when compared to conventional delta-sigma
converters. Additionally, due to its architecture, there is
negligible current leakage between the input pins.
The LTC2452 can sample at 60 conversions per second,
and due to the very large oversampling ratio, has extremely
relaxed antialiasing requirements. The LTC2452 includes
continuous internal offset and full-scale calibration algorithms which are transparent to the user, ensuring accuracy
over time and over the operating temperature range. The
converter has an external REF pin and the differential input
voltage range can extend up to ±VREF .
Following a single conversion, the LTC2452 can automatically enter a sleep mode and reduce its supply current to
less than 0.2µA. If the user reads the ADC once a second,
the LTC2452 consumes an average of less than 50µW
from a 2.7V supply.
TYPICAL APPLICATION
Integral Nonlinearity, VCC = 3V
3
2.7V TO 5.5V
0.1µF
10k
IN+
10k
IN–
10k
R
0.1µF
REF
VCC
1
CS
LTC2452
SCK
SDO
3-WIRE SPI
INTERFACE
INL (LSB)
0.1µF
2
10µF
TA = –45°C, 25°C, 90°C
0
–1
GND
–2
2452 TA01a
–3
–3
1
2
–2
–1
0
DIFFERENTIAL INPUT VOLTAGE (V)
3
2452 TA01b
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1
LTC2452
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VCC).................................... –0.3V to 6V
Analog Input Voltage (VIN+, VIN–)... –0.3V to (VCC + 0.3V)
Reference Voltage (VREF)............... –0.3V to (VCC + 0.3V)
Digital Voltage (VSDO, VSCK, VCS)... –0.3V to (VCC + 0.3V)
Storage Temperature Range.................... –65°C to 150°C
Operating Temperature Range
LTC2452C................................................. 0°C to 70°C
LTC2452I.............................................. –40°C to 85°C
PIN CONFIGURATION
TOP VIEW
SCK
1
GND
2
REF
3
VCC
4
9
8
SDO
7
CS
6
IN
+
5
IN–
TOP VIEW
SCK 1
GND 2
REF 3
VCC 4
DD8 PACKAGE
8-LEAD (3mm × 2mm) PLASTIC DFN
C/I GRADE TJMAX = 125°C, θJA = 76°C/W
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
8 SDO
7 CS
6 IN+
5 IN–
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
C/I GRADE TJMAX = 125°C, θJA = 140°C/W
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI)
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2452CDDB#TRMPBF
LTC2452CDDB#TRPBF
LDNJ
8-Lead Plastic (3mm × 2mm) DFN
LTC2452IDDB#TRMPBF
LTC2452IDDB#TRPBF
LDNJ
8-Lead Plastic (3mm × 2mm) DFN
LTC2452CTS8#TRMPBF
LTC2452CTS8#TRPBF
LTDPK
8-Lead Plastic TSOT-23
LTC2452ITS8#TRMPBF
LTC2452ITS8#TRPBF
LTDPK
8-Lead Plastic TSOT-23
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
16
UNITS
Bits
Resolution (No Missing Codes)
(Note 3)
l
Integral Nonlinearity
(Note 4)
l
1
10
LSB
l
2
10
LSB
Offset Error
Offset Error Drift
Gain Error
0.02
l
0.01
LSB/°C
0.02
% of FS
Gain Error Drift
0.02
LSB/°C
Transition Noise
2.2
µVRMS
Power Supply Rejection DC
80
dB
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2
LTC2452
ANALOG INPUTS AND REFERENCES
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0
VCC
V
l
0
VCC
V
l
2.5
+
Positive Input Voltage Range
l
VIN
–
Negative Input Voltage Range
VREF
Reference Voltage Range
VOR+ + VUR+
Overrange + Underrange Voltage, IN+
VREF = 5V, VIN– = 2.5V (See Figure 3)
31
LSB
VOR– + VUR–
Overrange + Underrange Voltage, IN–
VREF = 5V, VIN+ = 2.5V (See Figure 3)
31
LSB
CIN
IN+, IN– Sampling Capacitance
IDC_LEAK(IN+)
IN+ DC Leakage Current
VIN = GND (Note 10)
VIN = VCC (Note 10)
l
l
–10
–10
1
1
10
10
nA
nA
IDC_LEAK(IN–)
IN– DC Leakage Current
VIN = GND (Note 10)
VIN = VCC (Note 10)
l
l
–10
–10
1
1
10
10
nA
nA
IDC_LEAK(REF)
REF DC Leakage Current
VREF = 3V (Note 10)
l
–10
1
10
nA
ICONV
Input Sampling Current (Note 5)
VIN
VCC
V
0.35
pF
50
nA
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
Conversion
Sleep
CONDITIONS
MIN
l
CS = GND (Note 6)
CS = VCC (Note 6)
TYP
2.7
800
0.2
l
l
MAX
UNITS
5.5
V
1200
0.6
µA
µA
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the full
operating temperature range,otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
l
VIL
Low Level Input Voltage
l
IIN
Digital Input Current
l
–10
VCC – 0.5
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
IO = –800µA
l
VOL
Low Level Output Voltage
IO = 1.6mA
l
IOZ
Hi-Z Output Leakage Current
TYP
MAX
VCC – 0.3
V
0.3
V
10
µA
10
l
–10
UNITS
pF
V
0.4
V
10
µA
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LTC2452
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range,otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
tCONV
Conversion Time
CONDITIONS
l
fSCK
SCK Frequency Range
l
tlSCK
SCK Low Period
l
250
ns
thSCK
SCK High Period
l
250
ns
t1
CS Falling Edge to SDO Low Z
(Notes 7, 8)
l
0
100
ns
t2
CS Rising Edge to SDO High Z
(Notes 7, 8)
l
0
100
ns
t3
CS Falling Edge to SCK Falling Edge
l
100
tKQ
SCK Falling Edge to SDO Valid
l
0
(Note 7)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. All voltage values are with respect to GND. VCC = 2.7V to 5.5V
unless otherwise specified.
VREFCM = VREF/2, FS = VREF
VIN = VIN+ – VIN–, –VREF ≤ VIN ≤ VREF; VINCM = (VIN+ + VIN–)/2.
Note 3. Guaranteed by design, not subject to test.
Note 4. Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
Guaranteed by design and test correlation.
Integral Nonlinearity, VCC = 5V
3
2
2
TA = 90°C
Integral Nonlinearity, VCC = 3V
TA = –45°C, 25°C
0
–2
–2
2452 G01
MHz
ns
100
ns
–3
1
2
–2
–1
0
DIFFERENTIAL INPUT VOLTAGE (V)
3
2452 G02
VCC = VREF = 5V, 4.1V, 3V
0
–2
–3
2
1
TA = –45°C, 25°C, 90°C
–1
5
ms
2
–1
–5 –4 –3 –2 –1 0 1 2 3 4
DIFFERENTIAL INPUT VOLTAGE (V)
UNITS
Maximum INL vs Temperature
–1
–3
23
3
INL (LSB)
0
MAX
16.6
(TA = 25°C, unless otherwise noted)
1
INL (LSB)
INL (LSB)
1
TYP
13
Note 5: CS = VCC. A positive current is flowing into the DUT pin.
Note 6: SCK = VCC or GND. SDO is high impedance.
Note 7: See Figure 4.
Note 8: See Figure 5.
Note 9: Input sampling current is the average input current drawn from the
input sampling network while the LTC2452 is actively sampling the input.
Note 10: A positive current is flowing into the DUT pin.
TYPICAL PERFORMANCE CHARACTERISTICS
3
MIN
–3
–50
–25
25
50
0
TEMPERATURE (°C)
75
100
2452 G03
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LTC2452
TYPICAL PERFORMANCE CHARACTERISTICS
Gain Error vs Temperature
5
4
4
3
3
2
2
1
VCC = VREF = 5V
0
–1
–2
VCC = VREF = 3V
–3
VCC = VREF = 4.1V
Transition Noise vs Temperature
10
9
VCC = VREF = 3V
TRANSITION NOISE RMS (µV)
5
GAIN ERROR (LSB)
OFFSET ERROR (LSB)
Offset Error vs Temperature
(TA = 25°C, unless otherwise noted)
VCC = VREF = 4.1V
1
0
VCC = VREF = 5V
–1
–2
–3
–4
–4
–5
–50
–25
25
50
0
TEMPERATURE (°C)
75
–25
25
50
0
TEMPERATURE (°C)
75
2452 G04
VCC = 4.1V
100
50
75
VCC = 3V
100
0
–50
–25
25
50
0
TEMPERATURE (°C)
2452 G07
25
50
0
TEMPERATURE (°C)
75
100
75
100
25Hz OUTPUT SAMPLE RATE
10Hz OUTPUT SAMPLE RATE
100
1Hz OUTPUT SAMPLE RATE
10
0
–50
–25
25
50
0
TEMPERATURE (°C)
75
100
2452 G09
2452 G08
Power Supply Rejection
vs Frequency at VCC
Conversion Time vs Temperature
21
0
20
CONVERSION TIME (ms)
–20
–40
–60
–80
–100
–120
–25
2452 G06
AVERAGE POWER DISSIPATION (µW)
SLEEP CURRENT (nA)
150
100
25
50
0
TEMPERATURE (°C)
VCC = 3V
1000
VCC = 5V
200
REJECTION (dB)
CONVERSION CURRENT (µA)
VCC = 4.1V
300
–25
2
10000
200
VCC = 5V
400
0
–50
3
Average Power Dissipation
vs Temperature, VCC = 3V
250
VCC = 3V
VCC = 5V
4
0
–50
100
800
500
5
Sleep Mode Power Supply
Current vs Temperature
900
600
6
2452 G05
Conversion Mode Power Supply
Current vs Temperature
700
7
1
–5
–50
100
8
19
VCC = 5V, 4.1V, 3V
18
17
16
15
1
10
100 1k 10k 100k
FREQUENCY AT VCC (Hz)
1M
10M
2452 G10
14
–50
–25
25
50
0
TEMPERATURE (°C)
75
100
2452 G11
2452fc
5
LTC2452
PIN FUNCTIONS
SCK (Pin 1): Serial Clock Input. SCK synchronizes the serial
data output. While digital data is available (the ADC is not
in CONVERT state) and CS is LOW (ADC is not in SLEEP
state) a new data bit is produced at the SDO output pin
following every falling edge applied to the SCK pin.
GND (Pin 2): Ground. Connect to a ground plane through
a low impedance connection.
REF (Pin 3): Reference Input. The voltage on REF can have
any value between 2.5V and VCC. The reference voltage
sets the full-scale range.
VCC (Pin 4): Positive Supply Voltage. Bypass to GND
(Pin 2) with a 10µF capacitor in parallel with a low-series-inductance 0.1µF capacitor located as close to the
LTC2452 as possible.
IN– (Pin 5), IN+ (Pin 6): Differential Analog Input.
CS (Pin 7): Chip Select (Active LOW) Digital Input. A
LOW on this pin enables the SDO digital output. A HIGH
on this pin places the SDO output pin in a high impedance state.
SDO (Pin 8): Three-State Serial Data Output. SDO is used
for serial data output during the DATA OUTPUT state and
can be used to monitor the conversion status.
Exposed Pad (Pin 9): Ground. Must be soldered to PCB
ground. For prototyping purposes, this pad may remain
floating.
BLOCK DIAGRAM
3
4
REF
VCC
CS
6
IN
+
SPI
INTERFACE
16-BIT ΔΣ
A/D CONVERTER
–
5
IN–
16-BIT ΔΣ
A/D CONVERTER
2, 9
SDO
SCK
7
8
1
DECIMATING
SINC FILTER
INTERNAL
OSCILLATOR
GND
2452 BD
Figure 1. Functional Block Diagram
APPLICATIONS INFORMATION
CONVERTER OPERATION
Converter Operation Cycle
The LTC2452 is a low power, fully differential, delta-sigma
analog-to-digital converter with a simple 3-wire SPI interface (see Figure 1). Its operation is composed of three
successive states: CONVERT, SLEEP and DATA OUTPUT.
The operating cycle begins with the CONVERT state, is
followed by the SLEEP state, and ends with the DATA OUTPUT state (see Figure 2). The 3-wire interface consists of
serial data output (SDO), serial clock input (SCK), and the
active low chip select input (CS).
The CONVERT state duration is determined by the LTC2452
conversion time (nominally 16.6 milliseconds). Once
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LTC2452
APPLICATIONS INFORMATION
corresponds to the last completed conversion. A new bit
of data appears at the SDO pin following each falling edge
detected at the SCK input pin and appears from MSB to
LSB. The user can reliably latch this data on every rising
edge of the external serial clock signal driving the SCK
pin (see Figure 3).
POWER-ON RESET
CONVERT
SLEEP
NO
The DATA OUTPUT state concludes in one of two different
ways. First, the DATA OUTPUT state operation is completed
once all 16 data bits have been shifted out and the clock
then goes low. This corresponds to the 16th falling edge
of SCK. Second, the DATA OUTPUT state can be aborted
at any time by a LOW-to-HIGH transition on the CS input.
Following either one of these two actions, the LTC2452
will enter the CONVERT state and initiate a new conversion cycle.
SCK = LOW
AND
CS = LOW?
YES
DATA OUTPUT
NO
16TH FALLING
EDGE OF SCK
OR
CS = HIGH?
YES
2452 F02
Figure 2. LTC2452 State Transition Diagram
started, this operation can not be aborted except by a low
power supply condition (VCC < 2.1V) which generates an
internal power-on reset signal.
After the completion of a conversion, the LTC2452 enters
the SLEEP state and remains there until both the chip
select and serial clock inputs are low (CS = SCK = LOW).
Following this condition, the ADC transitions into the DATA
OUTPUT state.
While in the SLEEP state, whenever the chip select input
is pulled high (CS = HIGH), the LTC2452’s power supply
current is reduced to less than 200nA. When the chip select
input is pulled low (CS = LOW), and SCK is maintained
at a HIGH logic level, the LTC2452 will return to a normal
power consumption level. During the SLEEP state, the
result of the last conversion is held indefinitely in a static
register.
Upon entering the DATA OUTPUT state, SDO outputs the
sign (D15) of the conversion result. During this state,
the ADC shifts the conversion result serially through the
SDO output pin under the control of the SCK input pin.
There is no latency in generating this data and the result
Power-Up Sequence
When the power supply voltage (VCC) applied to the converter is below approximately 2.1V, the ADC performs a
power-on reset. This feature guarantees the integrity of
the conversion result.
When VCC rises above this critical threshold, the converter
generates an internal power-on reset (POR) signal for
approximately 0.5ms. The POR signal clears all internal
registers. Following the POR signal, the LTC2452 starts a
conversion cycle and follows the succession of states shown
in Figure 2. The first conversion result following POR is
accurate within the specifications of the device if the power
supply voltage VCC is restored within the operating range
(2.7V to 5.5V) before the end of the POR time interval.
Ease of Use
The LTC2452 data output has no latency, filter settling delay
or redundant results associated with the conversion cycle.
There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple
analog input voltages requires no special actions.
The LTC2452 performs offset calibrations every conversion. This calibration is transparent to the user and has no
effect upon the cyclic operation described previously. The
advantage of continuous calibration is stability of the ADC
performance with respect to time and temperature.
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LTC2452
APPLICATIONS INFORMATION
The LTC2452 includes a proprietary input sampling scheme
that reduces the average input current by several orders
of magnitude when compared to traditional delta-sigma
architectures. This allows external filter networks to interface directly to the LTC2452. Since the average input
sampling current is 50nA, an external RC lowpass filter
using 1kΩ and 0.1µF results in <1LSB additional error.
Additionally, there is negligible leakage current between
IN+ and IN–.
20
16
12
OUTPUT CODE
8
4
0
–4
SIGNALS
BELOW
GND
–8
–12
–16
–20
–0.001
–0.005
Reference Voltage Range
0.005
0
VIN+/VREF+
0.001
0.0015
2452 F03
The LTC2453 reference input range is 2.5V to VCC. For the
simplest operation, REF can be shorted to VCC.
Input Voltage Range
As mentioned in the Output Data Format section, the output
code is given as 32768•VIN/VREF + 32768. For VIN ≥ VREF,
the output code is clamped at 65535 (all ones). For VIN ≤
–VREF, the output code is clamped at 0 (all zeroes).
The LTC2452 includes a proprietary system that can,
typically, digitize each input 8LSB above VREF and below
GND, if the differential input is within ±VREF. As an example (Figure 3), if the user desires to measure a signal
slightly below ground, the user could set VIN– = GND,
and VREF = 5V. If VIN+ = GND, the output code would be
approximately 32768. If VIN+ = GND – 8LSB = –1.22 mV,
the output code would be approximately 32760.
Figure 3. Output Code vs VIN+ with VIN– = 0
The total amount of overrange and underrange capability
is typically 31LSB for a given device. The 31LSB total
is distributed between the overrange and underrange
capability. For example, if the underrange capability is
8LSB, the overrange capability is typically 31 – 8 = 23LSB.
Output Data Format
The LTC2452 generates a 16-bit direct binary encoded
result. It is provided as a 16-bit serial stream through the
SDO output pin under the control of the SCK input pin
(see Figure 4).
Letting VIN = (VIN+ – VIN–), the output code is given
as 32768•VIN/VREF + 32768. The first bit output by the
LTC2452, D15, is the MSB, which is 1 for VIN+ ≥ VIN– and
0 for VIN+ < VIN–. This bit is followed by successively less
significant bits (D14, D13...) until the LSB is output by the
LTC2452. Table 1 shows some example output codes.
Table 1. LTC2452 Output Data Format
DIFFERENTIAL INPUT
VOLTAGE VIN+ – VIN–
≥VREF
D15
(MSB)
D14
D13
D12...D2
D1
1
1
1
1
1
D0 CORRESPONDING
(LSB) DECIMAL VALUE
1
65535
VREF – 1LSB
1
1
1
1
1
0
65534
0.5•VREF
1
1
0
0
0
0
49152
0.5•VREF – 1LSB
1
0
1
1
1
1
49151
0
1
0
0
0
0
0
32768
–1LSB
0
1
1
1
1
1
32767
–0.5•VREF
0
1
0
0
0
0
16384
–0.5•VREF – 1LSB
0
0
1
1
1
1
16383
≤ –VREF
0
0
0
0
0
0
0
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LTC2452
APPLICATIONS INFORMATION
t1
t3
t2
CS
D14
D15
SDO
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
MSB
D3
D2
D1
D0
LSB
SCK
2452 F04
tKQ
tlSCK
thSCK
Figure 4. Data Output Timing
t2
t1
CS
SDO
SCK = HIGH
CONVERT
SLEEP
2452 F05
Figure 5. Conversion Status Monitoring Mode
During the data output operation the CS input pin must
be pulled low (CS = LOW). The data output process starts
with the most significant bit of the result being present
at the SDO output pin (SDO = D15) once CS goes low.
A new data bit appears at the SDO output pin after each
falling edge detected at the SCK input pin. The output
data can be reliably latched by the user using the rising
edge of SCK.
indication of a completed conversion cycle. An example
of such a sequence is shown in Figure 5.
Conversion status monitoring, while possible, is not required for LTC2452 as its conversion time is fixed and equal
at approximately 16.6ms (23ms maximum). Therefore,
external timing can be used to determine the completion of a
conversion cycle.
Conversion Status Monitor
SERIAL INTERFACE
For certain applications, the user may wish to monitor
the LTC2452 conversion status. This can be achieved
by holding SCK HIGH during the conversion cycle. In
this condition, whenever the CS input pin is pulled low
(CS = LOW), the SDO output pin will provide an indication
of the conversion status. SDO = HIGH is an indication of
a conversion cycle in progress while SDO = LOW is an
The LTC2452 transmits the conversion result and receives
the start of conversion command through a synchronous
3-wire interface. This interface can be used during the
CONVERT and SLEEP states to assess the conversion
status and during the DATA OUTPUT state to read the
conversion result, and to trigger a new conversion.
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LTC2452
APPLICATIONS INFORMATION
Serial Interface Operation Modes
Serial Clock Idle-High (CPOL = 1) Examples
The modes of operation can be summarized as follows:
In Figure 6, following a conversion cycle the LTC2452
automatically enters the low power sleep mode. The user
can monitor the conversion status at convenient intervals
using CS and SDO.
1) The LTC2452 functions with SCK idle high (commonly
known as CPOL = 1) or idle low (commonly known as
CPOL = 0).
Pulling CS LOW while SCK is HIGH tests whether or not
the chip is in the CONVERT state. While in the CONVERT
state, SDO is HIGH while CS is LOW. In the SLEEP state,
SDO is LOW while CS is LOW. These tests are not required
operational steps but may be useful for some applications.
2) After the 16th bit is read, the user can choose one of
two ways to begin a new conversion. First, one can
pull CS high (CS = ↑). Second, one can use a high-low
transition on SCK (SCK = ↓).
3) At any time during the Data Output state, pulling CS
high (CS = ↑) causes the part to leave the I/O state,
abort the output and begin a new conversion.
When the data is available, the user applies 16 clock cycles
to transfer the result. The CS rising edge is then used to
initiate a new conversion.
4) When SCK = HIGH, it is possible to monitor the conversion status by pulling CS low and watching for SDO to
go low. This feature is available only in the idle-high
(CPOL = 1) mode.
The operation example of Figure 7 is identical to that of
Figure 6, except the new conversion cycle is triggered by
the falling edge of the serial clock (SCK). A 17th clock
pulse is used to trigger a new conversion cycle.
CS
SD0
D15
D14
D13
D12
D2
D1
D0
SCK
clk1
CONVERT
clk2
clk3
SLEEP
clk4
clk15
clk16
DATA OUTPUT
CONVERT
2452 F06
Figure 6. Idle-High (CPOL = 1) Serial Clock Operation Example.
The Rising Edge of CS Starts a New Conversion
CS
SD0
D15
D14
D13
D12
D2
D1
D0
SCK
clk1
CONVERT
SLEEP
clk2
clk3
clk4
clk15
clk16
DATA OUTPUT
clk17
CONVERT
2452 F07
Figure 7. Idle-High (CPOL = 1) Clock Operation Example.
A 17th Clock Pulse is Used to Trigger a New Conversion Cycle
2452fc
10
LTC2452
APPLICATIONS INFORMATION
CS
SD0
D15
D14
D13
clk1
clk2
clk3
D12
D2
D1
D0
clk15
clk16
SCK
CONVERT
SLEEP
clk4 clk14
DATA OUTPUT
CONVERT
2452 F08
Figure 8. Idle-Low (CPOL = 0) Clock. CS Triggers a New Conversion
CS
SD0
D15
D14
clk1
clk2
D13
D12
D2
D1
clk14
clk15
D0
SCK
CONVERT
SLEEP
clk3
clk4
DATA OUTPUT
clk16
CONVERT
2452 F09
Figure 9. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge Triggers a New Conversion
Serial Clock Idle-Low (CPOL = 0) Examples
Examples of Aborting Cycle using CS
In Figure 8, following a conversion cycle the LTC2452
automatically enters the low-power sleep state. The user
determines data availability (and the end of conversion)
based upon external timing. The user then pulls CS low
(CS = ↓) and uses 16 clock cycles to transfer the result.
Following the 16th rising edge of the clock, CS is pulled high
(CS = ↑), which triggers a new conversion.
For some applications, the user may wish to abort the I/O
cycle and begin a new conversion. If the LTC2452 is in
the data output state, a CS rising edge clears the remaining data bits from the output registers, aborts the output
cycle and triggers a new conversion. Figure 10 shows
an example of aborting an I/O with idle-high (CPOL = 1)
and Figure 11 shows an example of aborting an I/O with
idle-low (CPOL = 0).
The timing diagram in Figure 9 is identical to that of Figure 8,
except in this case a new conversion is triggered by SCK.
The 16th SCK falling edge triggers a new conversion cycle
and the CS signal is subsequently pulled high.
A new conversion cycle can be triggered using the CS
signal without having to generate any serial clock pulses
as shown in Figure 12. If SCK is maintained at a low logic
level, after the end of a conversion cycle, a new conver2452fc
11
LTC2452
APPLICATIONS INFORMATION
CS
SD0
D15
D14
D13
SCK
clk1
CONVERT
SLEEP
clk2
clk3
clk4
DATA OUTPUT
CONVERT
2452 F10
Figure 10. Idle-High (CPOL = 1) Clock and Aborted I/O Example
CS
SD0
D15
D14
clk1
clk2
D13
SCK
CONVERT
SLEEP
DATA OUTPUT
clk3
CONVERT
2452 F11
Figure 11. Idle-Low (CPOL = 0) Clock and Aborted I/O Example
CS
SD0
D15
SCK = LOW
CONVERT
SLEEP
DATA OUTPUT
CONVERT
2452 F12
Figure 12. Idle-Low (CPOL = 0) Clock and Minimum Data Output Length Example
2452fc
12
LTC2452
APPLICATIONS INFORMATION
Figure 13 shows a 2-wire operation sequence which uses
an idle-high (CPOL = 1) serial clock signal. The conversion
status can be monitored at the SDO output. Following a
conversion cycle, the ADC enters SLEEP state and the
SDO output transitions from HIGH to LOW. Subsequently
16 clock pulses are applied to the SCK input in order
to serially shift the 16 bit result. Finally, the 17th clock
pulse is applied to the SCK input in order to trigger a new
conversion cycle.
sion operation can be triggered by pulling CS low and
then high. When CS is pulled low (CS = LOW), SDO will
output the sign (D15) of the result of the just completed
conversion. While a low logic level is maintained at SCK
pin and CS is subsequently pulled high (CS = HIGH) the
remaining 15 bits of the result (D14:D0) are discarded
and a new conversion cycle starts.
Following the aborted I/O, additional clock pulses in the
CONVERT state are acceptable, but excessive signal transitions on SCK can potentially create noise on the ADC
during the conversion, and thus may negatively influence
the conversion accuracy.
Figure 14 shows a 2-wire operation sequence which uses
an idle-low (CPOL = 0) serial clock signal. The conversion
status cannot be monitored at the SDO output. Following
a conversion cycle, the LTC2452 bypasses the SLEEP
state and immediately enters the DATA OUTPUT state. At
this moment the SDO pin outputs the sign (D15) of the
conversion result. The user must use external timing in
order to determine the end of conversion and result availability. Subsequently 16 clock pulses are applied to SCK
in order to serially shift the 16-bit result. The 16th clock
falling edge triggers a new conversion cycle.
2-Wire Operation
The 2-wire operation modes, while reducing the number of
required control signals, should be used only if the LTC2452
low power sleep capability is not required. In addition the
option to abort serial data transfers is no longer available.
Hardwire CS to GND for 2-wire operation.
CS = LOW
D15
SD0
D14
D13
D12
D2
D1
D0
SCK
clk1
CONVERT
clk2
clk3
SLEEP
clk4
clk15
clk16
clk17
DATA OUTPUT
CONVERT
2452 F13
Figure 13. 2-Wire, Idle-High (CPOL = 1) Serial Clock, Operation Example
CS = LOW
SD0
D15
D14
D13
D12
D2
D1
D0
clk1
clk2
clk3
clk4 clk14
clk15
clk16
SCK
CONVERT
DATA OUTPUT
CONVERT
2452 F14
Figure 14. 2-Wire, Idle-Low (CPOL = 0) Serial Clock Operation Example
2452fc
13
LTC2452
APPLICATIONS INFORMATION
PRESERVING THE CONVERTER ACCURACY
The LTC2452 is designed to minimize the conversion result’s
sensitivity to device decoupling, PCB layout, antialiasing
circuits, line and frequency perturbations. Nevertheless,
in order to preserve the high accuracy capability of this
part, some simple precautions are desirable.
Digital Signal Levels
Due to the nature of CMOS logic, it is advisable to keep input
digital signals near GND or VCC. Voltages in the range of
0.5V to VCC – 0.5V may result in additional current leakage
from the part. Undershoot and overshoot should also be
minimized, particularly while the chip is converting. It is
thus beneficial to keep edge rates of about 10ns and limit
overshoot and undershoot to less than 0.3V.
Noisy external circuitry can potentially impact the output
under 2-wire operation. In particular, it is possible to get
the LTC2452 into an unknown state if an SCK pulse is
missed or noise triggers an extra SCK pulse. In this situation, it is impossible to distinguish SDO = 1 (indicating
conversion in progress) from valid “1” data bits. As such,
CPOL = 1 is recommended for the 2-wire mode. The user
should look for SDO = 0 before reading data, and look
for SDO = 1 after reading data. If SDO does not return a
“0” within the maximum conversion time (or return a “1”
after a full data read), generate 16 SCK pulses to force a
new conversion.
Driving VCC and GND
In relation to the VCC and GND pins, the LTC2452 combines
internal high frequency decoupling with damping elements,
which reduce the ADC performance sensitivity to PCB
layout and external components. Nevertheless, the very
high accuracy of this converter is best preserved by careful
low and high frequency power supply decoupling.
A 0.1µF, high quality, ceramic capacitor in parallel with a
10µF ceramic capacitor should be connected between the
VCC and GND pins, as close as possible to the package.
The 0.1µF capacitor should be placed closest to the ADC
package. It is also desirable to avoid any via in the circuit
path, starting from the converter VCC pin, passing through
these two decoupling capacitors, and returning to the
converter GND pin. The area encompassed by this circuit
path, as well as the path length, should be minimized.
Furthermore, as shown in Figure 15, GND is used as the
negative reference voltage. It is thus important to keep the
GND line quiet and connect GND through a low-impedance trace.
Very low impedance ground and power planes, and star
connections at both VCC and GND pins, are preferable.
The VCC pin should have two distinct connections: the
first to the decoupling capacitors described above, and
the second to the ground return for the power supply
voltage source.
Driving REF
A simplified equivalent circuit for REF is shown in Figure
15. Like all other A/D converters, the LTC2452 is only
as accurate as the reference it is using. Therefore, it is
important to keep the reference line quiet by careful low
and high frequency decoupling.
VCC
ILEAK
RSW
15k
(TYP)
REF
ILEAK
VCC
ILEAK
IN+
RSW
15k
(TYP)
ILEAK
VCC
ILEAK
IN–
CEQ
0.35pF
(TYP)
RSW
15k
(TYP)
ILEAK
VCC
ILEAK
GND
RSW
15k
(TYP)
2452 F15
ILEAK
Figure 15. LTC2452 Analog Input/Reference Equivalent Circuit
2452fc
14
LTC2452
APPLICATIONS INFORMATION
The LT6660 reference is an ideal match for driving the
LTC2452’s REF pin. The LTC6660 is available in a 2mm
× 2mm DFN package with 2.5V, 3V, 3.3V and 5V options.
There are some immediate trade-offs in RS and CIN without
needing a full circuit analysis. Increasing RS and CIN can
give the following benefits:
A 0.1µF, high quality, ceramic capacitor in parallel with a
10µF ceramic capacitor should be connected between the
REF and GND pins, as close as possible to the package. The
0.1µF capacitor should be placed closest to the ADC.
1) Due to the LTC2452’s input sampling algorithm, the input
current drawn by either VIN+ or VIN– over a conversion
cycle is typically 50nA. A high RS • CIN attenuates the
high frequency components of the input current, and
RS values up to 1k result in <1LSB error.
Driving VIN+ and VIN–
The input drive requirements can best be analyzed using
the equivalent circuit of Figure 16. The input signal VSIG is
connected to the ADC input pins (IN+ and IN–) through an
equivalent source resistance RS. This resistor includes both
the actual generator source resistance and any additional
optional resistors connected to the input pins. Optional
input capacitors CIN are also connected to the ADC input
pins. This capacitor is placed in parallel with the ADC
input parasitic capacitance CPAR. Depending on the PCB
layout, CPAR has typical values between 2pF and 15pF. In
addition, the equivalent circuit of Figure 16 includes the
converter equivalent internal resistor RSW and sampling
capacitor CEQ.
VCC
ILEAK
RS
SIG+
+
–
IN+
ILEAK
CIN
CEQ
0.35pF
(TYP)
CPAR
VCC
ILEAK
RS
SIG–
+
–
IN–
ILEAK
CIN
CPAR
RSW
15k
(TYP)
ICONV
RSW
15k
(TYP)
CEQ
0.35pF
(TYP)
ICONV
2452 F16
Figure 16. LTC2452 Input Drive Equivalent Circuit
2) The bandwidth from VSIG is reduced at the input pins
(IN+, IN–). This bandwidth reduction isolates the ADC
from high frequency signals, and as such provides
simple antialiasing and input noise reduction.
3) Switching transients generated by the ADC are attenuated before they go back to the signal source.
4) A large CIN gives a better AC ground at the input pins,
helping reduce reflections back to the signal source.
5) Increasing RS protects the ADC by limiting the current
during an outside-the-rails fault condition.
There is a limit to how large RS • CIN should be for a given
application. Increasing RS beyond a given point increases
the voltage drop across RS due to the input current,
to the point that significant measurement errors exist.
Additionally, for some applications, increasing the RS • CIN
product too much may unacceptably attenuate the signal
at frequencies of interest.
For most applications, it is desirable to implement CIN as
a high-quality 0.1µF ceramic capacitor and RS ≤ 1k. This
capacitor should be located as close as possible to the
actual VIN package pin. Furthermore, the area encompassed
by this circuit path, as well as the path length, should be
minimized.
In the case of a 2-wire sensor that is not remotely
grounded, it is desirable to split RS and place series
resistors in the ADC input line as well as in the sensor
ground return line, which should be tied to the ADC GND
pin using a star connection topology.
2452fc
15
LTC2452
APPLICATIONS INFORMATION
Figure 17 shows the measured LTC2452 INL vs Input
Voltage as a function of RS value with an input capacitor
CIN = 0.1µF.
In some cases, RS can be increased above these guidelines.
The input current is zero when the ADC is either in sleep
or I/O modes. Thus, if the time constant of the input RC
circuit t = RS • CIN, is of the same order of magnitude or
longer than the time periods between actual conversions,
then one can consider the input current to be reduced
correspondingly.
These considerations need to be balanced out by the input
signal bandwidth. The 3dB bandwidth ≈ 1/(2pRSCIN).
8
6
10
CIN = 0.1µF
VCC = 5V
TA = 25°C
CIN = 0
8 V = 5V
CC
6 TA = 25°C
RS = 10k
INL (LSB)
4
2
0
–2
4
RS = 2k
RS = 1k
INL (LSB)
10
Finally, if the recommended choice for CIN is unacceptable
for the user’s specific application, an alternate strategy is to
eliminate CIN and minimize CPAR and RS. In practical terms,
this configuration corresponds to a low impedance sensor
directly connected to the ADC through minimum length
traces. Actual applications include current measurements
through low value sense resistors, temperature measurements, low impedance voltage source monitoring, and so
on. The resultant INL vs VIN is shown in Figure 18. The
measurements of Figure 18 include a capacitor CPAR corresponding to a minimum sized layout pad and a minimum
width input trace of about 1 inch length.
RS = 0
2
0
–2
–4
–4
–6
–6
–8
–8
–10
–10
–5 –4 –3 –2 –1 0 1 2 3 4
DIFFERENTIAL INPUT VOLTAGE (V)
5
2452 F17
Figure 17. Measured INL vs Input Voltage,
CIN = 0.1µF, VCC = 5V, TA = 25°C
RS = 10k
RS = 0
RS = 1k, 2k
–5 –4 –3 –2 –1 0 1 2 3 4
DIFFERENTIAL INPUT VOLTAGE (V)
5
2452 F18
Figure 18. Measured INL vs Input Voltage,
CIN = 0, VCC = 5V, TA = 25°C
2452fc
16
LTC2452
APPLICATIONS INFORMATION
Signal Bandwidth, Transition Noise and Noise
Equivalent Input Bandwidth
The LTC2452 includes a sinc1 type digital filter with the first
notch located at f0 = 60Hz. As such, the 3dB input signal
bandwidth is 26.54Hz. The calculated LTC2452 input signal
attenuation vs frequency over a wide frequency range is
shown in Figure 19. The calculated LTC2452 input signal
attenuation vs frequency at low frequencies is shown in
Figure 20. The converter noise level is about 2.2µVRMS
and can be modeled by a white noise source connected
at the input of a noise-free converter.
On a related note, the LTC2452 uses two separate A/D
converters to digitize the positive and negative inputs.
Each of these A/D converters has 2.2µVRMS transition
noise. If one of the input voltages is within this small
transition noise band, then the output will fluctuate one
bit, regardless of the value of the other input voltage. If
both of the input voltages are within their transition noise
bands, the output can fluctuate 2 bits.
For a simple system noise analysis, the VIN drive circuit can
be modeled as a single-pole equivalent circuit characterized by a pole location fi and a noise spectral density ni.
If the converter has an unlimited bandwidth, or at least a
bandwidth substantially larger than fi, then the total noise
contribution of the external drive circuit would be:
Vn = ni p / 2 • fi
Then, the total system noise level can be estimated as
the square root of the sum of (Vn2) and the square of the
LTC2452 noise floor (~2.2µV2).
0
INPUT SIGNAL ATTENUATIOIN (dB)
INPUT SIGNAL ATTENUATION (dB)
0
–20
–40
–60
–80
–100
0
2.5
5.0
7.5
1.00
1.25
1.50
INPUT SIGNAL FREQUENCY (MHz)
2452 F19
Figure 19. LTC2452 Input Signal Attentuation vs Frequency
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
0
60 120 180 240 300 360 420 480 540 600
INPUT SIGNAL FREQUENCY (Hz)
2452 F20
Figure 20. LTC2452 Input Signal Attenuation
vs Frequency (Low Frequencies)
2452fc
17
LTC2452
TYPICAL APPLICATION
JP1
VCC
VCC
U2
3 LT6660HCDC-5 1
IN
OUT
V+
1µF
GND
GND
2
+5V
EXT
1 2 3
1µF
GND
4
1k
REF+
VCC 0.1µF
0.1µF
3
IN+
IN–
1k
1k
0.1µF
0.1µF
6
IN+
5
IN–
0.1µF
CS SCK SDO
4
REF+ VCC
LTC2452
REF– GND
2
1µF
9
CS
SCK
SDO
7
1
8
U1*
VCC V+
1 10V
2
5V
TO
CONTROLLER
6
CS
4
SCK/SCL
7
MOSI/SDA
5
MISO/SDO
GND GND GND
3
8
13
2452 TA02
2452fc
18
LTC2452
PACKAGE DESCRIPTION
DDB Package
8-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1702 Rev B)
0.61 ±0.05
(2 SIDES)
0.70 ±0.05
2.55 ±0.05
1.15 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
2.20 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ±0.10
(2 SIDES)
R = 0.115
TYP
5
R = 0.05
TYP
0.40 ± 0.10
8
2.00 ±0.10
(2 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.56 ± 0.05
(2 SIDES)
0.200 REF
0.75 ±0.05
0 – 0.05
4
0.25 ± 0.05
1
PIN 1
R = 0.20 OR
0.25 × 45°
CHAMFER
(DDB8) DFN 0905 REV B
0.50 BSC
2.15 ±0.05
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
2452fc
19
LTC2452
PACKAGE DESCRIPTION
TS8 Package
8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637 Rev A)
0.40
MAX
2.90 BSC
(NOTE 4)
0.65
REF
1.22 REF
1.4 MIN
3.85 MAX 2.62 REF
2.80 BSC
1.50 – 1.75
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.22 – 0.36
8 PLCS (NOTE 3)
0.65 BSC
0.80 – 0.90
0.20 BSC
0.01 – 0.10
1.00 MAX
DATUM ‘A’
0.30 – 0.50 REF
0.09 – 0.20
(NOTE 3)
1.95 BSC
TS8 TSOT-23 0710 REV A
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
2452fc
20
LTC2452
REVISION HISTORY
(Revision history begins at Rev C)
REV
DATE
DESCRIPTION
PAGE NUMBER
C
03/10
Updated Analog Inputs and References section
3
Added text to Input Voltage Range section
8
2452fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
21
LTC2452
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max, 5ppm/°C Drift
LT1461
Micropower Series Reference, 2.5V
0.04% Max, 3ppm/°C Drift
LT1790
Micropower Precision Reference in TSOT-23-6 Package
60µA Max Supply Current, 10ppm/°C Max Drift, 1.25V, 2.048V,
2.5V, 3V, 3.3V, 4.096V and 5V Options
LTC1860/LTC1861
12-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP
850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages
LTC1860L/LTC1861L
12-Bit, 3V, 1-/2-Channel 150ksps SAR ADC
450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages
LTC1864/LTC1865
16-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP
850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages
LTC1864L/LTC1865L
16-bit, 3V, 1-/2-Channel 150ksps SAR ADC
450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages
LTC2440
24-Bit No Latency DS™ ADC
200nVRMS Noise, 4kHz Output Rate, 15ppm INL
LTC2480
16-Bit, Differential Input, No Latency DS ADC, with PGA,
Temp. Sensor, SPI
Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
LTC2481
16-Bit, Differential Input, No Latency DS ADC, with PGA,
Temp. Sensor, I2C
Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
LTC2482
16-Bit, Differential Input, No Latency DS ADC, SPI
Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
LTC2483
16-Bit, Differential Input, No Latency DS ADC, I2C
Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
LTC2484
24-Bit, Differential Input, No Latency DS ADC, SPI with
Temp. Sensor
Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
LTC2485
24-Bit, Differential Input, No Latency DS ADC, I2C with
Temp. Sensor
Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
LTC6241
Dual, 18MHz, Low Noise, Rail-to-Rail Op Amp
550nVP-P Noise, 125µV Offset Max
LT6660
Micropower References in 2mm × 2mm DFN Package,
2.5V, 3V, 3.3V, 5V
20ppm/°C max drift, 0.2% Max
LTC2450
Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI
2 LSB INL, 50nA Sleep current, Tiny 2mm × 2mm DFN-6 Package,
30Hz Output Rate
LTC2450-1
Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI
2 LSB INL, 50nA Sleep Current, Tiny 2mm × 2mm DFN-6 Package,
60Hz Output Rate
LTC2451
Easy-to-Use, Ultra-Tiny 16-Bit ADC, I2C
2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT
Package, Programmable 30Hz/60Hz Output Rates
LTC2453
Easy-to-Use, Ultra-Tiny 16-Bit Differential ADC, I2C
2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT
Package
2452fc
22 Linear Technology Corporation
LT 0311 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 l FAX: (408) 434-0507
l
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2008