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DLP2010NIR
DLPS059A – MARCH 2015 – REVISED OCTOBER 2015
DLP2010NIR (0.2 WVGA Near-Infrared DMD)
1 Features
2 Applications
•
•
1
•
•
•
•
0.2-Inch (5.29-mm) Diagonal Micromirror Array
– 854 × 480 Array of Aluminum MicrometerSized Mirrors, in an Orthogonal Layout
– 5.4-µm Micromirror Pitch
– ±17° Micromirror Tilt (Relative to Flat Surface)
– Side Illumination for Optimal Efficiency and
Optical Engine Size
Highly Efficient Steering of NIR light
– Window Transmission Efficiency 96% Nominal
(700 to 2000 nm, Single Pass Through Two
Window Surfaces)
– Window Transmission Efficiency 90% Nominal
(2000 to 2500 nm, Single Pass Through Two
Window Surfaces)
– Polarization Independent Aluminum
Micromirrors
Dedicated DLPC150 Controller for Reliable
Operation
– Binary Pattern Rates up to 2880 Hz
– Pattern Sequence Mode for Control over Each
Micromirror in Array
Dedicated Power Management Integrated Circuit
(PMIC) DLPA2000 or DLPA2005 for Reliable
Operation
15.9-mm × 5.3-mm × 4-mm Body Size for
Portable Instruments
•
•
•
•
•
•
•
•
Spectrometers (Chemical Analysis):
– Portable Process Analyzers
– Portable Equipment
Compressive Sensing (Single Pixel NIR Cameras)
3D Biometrics
Machine Vision
Infrared Scene Projection
Microscopes
Laser Marking
Optical Choppers
Optical Networking
3 Description
The DLP2010NIR digital micromirror device (DMD)
acts as a spatial light modulator (SLM) to steer nearinfrared (NIR) light and create patterns with speed,
precision, and efficiency. Featuring high resolution in
a compact form factor, the DLP2010NIR DMD is
often combined with a grating single element detector
to replace expensive InGaAs linear array-based
detector designs, leading to high performance, costeffective portable NIR Spectroscopy solutions. The
DLP2010NIR DMD enables wavelength control and
programmable spectrum and is well suited for low
power mobile applications such as skin analysis,
material identification and chemical sensing.
Device Information(1)
PART NUMBER
DLP2010NIR
PACKAGE
CLGA (40)
BODY SIZE (NOM)
15.90 × 5.30 × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
DLP® 0.2" WVGA Chipset
DLPC150
Display Controller
600-MHz
SubLVDS
DDR
Interface
D_P(0)
D_N(0)
DLP2010 DMD
or
DLP2010NIR DMD
VOFFSET
D_P(1)
D_N(1)
VBIAS
D_P(2)
D_N(2)
VRESET
DLPA2000
or
DLPA2005
(PMIC and LED
Driver)
D_P(3)
D_N(3)
VDDI
DCLK_P
DCLK_N
VDD
120-MHz
SDR
Interface
LS_WDATA
LS_CLK
LS_RDATA
VSS
DMD_DEN_ARSTZ
System Signal Routing Omitted For Clarity
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLP2010NIR
DLPS059A – MARCH 2015 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
7
1
1
1
2
3
6
Absolute Maximum Ratings ..................................... 6
Storage Conditions.................................................... 6
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 9
Electrical Characteristics........................................... 9
Timing Requirements .............................................. 10
Switching Characteristics ....................................... 15
System Mounting Interface Loads .......................... 15
Physical Characteristics of the Micromirror Array. 16
Micromirror Array Optical Characteristics ............. 17
Window Characteristics......................................... 18
Chipset Component Usage Specification ............. 18
Typical Characteristics .......................................... 18
Detailed Description ............................................ 19
7.1 Overview ................................................................. 19
7.2 Functional Block Diagram ....................................... 19
7.3
7.4
7.5
7.6
7.7
8
Feature Description.................................................
Device Functional Modes........................................
Window Characteristics and Optics ........................
Micromirror Array Temperature Calculation............
Micromirror Landed-On/Landed-Off Duty Cycle ....
20
20
20
21
22
Application and Implementation ........................ 24
8.1 Application Information............................................ 24
8.2 Typical Application .................................................. 24
9
Power Supply Recommendations...................... 27
9.1 Power Supply Power-Up Procedure ...................... 27
9.2 Power Supply Power-Down Procedure .................. 27
9.3 Power Supply Sequencing Requirements .............. 28
10 Layout................................................................... 30
10.1 Layout Guidelines ................................................. 30
10.2 Layout Example .................................................... 30
11 Device and Documentation Support ................. 32
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
33
33
33
33
12 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2015) to Revision A
Page
•
Lowered minimum delay time .............................................................................................................................................. 29
•
Added Community Resources ............................................................................................................................................. 33
2
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DLPS059A – MARCH 2015 – REVISED OCTOBER 2015
5 Pin Configuration and Functions
FQJ Package
40-Pin CLGA
Bottom View
Pin Functions – Connector Pins (1)
PIN
NAME
NO.
TYPE
SIGNAL
DATA RATE
DESCRIPTION
PACKAGE NET TRACE
LENGTH (2) (mm)
DATA INPUTS, SUBLVDS INTERFACE
D_N(0)
G4
I
SubLVDS
Double
Input Data Pair 0, Negative
7.03
D_P(0)
G3
I
SubLVDS
Double
Input Data Pair 0, Positive
7.03
D_N(1)
G8
I
SubLVDS
Double
Input Data Pair 1, Negative
7.03
D_P(1)
G7
I
SubLVDS
Double
Input Data Pair 1, Positive
7.03
D_N(2)
H5
I
SubLVDS
Double
Input Data Pair 2, Negative
7.02
D_P(2)
H6
I
SubLVDS
Double
Input Data Pair 2, Positive
7.02
(1)
(2)
Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard
No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.
Net trace lengths inside the package:
Relative dielectric constant for the FQJ ceramic package is 9.8.
Propagation speed = 11.8 / sqrt(9.8) = 3.769 inches/ns.
Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm.
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Pin Functions – Connector Pins(1) (continued)
PIN
NAME
NO.
TYPE
SIGNAL
DATA RATE
DESCRIPTION
PACKAGE NET TRACE
LENGTH (2) (mm)
D_N(3)
H1
I
SubLVDS
Double
Input Data Pair 3, Negative
7.00
D_P(3)
H2
I
SubLVDS
Double
Input Data Pair 3, Positive
7.00
DCLK_N
H9
I
SubLVDS
Double
Clock, Negative
7.03
DCLK_P
H10
I
SubLVDS
Double
Clock, Positive
7.03
Active low asynchronous DMD reset
signal. A low signal places the DMD in
reset. A high signal releases the DMD
from reset and places it in active mode.
5.72
CONTROL INPUTS, LPSDR INTERFACE
(1)
DMD_DEN_ARSTZ
G12
I
LPSDR
LS_CLK
G19
I
LPSDR
Single
Clock for low-speed interface
3.54
LS_WDATA
G18
I
LPSDR
Single
Write data for low-speed interface
3.54
LS_RDATA
G11
O
LPSDR
Single
Read data for low-speed interface
8.11
H17
Power
Supply voltage for Micromirror positive
bias level
POWER
VBIAS (3)
VOFFSET (3)
H13
Power
Supply voltage for High Voltage CMOS
(HVCMOS) core logic.
Includes: supply voltage for stepped high
level at micromirror address electrodes
and supply voltage for offset level at
micromirrors.
VRESET (3)
H18
Power
Supply voltage for Micromirror negative
reset level
VDD (3)
G20
Power
VDD
H14
Power
VDD
H15
Power
VDD
H16
Power
VDD
H19
Power
VDD
H20
Power
VDDI (3)
G1
Power
VDDI
G2
Power
VDDI
G5
Power
VDDI
G6
Power
VSS (3)
G9
Power
VSS
G10
Power
VSS
G13
Power
VSS
G14
Power
VSS
G15
Power
VSS
G16
Power
VSS
G17
Power
VSS
H3
Power
VSS
H4
Power
VSS
H7
Power
VSS
H8
Power
VSS
H11
Power
VSS
H12
Power
(3)
4
Supply voltage for low voltage CMOS
(LVCMOS) core logic. Includes supply
voltage for LPSDR inputs and supply
voltage for normal high level at micromirror
address electrodes.
Supply voltage for SubLVDS receivers
Ground. Common return for all power.
The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.
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Pin Functions – Connector Pins(1) (continued)
PIN
NAME
NO.
TYPE
SIGNAL
DATA RATE
PACKAGE NET TRACE
LENGTH (2) (mm)
DESCRIPTION
RESERVED
No Connect
A2,
A3,
A4,
A5,
A6
A7,
A8,
A9,
A10,
A11,
A12,
A13,
A14,
A15,
A16,
A17,
A18,
A19
Reserved pins. For proper device
operation, leave these pins unconnected.
No Connect
B2,
B3,
B17,
B18
Reserved pins. For proper device
operation, leave these pins unconnected.
No Connect
C2,
C3,
C17,
C18
Reserved pins. For proper device
operation, leave these pins unconnected.
No Connect
D2,
D3,
D17,
D18
Reserved pins. For proper device
operation, leave these pins unconnected.
No Connect
E2,
E3,
E17,
E18
Reserved pins. For proper device
operation, leave these pins unconnected.
No Connect
F1,
F2,
F3,
F4,
F5,
F6,
F7,
F8,
F9,
F10,
F11,
F12,
F13,
F14,
F15,
F16,
F17,
F18,
F19
Resereved pins. For proper device
operation, leave these pins unconnected.
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6 Specifications
6.1 Absolute Maximum Ratings
(see
(1)
)
Supply voltage for LVCMOS core logic and LPSDR
low speed interface (2)
VDD
Environmental
(2)
(3)
(4)
(5)
(6)
(7)
(8)
2.3
V
–0.5
2.3
V
VOFFSET
–0.5
10.6
V
Supply voltage for micromirror electrode bias
circuits (2)
–0.5
19
V
Supply voltage for micromirror electrode reset
circuits (2)
–15
0.3
V
| VDDI–VDD |
Supply voltage delta (absolute value)
(4)
0.3
V
| VBIAS–VOFFSET |
Supply voltage delta (absolute value) (5)
11
V
(6)
34
V
–0.5
VDD + 0.5
V
–0.5
VDDI + 0.5
V
Supply voltage delta (absolute value)
Input voltage for other
inputs LPSDR (2)
Input voltage for other
inputs SubLVDS (2) (7)
(7)
| VID |
SubLVDS input differential voltage (absolute value)
810
mV
IID
SubLVDS input differential current
8.1
mA
ƒclock
Clock frequency for low speed interface LS_CLK
130
MHz
ƒclock
Clock frequency for high speed interface DCLK
620
MHz
TARRAY and TWINDOW
TDP
(1)
–0.5
Supply voltage for HVCMOS and micromirror
electrode (2) (3)
| VBIAS–VRESET |
Clock
frequency
UNIT
Supply voltage for SubLVDS receivers
VRESET
Input pins
MAX
VDDI
Supply voltage VBIAS
Input voltage
(2)
MIN
Temperature – operational (8)
–10
90
°C
Temperature – non-operational (8)
–40
90
°C
81
°C
Dew Point (operating and non-operating)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure above or below Recommended Operating Conditions for extended periods may affect device reliability.
All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:
VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET.
VOFFSET supply transients must fall within specified voltages.
Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.
Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current
draw.
Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.
This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential
inputs must not exceed the specified limit or damage may result to the internal termination resistors.
The highest temperature of the active array (as calculated by the Micromirror Array Temperature Calculation), or of any point along the
Window Edge as defined in Figure 19. The locations of thermal test points TP2 and TP3 in Figure 19 are intended to measure the
highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature,
that test point should be used.
6.2 Storage Conditions
applicable before the DMD is installed in the final product.
Tstg
TDP
(1)
(2)
6
DMD storage temperature
Storage Dew Point - long-term
Storage Dew Point - short-term
(1)
MIN
MAX
–40
85
24
(2)
UNIT
°C
28
Long-term is defined as the usable life of the device.
Dew points beyond the specified long-term dew point are for short-term conditions only, where Short-term is defined as less than 60
cumulative days over the usable life of the device (operating, non-operating, or storage).
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6.3 ESD Ratings
V(ESD)
(1)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
NOM
MAX
UNIT
SUPPLY VOLTAGE RANGE (3)
VDD
Supply voltage for LVCMOS core logic
Supply voltage for LPSDR low-speed interface
1.65
1.8
1.95
V
VDDI
Supply voltage for SubLVDS receivers
1.65
1.8
1.95
V
VOFFSET
Supply voltage for HVCMOS and micromirror
electrode (4)
9.5
10
10.5
V
VBIAS
Supply voltage for mirror electrode
VRESET
Supply voltage for micromirror electrode
17.5
18
18.5
V
–14.5
–14
–13.5
V
|VDDI–VDD|
Supply voltage delta (absolute value)
(5)
0.3
V
|VBIAS–VOFFSET|
Supply voltage delta (absolute value) (6)
10.5
V
|VBIAS–VRESET|
Supply voltage delta (absolute value) (7)
33
V
OUTPUT TERMINALS
IOH
High-level output current at Voh = 0.8 × VDD
–30
mA
IOL
Low-level output current at Vol = 0.2 × VDD
30
mA
CLOCK FREQUENCY
ƒclock
Clock frequency for low speed interface LS_CLK (8)
108
120
MHz
ƒclock
Clock frequency for high speed interface DCLK (9)
300
600
MHz
44%
56%
Duty cycle distortion DCLK
SUBLVDS INTERFACE (9)
| VID |
SubLVDS input differential voltage (absolute value)
Figure 8, Figure 9
150
250
350
mV
VCM
Common mode voltage Figure 8, Figure 9
700
900
1100
mV
VSUBLVDS
SubLVDS voltage Figure 8, Figure 9
575
1225
mV
ZLINE
Line differential impedance (PWB/trace)
90
100
110
Ω
ZIN
Internal differential termination resistance Figure 10
80
100
120
Ω
100-Ω differential PCB trace
6.35
Line differential impedance (PWB/trace)
61.2
152.4
mm
74.8
Ω
LPSDR INTERFACE (10)
ZLINE
68
(1)
(2)
Recommended Operating Conditions are applicable after the DMD is installed in the final product.
The functional performance of the device specified in this datasheet is achieved when operating the device within the limits defined by
the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the
Recommended Operating Conditions limits.
(3) All voltage values are with respect to the ground pins (VSS).
(4) VOFFSET supply transients must fall within specified max voltages.
(5) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.
(6) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.
(7) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit.
(8) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.
(9) Refer to the SubLVDS timing requirements in Timing Requirements.
(10) Refer to the LPSDR timing requirements in Timing Requirements.
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Recommended Operating Conditions (continued)
Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
NOM
MAX
UNIT
ENVIRONMENTAL
TARRAY
Array temperature – operational, long-term
Array temperature – operational, short-term
(11) (12) (13)
0
40 to 70 (11)
–10
75
(14) (12)
(13)
°C
TWINDOW
Window temperature – operational (15)
90
°C
|TDELTA |
Absolute Temperature difference between any point
on the window edge and the ceramic test point TP1 (16)
30
°C
ILLUV&VIS
Illumination, wavelength < 700 nm
0.68
mW/cm2
ILLNIR
Illumination, wavelength 700 - 2500 nm
2000
mW/cm2
ILLIR
Illumination, wavelength > 2500 nm
10
mW/cm2
(11) Per Figure 1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD
experiences in the end application. Refer to Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty
cycle.
(12) Long-term is defined as the usable life of the device.
(13) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1
(TP1) shown in Figure 19 and the package thermal resistance using Micromirror Array Temperature Calculation.
(14) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is
defined as cumulative time over the usable life of the device and is less than 500 hours for temperatures between long-term maximum
and 75°C, less than 500 hours for temperatures between 0°C and -10°C.
(15) Window temperature is the highest temperature on the window edge shown in Figure 19. The locations of thermal test points TP2 and
TP3 in Figure 19 are intended to measure the highest window edge temperature. If a particular application causes another point on the
window edge to be at a higher temperature, a test point should be added to that location.
(16) Temperature delta is the highest difference from the ceramic test point 1 (TP1) and anywhere on the window edge shown in Figure 19.
The window test points TP2 and TP3 shown in Figure 19 are intended to result in the worst case delta temperature. If a particular
application causes another point on the window edge to result in a larger delta temperature, that point should be used.
Max Recommended Array Temperature –
Operational (°C)
SPACE
80
70
60
50
40
30
0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50
100/0
95/5
90/10
85/15
80/20
75/25
70/30
65/35
60/40
Micromirror Landed Duty Cycle
55/45
D001
Figure 1. Max Recommended Array Temperature – Derating Curve
8
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6.5 Thermal Information
DLP2010NIR
FQJ (CLGA)
THERMAL METRIC (1)
MIN
Thermal resistance Active area to test point TP1
(1)
UNIT
40 PINS
TYP
MAX
(1)
7.9
°C/W
The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the package within the temperature range specified in the Recommended Operating Conditions . The total heat load on the
DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the
window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling
outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.
6.6 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted) (1)
TEST CONDITIONS (2)
PARAMETER
MIN
TYP
MAX
UNIT
CURRENT
IDD
Supply current: VDD (3)
IDDI
Supply current: VDDI (3)
IOFFSET
Supply current: VOFFSET (5)
IBIAS
Supply current: VBIAS (5)
IRESET
Supply current: VRESET (6)
VDD = 1.95 V
(4)
34.7
VDD = 1.8 V
27.5
VDDI = 1.95 V
(4)
9.4
VDD = 1.8 V
6.6
VOFFSET = 10.5 V
(6)
1.7
VOFFSET = 10 V
0.9
VBIAS = 18.5 V
(6)
0.4
VBIAS = 18 V
0.2
VRESET = –14.5 V
2
VRESET = –14 V
1.2
mA
mA
mA
mA
mA
POWER (7)
PDD
Supply power dissipation: VDD (3)
PDDI
Supply power dissipation: VDDI (3)
POFFSET
Supply power dissipation:
VOFFSET (5) (6)
PBIAS
Supply power dissipation: VBIAS (5)
PRESET
Supply power dissipation: VRESET (6)
PTOTAL
Supply power dissipation: Total
LPSDR INPUT
VDD = 1.95 V
67.7
VDD = 1.8 V
(4)
49.5
VDDI = 1.95 V
18.3
VDD = 1.8 V
11.9
VOFFSET = 10.5 V
17.9
VOFFSET = 10 V
(6)
9
VBIAS = 18.5 V
7.4
VBIAS = 18 V
3.6
VRESET = –14.5 V
29
VRESET = –14 V
16.8
90.8
140.3
mW
mW
mW
mW
mW
mW
(8)
VIH(DC)
DC input high voltage (9)
VIL(DC)
DC input low voltage (9)
(9)
VIH(AC)
AC input high voltage
VIL(AC)
AC input low voltage (9)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(4)
0.7 × VDD
VDD + 0.3
V
–0.3
0.3 × VDD
V
0.8 × VDD
VDD + 0.3
V
–0.3
0.2 × VDD
V
Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
All voltage values are with respect to the ground pins (VSS).
To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.
Supply power dissipation based on non–compressed commands and data.
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.
Supply power dissipation based on 3 global resets in 200 µs.
The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.
LPSDR specifications are for pins LS_CLK and LS_WDATA.
Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard
No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)(1)
TEST CONDITIONS (2)
PARAMETER
∆VT
Hysteresis ( VT+ – VT– )
Figure 10
IIL
Low–level input current
VDD = 1.95 V; VI = 0 V
IIH
High–level input current
VDD = 1.95 V; VI = 1.95 V
LPSDR OUTPUT
MIN
TYP
MAX
0.1 × VDD
0.4 × VDD
–100
UNIT
V
nA
100
nA
(10)
VOH
DC output high voltage
IOH = –2 mA
VOL
DC output low voltage
IOL = 2 mA
0.8 × VDD
0.2 × VDD
V
V
Input capacitance LPSDR
ƒ = 1 MHz
10
pF
Input capacitance SubLVDS
ƒ = 1 MHz
20
pF
COUT
Output capacitance
ƒ = 1 MHz
10
pF
CRESET
Reset group capacitance
ƒ = 1 MHz; (480 × 108) micromirrors
113
pF
MAX
UNIT
CAPACITANCE
CIN
95
(10) LPSDR specification is for pin LS_RDATA.
6.7 Timing Requirements
Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
MIN
NOM
LPSDR
tR
Rise slew rate (1)
(30% to 80%) × VDD, Figure 3
1
3
V/ns
tV
Fall slew rate (1)
(70% to 20%) × VDD, Figure 3
1
3
V/ns
(2)
tR
Rise slew rate
(20% to 80%) × VDD, Figure 3
0.25
tF
Fall slew rate (2)
(80% to 20%) × VDD, Figure 3
0.25
tC
Cycle time LS_CLK,
Figure 2
tW(H)
Pulse duration LS_CLK
high
50% to 50% reference points,Figure 2
tW(L)
Pulse duration LS_CLK
low
50% to 50% reference points, Figure 2
tSU
Setup time
tH
Hold time
tWINDOW
Window time (1)
tDERATING
(3)
Window time derating
V/ns
8.3
ns
3.1
ns
3.1
ns
LS_WDATA valid before LS_CLK ↑, Figure 2
1.5
ns
LS_WDATA valid after LS_CLK ↑, Figure 2
1.5
ns
3
ns
Setup time + Hold time, Figure 2
(1)
7.7
V/ns
(3)
For each 0.25 V/ns reduction in slew rate below
1 V/ns, Figure 5
0.35
ns
tR
Rise slew rate
20% to 80% reference points, Figure 4
tF
Fall slew rate
80% to 20% reference points, Figure 4
tC
Cycle time LS_CLK,
Figure 6
tW(H)
Pulse duration DCLK high
50% to 50% reference points, Figure 6
0.71
ns
tW(L)
Pulse duration DCLK low
50% to 50% reference points, Figure 6
0.71
ns
tSU
Setup time
D(0:3) valid before
DCLK ↑ or DCLK ↓, Figure 6
tH
Hold time
D(0:3) valid after
DCLK ↑ or DCLK ↓, Figure 6
tWINDOW
Window time
Setup time + Hold time, Figure 6,Figure 7
tLVDS-
Power-up receiver (4)
SubLVDS
0.7
1
V/ns
0.7
1
V/ns
1.61
1.67
ns
0.3
ns
2000
ns
ENABLE+REFGEN
(1)
(2)
(3)
(4)
10
Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 3.
Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 3.
Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.
Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.
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tc
tw(H)
LS_CLK
50%
tw(L)
50%
50%
th
tsu
LS_ WDATA
50%
50%
twindow
Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in
JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.
Figure 2. LPSDR Switching Parameters
LS_CLK, LS_WDATA
DMD_DEN_ARSTZ
1.0 * VDD
1.0 * VDD
0.8 * VDD
0.7 * VDD
VIH(AC)
VIH(DC)
0.3 * VDD
0.2 * VDD
VIL(DC)
VIL(AC)
0.8 * VDD
0.2 * VDD
0.0 * VDD
0.0 * VDD
tr
tf
tr
tf
Figure 3. LPSDR Input Rise and Fall Slew Rate
VDCLK_P , VDCLK_N
VD_P(0:3) , VD_N(0:3)
1.0 * VID
0.8 * VID
VCM
0.2 * VID
0.0 * VID
tr
tf
Figure 4. SubLVDS Input Rise and Fall Slew Rate
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VIH MIN
LS_CLK Midpoint
VIL MAX
tSU
tH
VIH MIN
LS_WDATA Midpoint
VIL MAX
tWINDOW
VIH MIN
Midpoint
LS_CLK
VIL MAX
tDERATING
tSU
tH
VIH MIN
Midpoint
LS_WDATA
VIL MAX
tWINDOW
Figure 5. Window Time Derating Concept
tc
tw(L)
DCLK _ P
DCLK _ N
50%
tw(H)
50%
50%
th
tsu
D_P (0:3)
D_N(0:3)
50%
50%
twindow
Figure 6. SubLVDS Switching Parameters
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High Speed Training Scan Window
tc
DCLK _ P
DCLK _ N
¼ tc
¼ tc
D_P (0:3)
D_N(0:3)
Note: Refer to High-Speed Interface for details.
Figure 7. High-Speed Training Scan Window
(VIP + V IN) / 2
DCLK _P , D_P(0:3)
SubLVDS
Receiver
VID
DCLK _N , D_N(0:3)
VIP
VCM
VIN
Figure 8. SubLVDS Voltage Parameters
1.225V
V SubLVDS max = V CM max + | 1/2 * V ID max |
VCM
VID
VSubLVDS min = VCM min – | 1/2 * VID max |
0.575V
Figure 9. SubLVDS Waveform Parameters
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DCLK _P , D_P(0:3)
ESD
Internal
Termination
SubLVDS
Receiver
DCLK _N , D_N(0:3)
ESD
Figure 10. SubLVDS Equivalent Input Circuit
Not to Scale
VIH
VT+
Δ VT
VT-
VIL
LS_CLK
LS_WDATA
Figure 11. LPSDR Input Hysteresis
LS_CLK
LS_WDATA
Stop Start
tPD
LS_RDATA
Acknowledge
Figure 12. LPSDR Read Out
Data Sheet Timing Reference Point
Device Pin
Output Under Test
Tester Channel
CL
See Timing for more information.
Figure 13. Test Load Circuit for Output Propagation Measurement
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6.8 Switching Characteristics (1)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Output propagation, Clock to Q, rising
edge of LS_CLK input to LS_RDATA
output. Figure 12
tPD
MAX
UNIT
CL = 5 pF
11.1
ns
CL = 10 pF
11.3
ns
CL = 85 pF
15
Slew rate, LS_RDATA
TYP
0.5
Output duty cycle distortion, LS_RDATA
(1)
MIN
ns
V/ns
40%
60%
Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
6.9 System Mounting Interface Loads
PARAMETER
MIN
NOM
MAX
UNIT
Maximum system mounting interface load to be applied to the:
•
Connector area (see Figure 14)
•
DMD mounting area uniformly distributed over 4 areas (see Figure 14)
45
N
100
N
µuZ[
(3 places)
µuZ[
(1 place)
DMD Mounting Area
(4 o}}]µuZ[vZ[
Connector Area
Figure 14. System Interface Loads
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6.10 Physical Characteristics of the Micromirror Array
ε
(1)
VALUE
UNIT
Number of active columns
See Figure 15
854
micromirrors
Number of active rows
See Figure 15
480
micromirrors
Micromirror (pixel) pitch
See Figure 16
5.4
µm
Micromirror active array width
Micromirror pitch × number of active columns; see
Figure 15
4.6116
mm
Micromirror active array height
Micromirror pitch × number of active rows; see Figure 15
2.592
mm
Micromirror active border
Pond of micromirror (POM) (1)
20
micromirrors/side
The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.
Not To Scale
Width
Mirror
Mirror
Mirror
Mirror
479
478
477
476
Height
Illumination
DMD Active Mirror Array
854 Mirrors * 480 Mirrors
3
2
1
0
Mirror
Mirror
Mirror
Mirror
Mirror
Mirror
Mirror
Mirror
850
851
852
853
0
1
2
3
Mirror
Mirror
Mirror
Mirror
Figure 15. Micromirror Array Physical Characteristics
ε
ε
ε
ε
Figure 16. Mirror (Pixel) Pitch
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6.11 Micromirror Array Optical Characteristics
PARAMETER
TEST CONDITIONS
MIN
DMD landed state (1)
Micromirror tilt angle
Micromirror tilt angle tolerance (1)
(5)
(6)
(7)
(8)
UNIT
°
(2) (3) (4)
–1
1
Landed ON state
180
Landed OFF state
270
Micromirror crossover time
Typical Performance
1.5
Micromirror switching time
Typical Performance
Number of out-of-specification
micromirrors (8)
Adjacent micromirrors
Micromirror tilt direction (6)
MAX
17
(5)
(1)
(2)
(3)
(4)
NOM
(7)
°
4
6
0
Non-adjacent micromirrors
°
10
μs
micromirrors
Measured relative to the plane formed by the overall micromirror array.
Additional variation exists between the micromirror array and the package datums.
Represents the landed tilt angle variation relative to the nominal landed tilt angle.
Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in
colorimetry variations, system efficiency variations or system contrast variations.
When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of
the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON State
direction. A binary value of 0 results in a micromirror landing in the OFF State direction.
Micromirror tilt direction is measured as in a typical polar coordinate system: measuring counter-clockwise from a 0° reference which is
aligned with the +X Cartesian axis.
An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states within the
specified Micromirror Switching Time.
(0,479)
(853,479)
Incident
Illumination
Light Path
Tilted Axis of
Pixel Rotation
On-State
Landed Edge
Off-State
Landed Edge
(853,0)
(0,0)
Off-State
Light Path
Figure 17. Landed Pixel Orientation and Tilt
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6.12 Window Characteristics
PARAMETER (1)
MIN
NOM
Window material designation
Window refractive index
Window aperture
at wavelength 546.1 nm
UNIT
1.5119
(2)
Illumination overfill
MAX
Corning Eagle XG
(3)
See
(2)
See
(3)
Window transmittance, single-pass
through both surfaces and glass
Minimum within the wavelength range
700 to 2000 nm. at 0° angle of
incidence.
92
96
%
Window transmittance, single-pass
through both surfaces and glass
Minimum within the wavelength range
2000 to 2500 nm. at 0° angle of
incidence.
85
90
%
(1)
(2)
(3)
See Window Characteristics and Optics for more information.
See the package mechanical characteristics for details regarding the size and location of the window aperture.
The active area of the DLP2010NIR device is surrounded by an aperture on the inside of the DMD window surface that masks
structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light
illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the
DMD. The illumination optical system should be designed to limit light flux incident outside the active array to less than 10% of the
average flux level in the active area. Depending on the particular system's optical architecture and assembly tolerances, the amount of
overfill light on the outside of the active array may cause system performance degradation.
6.13 Chipset Component Usage Specification
The DLP2010NIR is a component of one or more DLP chipsets. Reliable function and operation of the
DLP2010NIR requires that it be used in conjunction with the other components of the applicable DLP chipset,
including those components that contain or implement TI DMD control technology. TI DMD control technology is
the TI technology and devices for operating or controlling a DLP DMD.
NOTE
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical
system operating conditions exceeding limits described previously.
6.14 Typical Characteristics
100
95
Transmittance (%)
90
85
80
75
70
65
Nominal
Minimum
60
700
900
1100 1300 1500 1700 1900 2100 2300 2500
Wavelength (nm)
D001
Figure 18. DLP2010NIR DMD Window Transmittance
18
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7 Detailed Description
7.1 Overview
The DLP2010NIR is a 0.2 inch diagonal spatial light modulator designed for near-infrared applications. Pixel
array size is 854 columns by 480 rows in a square grid pixel arrangement. The electrical interface is Sub Low
Voltage Differential Signaling (SubLVDS) data.
DLP2010NIR is one device in a chipset, which includes the DLP2010NIR DMD, the DLPC150 controller and the
DLPA200X (DLPA2000 or DLPA2005) PMIC. To ensure reliable operation, the DLP2010NIR DMD must always
be used with a DLPC150 controller and a DLPA200X PMIC.
VSS
VDD
VDDI
VOFFSET
VBIAS
VRESET
D_P(0:3)
D_N(0:3)
DCLK_P
DCLK_N
7.2 Functional Block Diagram
High Speed Interface
Misc
Column Write
Control
Bit Lines
(0,0)
Voltage
Generators
Voltages
SRAM
Word Lines
Row
(479, 853)
Control
Column Read
Control
VSS
VDD
VOFFSET
VBIAS
VRESET
LS_RDATA
LS_WDATA
LS_CLK
DMD_DEN_ARSTZ
Low Speed Interface
Details omitted for clarity.
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7.3 Feature Description
7.3.1 Power Interface
The power management IC, DLPA200X, contains 3 regulated DC supplies for the DMD reset circuitry: VBIAS,
VRESET and VOFFSET, as well as the 2 regulated DC supplies for the DLPC150 controller.
7.3.2 Low-Speed Interface
The Low Speed Interface handles instructions that configure the DMD and control reset operation. LS_CLK is the
low–speed clock, and LS_WDATA is the low speed data input.
7.3.3 High-Speed Interface
The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high speed
DDR transfer and compression techniques to save power and time. The high-speed interface is composed of
differential SubLVDS receivers for inputs, with a dedicated clock.
7.3.4 Timing
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. Figure 13 shows an equivalent test load circuit for the
output under test. Timing reference loads are not intended as a precise representation of any particular system
environment or depiction of the actual load presented by a production test. System designers should use IBIS or
other simulation tools to correlate the timing reference load to a system environment. The load capacitance value
stated is only for characterization and measurement of AC timing signals. This load capacitance value does not
indicate the maximum load the device is capable of driving.
7.4 Device Functional Modes
DMD functional modes are controlled by the DLPC150 controller. See the DLPC150 controller data sheet or
contact a TI applications engineer.
7.5 Window Characteristics and Optics
NOTE
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical
system operating conditions exceeding limits described previously.
7.5.1 Optical Interface and System Image Quality
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections:
7.5.1.1 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate
apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the
projection lens. The mirror tilt angle defines DMD capability to separate the ON optical path from any other light
path, including undesirable flat–state specular reflections from the DMD window, DMD border structures, or other
system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt
angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination
numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur and affect
system performance.
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Window Characteristics and Optics (continued)
7.5.1.2 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable
artifacts in the display’s border and/or active area, which may require additional system apertures to control,
especially if the numerical aperture of the system exceeds the pixel tilt angle.
7.5.1.3 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating
conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window
aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system
should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately
10% of the average flux level in the active area. Depending on the particular system’s optical architecture, overfill
light may have to be further reduced below the suggested 10% level in order to be acceptable.
7.6 Micromirror Array Temperature Calculation
Illumination
Direction
Off-state
Light
Figure 19. DMD Thermal Test Points
Micromirror array temperature can be computed analytically from measurement points on the outside of the
package, the ceramic package thermal resistance, the electrical power dissipation, and the illumination heat load.
The relationship between micromirror array temperature and the reference ceramic temperature is provided by
the following equations:
TARRAY = TCERAMIC + (QARRAY × RARRAY–TO–CERAMIC)
QARRAY = QELECTRICAL + QILLUMINATION
QILLUMINATION = (AILLUMINATION × PNIR X DMD absorption factor)
(1)
(2)
where
•
•
•
TARRAY = Computed DMD array temperature (°C)
TCERAMIC = Measured ceramic temperature (°C), TP1 location in Figure 19
RARRAY–TO–CERAMIC = DMD package thermal resistance from array to outside ceramic (°C/W) specified in
Thermal Information
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Micromirror Array Temperature Calculation (continued)
•
•
•
•
QARRAY = Total DMD power; electrical, specified in Electrical Characteristics , plus absorbed (calculated) (W)
QELECTRICAL = Nominal DMD electrical power dissipation (W), specified in Electrical Characteristics
AILLUMINATION = Illumination area (assumes 83.7% on the active array and 16.3% overfill)
PNIR = Illumination Power Density (W/cm2)
(3)
Electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating
frequencies. Refer to the specifications in Electrical Characteristics. Absorbed power from the illumination source
is variable and depends on the operating state of the mirrors and the intensity of the light source.
The DMD
absorption constant of 0.42 assumes nominal operation with an illumination distribution of 83.7% on the DMD
active array, and 16.3% on the DMD array border and window aperture.
A sample calculation is detailed below:
TCERAMIC = 35 °C, assumed system measurement; see Recommended Operating Conditions for specification
limits
PNIR= 2 W/cm2
QELECTRICAL = 0.0908 W; See the table notes in Recommended Operating Conditions for details.
AILLUMINATION = 0.143 cm2
QARRAY = QELECTRICAL + (QILLUMINATION X DMD absoprtion factor) = 0.0908 W + (2 W/cm2 X 0.143 cm2 X 0.42)
= 0.211 W
TARRAY = 35 °C + (0.211 W × 7.9°C/W) = 36.67 °C
7.7 Micromirror Landed-On/Landed-Off Duty Cycle
7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the On state versus the amount of time the same
micromirror is landed in the Off state.
As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On state 100% of the
time (and in the Off state 0% of the time), whereas 0/100 would indicate that the pixel is in the Off state 100% of
the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (On or Off), the two numbers (percentages)
always add to 100.
7.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed
duty cycle for a prolonged period of time can reduce the DMD’s usable life.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed
duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed
duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
7.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this
interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s
usable life. This is quantified in the de-rating curve shown in Figure 1. The importance of this curve is that:
• All points along this curve represent the same usable life.
• All points above this curve represent lower usable life (and the further away from the curve, the lower the
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Micromirror Landed-On/Landed-Off Duty Cycle (continued)
•
usable life).
All points below this curve represent higher usable life (and the further away from the curve, the higher the
usable life).
In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at
for a give long-term average Landed Duty Cycle.
7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in binary pattern display with value '1' or when displaying pure-white on a given pixel for a given
time period, that pixel will experience a 100/0 Landed Duty Cycle during that time period. Likewise, a binary
pattern display with value '0' or when displaying pure-black, the pixel will experience a 0/100 Landed Duty Cycle.
Table 1. Binary Pattern Mode
Example: Binary Value and
Landed Duty Cycle
BINARY
VALUE
LANDED DUTY
CYCLE
0
0/100
1
100/0
During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:
Landed Duty Cycle = ∑{Pattern[i]_Binary_Value} / {Total_Patterns}
where
•
Pattern[i]_Binary_Value represent a pixel's pattern and its corresponding binary value over all patterns in the
pattern sequence: Total_Patterns.
(4)
For example, assume a pattern sequence with three patterns using pixel x. In this sequence the first pattern has
pixel x on, the second pattern has pixel x off, and the third pattern has pixel x off. Thus, the Landed Duty Cycle is
33%.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two
directions, with the primary direction being into a projection or collection optic. Each application is derived
primarily from the optical architecture of the system and the format of the data coming into the DLPC150
controller. The new high tilt pixel in the side illuminated DMD increases device efficiency and enables a compact
optical system. The DLP2010NIR DMD can be combined with a grating and single element detector to replace
expensive InGaAs linear array detector designs, leading to high performance, cost-effective portable NIR
Spectroscopy solutions. Applications of interest include machine vision systems, spectrometers, medical
systems, skin analysis, material identification, chemical sensing, infrared projection, and compressive sensing.
DMD power-up and power-down sequencing is strictly controlled by the DLPA2000 or DLPA2005. Refer to
Power Supply Recommendations for power-up and power-down specifications. DLP2010NIR DMD reliability is
only specified when used with DLPC150 controller and DLPA2000 or DLPA2005 PMIC/LED Driver.
8.2 Typical Application
A typical embedded system application using the DLPC150 controller and DLP2010NIR is shown in Figure 20. In
this configuration, the DLPC150 controller supports a 24-bit parallel RGB input, typical of LCD interfaces, from an
external source or processor. The DLPC150 controller processes the digital input image and converts the data
into the format needed by the DLP2010NIR. The DLP2010NIR steers light by setting specific micromirrors to the
on position, directing light to the detector, while unwanted micromirrors are set to "off" position, directing light
away from the detector. The microprocessor sends binary images to the DMD to steer specific wavelengths of
light into the detector. The microprocessor uses an analog-to-digital converter to sample the signal received by
the detector into a digital value. By sequentially selecting different wavelengths of light and capturing the values
at the detector, the microprocessor can then plot a spectral response to the light.
24
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Power
Management
On/Off
BAT
–
Charger
DC_IN
+
Typical Application (continued)
2.3 to 5.5 V
1.8 V
Other
Supplies
VIN
SYSPWR
VDD
1.1 V
1.1-V
Reg
1.8 V
1.8S V
LS_IN
PROJ_ON
PROJ_ON
USB
DLPA2000
or
DLPA2005
PROJ_ON
Detector
ADC
FLASH
FLASH,
SDRAM
4
SPI_0
SPI_1
4
PARKZ
RESETZ
INTZ
Microprocessor
HOST_IRQ
Thermistor
I2C
1.8S V
Bluetooth
Illumination
Optics
CMP_OUT
Parallel RGB I/F (28)
SD
Card
Current
Sense
CMP_PWM
DLPC150
TRIG_OUT (2)
RED
BIAS, RST, OFS
3
LED_SEL(2)
TRIG_IN
Keypad
VLED
Sub-LVDS DATA
LPSDR CTRL
VIO
DLP2010NIR
WVGA
(WVGA
DDR
DMD
DMD)
VCC_INTF
VCC_FLSH
1.1 V
Projection
Optics
VCORE
ADC + Amplifier
NIR
Detector
DLP® Chip Set
Figure 20. Typical Application Diagram
8.2.1 Design Requirements
All applications using DLP 0.2-inch WVGA chipset require the DLPC150 controller, DLPA2000 or DLPA2005
PMIC, and DLP2010NIR DMD components for operation. The system also requires an external SPI flash
memory device loaded with the DLPC150 Configuration and Support Firmware. The chipset has several system
interfaces and requires some support circuitry. The following interfaces and support circuitry are required for the
DLP2010NIR:
•
•
DMD Interfaces:
– DLPC150 to DLP2010NIR SubLVDS Digital Data
– DLPC150 to DLP2010NIR LPSDR Control Interface
DMD Power:
– DLPA2000 or DLPA2005 to DLP2010NIR VBIAS Supply
– DLPA2000 or DLPA2005 to DLP2010NIR VOFFSET Supply
– DLPA2000 or DLPA2005 to DLP2010NIR VRESET Supply
– DLPA2000 or DLPA2005 to DLP2010NIR VDDI Supply
– DLPA2000 or DLPA2005 to DLP2010NIR VDD Supply
The illumination light that is applied to the DMD is typically from an infrared LED or lamp.
8.2.2 Detailed Design Procedure
For connecting together the DLPC150, the DLPA2005, and the DLP2010NIR DMD, see the TI DLP NIRscan
Nano EVM reference design schematic.
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Typical Application (continued)
8.2.3 Application Curve
In a reflective spectroscopy application, a broadband light source illuminates a sample and the reflected light
spectrum is dispersed onto the DLP2010NIR. A microprocessor in conjunction with the DLPC150 controls
individual DLP2010NIR micromirrors to reflect specific wavelengths of light to a single point detector. The
microprocessor uses an analog-to-digital converter to sample the signal received by the detector into a digital
value. By sequentially selecting different wavelengths of light and capturing the values at the detector, the
microprocessor can then plot a spectral response to the light. This systems allows the measurement of the
collected light and derive the wavelengths absorbed by the sample. This process leads to the absorption
spectrum shown in Figure 21.
SPACE
Figure 21. Sample DLP2010NIR Based Spectrometer Output
26
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9 Power Supply Recommendations
The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, and
VRESET. DMD power-up and power-down sequencing is strictly controlled by the DLPA2000 or DLPA2005
device.
CAUTION
For reliable operation of the DMD, the following power supply sequencing
requirements must be followed. Failure to adhere to the prescribed power-up and
power-down procedures may affect device reliability.
VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated
during power-up and power-down operations. Failure to meet any of the below
requirements will result in a significant reduction in the DMD’s reliability and lifetime.
Refer to Figure 23. VSS must also be connected.
9.1 Power Supply Power-Up Procedure
•
•
•
•
During power-up, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET
voltages are applied to the DMD.
During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the
specified limit shown in Recommended Operating Conditions. Refer to Table 2 and the Layout Example for
power-up delay requirements.
During power-up, the DMD’s LPSDR input pins shall not be driven high until after VDD and VDDI have settled
at operating voltage.
During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS. Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow
the requirements listed previously and in Figure 22.
9.2 Power Supply Power-Down Procedure
•
•
•
•
•
Power-down sequence is the reverse order of the previous power-up sequence. VDD and VDDI must be
supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.
During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement
that the delta between VBIAS and VOFFSET must be within the specified limit shown in Recommended
Operating Conditions (Refer to Note 2 for Figure 22).
During power-down, the DMD’s LPSDR input pins must be less than VDDI, the specified limit shown in
Recommended Operating Conditions.
During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS.
Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements listed previously and in Figure 22.
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9.3 Power Supply Sequencing Requirements
DLP Display Controller and
PMIC control start of DMD
operation
DLP Display Controller and PMIC
disable VBIAS, VOFFSET and
VRESET
Mirror Park
Sequence
Note 4
Power Off
VDD / VDDI
VDD / VDDI
VDD / VDDI VSS
VSS
VOFFSET
VOFFSET
VDD < VOFFSET < 6 V
VOFFSET
VBIAS < 4 V
VSS
Note 2
ûV < Specification Limit
Note 1
Note 2
VSS
<6V
Note 3
VDD < VBIAS
VBIAS
ûV < Specification Limit
VBIAS
ûV < Specification Limit
VBIAS
VOFFSET < 4 V
VSS
VSS
VRESET < 0.5 V
VSS
VSS
VRESET > - 4 V
VRESET
VRESET
VRESET
VDD
VDD
DMD_DEN_ARSTZ VSS
INITIALIZATION
LS_CLK
LS_WDATA
VSS
VDD
VDD
VSS
VSS
VID
VID
D_P(0:3), D_N(0:3)
DCLK_P, DCLK_N
VSS
VSS
(1)
Refer to Table 2 and Figure 23 for critical power-up sequence delay requirements.
(2)
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in
Recommended Operating Conditions. OEMs may find that the most reliable way to ensure this is to power VOFFSET
prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during power-down. Refer to Table 2 and
Figure 23 for power-up delay requirements
(3)
To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit shown in
Recommended Operating Conditions.
(4)
When system power is interrupted, the ASIC driver initiates hardware power-down that disables VBIAS, VRESET and
VOFFSET after the Micromirror Park Sequence. Software power-down disables VBIAS, VRESET, and VOFFSET
after the Micromirror Park Sequence through software control.
(5)
Drawing is not to scale and details are omitted for clarity.
Figure 22. Power Supply Sequencing Requirements (Power Up and Power Down)
28
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Power Supply Sequencing Requirements (continued)
Table 2. Power-Up Sequence Delay Requirement
PARAMETER
MIN
UNIT
tDELAY
Delay requirement from VOFFSET power up to VBIAS power up
2
ms
VOFFSET
Supply voltage level during power–up sequence delay (see Figure 23)
6
V
VBIAS
Supply voltage level during power–up sequence delay (see Figure 23)
6
V
12 V
VOFFSET
8V
VDD ≤ VOFFSET < 6 V
4V
VSS
tDELAY
0V
VBIAS
20 V
16 V
12 V
8V
VDD ≤ VBIAS < 6 V
4V
VSS
A.
0V
Refer to Table 2 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay.
Figure 23. Power-Up Sequence Delay Requirement
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10 Layout
10.1 Layout Guidelines
There are no specific layout guidelines for the DMD as typically DMD is connected using a board to board
connector to a flex cable. Flex cable provides the interface of data and Ctrl signals between the DLPC343x
controller and the DLP2010 DMD. For detailed layout guidelines refer to the layout design files. Some layout
guideline for the flex cable interface with DMD are:
• Match lengths for the LS_WDATA and LS_CLK signals.
• Minimize vias, layer changes, and turns for the HS bus signals. Refer Figure 24.
• Minimum of 100-nF decoupling capacitor close to VBIAS. Capacitor C4 in Figure 25.
• Minimum of 100-nF decoupling capacitor close to VRST. Capacitor C6 in Figure 25.
• Minimum of 220-nF decoupling capacitor close to VOFS. Capacitor C7 in Figure 25.
• Optional minimum 200- to 220-nF decoupling capacitor to meet the ripple requirements of the DMD. C5 in
Figure 25.
• Minimum of 100-nF decoupling capacitor close to Vcci. Capacitor C1 in Figure 25.
• Minimum of 100-nF decoupling capacitor close to both groups of Vcc pins, for a total of 200 nF for Vcc.
Capacitor C2/C3 in Figure 25.
10.2 Layout Example
Figure 24. High-Speed (HS) Bus Connections
30
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Layout Example (continued)
Figure 25. Power Supply Connections
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
DLP2010NIRFQJ
Package Type
NIR DMD
Device Descriptor
Figure 26. Part Number Description
11.1.2 Device Markings
Device Marking will include the human–readable character string GHJJJJK VVVV on the electrical connector.
GHJJJJK is the lot trace code. VVVV is a 4 character encoded device part number
GHJJJJKHVVVV
Figure 27. DMD Marking
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
32
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DLPC150
Click here
Click here
Click here
Click here
Click here
DLPA2000
Click here
Click here
Click here
Click here
Click here
DLPA2005
Click here
Click here
Click here
Click here
Click here
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11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
DLP is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
DLP2010NIRFQJ
ACTIVE
Package Type Package Pins Package
Drawing
Qty
CLGA
FQJ
40
1
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
Call TI
Level-1-NC-NC
Op Temp (°C)
Device Marking
(4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2015
Addendum-Page 2
8
5
6
7
3
4
C
NOTES UNLESS OTHERWISE SPECIFIED:
COPYRIGHT 2012 TEXAS INSTRUMENTS
UN-PUBLISHED, ALL RIGHTS RESERVED. REV
A
1 DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY.
B
2 ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION
TOLERANCE AND HAS A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES.
C
D
E
3 BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY.
D
2512515
DWG NO.
SH
1
1
REVISIONS
DESCRIPTION
ECO 2127544: INITIAL RELEASE
ECO 2129552: ENLARGE APERTURE ON RIGHT SIDE;
MOVE ACTIVE ARRAY Y-LOCATION DIM, SH. 3
ECO 2131252: ENLARGE APERTURE ALONG BOTTOM EDGE
ECO 2135244: CORRECT WINDOW THK TOL, ZONE B6
ECO 2138016: INCREASE WINDOW THK NOMINAL
DATE
9/14/2012
BY
BMH
12/10/2012
BMH
2/20/2013
8/5/2013
11/21/2013
BMH
BMH
BMH
4 DMD MARKING TO APPEAR IN CONNECTOR RECESS.
D
5 NOTCH DIMENSIONS ARE DEFINED BY UPPERMOST LAYERS OF CERAMIC,
AS SHOWN IN SECTION A-A.
6 ENCAPSULANT TO BE CONTAINED WITHIN DIMENSIONS SHOWN IN VIEW C
(SHEET 2). NO ENCAPSULANT IS ALLOWED ON TOP OF THE WINDOW.
7 ENCAPSULANT NOT TO EXCEED THE HEIGHT OF THE WINDOW.
8 DATUM B IS DEFINED BY A DIA. 2.5 PIN, WITH A FLAT ON THE SIDE FACING
TOWARD THE CENTER OF THE ACTIVE ARRAY, AS SHOWN IN VIEW B (SHEET 2).
9 WHILE ONLY THE THREE DATUM A TARGET AREAS A1, A2, AND A3 ARE USED
FOR MEASUREMENT, ALL 4 CORNERS SHOULD BE CONTACTED, INCLUDING E1,
TO SUPPORT MECHANICAL LOADS.
1.176 0.05
5
4X (R0.2)
5
+0.3
5.3 - 0.1
C
5
(ILLUMINATION
DIRECTION)
5
90° 1°
C
5
4X R0.4 0.1
2X 2.5 0.075
(2.5)
5
+0.2
2.65 0.1
8
5
A
1.25
C
5
B
+0.2
1.4 - 0.1
5
A
5
5
+0.2
0.8 0.1
(1)
14.1 0.08
+0.3
15.9 0.1
(OFF-STATE
DIRECTION)
B
1.003 0.077
1 9
(2.5)
2X ENCAPSULANT
(1.783)
0.78 0.063
1.4 0.1
H
(SHEET 3)
H
(SHEET 3)
(PANASONIC AXT640124DD1, 40-CONTACT, 0.4 mm
PITCH BOARD-TO-BOARD CONNECTOR HEADER)
MATES WITH PANASONIC AXT540124DD1 OR EQUIVALENT
CONNECTOR SOCKET
SECTION A-A
NOTCH OFFSETS
UNLESS OTHERWISE SPECIFIED
DIMENSIONS ARE IN MILLIMETERS
TOLERANCES:
0314DA
THIRD ANGLE
PROJECTION
NEXT ASSY
USED ON
8
7
6
5
4
DRAWN
9/14/2012
ENGINEER
9/14/2012
B. HASKETT
2 PLACE DECIMALS 0.25
QA/CE
1 PLACE DECIMALS 0.50
DIMENSIONAL LIMITS APPLY BEFORE PROCESSES
INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME
Y14.5M-1994
REMOVE ALL BURRS AND SHARP EDGES
PARENTHETICAL INFORMATION FOR REFERENCE ONLY
P. KONRAD
Dallas Texas
TITLE
ICD, MECHANICAL, DMD,
.2 WVGA SERIES 244
9/26/2012
F. ARMSTRONG 9/26/2012
M. DORAK
9/18/2012
SIZE
APPROVED
9/18/2012
SCALE
2
A
TEXAS
INSTRUMENTS
CM
M. SOUCEK
3
DATE
B. HASKETT
ANGLES 1
APPLICATION
INV11-2006a
9
0.05
(0.88)
0 MIN TYP.
3 SURFACES INDICATED
IN VIEW B (SHEET 2)
A
5
0.4 MIN
TYP.
A
D
0.038 A
0.02 D
ACTIVE ARRAY
(1.4)
0.7 0.05
B
6 7
REV
DWG NO
D
E
2512515
20:1
SHEET
1
1
OF
3
8
7
2X 1.176
6
5
3
4
DWG NO.
2512515
SH
1
2
2X (1)
2X 14.1
2X (0.8)
D
A2
A3
D
4X 1.45
C
1.25
2.5
4X (1.2)
B
8
(1.1)
E1
9
A1
VIEW B
DATUMS A, B, C, AND E
C
1.176
(FROM SHEET 1)
C
14.1
5.5
(2.5)
2.75
C
1.25
B
B
B
VIEW C 6
ENCAPSULANT MAXIMUM X/Y DIMENSIONS
(FROM SHEET 1)
2X 0 MIN
7
A
A
VIEW D
ENCAPSULANT MAXIMUM HEIGHT
TEXAS
INSTRUMENTS
Dallas Texas
INV11-2006a
8
7
6
5
4
3
DRAWN
B. HASKETT
DATE
9/14/2012
SIZE
D
SCALE
2
DWG NO
REV
2512515
SHEET
1
2
OF
E
3
8
5
6
7
3
2512515
DWG NO.
SH
1
3
(4.6116)
ACTIVE ARRAY
6.454 0.075
0.94 0.05
3
4
4X (0.108)
0.134 0.0635
D
(ILLUMINATION
DIRECTION)
(4.86)
WINDOW
(2.592)
ACTIVE ARRAY
3.016 0.0635
3.92 0.05
F
(2.5)
1.102 0.075
G
1.25
C
D
(3.15)
APERTURE
B
2
0.424 0.0635
4.839 0.0635
C
(5.263)
APERTURE
2.961 0.05
C
6.505 0.05
(9.466)
WINDOW
VIEW E
WINDOW AND ACTIVE ARRAY
(FROM SHEET 1)
53X TEST PADS
0.2 A B C
0.1 A
4
50X 0.6±0.1 X 0.54±0.1
(9.8)
3.326
BACK INDEX MARK
3X Ø0.54±0.1
0.4 A B C
(42°) TYP.
2.23
C
B
1.25
(2.5)
(0.15) TYP.
B
G20
B
G1
(42°) TYP.
2X (1.86)
(0.075) TYP.
2X 0.93
0.4 A B C
H1
H20
5 X 0.892 = 4.46
(42°) TYP.
(0.068) TYP.
(0.068) TYP.
18 X 0.8 = 14.4
DETAIL G
APERTURE RIGHT EDGE
DETAIL F
APERTURE LEFT EDGE
VIEW H-H
TEST PADS AND CONNECTOR
(POND OF MIRRORS OMITTED FOR CLARITY)
SCALE 60 : 1
SCALE 60 : 1
A
1.026
A
(FROM SHEET 1)
TEXAS
INSTRUMENTS
Dallas Texas
INV11-2006a
8
7
6
5
4
3
DRAWN
B. HASKETT
DATE
9/14/2012
SIZE
D
SCALE
2
DWG NO
REV
2512515
SHEET
1
3
OF
E
3
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