TOSHIBA TC74VHC9273FK

TC74VHC9273P/FT/FK
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74VHC9273P,TC74VHC9273FT,TC74VHC9273FK
Octal D-Type Flip Flop with Clear
The TC74VHC9273 is an advanced high speed CMOS OCTAL
D-TYPE FLIP FLOP fabricated with silicon gate C2MOS
technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
Information signals applied to D inputs are transferred to the
Q outputs on the positive going edge of the clock pulse.
When the CLR input is held “L”, the Q outputs are at a low
logic level independent of the other inputs.
The CLR input and CK input have hysteresis between the
positive-going and negative-going thresholds. Thus the
TC74VHC9273 is capable of squaring up transitions of slowly
changing input signals and provides an improved noise
immunity.
It is easy to wire on the board because Input terminals are at
the opposite side of Output terminals.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
TC74VHC9273P
TC74VHC9273FT
TC74VHC9273FK
Features
•
High speed: fmax = 195 MHz (typ.) at VCC = 5 V
•
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
•
High noise immunity: VNIH = VNIL = 28% VCC (min)
•
•
Power down protection is provided on all inputs.
Balanced propagation delays: tpLH ∼
− tpHL
•
Wide operating voltage range: VCC (opr) = 2 to 5.5 V
•
Function compatible with 74VHC273
•
Input terminals are at the opposite side of Output terminals
Weight
DIP20-P-300-2.54A
TSSOP20-P-0044-0.65A
VSSOP20-P-0030-0.50
1
: 1.30 g ( typ.)
: 0.08 g ( typ.)
: 0.03 g ( typ.)
2009-04-01
TC74VHC9273P/FT/FK
Pin Assignment
CLR
IEC Logic Symbol
1
20
VCC
D1
2
19
Q1
D2
3
18
Q2
D3
4
17
Q3
D4
5
16
Q4
D5
6
15
Q5
D6
7
14
Q6
D7
8
13
Q7
D8
9
12
Q8
GND 10
11
CK
CLR
CK
D1
D2
D3
D4
D5
D6
D7
D8
(1)
(11)
R
C1
(2)
(3)
(4)
(5)
(6)
(7)
1D
(19)
(18)
(17)
(16)
(15)
(14)
(8)
(9)
Q1
Q2
Q3
Q4
Q5
Q6
(13)
(12)
Q7
Q8
(top view)
Truth Table
Inputs
Output
Function
CLR
D
CK
Q
L
X
X
L
Clear
H
L
L
―
H
H
H
―
H
X
Qn
No Change
X: Don’t care
System Diagram
CLR
1
D1
2
D2
3
D R
CK
CK
D3
4
D R
Q
CK
D R
Q
D5
D4
5
CK
D R
Q
D6
6
CK
D R
Q
D7
CK
D R
Q
D8
8
7
CK
9
D R
Q
CK
D R
Q
CK
Q
11
19
Q1
18
Q2
17
16
Q4
Q3
2
15
Q5
13
14
Q6
12
Q7
Q8
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TC74VHC9273P/FT/FK
Absolute Maximum Ratings (Note1)
Characteristics
Symbol
Rating
Unit
Supply voltage range
VCC
−0.5 to 7.0
V
DC input voltage
VIN
−0.5 to 7.0
V
VOUT
−0.5 to VCC + 0.5
V
Input diode current
IIK
−20
mA
Output diode current
IOK
±20
mA
DC output current
IOUT
±25
mA
DC VCC/ground current
ICC
±75
mA
Power dissipation
PD
500 (DIP) (Note 2)/180(TSSOP/VSSOP)
mW
Storage temperature
Tstg
−65 to 150
°C
DC output voltage
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C shall be
applied until 300 mW.
Operating Ranges (Note)
Characteristics
Symbol
Rating
Unit
Supply voltage
VCC
2.0 to 5.5
V
Input voltage
VIN
0 to 5.5
V
VOUT
0 to VCC
V
Topr
−40 to 85
°C
Output voltage
Operating temperature
Note: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
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TC74VHC9273P/FT/FK
Electrical Characteristics
DC Characteristics
Test Condition
Characteristics
Ta = 25°C
Symbol
High-level input
voltage
VIH
Low-level input
voltage
Hysteresis voltage
(CK、 CLR )
Min
Typ.
Max
Min
Max
3.0
―
―
2.20
―
2.20
4.5
―
―
3.15
―
3.15
5.5
―
―
3.85
―
3.85
3.0
0.90
―
―
0.90
―
4.5
1.35
―
―
1.35
―
5.5
1.65
―
―
1.65
―
3.0
0.30
―
1.20
0.30
1.20
4.5
0.40
―
1.40
0.40
1.40
5.5
0.50
―
1.60
0.50
1.60
2.0
1.9
2.0
―
1.9
―
3.0
2.9
3.0
―
2.9
―
4.5
4.4
4.5
―
4.4
―
IOH = −4 mA
3.0
2.58
―
―
2.48
―
IOH = −8 mA
4.5
3.94
―
―
3.80
―
2.0
―
0.0
0.1
―
0.1
3.0
―
0.0
0.1
―
0.1
4.5
―
0.0
0.1
―
0.1
IOL = 4 mA
3.0
―
―
0.36
―
0.44
IOL = 8 mA
4.5
―
―
0.36
―
0.44
―
VH
―
IOH = −50 μA
High-level output
voltage
VOH
VIN
= VIH or VIL
IOL = 50 μA
Low-level output
voltage
VOL
Unit
VCC
(V)
―
VIL
Ta = −40 to 85°C
VIN
= VIH or VIL
Input leakage current
IIN
VIN = 5.5 V or
GND
0 to
5.5
―
―
±0.1
―
±1.0
Quiescent supply
current
ICC
VIN = VCC or
GND
5.5
―
―
4.0
―
40.0
Ta = 25°C
Ta =
−40 to
85°C
V
V
V
V
μA
Timing Requirements (input: tr = tf = 3 ns)
Characteristics
Minimum pulse width (CK)
Minimum pulse width ( CLR )
Test Condition
Symbol
tw (L)
―
tw (H)
tw (L)
―
Minimum set-up time
ts
―
Minimum hold time
th
―
trem
―
Minimum removal time ( CLR )
4
VCC (V)
Typ.
Limit
Limit
3.3 ± 0.3
―
5.5
6.5
5.0 ± 0.5
―
5.0
5.0
3.3 ± 0.3
―
5.0
6.0
5.0 ± 0.5
―
5.0
5.0
3.3 ± 0.3
―
6.0
7.0
5.0 ± 0.5
―
4.5
4.5
3.3 ± 0.3
―
1.0
1.0
5.0 ± 0.5
―
1.0
1.0
3.3 ± 0.3
―
2.5
2.5
5.0 ± 0.5
―
2.0
2.0
Unit
ns
ns
ns
ns
ns
2009-04-01
TC74VHC9273P/FT/FK
AC Characteristics (input: tr = tf = 3 ns)
Characteristics
Test Condition
Symbol
VCC (V)
Propagation delay
time
tpLH
(CK-Q)
tpHL
Propagation delay
time
Min
Typ.
Max
Min
Max
15
―
5.7
11.8
1.0
13.4
50
―
8.7
18.4
1.0
20.9
15
―
4.2
7.7
1.0
8.8
50
―
6.5
12.1
1.0
13.8
15
―
5.9
12.3
1.0
14.0
50
―
8.6
18.0
1.0
20.6
15
―
4.3
8.0
1.0
9.1
50
―
6.5
11.9
1.0
13.6
15
85
140
―
75
―
50
50
75
―
45
―
15
130
195
―
115
―
50
80
100
―
70
―
3.3 ± 0.3
50
―
―
1.5
―
1.5
5.0 ± 0.5
50
―
―
1.0
―
1.0
―
4
10
―
10
pF
―
11
―
―
―
pF
3.3 ± 0.3
―
5.0 ± 0.5
―
( CLR -Q)
5.0 ± 0.5
3.3 ± 0.3
Maximum clock
frequency
fmax
―
5.0 ± 0.5
Output to output skew
tosLH
tosHL
Input capacitance
CIN
Power dissipation
capacitance
CPD
(Note 1)
Unit
CL (pF)
3.3 ± 0.3
tpHL
Ta = −40 to
85°C
Ta = 25°C
―
(Note 2)
ns
ns
MHz
ns
Note 1: Parameter guaranteed by design.
tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn|
Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC/8 (per bit)
And the total CPD when n pcs.of flip flop operate can be calculated by the following equation:
CPD (total) = 7 + 4·n
Input Equivalent Circuit
INPUT
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TC74VHC9273P/FT/FK
Package Dimensions
Weight: 1.30 g (typ.)
6
2009-04-01
TC74VHC9273P/FT/FK
Package Dimensions
Weight: 0.08 g (typ.)
7
2009-04-01
TC74VHC9273P/FT/FK
Package Dimensions
Weight: 0.03 g (typ.)
8
2009-04-01
TC74VHC9273P/FT/FK
RESTRICTIONS ON PRODUCT USE
• Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively “Product”) without notice.
• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA’s written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product’s quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before creating and producing designs and using, customers must
also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document,
the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the “TOSHIBA
Semiconductor Reliability Handbook” and (b) the instructions for the application that Product will be used with or for. Customers are
solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the
appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the applicability of any
information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other
referenced documents; and (c) validating all operating parameters for such designs and applications. TOSHIBA ASSUMES NO
LIABILITY FOR CUSTOMERS’ PRODUCT DESIGN OR APPLICATIONS.
• Product is intended for use in general electronics applications (e.g., computers, personal equipment, office equipment, measuring
equipment, industrial robots and home electronics appliances) or for specific applications as expressly stated in this document.
Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or
reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious
public impact (“Unintended Use”). Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used
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noncompliance with applicable laws and regulations.
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