4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA AD7192 FEATURES Temperature measurement Chromatography PLC/DCS analog input modules Data acquisition Medical and scientific instrumentation RMS noise: 11 nV @ 4.7 Hz (gain = 128) 15.5 noise-free bits @ 2.4 kHz (gain = 128) Up to 22 noise-free bits (gain = 1) Offset drift: 5 nV/°C Gain drift: 1 ppm/°C Specified drift over time 2 differential/4 pseudo differential input channels Automatic channel sequencer Programmable gain (1 to 128) Output data rate: 4.7 Hz to 4.8 kHz Internal or external clock Simultaneous 50 Hz/60 Hz rejection 4 general-purpose digital outputs Power supply AVDD: 3 V to 5.25 V DVDD: 2.7 V to 5.25 V Current: 4.35 mA Temperature range: –40°C to +105°C Package: 24-lead TSSOP GENERAL DESCRIPTION The AD7192 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can be interfaced directly to the ADC. The device can be configured to have two differential inputs or four pseudo differential inputs. The on-chip channel sequencer allows several channels to be enabled, and the AD7192 sequentially converts on each enabled channel. This simplifies communication with the part. The on-chip 4.92 MHz clock can be used as the clock source to the ADC or, alternatively, an external clock or crystal can be used. The output data rate from the part can be varied from 4.7 Hz to 4.8 kHz. The device has two digital filter options. The choice of filter affects the rms noise/noise-free resolution at the programmed output data rate, the settling time, and the 50 Hz/60 Hz rejection. For applications that require all conversions to be settled, the AD7192 includes a zero latency feature. INTERFACE 3-wire serial SPI, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLK APPLICATIONS The part operates with a power supply from 3 V to 5.25 V. It consumes a current of 4.35 mA. It is housed in a 24-lead TSSOP package. Weigh scales Strain gage transducers Pressure measurement FUNCTIONAL BLOCK DIAGRAM AGND AIN1 AIN2 AIN3 AIN4 AINCOM AVDD AVDD MUX DVDD DGND REFIN1(+) REFIN1(–) REFERENCE DETECT AD7192 Σ-Δ ADC PGA SERIAL INTERFACE AND CONTROL LOGIC DOUT/RDY DIN SCLK CS SYNC AGND TEMP SENSOR P3 P2 BPDSW AGND MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+) 07822-001 CLOCK CIRCUITRY Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD7192 TABLE OF CONTENTS Features .............................................................................................. 1 Offset Register ............................................................................ 24 Interface ............................................................................................. 1 Full-Scale Register ...................................................................... 24 Applications ....................................................................................... 1 ADC Circuit Information.............................................................. 25 General Description ......................................................................... 1 Overview ..................................................................................... 25 Functional Block Diagram .............................................................. 1 Filter, Output Data Rate, and Settling Time ........................... 25 Revision History ............................................................................... 2 Digital Interface .......................................................................... 28 Specifications..................................................................................... 3 Circuit Description......................................................................... 32 Timing Characteristics..................................................................... 7 Analog Input Channel ............................................................... 32 Circuit and Timing Diagrams..................................................... 7 Programmable Gain Array (PGA) ........................................... 32 Absolute Maximum Ratings............................................................ 9 Bipolar/Unipolar Configuration .............................................. 32 Thermal Resistance ...................................................................... 9 Data Output Coding .................................................................. 32 ESD Caution .................................................................................. 9 Clock ............................................................................................ 32 Pin Configuration and Function Descriptions ........................... 10 Burnout Currents ....................................................................... 33 Typical Performance Characteristics ........................................... 12 Reference ..................................................................................... 33 RMS Noise and Resolution............................................................ 14 Reference Detect ......................................................................... 33 4 Reset ............................................................................................. 34 3 System Synchronization ............................................................ 34 4 Temperature Sensor ................................................................... 34 3 Sinc Chop Enabled .................................................................... 17 Bridge Power-Down Switch ...................................................... 34 On-Chip Registers .......................................................................... 18 Logic Outputs ............................................................................. 34 Communications Register ......................................................... 18 Enable Parity ............................................................................... 35 Status Register ............................................................................. 19 Calibration................................................................................... 35 Mode Register ............................................................................. 19 Grounding and Layout .............................................................. 36 Configuration Register .............................................................. 21 Applications Information .............................................................. 37 Data Register ............................................................................... 23 Weigh Scales ................................................................................ 37 ID Register ................................................................................... 23 Outline Dimensions ....................................................................... 38 GPOCON Register ..................................................................... 24 Ordering Guide .......................................................................... 38 Sinc Chop Disabled ................................................................... 14 Sinc Chop Disabled ................................................................... 15 Sinc Chop Enabled .................................................................... 16 REVISION HISTORY 5/09—Rev. 0 to Rev. A Change to Gain Error Specification ............................................... 3 Changes to Table 3 ............................................................................ 9 5/09—Revision 0: Initial Version Rev. A | Page 2 of 40 AD7192 SPECIFICATIONS AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = AVDD, REFINx(−) = AGND, MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter ADC Output Data Rate No Missing Codes2 Resolution RMS Noise and Output Data Rates Integral Nonlinearity Gain = 12 Gain > 1 Offset Error4, 5 Offset Error Drift vs. Temperature Offset Error Drift vs. Time Gain Error4 Gain Drift vs. Temperature Gain Drift vs. Time Power Supply Rejection Common-Mode Rejection @ DC2 @ DC @ 50 Hz, 60 Hz2 @ 50 Hz, 60 Hz2 Normal Mode Rejection2 Sinc4 Filter Internal Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz AD7192B Unit Test Conditions/Comments1 4.7 to 4800 1.17 to 1200 1.56 to 1600 24 24 Hz nom Hz nom Hz nom Bits min Bits min Chop disabled Chop enabled, sinc4 filter Chop enabled, sinc3 filter FS > 1, sinc4 filter3 FS > 4, sinc3 filter3 See the RMS Noise and Resolution section See the RMS Noise and Resolution section ±10 ±15 ±30 ±30 ±150/gain ±0.5 ±150/gain ±5 ±5 25 ±0.001 ppm of FSR max ppm of FSR max ppm of FSR max ppm of FSR max μV typ μV typ nV/°C typ nV/°C typ nV/°C typ nV/1000 hours typ % typ −0.39 % typ ±0.003 % typ ±0.005 % typ ±2 ppm typical, AVDD = 5 V ±2 ppm typical, AVDD = 3 V ±5 ppm typical, AVDD = 5 V ±12 ppm typical, AVDD = 3 V Chop disabled Chop enabled Gain = 1 to 16; chop disabled Gain = 32 to 128; chop disabled Chop enabled Gain > 32 AVDD = 5 V, gain = 1, TA = 25°C (factory calibration conditions) Gain = 128, before full-scale calibration (see Table 23) Gain > 1, after internal full-scale calibration, AVDD ≥ 4.75 V. Gain > 1, after internal full-scale calibration, AVDD < 4.75 V ±1 10 90 95 ppm/°C typ ppm/1000 hours typ dB typ dB min 100 110 120 120 dB min dB min dB min dB min Gain = 1, VIN = 1 V. Gain > 1, VIN = 1 V/gain. 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 50 ± 1 Hz (50 Hz output data rate), 60 ± 1 Hz (60 Hz output data rate). 100 74 dB min dB min 96 97 dB min dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, 50 ± 1 Hz. 60 Hz output data rate, 60 ± 1 Hz. Rev. A | Page 3 of 40 Gain = 1. Gain = 1, VIN = 1 V. Gain > 1, VIN = 1 V/gain, 110 dB typ. AD7192 Parameter External Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz 3 Sinc Filter Internal Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz External Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz ANALOG INPUTS Differential Input Voltage Ranges Absolute AIN Voltage Limits2 Unbuffered Mode Buffered Mode Analog Input Current Buffered Mode Input Current2 Input Current Drift Unbuffered Mode Input Current Input Current Drift REFERENCE INPUT REFIN Voltage Absolute REFIN Voltage Limits2 Average Reference Input Current AD7192B Unit Test Conditions/Comments1 120 82 dB min dB min 120 120 dB min dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, 50 ± 1 Hz. 60 Hz output data rate, 60 ± 1 Hz. 75 60 dB min dB min 70 70 dB min dB min 100 67 dB min dB min 95 95 dB min dB min ± VREF/gain V nom ± (AVDD – 1.25 V)/gain V min/max AGND − 50 mV AVDD + 50 mV AGND + 250 mV AVDD − 250 mV V min V max V min V max ±2 ±3 ±5 nA max nA max pA/°C typ Gain = 1. Gain > 1. ±3.5 μA/V typ ±1 ±0.05 ±1.6 μA/V typ nA/V/°C typ nA/V/°C typ Gain = 1, input current varies with input voltage. Gain > 1. External clock. Internal clock. AVDD 1 AVDD V nom V min V max GND – 50 mV AVDD + 50 mV 4.5 V min V max μA/V typ Rev. A | Page 4 of 40 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, 50 ± 1 Hz. 60 Hz output data rate, 60 ± 1 Hz. 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, 50 ± 1 Hz. 60 Hz output data rate, 60 ± 1 Hz. VREF = REFINx(+) − REFINx(−), gain = 1 to 128. Gain > 1. REFIN = REFINx(+) − REFINx(−). The differential input must be limited to ±(AVDD – 1.25 V)/gain when gain > 1. AD7192 Parameter Average Reference Input Current Drift Normal Mode Rejection2 Common-Mode Rejection Reference Detect Levels TEMPERATURE SENSOR Accuracy Sensitivity BRIDGE POWER-DOWN SWITCH RON Allowable Current2 BURNOUT CURRENTS AIN Current DIGITAL OUTPUTS (P0 to P3) Output High Voltage, VOH Output Low Voltage, VOL Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current2 Floating-State Output Capacitance INTERNAL/EXTERNAL CLOCK Internal Clock Frequency Duty Cycle External Clock/Crystal Frequency Input Low Voltage VINL Input High Voltage, VINH Input Current LOGIC INPUTS Input High Voltage, VINH2 Input Low Voltage, VINL2 Hysteresis2 Input Currents LOGIC OUTPUT (DOUT/RDY) Output High Voltage, VOH2 Output Low Voltage, VOL2 Output High Voltage, VOH2 Output Low Voltage, VOL2 Floating-State Leakage Current Floating-State Output Capacitance Data Output Coding AD7192B ±0.03 Unit nA/V/°C typ Test Conditions/Comments 1 External clock. ±1.3 Same as for analog inputs 100 0.3 0.6 nA/V/°C typ Internal clock. ±2 2815 °C typ Codes/°C typ Applies after user calibration at 25°C. Bipolar mode. 10 30 Ω max mA max Continuous current. 500 nA nom Analog inputs must be buffered and chop disabled. AVDD − 0.6 0.4 4 0.4 ±100 10 V min V max V min V max nA max pF typ AVDD = 3 V, ISOURCE = 100 μA. AVDD = 3 V, ISINK = 100 μA. AVDD = 5 V, ISOURCE = 200 μA. AVDD = 5 V, ISINK = 800 μA. 4.92 ± 4% 50:50 MHz min/max % typ 4.9152 2.4576/5.12 0.8 0.4 2.5 3.5 ±10 MHz nom MHz min/max V max V max V min V min μA max 2 0.8 0.1/0.25 ±10 V min V max V min/V max μA max DVDD − 0.6 0.4 4 0.4 ±10 10 V min V max V min V max μA max pF typ dB typ V min V max Offset binary Rev. A | Page 5 of 40 DVDD = 5 V. DVDD = 3 V. DVDD = 3 V. DVDD = 5 V. DVDD = 3 V, ISOURCE = 100 μA. DVDD = 3 V, ISINK = 100 μA. DVDD = 5 V, ISOURCE = 200 μA. DVDD = 5 V, ISINK = 1.6 mA. AD7192 Parameter SYSTEM CALIBRATION2 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span POWER REQUIREMENTS 7 Power Supply Voltage AVDD − AGND DVDD − DGND Power Supply Currents AIDD Current DIDD Current IDD (Power-Down Mode) AD7192B Unit 1.05 × FS −1.05 × FS 0.8 × FS 2.1 × FS V max V min V min V max 3/5.25 2.7/5.25 V min/max V min/max 0.6 0.85 3.2 3.6 4.5 5 0.4 0.6 1.5 3 mA max mA max mA max mA max mA max mA max mA max mA max mA typ μA max 1 Test Conditions/Comments 1 0.53 mA typical, gain = 1, buffer off. 0.75 mA typical, gain = 1, buffer on. 2.5 mA typical, gain = 8, buffer off. 3 mA typical, gain = 8, buffer on. 3.5 mA typical, gain = 16 to 128, buffer off. 4 mA typical, gain = 16 to 128, buffer on. 0.35 mA typical, DVDD = 3 V. 0.5 mA typical, DVDD = 5 V. External crystal used. Temperature range: −40°C to +105°C. Specification is not production tested but is supported by characterization data at initial product release. 3 FS is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. 4 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system fullscale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate. 5 The analog inputs are configured for differential mode. 6 REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection. 7 Digital inputs equal to DVDD or DGND. 2 Rev. A | Page 6 of 40 AD7192 TIMING CHARACTERISTICS AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 2. Parameter t3 t4 READ OPERATION t1 t2 3 t5 5, 6 t6 t7 WRITE OPERATION t8 t9 t10 t11 Limit at TMIN, TMAX (B Version) 100 100 Unit ns min ns min Conditions/Comments 1, 2 SCLK high pulse width SCLK low pulse width 0 60 80 0 60 80 10 80 0 10 ns min ns max ns max ns min ns max ns max ns min ns max ns min ns min CS falling edge to DOUT/RDY active time DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V SCLK active edge to data valid delay 4 DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V Bus relinquish time after CS inactive edge 0 30 25 0 ns min ns min ns min ns min CS falling edge to SCLK active edge setup time4 Data valid to SCLK edge setup time Data valid to SCLK edge hold time CS rising edge to SCLK edge hold time SCLK inactive edge to CS inactive edge SCLK inactive edge to DOUT/RDY high 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. See Figure 3 and Figure 4. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once. 2 CIRCUIT AND TIMING DIAGRAMS ISINK (1.6mA WITH DVDD = 5V, 100µA WITH DVDD = 3V) TO OUTPUT PIN 1.6V ISOURCE (200µA WITH DVDD = 5V, 100µA WITH DVDD = 3V) Figure 2. Load Circuit for Timing Characterization Rev. A | Page 7 of 40 07822-002 50pF AD7192 CS (I) t6 t1 t5 MSB DOUT/RDY (O) LSB t7 t2 t3 07822-003 SCLK (I) t4 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t11 t8 SCLK (I) t9 t10 MSB LSB I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev. A | Page 8 of 40 07822-004 DIN (I) AD7192 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 3. Parameter AVDD to AGND DVDD to AGND AGND to DGND Analog Input Voltage to AGND Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND AIN/Digital Input Current Operating Temperature Range Rating −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.3 V 10 mA −40°C to +105°C Storage Temperature Range Maximum Junction Temperature Lead Temperature, Soldering Reflow −65°C to +150°C 150°C θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 24-Lead TSSOP ESD CAUTION 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 9 of 40 θJA 128 θJC 42 Unit °C/W AD7192 MCLK1 1 24 DIN MCLK2 2 23 DOUT/RDY SCLK 3 22 SYNC CS 4 AD7192 21 DVDD P3 5 TOP VIEW (Not to Scale) 20 AVDD P2 6 19 DGND P1/REFIN2(+) 7 18 AGND P0/REFIN2(–) 8 17 BPDSW NC 9 16 REFIN1(–) AINCOM 10 15 REFIN1(+) AIN1 11 14 AIN4 AIN2 12 13 AIN3 NC = NO CONNECT 07822-005 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 Mnemonic MCLK1 2 MCLK2 3 SCLK 4 CS 5 6 7 P3 P2 P1/REFIN2(+) 8 P0/REFIN2(−) 9 10 11 NC AINCOM AIN1 12 AIN2 Description When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2. Master Clock Signal for the Device. The AD7192 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7192 can be provided externally also in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and the MCLK1 pin left unconnected. Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitttriggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information transmitted to or from the ADC in smaller batches of data. Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND. Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND. Digital Output Pin/Positive Reference Input. This pin functions as a general-purpose output bit referenced between AVDD and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as REFIN2(+). An external reference can be applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN2(+) − REFIN2(−)), is AVDD, but the part functions with a reference from 1 V to AVDD. Digital Output Pin/Negative Reference Input. This pin functions as a general-purpose output bit referenced between AVDD and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as REFIN2(−). This reference input can lie anywhere between AGND and AVDD − 1 V. No Connect. This pin should be tied to AGND. Analog inputs AIN1 to AIN4 are referenced to this input when configured for pseudodifferential operation. Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN2 or as a pseudodifferential input when used with AINCOM. Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN1 or as a pseudodifferential input when used with AINCOM. Rev. A | Page 10 of 40 AD7192 Pin No. 13 Mnemonic AIN3 14 AIN4 15 REFIN1(+) 16 17 18 19 20 REFIN1(−) BPDSW AGND DGND AVDD 21 DVDD 22 SYNC 23 DOUT/RDY 24 DIN Description Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN4 or as a pseudodifferential input when used with AINCOM. Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN3 or as a pseudodifferential input when used with AINCOM. Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+) can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN1(+) − REFIN1(−)), is AVDD, but the part functions with a reference from 1 V to AVDD. Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V. Bridge Power-Down Switch to AGND. Analog Ground Reference Point. Digital Ground Reference Point. Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore, DVDD can be operated at 3 V with AVDD at 5 V or vice versa. Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, AVDD can be operated at 3 V with DVDD at 5 V or vice versa. Logic input that allows for synchronization of the digital filters and analog modulators when using a number of AD7192 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor internally to DVDD. Serial Data Output/Data Ready Output. DOUT/RDYserves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data-/control-word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register selection bits of the communications register identifying the appropriate register. Rev. A | Page 11 of 40 AD7192 45 8,388,882 40 8,388,880 35 8,388,878 30 8,388,876 8,388,874 25 20 8,388,872 15 8,388,870 10 8,388,868 5 8,388,866 0 200 400 600 800 1000 SAMPLE 0 8,388,850 8,388,870 8,388,890 8,388,910 07822-009 OCCURRENCE 8,388,884 07822-006 CODE TYPICAL PERFORMANCE CHARACTERISTICS 8,388,930 CODE Figure 9. Noise Distribution Histogram (VREF = AVDD = 5 V, Output Data Rate = 2400 Hz, Gain = 1, Chop Disabled, Sinc4 Filter) Figure 6. Noise (VREF = AVDD = 5 V, Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4 Filter) 8,389,050 200 8,389,000 8,388,950 8,388,900 CODE OCCURRENCE 150 100 8,388,850 8,388,800 8,388,750 50 8,388,869 8,388,873 8,388,877 8,388,881 8,388,650 07822-007 0 8,388,865 8,388,885 CODE 0 200 400 600 800 1000 SAMPLE Figure 10. Noise (VREF = AVDD = 5 V, Output Data Rate = 2400 Hz, Gain = 128, Chop Disabled, Sinc4 Filter) Figure 7. Noise Distribution Histogram (VREF = AVDD = 5 V, Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4 Filter) 15 8,388,940 8,388,930 8,388,920 OCCURRENCE 8,388,910 8,388,890 8,388,880 10 5 8,388,870 8,388,860 8,388,840 0 200 400 600 800 1000 SAMPLE Figure 8. Noise (VREF = AVDD = 5 V, Output Data Rate = 2400 Hz, Gain = 1, Chop Disabled, Sinc4 Filter) 0 8,388,740 8,388,800 8,388,860 8,388,920 CODE 8,388,980 8,389,040 07822-011 8,388,850 07822-008 CODE 8,388,900 Figure 11. Noise Distribution Histogram (VREF = AVDD = 5 V, Output Data Rate = 2400 Hz, Gain = 128, Chop Disabled, Sinc4 Filter) Rev. A | Page 12 of 40 07822-010 8,388,700 AD7192 0.4 5 0.2 4 0 –0.2 OFFSET (µV) INL (ppm of FSR) 3 2 1 –0.4 –0.6 –0.8 0 –1.0 –1 –2 –1 0 1 2 3 4 VIN (V) –1.4 –60 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 12. INL (Gain = 1) 07822-115 –3 07822-112 –2 –4 –1.2 Figure 15. Offset Error (Gain = 128, Chop Disabled) 20 1.000008 15 1.000006 1.000004 1.000002 5 1.000000 GAIN INL (ppm of FSR) 10 0 0.999998 0.999996 –5 0.999994 –10 0.999992 –15 –0.01 0 0.01 0.02 0.03 VIN (V) 0.999988 –60 –40 128.002 166 128.000 164 127.998 GAIN 168 162 127.994 158 127.992 156 127.990 0 20 40 60 40 60 80 100 120 80 100 120 127.996 160 80 100 TEMPERATURE (°C) 120 07822-114 OFFSET (µV) 128.004 –20 20 Figure 16. Gain Error (Gain = 1) 170 –40 0 TEMPERATURE (°C) Figure 13. INL (Gain = 128) 154 –60 –20 127.988 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) Figure 17. Gain Error (Gain = 128) Figure 14. Offset Error (Gain = 1, Chop Disabled) Rev. A | Page 13 of 40 07822-117 –0.02 07822-116 0.999990 07822-113 –20 –0.03 AD7192 RMS NOISE AND RESOLUTION The AD7192 has a choice of two filter types: sinc4 and sinc3. In addition, the AD7192 can be operated with chop enabled or chop disabled. The following tables show the rms noise of the AD7192 for some of the output data rates and gain settings with chop disabled and enabled for the sinc4 and sinc3 filters. The numbers given are for the bipolar input range with the external 5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V when the ADC is continuously converting on a single channel. The effective resolution is also shown, and the output peak-to-peak (p-p) resolution, or noise-free resolution, is listed in parentheses. It is important to note that the effective resolution is calculated using the rms noise, whereas the p-p resolution is calculated based on peak-to-peak noise. The p-p resolution represents the resolution for which there is no code flicker. These numbers are typical and are rounded to the nearest ½ LSB. SINC4 CHOP DISABLED Table 6. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 120 150 300 960 2400 4800 Settling Time (ms) 852.5 533 400 80 66.7 33.3 26.7 13.3 4.17 1.67 0.83 Gain of 1 350 425 490 2000 2100 2400 2500 3100 4800 7500 16,300 Gain of 8 50 62 85 260 273 315 335 420 690 1100 2200 Gain of 16 30 36 43 134 139 175 185 240 390 640 1200 Gain of 32 18 21 23 73 77 95 110 145 240 390 670 Gain of 64 13 15 17 46 48 64 71 95 170 273 427 Gain of 128 11 13 15 34 38 51 58 81 145 235 345 Table 7. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 120 150 300 960 2400 4800 Settling Time (ms) 852.5 533 400 80 66.7 33.3 26.7 13.3 4.17 1.67 0.83 Gain of 1 1 24 (22) 24 (22) 24 (21.5) 22 (19.5) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 20.5 (18) 20 (17.5) 19 (16.5) Gain of 81 24 (22) 24 (21.5) 23.5 (21) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 21.5 (19) 20.5 (18) 20 (17.5) 19 (16.5) Gain of 161 24 (21.5) 24 (21.5) 23.5 (21) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 20.5 (18) 19.5 (17) 19 (16.5) The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. A | Page 14 of 40 Gain of 321 24 (21.5) 23.5 (21) 23.5 (21) 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 21 (18.5) 20 (17.5) 19.5 (17) 18.5 (16) Gain of 641 23.5 (21) 23 (20.5) 23 (20.5) 21.5 (19) 21.5 (19) 21 (18.5) 21 (18.5) 20.5 (18) 19.5 (17) 19 (16.5) 18.5 (16) Gain of 1281 22.5 (20) 22.5 (20) 22 (19.5) 21 (18.5) 20.5 (18) 20.5 (18) 20 (17.5) 19.5 (17) 19 (16.5) 18 (15.5) 17.5 (15) AD7192 SINC3 CHOP DISABLED Table 8. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 120 150 300 960 2400 4800 Settling Time (ms) 639.4 400 300 60 50 25 20 10 3.13 1.25 0.625 Gain of 1 350 440 500 2000 2100 2400 2500 3100 5300 55800 446,000 Gain of 8 51 62 87 255 273 315 335 425 745 7100 55,400 Gain of 16 30 36 45 134 139 168 185 235 415 3600 28,000 Gain of 32 18 22 26 73 77 96 105 136 250 1750 14,000 Gain of 64 15 18 19 47 49 66 73 100 180 910 7000 Gain of 128 12 15 17 36 40 55 62 86 156 500 3500 Table 9. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 120 150 300 960 2400 4800 Settling Time (ms) 639.4 400 300 60 50 25 20 10 3.13 1.25 0.625 Gain of 1 1 24 (22) 24 (21.5) 24 (21.5) 22 (19.5) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 20.5 (18) 17 (14.5) 14 (11.5) Gain of 81 24 (22) 24 (21.5) 23.5 (21) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 21.5 (19) 20.5 (18) 17 (14.5) 14 (11.5) Gain of 161 24 (21.5) 24 (21.5) 23.5 (21) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 20.5 (18) 17 (14.5) 14 (11.5) The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. A | Page 15 of 40 Gain of 321 24 (21.5) 23.5 (21) 23.5 (21) 22 (19.5) 21.5 (19) 21.5 (19) 21.5 (19) 21 (18.5) 20 (17.5) 17 (14.5) 14 (11.5) Gain of 641 23 (20.5) 23 (20.5) 22.5 (20) 21.5 (19) 21.5 (19) 21 (18.5) 21 (18.5) 20.5 (18) 19.5 (17) 17 (14.5) 14 (11.5) Gain of 1281 22.5 (20) 22 (19.5) 22 (19.5) 21 (18.5) 20.5 (18) 20 (17.5) 20 (17.5) 19.5 (17) 18.5 (16) 17 (14.5) 14 (11.5) AD7192 SINC4 CHOP ENABLED Table 10. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 Output Data Rate (Hz) 1.175 1.875 2.5 12.5 15 30 37.5 75 240 600 1200 Settling Time (ms) 1702 1067 800 160 133 66.7 53.3 26.7 8.33 3.33 1.67 Gain of 1 248 301 347 1420 1490 1700 1770 2200 3400 5310 11,600 Gain of 8 36 44 61 184 194 223 237 297 488 780 1560 Gain of 16 22 26 31 95 99 124 131 170 276 453 849 Gain of 32 13 15 17 52 55 68 78 103 170 276 474 Gain of 64 9 11 13 33 34 46 51 68 121 194 302 Gain of 128 8 10 11 25 27 37 42 58 103 167 244 Gain of 641 24 (21.5) 23.5 (21) 23.5 (21) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 20 (17.5) 19.5 (17) 19 (16.5) Gain of 1281 23 (20.5) 23 (20.5) 22.5 (20) 21.5 (19) 21 (18.5) 21 (18.5) 20.5 (18) 20 (17.5) 19.5 (17) 18.5 (16) 18 (15.5) Table 11. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 1 Output Data Rate (Hz) 1.175 1.875 2.5 12.5 15 30 37.5 75 240 600 1200 Settling Time (ms) 1702 1067 800 160 133 66.7 53.3 26.7 8.33 3.33 1.67 Gain of 1 1 24 (22.5) 24 (22.5) 24 (22) 22.5 (20) 22.5 (20) 22.5 (20) 22 (19.5) 22 (19.5) 21 (18.5) 20.5 (18) 19.5 (17) Gain of 81 24 (22.5) 24 (22) 24 (21.5) 22.5 (20) 22.5 (20) 22 (19.5) 22 (19.5) 22 (19.5) 21 (18.5) 20.5 (18) 19.5 (17) Gain of 161 24 (22) 24 (22) 24 (21.5) 22.5 (20) 22.5 (20) 22 (19.5) 22 (19.5) 21.5 (19) 21 (18.5) 20 (17.5) 19.5 (17) The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. A | Page 16 of 40 Gain of 321 24 (22) 24 (21.5) 24 (21.5) 22.5 (20) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 20.5 (18) 20 (17.5) 19 (16.5) AD7192 SINC3 CHOP ENABLED Table 12. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 Output Data Rate (Hz) 1.56 2.5 3.33 16.6 20 40 50 100 320 800 1600 Settling Time (ms) 1282 800 600 120 100 50 40 20 6.25 2.5 1.25 Gain of 1 248 312 354 1415 1485 1698 1768 2193 3748 39500 315,400 Gain of 8 37 44 62 181 194 223 237 301 527 5020 39,200 Gain of 16 22 26 32 95 99 119 131 167 294 2546 19,800 Gain of 32 13 16 19 52 55 68 75 97 177 1240 9900 Gain of 64 11 13 14 34 35 47 52 71 128 644 4950 Gain of 128 9 11 13 26 29 39 44 61 111 354 2500 Table 13. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 1 Output Data Rate (Hz) 1.56 2.5 3.33 16.6 20 40 320 100 320 800 1600 Settling Time (ms) 1282 800 600 120 100 50 40 20 6.25 2.5 1.25 Gain of 1 1 24 (22.5) 24 (22) 24 (22) 22.5 (20) 22.5 (20) 22.5 (20) 22 (19.5) 22(19.5) 21 (18.5) 17.5 (15) 14.5 (12) Gain of 81 24 (22.5) 24 (22) 24 (21.5) 22.5 (20) 22.5 (20) 22 (19.5) 22 (19.5) 22 (19.5) 20.5 (18) 17.5 (15) 14.5 (12) Gain of 161 24 (22) 24 (22) 24 (21.5) 22.5 (20) 22.5 (20) 22 (19.5) 22 (19.5) 21.5 (19) 20.5 (18) 17.5 (15) 14.5 (12) The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. A | Page 17 of 40 Gain of 321 24 (22) 24 (21.5) 24 (21.5) 22.5 (20) 22 (19.5) 22 (19.5) 22 (19.5) 21.5 (19) 20 (17.5) 17.5 (15) 14.5 (12) Gain of 641 23.5 (21) 23.5 (21) 23 (20.5) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 19.5 (17) 17.5 (15) 14.5 (12) Gain of 1281 23 (20.5) 22.5 (20) 22.5 (20) 21.5 (19) 21 (18.5) 20.5 (18) 20.5 (18) 20 (17.5) 18.5 (16) 17.5 (15) 14.5 (12) AD7192 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers that are described on the following pages. In the following descriptions, “set” implies a Logic 1 state and “cleared” implies a Logic 0 state, unless otherwise noted. COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0) The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determines whether the next operation is a read or write operation and in which register this operation takes place. For read or write operations, when the subsequent read CR7 WEN(0) CR6 R/W(0) CR5 RS2(0) CR4 RS1(0) or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications register. In situations where the interface sequence is lost, a write operation of at least 40 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 14 outlines the bit designations for the communications register. CR0 through CR7 indicate the bit location, CR denoting that the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. CR3 RS0(0) CR2 CREAD(0) CR1 0(0) CR0 0(0) Table 14. Communications Register Bit Designations Bit Location CR7 Bit Name WEN CR6 R/W CR5 to CR3 RS2 to RS0 CR2 CREAD CR1 to CR0 0 Description Write enable bit. A 0 must be written to this bit so that the write to the communications register actually occurs. If a 1 is the first bit written, the part does not clock on to subsequent bits in the register. It stays at this bit location until a 0 is written to this bit. After a 0 is written to the WEN bit, the next seven bits are loaded to the communications register. Idling the DIN pin high between data transfers minimizes the effects of spurious SCLK pulses on the serial interface. A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position indicates that the next operation is a read from the designated register. Register address bits. These address bits are used to select which registers of the ADC are selected during the serial interface communication (see Table 15). Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read; that is, the contents of the data register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin goes low to indicate that a conversion is complete. The communications register does not have to be written to for subsequent data reads. To enable continuous read, the Instruction 01011100 must be written to the communications register. To disable continuous read, the Instruction 01011000 must be written to the communications register while the RDY pin is low. While continuous read is enabled, the ADC monitors activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset occurs if 40 consecutive 1s are seen on DIN. Therefore, DIN should be held low until an instruction is to be written to the device. These bits must be programmed to Logic 0 for correct operation. Table 15. Register Selection RS2 0 0 0 0 0 1 1 1 1 RS1 0 0 0 1 1 0 0 1 1 RS0 0 0 1 0 1 0 1 0 1 Register Communications register during a write operation Status register during a read operation Mode register Configuration register Data register/data register plus status information ID register GPOCON register Offset register Full-scale register Rev. A | Page 18 of 40 Register Size 8 bits 8 bits 24 bits 24 bits 24 bits/32 bits 8 bits 8 bits 24 bits 24 bits AD7192 STATUS REGISTER (RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 16 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting that the bits are in the status register. SR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. SR7 RDY(1) SR6 ERR(0) SR5 NOREF(0) SR4 PARITY(0) SR3 0(0) SR2 CHD2(0) SR1 CHD1(0) SR0 CHD0(0) Table 16. Status Register Bit Designations Bit Location SR7 Bit Name RDY SR6 ERR SR5 NOREF SR4 PARITY SR3 SR2 to SR0 0 CHD2 to CHD0 Description Ready bit for the ADC. This bit is cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register is read, or a period of time before the data register is updated, with a new conversion result to indicate to the user that the conversion data should not be read. It is also set when the part is placed in power-down mode or idle mode or when SYNC is taken low. The end of a conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. ADC error bit. This bit is written to at the same time as the RDY bit. This bit is set to indicate that the result written to the ADC data register is clamped to all 0s or all 1s. Error sources include overrange or underrange or the absence of a reference voltage. This bit is cleared when the result written to the data register is within the allowed analog input range again. No external reference bit. This bit is set to indicate that the selected reference (REFIN1 or REFIN2) is at a voltage that is below a specified threshold. When set, conversion results are clamped to all 1s. This bit is cleared to indicate that a valid reference is applied to the selected reference pins. The NOREF bit is enabled by setting the REFDET bit in the configuration register to 1. Parity check of the data register. If the ENPAR bit in the mode register is set, the PARITY bit is set if there is an odd number of 1s in the data register. It is cleared if there is an even number of 1s in the data register. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read. This bit is set to 0. These bits indicate which channel corresponds to the data register contents. They do not indicate which channel is presently being converted but indicate which channel was selected when the conversion contained in the data register was generated. MODE REGISTER (RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x080060) The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the operating mode, the output data rate, and the clock source. Table 17 outlines the bit designations for the mode register. MR0 through MR23 indicate the bit locations, MR denoting that the bits are in the mode register. MR23 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. Any write to the mode register resets the modulator and filter and sets the RDY bit. MR23 MD2(0) MR15 SINC3(0) MR7 FS7(0) MR22 MD1(0) MR14 0 MR6 FS6(1) MR21 MD0(0) MR13 ENPAR(0) MR5 FS5(1) MR20 DAT_STA(0) MR12 CLK_DIV(0) MR4 FS4(0) MR19 CLK1(1) MR11 SINGLE(0) MR3 FS3(0) Rev. A | Page 19 of 40 MR18 CLK0(0) MR10 REJ60(0) MR2 FS2(0) MR17 0 MR9 FS9(0) MR1 FS1(0) MR16 0 MR8 FS8(0) MR0 FS0(0) AD7192 Table 17. Mode Register Bit Designations Bit Location MR23 to MR21 MR20 Bit Name MD2 to MD0 DAT_STA MR19, MR18 CLK1, CLK0 MR17, MR16 MR15 0 SINC3 MR14 MR13 0 ENPAR MR12 CLK_DIV MR11 SINGLE MR10 REJ60 MR9 to MR0 FS9 to FS0 Description Mode select bits. These bits select the operating mode of the AD7192 (see Table 18). This bit enables the transmission of status register contents after each data register read. When DAT_STA is set, the contents of the status register are transmitted along with each data register read. This function is useful when several channels are selected because the status register identifies the channel to which the data register value corresponds. These bits are used to select the clock source for the AD7192. Either the on-chip 4.92 MHz clock or an external clock can be used. The ability to use an external clock allows several AD7192 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7192. CLK1 CLK0 ADC Clock Source 0 0 External crystal. The external crystal is connected from MCLK1 to MCLK2. 0 1 External clock. The external clock is applied to the MCLK2 pin. 1 0 Internal 4.92 MHz clock. Pin MCLK2 is tristated. 1 1 Internal 4.92 MHz clock. The internal clock is available on MCLK2. These bits must be programmed with a Logic 0 for correct operation. Sinc3 filter select bit. When this bit is cleared, the sinc4 filter is used (default value). When this bit is set, the sinc3 filter is used. The benefit of the sinc3 filter compared to the sinc4 filter is its lower settling time. For a given output data rate, fADC, the sinc3 filter has a settling time of 3/fADC while the sinc4 filter has a settling time of 4/fADC when chop is disabled. The sinc4 filter, due to its deeper notches, gives better 50 Hz/60 Hz rejection. At low output data rates, both filters give similar rms noise and similar no missing codes for a given output data rate. At higher output data rates (FS values less than 5), the sinc4 filter gives better performance than the sinc3 filter for rms noise and no missing codes. This bit must be programmed with a Logic 0 for correct operation. Enable parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read. Clock Divide by 2. When CLK_DIV is set, the master clock is divided by 2. For normal conversions, this bit should be set to 0. When performing internal full-scale calibrations, this bit must be set when AVDD is less than 4.75 V. The calibration accuracy is optimized when chop is enabled and a low output data rate is used while performing the calibration. When AVDD is greater than or equal to 4.75 V, it is not compulsory to set the CLK_DIV bit when performing internal full-scale calibrations. Single cycle conversion enable bit. When this bit is set, the AD7192 settles in one conversion cycle so that it functions as a zero-latency ADC. This bit has no effect when multiple analog input channels are enabled or when the single conversion mode is selected. This bit enables a notch at 60 Hz when the first notch of the sinc filter is at 50 Hz. When REJ60 is set, a filter notch is placed at 60 Hz when the sinc filter first notch is at 50 Hz. This allows simultaneous 50 Hz/ 60 Hz rejection. Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter cut-off frequency, the position of the first notch of the filter, and the output data rate for the part. In association with the gain selection, they also determine the output noise (and, therefore, the effective resolution) of the device (see Table 6 through Table 13). When chop is disabled and continuous conversion mode is selected, Output Data Rate = (MCLK/1024)/FS where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023, and MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in an output data rate from 4.69 Hz to 4.8 kHz. With chop disabled, the first notch frequency is equal to the output data rate when converting on a single channel. When chop is enabled, Output Data Rate = (MCLK/1024)/(N x FS) where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023, and MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in a conversion rate from 4.69/N Hz to 4.8/N kHz, where N is the order of the sinc filter. The sinc filter’s first notch frequency is equal to N × output data rate. The chopping introduces notches at odd integer multiples of (output data rate/2). Rev. A | Page 20 of 40 AD7192 Table 18. Operating Modes MD2 0 MD1 0 MD0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Mode Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. The DOUT/RDY pin and the RDY bit in the status register go low when a conversion is complete. The user can read these conversions by setting the CREAD bit in the communications register to 1, which enables continuous read. When continuous read is enabled, the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output each conversion by writing to the communications register. After power-on, a reset, or a reconfiguration of the ADC, the complete settling time of the filter is required to generate the first valid conversion. Subsequent conversions are available at the selected output data rate, which is dependent on filter choice. Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single conversion on the selected channel. The internal clock requires up to 1 ms to power up and settle. The ADC then performs the conversion, which requires the complete settling time of the filter. The conversion result is placed in the data register. RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register until another conversion is performed. RDY remains active (low) until the data is read or another conversion is performed. Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks are still provided. Power-down mode. In power-down mode, all AD7192 circuitry, except the bridge power-down switch, is powered down. The bridge power-down switch remains active because the user may need to power up the sensor prior to powering up the AD7192 for settling reasons. The external crystal, if selected, remains active. Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. Internal full-scale calibration. A full-scale input voltage is automatically connected to the input for this calibration. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed to minimize the fullscale error. When AVDD is less than 4.75 V, the CLK_DIV bit must be set when performing the internal full-scale calibration. System zero-scale calibration. The user should connect the system zero-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is required each time the gain of a channel is changed. System full-scale calibration. The user should connect the system full-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed. CONFIGURATION REGISTER (RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x000117) The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the gain, and to select the analog input channel. Table 19 outlines the bit designations for the filter register. CON0 through CON23 indicate the bit locations. CON denotes that the bits are in the configuration register. CON23 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. CON23 CHOP(0) CON15 CH7(0) CON7 BURN(0) CON22 0(0) CON14 CH6(0) CON6 REFDET(0) CON21 0(0) CON13 CH5(0) CON5 0(0) CON20 REFSEL(0) CON12 CH4(0) CON4 BUF(1) CON19 0(0) CON11 CH3(0) CON3 U/B (0) Rev. A | Page 21 of 40 CON18 0(0) CON10 CH2(0) CON2 G2(1) CON17 0(0) CON9 CH1(0) CON1 G1(1) CON16 (0) CON8 CH0(1) CON0 G0(1) AD7192 Table 19. Configuration Register Bit Designations Bit Location CON23 Bit Name CHOP CON22, CON21 CON20 0 REFSEL CON19 to CON16 CON15 to CON8 0 CH7 to CH0 CON7 BURN CON6 REFDET CON5 CON4 0 BUF CON3 U/B CON2 to CON0 G2 to G0 Description Chop enable bit. When the CHOP bit is cleared, chop is disabled. When the CHOP bit is set, chop is enabled. When chop is enabled, the offset and offset drift of the ADC are continuously removed. However, this increases the conversion time and settling time of the ADC. For example, when FS = 96 decimal and the sinc4 filter is selected, the conversion time with chop enabled equals 80 ms and the settling time equals 160 ms. With chop disabled, higher conversion rates are allowed. For an FS word of 96 decimal and the sinc4 filter selected, the conversion time is 20 ms and the settling time is 80 ms. However, at low gains, periodic calibrations may be required to remove the offset and offset drift. These bits must be programmed with a Logic 0 for correct operation. Reference select bits. The reference source for the ADC is selected using these bits. REFSEL Reference Voltage 0 External reference applied between REFIN1(+) and REFIN1(−). 1 External reference applied between the P1/REFIN2(+) and P0/REFIN2(−) pins. These bits must be programmed with a Logic 0 for correct operation. Channel select bits. These bits are used to select which channels are enabled on the AD7192 (see Table 20). Several channels can be selected, and the AD7192 automatically sequences them. The conversion on each channel requires the complete settling time. When performing calibrations or when accessing the calibration registers, only one channel can be selected. When this bit is set to 1, the 500 nA current sources in the signal path are enabled. When BURN = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer is active and when chop is disabled. Enables the reference detect function. When set, the NOREF bit in the status register indicates when the external reference being used by the ADC is open circuit or less than 0.6 V maximum. The reference detect circuitry operates only when the ADC is active. This bit must be programmed with a Logic 0 for correct operation. Enables the buffer on the analog inputs. If cleared, the analog inputs are unbuffered, lowering the power consumption of the device. If this bit is set, the analog inputs are buffered, allowing the user to place source impedances on the front end without contributing gain errors to the system. With the buffer disabled, the voltage on the analog input pins can be from 50 mV below AGND to 50 mV above AVDD. When the buffer is enabled, it requires some headroom; therefore, the voltage on any input pin must be limited to 250 mV within the power supply rails. Polarity select bit. When this bit is set, unipolar operation is selected. When this bit is cleared, bipolar operation is selected. Gain select bits. These bits are written by the user to select the ADC input range as follows: G2 G1 G0 Gain ADC Input Range (5 V Reference) 0 0 0 1 ±5 V 0 0 1 Reserved 0 1 0 Reserved 0 1 1 8 ±625 mV 1 0 0 16 ±312.5 mV 1 0 1 32 ±156.2 mV 1 1 0 64 ±78.125 mV 1 1 1 128 ±39.06 mV Rev. A | Page 22 of 40 AD7192 Table 20. Channel Selection Channel Enable Bits in the Configuration Register CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 1 1 1 1 1 1 1 1 Channel Enabled Positive Input Negative Input AIN(+) AIN(−) AIN1 AIN2 AIN3 AIN4 Temperature sensor AIN2 AIN2 AIN1 AINCOM AIN2 AINCOM AIN3 AINCOM AIN4 AINCOM Status Register Bits CHD[2:0] 000 001 010 011 100 101 110 111 Calibration Register Pair 0 1 None 0 0 1 2 3 ID REGISTER DATA REGISTER (RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xX0) (RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x000000) The conversion result from the ADC is stored in this data register. This is a read-only, 24-bit register. On completion of a read operation from this register, the RDY pin/bit is set. When the DAT_STA bit in the mode register is set to 1, the contents of the status register are appended to each 24-bit conversion. This is advisable when several analog input channels are enabled because the three LSBs of the status register (CHD2 to CHD0) identify the channel from which the conversion originated. The identification number for the AD7192 is stored in the ID register. This is a read-only register. Rev. A | Page 23 of 40 AD7192 GPOCON REGISTER (RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00) The GPOCON register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable the general-purpose digital outputs. GP7 0(0) GP6 BPDSW(0) GP5 GP32EN(0) GP4 GP10EN(0) Table 21 outlines the bit designations for the GPOCON register. GP0 through GP7 indicate the bit locations. GP denotes that the bits are in the GPOCON register. GP7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. GP3 P3DAT(0) GP2 P2DAT(0) GP1 P1DAT(0) GP0 P0DAT(0) Table 21. Register Bit Designations Bit Location GP7 GP6 Bit Name 0 BPDSW GP5 GP32EN GP4 GP10EN GP3 P3DAT GP2 P2DAT GP1 P1DAT GP0 P0DAT Description This bit must be programmed with a Logic 0 for correct operation. Bridge power-down switch control bit. This bit is set by the user to close the bridge power-down switch BPDSW to AGND. The switch can sink up to 30 mA. The bit is cleared by the user to open the bridge power– down switch. When the ADC is placed in power-down mode, the bridge power-down switch remains active. Digital Output P3 and Digital Output P2 enable. When GP32EN is set, the P3 and P2 digital outputs are active. When GP32EN is cleared, the P3 and P2 pins are tristated, and the P3DAT and P2DAT bits are ignored. Digital Output P1 and Digital Output P0 enable. When GP10EN is set, the P1 and P0 digital outputs are active. When GP10EN is cleared, the P1 and P0 outputs are tristated, and the P1DAT and P0DAT bits are ignored. The P1 and P0 pins can be used as a reference input to REFIN2 when the REFSEL bit in the configuration register is set to 1. Digital Output P3. When GP32EN is set, the P3DAT bit sets the value of the P3 general-purpose output pin. When P3DAT is high, the P3 output pin is high. When P3DAT is low, the P3 output pin is low. When the GPOCON register is read, the P3DAT bit reflects the status of the P3 pin if GP32EN is set. Digital Output P2. When GP32EN is set, the P2DAT bit sets the value of the P2 general-purpose output pin. When P2DAT is high, the P2 output pin is high. When P2DAT is low, the P2 output pin is low. When the GPOCON register is read, the P2DAT bit reflects the status of the P2 pin if GP32EN is set. Digital Output P1. When GP10EN is set, the P1DAT bit sets the value of the P1 general-purpose output pin. When P1DAT is high, the P1 output pin is high. When P1DAT is low, the P1 output pin is low. When the GPOCON register is read, the P1DAT bit reflects the status of the P1 pin if GP10EN is set. Digital Output P0. When GP10EN is set, the P0DAT bit sets the value of the P0 general-purpose output pin. When P0DAT is high, the P0 output pin is high. When P0DAT is low, the P0 output pin is low. When the GPOCON register is read, the P0DAT bit reflects the status of the P0 pin if GP10EN is set. OFFSET REGISTER FULL-SCALE REGISTER (RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x800000) (RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXXX0) The offset register holds the offset calibration coefficient for the ADC. The power-on reset value of the offset register is 0x800000. The AD7192 has four offset registers; therefore, each channel has a dedicated offset register (see Table 20). Each of these registers is a 24-bit read/write register. This register is used in conjunction with its associated full-scale register to form a register pair. The power-on reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. The AD7192 must be placed in powerdown mode or idle mode when writing to the offset register. The full-scale register is a 24-bit register that holds the full-scale calibration coefficient for the ADC. The AD7192 has four fullscale registers; therefore, each channel has a dedicated full-scale register (see Table 20). The full-scale registers are read/write registers. However, when writing to the full-scale registers, the ADC must be placed in power-down mode or idle mode. These registers are configured at power-on with factory-calibrated full-scale calibration coefficients, the calibration being performed at gain = 1. Therefore, every device has different default coefficients. The default value is automatically overwritten if an internal or system full-scale calibration is initiated by the user or if the full-scale register is written to. Rev. A | Page 24 of 40 AD7192 ADC CIRCUIT INFORMATION 5V REFIN1(+) AGND IN+ OUT+ OUT– IN– AIN1 AIN2 AIN3 AIN4 AINCOM MUX DVDD DGND AVDD REFERENCE DETECT AVDD Σ-Δ ADC PGA DOUT/RDY SERIAL INTERFACE AND CONTROL LOGIC DIN SCLK CS SYNC AGND TEMP SENSOR REFIN1(–) P3 P2 BPDSW AD7192 CLOCK CIRCUITRY MCLK1 MCLK2 07822-012 AGND P0/REFIN2(–) P1/REFIN2(+) Figure 18. Basic Connection Diagram fADC = fCLK/(1024 × FS[9:0]) OVERVIEW The AD7192 is an ultralow noise ADC that incorporates a Σ-Δ modulator, a buffer, PGA, and on-chip digital filtering intended for the measurement of wide dynamic range signals such as those in pressure transducers, weigh scales, and strain gage applications. where: fADC is the output data rate. fCLK = master clock (4.92 MHz nominal). FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. The part can be configured to have two differential inputs or four pseudo differential inputs that can be buffered or unbuffered. Figure 18 shows the basic connections required to operate the part. The output data rate can be programmed from 4.7 Hz to 4800 Hz; that is, FS[9:0] can have a value from 1 to 1023. FILTER, OUTPUT DATA RATE, AND SETTLING TIME A Σ-Δ ADC consists of a modulator followed by a digital filter. The AD7192 has two filter options: a sinc3 filter and a sinc4 filter. The filter is selected using the SINC3 bit in the mode register. When the SINC3 bit is set to 0 (default value), the sinc4 filter is selected. The sinc3 filter is selected when the SINC3 bit is set to 1. The previous equation is valid for both the sinc3 and sinc4 filters. The settling time for the sinc4 filter is equal to tSETTLE = 4/fADC and the settling time for the sinc3 filter is equal to tSETTLE = 3/fADC Figure 19 and Figure 20 show the frequency response of the sinc4 filter and sinc3 filter, respectively, for an output data rate of 50 Hz. 0 At low output data rates (<1 kHz), the noise-free resolution is comparable for the two filter types. However, at the higher update rates, the sinc4 filter gives better noise-free resolution. –10 –20 The sinc filter also leads to better 50 Hz and 60 Hz rejection. While the notch positions are not affected by the order of the filter, the higher order filter has wider notches, which leads to better rejection in the band (±1 Hz) around the notches. It also gives better stop-band attenuation. The benefit of the sinc3 filter is its lower settling time for the same output data rate. FILTER GAIN (dB) 4 –30 –40 –50 –60 –70 –80 Chop Disabled –100 0 25 50 75 100 125 FREQUENCY (Hz) Figure 19. Sinc4 Filter Response (50 Hz Output Data Rate) Rev. A | Page 25 of 40 150 07822-013 –90 The output data rate (the rate at which conversions are available on a single channel when the ADC is continuously converting) is equal to AD7192 0 The value of FS[9:0] can be varied from 1 to 1023. This results in an output data rate of 1.173 Hz to 1200 Hz for the sinc4 filter and 1.56 Hz to 1600 Hz for the sinc3 filter. The settling time for sinc3 or sinc4 is equal to –10 –30 tSETTLE = 2/fADC –40 Therefore, with chop enabled, the settling time is reduced for a given output data rate compared to the chop disabled mode. However, for a given FS[9:0] value, the output data rate is less with chop enabled when compared with the chop disabled mode. For either the sinc3 or sinc4 filter, the cutoff frequency f3dB is equal to –50 –60 –70 –80 25 50 75 100 125 150 FREQUENCY (Hz) Figure 20. Sinc3 Filter Response (50 Hz Output Data Rate) The sinc4 filter provides 50 Hz (±1 Hz) rejection in excess of 120 dB, assuming a stable master clock, and the sinc3 filter gives a rejection of 100 dB. The stop-band attenuation is, typically, 53 dB for the sinc4 filter but equal to 40 dB for the sinc3 filter. f3dB = 0.24 × fADC Figure 21 and Figure 22 show the filter response for the sinc4 filter and sinc3 filter, respectively, when chop is enabled. As shown in the plots, the stop-band attenuation is less when compared with the chop disabled modes. 0 –10 The 3 dB frequency for the sinc4 filter is equal to –20 FILTER GAIN (dB) f3dB = 0.23 × fADC and for the sinc filter, the 3 dB frequency is equal to f3dB = 0.272 × fADC Chop Enabled With chop enabled, the ADC offset and offset drift are minimized. When chop is enabled, the analog input pins are continuously swapped. Therefore, with the analog input pins connected in one direction, the settling time of the sinc filter is allowed to elapse until a valid conversion is available. The analog input pins are then inverted, and another valid conversion is obtained. Subsequent conversions are then averaged so that the offset is minimized. This continuous swapping of the analog input pins and the averaging of subsequent conversions means that the offset drift is also minimized. Chopping affects the output data rate and settling time of the ADC. For sinc4, the output data rate is equal to fADC = fCLK/(4 × 1024 × FS[9:0]) For sinc3, the output data rate is equal to –40 –50 –60 –80 –90 –100 0 25 50 75 100 125 150 FREQUENCY (Hz) Figure 21. Sinc4 Filter Response (Output Data Rate =12.5 Hz, Chop Enabled) 0 –10 –20 –30 –40 –50 –60 –70 fADC = fCLK/(3 × 1024 × FS[9:0]) where: fADC is the output data rate. fCLK = master clock (4.92 MHz nominal). FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. –30 –70 FILTER GAIN (dB) 3 07822-015 0 07822-014 –90 –100 –80 –90 –100 0 25 50 75 100 FREQUENCY (Hz) 125 150 07822-016 FILTER GAIN (dB) –20 Figure 22. Sinc3 Filter Response (Output Data Rate = 16.6 Hz, Chop Enabled) Rev. A | Page 26 of 40 AD7192 Normal mode rejection is one of the main functions of the digital filter. With chop disabled, 50 Hz rejection is obtained when the output data rate is set to 50 Hz, and 60 Hz rejection is achieved when the output data rate is set to 60 Hz. Simultaneous 50 Hz and 60 Hz rejection is obtained when the output data rate is set to 10 Hz. Simultaneous 50 Hz/60 Hz rejection can also be achieved using the REJ60 bit in the mode register. When the output data rate is programmed to 50 Hz and the REJ60 bit is set to 1, notches are placed at both 50 Hz and 60 Hz. Figure 23 and Figure 24 show the frequency response of the sinc4 filter and sinc3 filter, respectively, when the output data rate is programmed to 50 Hz and REJ60 is set to 1. filter is used. Figure 25 and Figure 26 show the filter response for both output data rates when REJ60 is set to 1. 0 –10 –20 FILTER GAIN (dB) 50 Hz/60 Hz Rejection –30 –40 –50 –60 –70 –80 –90 –100 0 –10 25 50 75 100 125 150 FREQUENCY (Hz) –30 Figure 25. Sinc4 Filter Response (12.5 Hz Output Data Rate, Chop Enabled, REJ60 = 1) –40 0 –50 –10 –60 –20 –70 –30 –80 0 25 50 75 100 125 150 FREQUENCY (Hz) –40 –50 –60 –70 4 Figure 23. Sinc Filter Response (50 Hz Output Data Rate, REJ60=1) –80 0 –90 –10 –100 0 25 FILTER GAIN (dB) –20 50 75 100 125 150 FREQUENCY (Hz) 07822-126 –100 07822-017 –90 FILTER GAIN (dB) FILTER GAIN (dB) –20 07822-125 0 Figure 26. Sinc3 Filter Response (16.7 Hz Output Data Rate, Chop Enabled, REJ60 = 1) –30 –40 Zero Latency –50 Zero latency is enabled by setting the SINGLE bit in the mode register to 1. With zero latency, the complete settling time is allowed for each conversion. Therefore, –60 –70 –80 fADC = 1/tSETTLE –100 0 25 50 75 100 125 150 FREQUENCY (Hz) 07822-018 –90 Figure 24. Sinc3 Filter Response (50 Hz Output Data Rate, REJ60=1) Again, the sinc4 filter provides better 50 Hz/60 Hz rejection than the sinc3 filter. Also, better stop-band attenuation is achieved with the sinc4 filter. When chop is enabled, lower output data rates must be used to achieve 50 Hz and 60 Hz rejection. With REJ60 set to 1, an output data rate of 12.5 Hz gives simultaneous 50 Hz/60 Hz rejection when the sinc4 filter is selected, whereas an output data rate of 16.7 Hz gives simultaneous 50 Hz/60 Hz rejection when the sinc3 Zero latency means that the output data rate is constant irrespective of the number of analog input channels enabled; the user does not need to consider the effects of channel changes on the output data rate. The disadvantages of zero latency are the increased noise for a given output data rate compared with the nonzero latency mode. For example, when zero latency is not enabled, the AD7192 has a noise-free resolution of 18.5 bits when the output data rate is 50 Hz and the gain is set to 128. When zero latency is enabled, the ADC has a resolution of 17.5 bits peak-to-peak when the output data rate is 50 Hz. The filter response also changes. Figure 19 shows the filter response for the sinc4 filter when the output data rate is 50 Hz (zero latency disabled). Figure 27 shows the filter response when zero latency is enabled and the output data rate Rev. A | Page 27 of 40 AD7192 is 50 Hz (sinc4 filter); 50 Hz rejection is no longer achieved. The ADC must operate with an output data rate of 12.5 Hz to obtain 50 Hz rejection when zero latency is enabled. To obtain simultaneous 50 Hz/60 Hz rejection, the REJ60 bit in the mode register can be set when the output data rate is equal to 12.5 Hz. The stop-band attenuation is considerably reduced also (3 dB compared with 53 dB in the nonzero latency mode). For example, if the sinc4 filter is selected, chop is disabled, and zero latency is disabled, the settling time for each channel is equal to tSETTLE = 4/fADC where fADC is the output data rate when continuously converting on a single channel. The time required to sample N channels is 4/(fADC × N) 0 –10 RDY –20 CHANNEL A –40 CHANNEL B 1/fADC CHANNEL C 07822-019 FILTER GAIN (dB) CONVERSIONS –30 Figure 28. Channel Sequencer –50 –60 DIGITAL INTERFACE –70 As indicated in the On-Chip Registers section, the programmable functions of the AD7192 are controlled using a set of on-chip registers. Data is written to these registers via the serial interface of the part. Read access to the on-chip registers is also provided by this interface. All communication with the part must start with a write to the communications register. After power-on or reset, the device expects a write to its communications register. The data written to this register determines whether the next operation is a read operation or a write operation and also determines to which register this read or write operation occurs. Therefore, write access to any of the other registers on the part begins with a write operation to the communications register, followed by a write to the selected register. A read operation from any other register (except when continuous read mode is selected) starts with a write to the communications register, followed by a read operation from the selected register. –80 0 50 100 150 200 250 300 350 400 450 500 550 600 FREQUENCY (Hz) 07822-020 –90 –100 Figure 27. Sinc4 Filter Response (50 Hz Output Data Rate, Zero Latency) Channel Sequencer The AD7192 includes a channel sequencer, which simplifies communications with the device in multichannel applications. The sequencer also optimizes the channel throughput of the device because the sequencer switches channels at the optimum rate rather than waiting for instructions via the SPI interface. Bit CH0 to Bit CH7 in the configuration register are used to enable the required channels. In continuous conversion mode, the ADC selects each of the enabled channels in sequence and performs a conversion on the channel. The RDY pin goes low when a valid conversion is available on each channel. When several channels are enabled, the contents of the status register should be attached to the 24-bit word so that the user can identify the channel that corresponds to each conversion. To attach the status register value to the conversion, Bit DAT_STA in the mode register should be set to 1. When several channels are enabled, the ADC must allow the complete settling time to generate a valid conversion each time that the channel is changed. The AD7192 takes care of this: when a channel is selected, the modulator and filter are reset and the RDY pin is taken high. The AD7192 then allows the complete settling time to generate the first conversion. RDY goes low only when a valid conversion is available. The AD7192 then selects the next enabled channel and converts on that channel. The user can then read the data register while the ADC is performing the conversion on the next channel. The time required to read a valid conversion from all enabled channels is equal to tSETTLE × number of enabled channels The serial interface of the AD7192 consists of four signals: CS, DIN, SCLK, and DOUT/RDY. The DIN line is used to transfer data into the on-chip registers, and DOUT/RDY is used for accessing data from the on-chip registers. SCLK is the serial clock input for the device, and all data transfers (either on DIN or DOUT/RDY) occur with respect to the SCLK signal. The DOUT/RDY pin functions as a data ready signal also, the line going low when a new data-word is available in the output register. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the data register to indicate when not to read from the device, to ensure that a data read is not attempted while the register is being updated. CS is used to select a device. It can be used to decode the AD7192 in systems where several components are connected to the serial bus. Figure 3 and Figure 4 show timing diagrams for interfacing to the AD7192, with CS being used to decode the part. Figure 3 shows the timing for a read operation from the output shift register of the AD7192, and Figure 4 shows the timing for a write operation to the input shift register. It is possible to read the same word from the data register several times even though the DOUT/RDY Rev. A | Page 28 of 40 AD7192 line returns high after the first read operation. However, care must be taken to ensure that the read operations are completed before the next output update occurs. In continuous read mode, the data register can be read only once. The serial interface can operate in 3-wire mode by tying CS low. In this case, the SCLK, DIN, and DOUT/RDY lines are used to communicate with the AD7192. The end of the conversion can be monitored using the RDY bit or pin. This scheme is suitable for interfacing to microcontrollers. If CS is required as a decoding signal, it can be generated from a port pin. For microcontroller interfaces, it is recommended that SCLK idle high between data transfers. The AD7192 can be operated with CS used as a frame synchronization signal. This scheme is useful for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS because CS normally occurs after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers, provided the timing numbers are obeyed. The serial interface can be reset by writing a series of 1s to the DIN input. If a Logic 1 is written to the AD7192 DIN line for at least 40 serial clock cycles, the serial interface is reset. This ensures that the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system. Reset returns the interface to the state in which it expects a write to the communications register. This operation resets the contents of all registers to their power-on values. Following a reset, the user should allow a period of 500 μs before addressing the serial interface. The AD7192 can be configured to continuously convert or to perform a single conversion (see Figure 29 through Figure 31). Single Conversion Mode In single conversion mode, the AD7192 is placed in powerdown mode after conversions. When a single conversion is initiated by setting MD2, MD1, and MD0 to 0, 0, 1, respectively, in the mode register, the AD7192 powers up, performs a single conversion, and then returns to power-down mode. The onchip oscillator requires 1 ms, approximately, to power up. DOUT/RDY goes low to indicate the completion of a conversion. When the data-word has been read from the data register, DOUT/RDY goes high. If CS is low, DOUT/RDY remains high until another conversion is initiated and completed. The data register can be read several times, if required, even when DOUT/RDY has gone high. If several channels are enabled, the ADC sequences through the enabled channels and performs a conversion on each channel. When a conversion is started, DOUT/RDY goes high and remains high until a valid conversion is available. As soon as the conversion is available, DOUT/RDY goes low. The ADC then selects the next channel and begins a conversion. The user can read the present conversion while the next conversion is being performed. As soon as the next conversion is complete, the data register is updated; therefore, the user has a limited period in which to read the conversion. When the ADC has performed a single conversion on each of the selected channels, it returns to power-down mode. If the DAT_STA bit in the mode register is set to 1, the contents of the status register are output along with the conversion each time that the data read is performed. The four LSBs of the status register indicate the channel to which the conversion corresponds. CS 0x08 0x280060 0x58 DIN DATA 07822-021 DOUT/RDY SCLK Figure 29. Single Conversion Rev. A | Page 29 of 40 AD7192 Continuous Conversion Mode Continuous conversion is the default power-up mode. The AD7192 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete. If CS is low, the DOUT/RDY line also goes low when a conversion is completed. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. When the data-word has been read from the data register, DOUT/RDY goes high. The user can read this register additional times, if required. However, the user must ensure that the data register is not being accessed at the completion of the next conversion or else the new conversion word is lost. When several channels are enabled, the ADC continuously loops through the enabled channels, performing one conversion on each channel per loop. The data register is updated as soon as each conversion is available. The DOUT/RDY pin pulses low each time a conversion is available. The user can then read the conversion while the ADC converts on the next enabled channel. If the DAT_STA bit in the mode register is set to 1, the contents of the status register are output along with the conversion each time that the data read is performed. The status register indicates the channel to which the conversion corresponds. CS 0x58 0x58 DIN DATA DATA 07822-022 DOUT/RDY SCLK Figure 30. Continuous Conversion Rev. A | Page 30 of 40 AD7192 Continuous Read conversion is complete, and the new conversion is placed in the output serial register. Rather than write to the communications register each time a conversion is complete to access the data, the AD7192 can be configured so that the conversions are placed on the DOUT/ RDY line automatically. By writing 01011100 to the communications register, the user need only apply the appropriate number of SCLK cycles to the ADC, and the conversion word is automatically placed on the DOUT/RDY line when a conversion is complete. The ADC should be configured for continuous conversion mode. To exit the continuous read mode, the Instruction 01011000 must be written to the communications register while the RDY pin is low. While in the continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit the continuous read mode. Additionally, a reset occurs if 40 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device. When several channels are enabled, the ADC continuously steps through the enabled channels and performs one conversion on each channel each time that it is selected. DOUT/ RDY pulses low when a conversion is available. When the user applies sufficient SCLK pulses, the data is automatically placed on the DOUT/RDY pin. If the DAT_STA bit in the mode register is set to 1, the contents of the status register are output along with the conversion. The status register indicates the channel to which the conversion corresponds. When DOUT/RDY goes low to indicate the end of a conversion, sufficient SCLK cycles must be applied to the ADC; the data conversion is then placed on the DOUT/RDY line. When the conversion is read, DOUT/RDY returns high until the next conversion is available. In this mode, the data can be read only once. Also, the user must ensure that the data-word is read before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion, or if insufficient serial clocks are applied to the AD7192 to read the word, the serial output register is reset when the next CS 0x5C DIN DATA DATA DATA 07822-023 DOUT/RDY SCLK Figure 31. Continuous Read Rev. A | Page 31 of 40 AD7192 CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL The AD7192 has two differential/four pseudodifferential analog input channels, which can be buffered or unbuffered. In buffered mode (the BUF bit in the configuration register is set to 1), the input channel feeds into a high impedance input stage of the buffer amplifier. Therefore, the input can tolerate significant source impedances and is tailored for direct connection to external resistive-type sensors such as strain gages or resistance temperature detectors (RTDs). When BUF = 0, the part is operated in unbuffered mode. This results in a higher analog input current. Note that this unbuffered input path provides a dynamic load to the driving source. Therefore, resistor/capacitor combinations on the input pins can cause gain errors, depending on the output impedance of the source that is driving the ADC input. Table 22 shows the allowable external resistance/capacitance values for unbuffered mode at a gain of 1 such that no gain error at the 20-bit level is introduced. Table 22. External R-C Combination for No 20-Bit Gain Error C (pF) R (Ω) 50 1.4 k 100 850 500 300 1000 230 5000 30 The absolute input voltage range in buffered mode is restricted to a range between AGND + 250 mV and AVDD − 250 mV. Care must be taken in setting up the common-mode voltage so that these limits are not exceeded. Otherwise, there is degradation in linearity and noise performance. The absolute input voltage in unbuffered mode includes the range between AGND − 50 mV and AVDD + 50 mV. The negative absolute input voltage limit does allow the possibility of monitoring small true bipolar signals with respect to AGND. PROGRAMMABLE GAIN ARRAY (PGA) When the gain stage is enabled, the output from the buffer is applied to the input of the PGA. The presence of the PGA means that signals of small amplitude can be gained within the AD7192 while still maintaining excellent noise performance. For example, when the gain is set to 128, the rms noise is 11 nV, typically, when the output data rate is 4.7 Hz, which is equivalent to 22.5 bits of effective resolution or 20 bits of noise-free resolution. The AD7192 can be programmed to have a gain of 1, 8, 16, 32, 64, and 128 using Bit G2 to Bit G0 in the configuration register. Therefore, with an external 2.5 V reference, the unipolar ranges are from 0 mV to 19.53 mV to 0 V to 2.5 V and the bipolar ranges are from ±19.53 mV to ±2.5 V. The analog input range must be limited to ±(AVDD – 1.25 V)/gain because the PGA requires some headroom. Therefore, if AVDD = 5 V, the maximum analog input that can be applied to the AD7192 is 0 to 3.75 V/gain in unipolar mode or ±3.75 V/gain in bipolar mode. BIPOLAR/UNIPOLAR CONFIGURATION The analog input to the AD7192 can accept either unipolar or bipolar input voltage ranges. A bipolar input range does not imply that the part can tolerate negative voltages with respect to system AGND. In pseudo-differential mode, signals are referenced to AINCOM, while in differential mode, signals are referenced to the negative input of the differential pair. For example, if AINCOM is 2.5 V and the AD7192 AIN1 analog input is configured for unipolar mode with a gain of 2, the input voltage range on the AIN1 pin is 2.5 V to 3.75 V when a 2.5 V reference is used. If AINCOM is 2.5 V and the AD7192 AIN1 analog input is configured for bipolar mode with a gain of 2, the analog input range on AIN1 is 1.25 V to 3.75 V The bipolar/unipolar option is chosen by programming the U/B bit in the configuration register. DATA OUTPUT CODING When the ADC is configured for unipolar operation, the output code is natural (straight) binary with a zero differential input voltage resulting in a code of 00...00, a midscale voltage resulting in a code of 100...000, and a full-scale input voltage resulting in a code of 111...111. The output code for any analog input voltage can be represented as Code = (2N × AIN × Gain)/VREF When the ADC is configured for bipolar operation, the output code is offset binary with a negative full-scale voltage resulting in a code of 000...000, a zero differential input voltage resulting in a code of 100...000, and a positive full-scale input voltage resulting in a code of 111...111. The output code for any analog input voltage can be represented as Code = 2N – 1 × [(AIN × Gain/VREF) + 1] where AIN is the analog input voltage, Gain is the PGA setting (1 to 128), and N = 24. CLOCK The AD7192 includes an internal 4.92 MHz clock on-chip. This internal clock has a tolerance of ±4%. Either the internal clock or an external crystal/clock can be used as the clock source to the AD7192. The clock source is selected using the CLK1 and CLK0 bits in the mode register. When an external crystal is used, it must be connected across the MCLK1 and MCLK2 pins. The crystal manufacturer recommends the load capacitances required for the crystal. The MCLK1 and MCLK2 pins of the AD7192 have a capacitance of 15 pF, typically. If an external Rev. A | Page 32 of 40 AD7192 BURNOUT CURRENTS The common-mode range for these differential inputs is from AGND to AVDD. The reference input is unbuffered; therefore, excessive R-C source impedances introduce gain errors. The reference voltage REFIN (REFINx(+) − REFINx(−)) is AVDD nominal, but the AD7192 is functional with reference voltages from 1 V to AVDD. In applications where the excitation (voltage or current) for the transducer on the analog input also drives the reference voltage for the part, the effect of the low frequency noise in the excitation source is removed because the application is ratiometric. If the AD7192 is used in a nonratiometric application, a low noise reference should be used. The AD7192 contains two 500 nA constant current generators, one sourcing current from AVDD to AIN(+) and one sinking current from AIN(−) to AGND, where AIN(+) is the positive analog input terminal and AIN(−) is the negative analog input terminal in differential mode and AINCOM in pseudodifferential mode. The currents are switched to the selected analog input pair. Both currents are either on or off, depending on the burnout current enable (BURN) bit in the configuration register. Recommended 2.5 V reference voltage sources for the AD7192 include the ADR421 and ADR431, which are low noise references. These references have low output impedances and are, therefore, tolerant to having decoupling capacitors on REFINx(+) without introducing gain errors in the system. Deriving the reference input voltage across an external resistor means that the reference input sees a significant external source impedance. External decoupling on the REFINx pins is not recommended in this type of circuit configuration. These currents can be used to verify that an external transducer is still operational before attempting to take measurements on that channel. After the burnout currents are turned on, they flow in the external transducer circuit, and a measurement of the input voltage on the analog input channel can be taken. It takes some time for the burnout currents to detect an open circuit condition because the currents must charge any external capacitors. REFERENCE DETECT clock source is used, the clock source must be connected to the MCLK2 pin, and the MCLK1 pin can be left floating. The internal clock can also be made available at the MCLK2 pin. This is useful when several ADCs are used in an application and the devices must be synchronized. The internal clock from one device can be used as the clock source for all ADCs in the system. Using a common clock, the devices can be synchronized by applying a common reset to all devices, or the SYNC pin can be pulsed. There are several reasons that a fault condition is detected. The front-end sensor may be open circuit. It could also mean that the front-end sensor is overloaded or the reference may be absent and the NOREF bit in the status register is set, thus clamping the data to all 1s. The user must check these three cases before making a judgment. If the voltage measured is 0 V, it may indicate that the transducer has short circuited. The current sources work over the normal absolute input voltage range specifications when the analog inputs are buffered and chop is disabled. REFERENCE The ADC has a fully differential input capability for the reference channel. In addition, the user has the option of selecting one of two external reference options (REFIN1(x) or REFIN2(x)). The reference source for the AD7192 is selected using the REFSEL bit in the configuration register. The REFIN2(x) pins are dual purpose: they can function as two general-purpose output pins or as reference pins. When the REFSEL bit is set to 1, these pins automatically function as reference pins. The AD7192 includes on-chip circuitry to detect whether the part has a valid reference for conversions or calibrations. This feature is enabled when the REFDET bit in the configuration register is set to 1. If the voltage between the selected REFINx(+) and REFINx(−) pins is between 0.3 V and 0.6 V, the AD7192 detects that it no longer has a valid reference. In this case, the NOREF bit of the status register is set to 1. If the AD7192 is performing normal conversions and the NOREF bit becomes active, the conversion result is all 1s. Therefore, it is not necessary to continuously monitor the status of the NOREF bit when performing conversions. It is only necessary to verify its status if the conversion result read from the ADC data register is all 1s. If the AD7192 is performing either an offset or full-scale calibration and the NOREF bit becomes active, the updating of the respective calibration registers is inhibited to avoid loading incorrect coefficients to these registers, and the ERR bit in the status register is set. If the user is concerned about verifying that a valid reference is in place every time a calibration is performed, the status of the ERR bit should be checked at the end of the calibration cycle. Rev. A | Page 33 of 40 AD7192 RESET TEMPERATURE SENSOR The circuitry and serial interface of the AD7192 can be reset by writing consecutive 1s to the device; 40 consecutive 1s are required to perform the reset. This resets the logic, the digital filter, and the analog modulator, whereas all on-chip registers are reset to their default values. A reset is automatically performed on power-up. When a reset is initiated, the user must allow a period of 500 μs before accessing any of the onchip registers. A reset is useful if the serial interface loses synchronization due to noise on the SCLK line. Embedded in the AD7192 is a temperature sensor. This is selected using the CH2 bit in the configuration register. When the CH2 bit is set to 1, the temperature sensor is enabled. When the temperature sensor is selected and bipolar mode is selected, the device should return a code of 0x800000 when the temperature is 0 K. A one-point calibration is needed to get the optimum performance from the sensor. Therefore, a conversion at 25°C should be recorded and the sensitivity calculated. The sensitivity is 2815 codes/°C, approximately. The equation for the temperature sensor is SYSTEM SYNCHRONIZATION The SYNC input allows the user to reset the modulator and the digital filter without affecting any of the setup conditions on the part. This allows the user to start gathering samples of the analog input from a known point in time, that is, the rising edge of SYNC. SYNC needs to be taken low for at least four master clock cycles to implement the synchronization function. If multiple AD7192 devices are operated from a common master clock, they can be synchronized so that their data registers are updated simultaneously. A falling edge on the SYNC pin resets the digital filter and the analog modulator and places the AD7192 into a consistent, known state. While the SYNC pin is low, the AD7192 is maintained in this state. On the SYNC rising edge, the modulator and filter are taken out of this reset state and, on the next clock edge, the part starts to gather input samples again. In a system using multiple AD7192 devices, a common signal to their SYNC pins synchronizes their operation. This is normally done after each AD7192 has performed its own calibration or has calibration coefficients loaded into its calibration registers. The conversions from the AD7192s are then synchronized. The part is taken out of reset on the master clock falling edge following the SYNC low to high transition. Therefore, when multiple devices are being synchronized, the SYNC pin should be taken high on the master clock rising edge to ensure that all devices begin sampling on the master clock falling edge. If the SYNC pin is not taken high in sufficient time, it is possible to have a difference of one master clock cycle between the devices; that is, the instant at which conversions are available differs from part to part by a maximum of one master clock cycle. The SYNC pin can also be used as a start conversion command. In this mode, the rising edge of SYNC starts conversion, and the falling edge of RDY indicates when the conversion is complete. The settling time of the filter has to be allowed for each data register update. For example, if the ADC is configured to use the sinc4 filter, zero latency is disabled, and chop is disabled, the settling time equals 4/fADC where fADC is the output data rate when continuously converting on a single channel. Temp (K) = (Conversion – 0x800000)/2815 K Temp (°C) = Temp (K) – 273 Following the one-point calibration, the internal temperature sensor has an accuracy of ±2 °C, typically. BRIDGE POWER-DOWN SWITCH In bridge applications such as strain gages and load cells, the bridge itself consumes the majority of the current in the system. For example, a 350 Ω load cell requires 15 mA of current when excited with a 5 V supply. To minimize the current consumption of the system, the bridge can be disconnected (when it is not being used) using the bridge power-down switch. Figure 18 shows how the bridge power-down switch is used. The switch can withstand 30 mA of continuous current, and it has an on resistance of 11 Ω maximum. LOGIC OUTPUTS The AD7192 has four general-purpose digital outputs, P0, P1, P2, and P3. These are enabled using the GP32EN and GP10EN bits in the GPOCON register. The pins can be pulled high or low using the P0DAT to P3DAT bits in the GPOCON register; that is, the value at the pin is determined by the setting of the P0DAT to P3DAT bits. The logic levels for these pins are determined by AVDD rather than by DVDD. When the GPOCON register is read, Bit P0DAT to Bit P3DAT reflect the actual value at the pins. This is useful for short-circuit detection. These pins can be used to drive external circuitry, for example, an external multiplexer. If an external multiplexer is used to increase the channel count, the multiplexer logic pins can be controlled via the AD7192 general-purpose output pins. The general-purpose output pins can be used to select the active multiplexer pin. Because the operation of the multiplexer is independent of the AD7192, the AD7192 modulator and filter should be reset using the SYNC pin or by a write to the mode or configuration register each time that the multiplexer channel is changed. Rev. A | Page 34 of 40 AD7192 ENABLE PARITY The AD7192 also has a parity check function on chip that detects 1-bit errors in the serial communications between the ADC and the microprocessor. When the ENPAR bit in the mode register is set to 1, parity is enabled. The contents of the status register must be transmitted along with each 24-bit conversion when the parity function is enabled. To append the contents of the status register to each conversion read, the DAT_STA bit in the mode register should be set to 1. For each conversion read, the parity bit in the status register is programmed so that the overall number of 1s transmitted in the 24-bit data-word is even. Therefore, for example, if the 24-bit conversion contains eleven 1s (binary format), the parity bit is set to 1 so that the total number of 1s in the serial transmission is even. If the microprocessor receives an odd number of 1s, it knows that the data received has been corrupted. The parity function detects only 1-bit errors. For example, two bits of corrupt data can result in the microprocessor receiving an even number of 1s. Therefore, an error condition is not detected. CALIBRATION The AD7192 provides four calibration modes that can be programmed via the mode bits in the mode register. These modes are internal zero-scale calibration, internal full-scale calibration, system zero-scale calibration, and system full-scale calibration. A calibration can be performed at any time by setting the MD2 to MD0 bits in the mode register appropriately. A calibration should be performed when the gain is changed. After each conversion, the ADC conversion result is scaled using the ADC calibration registers before being written to the data register. The offset calibration coefficient is subtracted from the result prior to multiplication by the full-scale coefficient. To start a calibration, write the relevant value to the MD2 to MD0 bits. The DOUT/RDY pin and the RDY bit in the status register go high when the calibration is initiated. When the calibration is complete, the contents of the corresponding calibration registers are updated, the RDY bit in the status register is reset, the DOUT/RDY pin returns low (if CS is low), and the AD7192 reverts to idle mode. During an internal zero-scale or full-scale calibration, the respective zero input and full-scale input are automatically connected internally to the ADC input pins. A system calibration, however, expects the system zero-scale and system full-scale voltages to be applied to the ADC pins before initiating the calibration mode. In this way, errors external to the ADC are removed. From an operational point of view, treat a calibration like another ADC conversion. A zero-scale calibration, if required, must always be performed before a full-scale calibration. Set the system software to monitor the RDY bit in the status register or the DOUT/RDY pin to determine the end of calibration via a polling sequence or an interrupt-driven routine. With chop disabled, both an internal zero-scale calibration and a system zero-scale calibration require a time equal to the settling time, tSETTLE (4/fADC for the sinc4 filter and 3/fADC for the sinc3 filter). With chop enabled, an internal zero-scale calibration is not needed because the ADC itself minimizes the offset continuously. However, if an internal zero-scale calibration is performed, the settling time, tSETTLE (2/fADC), is required to perform the calibration. Similarly, a system zero-scale calibration requires a time of tSETTLE to complete. To perform an internal full-scale calibration, a full-scale input voltage is automatically connected to the selected analog input for this calibration. For a gain of 1, the time required for an internal full-scale calibration is equal to tSETTLE. For higher gains, the internal full-scale calibration requires a time of 2 × tSETTLE. A full-scale calibration is recommended each time the gain of a channel is changed to minimize the full-scale error. A system full-scale calibration requires a time of tSETTLE. With chop disabled, the zero-scale calibration (internal or system zero-scale) should be performed before the system full-scale calibration is initiated. An internal zero-scale calibration, system zero-scale calibration, and system full-scale calibration can be performed at any output data rate. An internal full-scale calibration can be performed at any output data rate for which the filter word, FS[9:0], is divisible by 16, FS[9:0] being the decimal equivalent of the 10-bit word written to Bit FS9 to Bit FS0 in the mode register. Therefore, internal full-scale calibrations can be performed at output data rates such as 10 Hz or 50 Hz when chop is disabled. Using these lower output data rates results in better calibration accuracy. The offset error is, typically, 150 μV/gain. If the gain is changed, it is advisable to perform a calibration. A zero-scale calibration (an internal zero-scale calibration or a system zero-scale calibration) reduces the offset error to the order of the noise. The gain error of the AD7192 is factory calibrated at a gain of 1 with a 5 V power supply at ambient temperature. Following this calibration, the gain error is 0.001%, typically, at 5 V. Table 23 shows the typical uncalibrated gain error for the different gain settings. Table 23. Typical Precalibration Gain Error vs. Gain Gain 8 16 32 64 128 Precalibration Gain Error (%) −0.11 −0.20 −0.23 −0.29 −0.39 An internal full-scale calibration reduces the gain error to 0.001%, typically, when the gain is equal to 1. For higher gains, the gain error post internal full-scale calibration is 0.003%, typically when AVDD is equal to 5 V. When AVDD is less than Rev. A | Page 35 of 40 AD7192 4.75 V, the gain error post internal full-scale calibration is 0.005%, typically. etch technique is generally best for ground planes because it gives the best shielding. When AVDD is less than 4.75 V, the CLK_DIV bit must be set when performing internal full-scale calibrations. The accuracy of the internal full-scale calibration is further increased if chop is enabled and a low output data rate is used while performing the calibration. Although the AD7192 has separate pins for analog and digital ground, the AGND and DGND pins are tied together internally via the substrate. Therefore, the user must not tie these two pins to separate ground planes unless the ground planes are connected together near the AD7192. A system full-scale calibration reduces the gain error to the order of the noise irrespective of the analog power supply voltage. In systems in which the AGND and DGND are connected somewhere else in the system (that is, the power supply of the system), they should not be connected again at the AD7192 because a ground loop results. In these situations, it is recommended that the ground pins of the AD7192 be tied to the AGND plane. The AD7192 gives the user access to the on-chip calibration registers, allowing the microprocessor to read the calibration coefficients of the device and also to write its own calibration coefficients from prestored values in the EEPROM. A read of the registers can be performed at any time. However, the ADC must be placed in power-down or idle mode when writing to the registers. The values in the calibration registers are 24 bits wide. The span and offset of the part can also be manipulated using the registers. GROUNDING AND LAYOUT Because the analog inputs and reference inputs are differential, most of the voltages in the analog modulator are commonmode voltages. The high common-mode rejection of the part removes common-mode noise on these inputs. The analog and digital supplies to the AD7192 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. Connect an R-C filter to each analog input pin to provide rejection at the modulator sampling frequency. A 100 Ω resistor in series with each analog input, a 0.1 μF capacitor between the analog input pins, and a 0.01 μF capacitor from each analog input to AGND are advised. The digital filter also removes noise from the analog and reference inputs provided that these noise sources do not saturate the analog modulator. As a result, the AD7192 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD7192 is so high and the noise levels from the converter so low, care must be taken with regard to grounding and layout. The printed circuit board (PCB) that houses the ADC must be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum In any layout, the user must keep in mind the flow of currents in the system, ensuring that the paths for all currents are as close as possible to the paths the currents took to reach their destinations. Avoid forcing digital currents to flow through the AGND. Avoid running digital lines under the device, because this couples noise onto the die, and allow the analog ground plane to run under the AD7192 to prevent noise coupling. The power supply lines to the AD7192 must use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board, and never run clock signals near the analog inputs. Avoid crossover of digital and analog signals. Run traces on opposite sides of the board at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, whereas signals are placed on the solder side. Good decoupling is important when using high resolution ADCs. Decouple all analog supplies with 10 μF tantalum capacitors in parallel with 0.1 μF capacitors to AGND. To achieve the best results from these decoupling components, place them as close as possible to the device, ideally right up against the device. Decouple all logic chips with 0.1 μF ceramic capacitors to DGND. In systems in which a common supply voltage is used to drive both the AVDD and DVDD of the AD7192, it is recommended that the system AVDD supply be used. For this supply, place the recommended analog supply decoupling capacitors between the AVDD pin of the AD7192 and AGND and the recommended digital supply decoupling capacitor between the DVDD pin of the AD7192 and DGND. Rev. A | Page 36 of 40 AD7192 APPLICATIONS INFORMATION measurements can be taken. In applications in which current consumption is being minimized, the AD7192 can be placed in standby mode, thus significantly reducing the power consumed in the application. In addition, the bridge power-down switch can be opened while in standby mode, thus avoiding unnecessary power consumption by the front-end transducer. When the part is taken out of standby mode and the bridge power-down switch is closed, the user should ensure that the front end circuitry is fully settled before attempting a read from the AD7192. The AD7192 provides a low-cost, high resolution analog-todigital function. Because the analog-to-digital function is provided by a Σ-Δ architecture, the part is more immune to noisy environments, making it ideal for use in sensor measurement and industrial and process control applications. WEIGH SCALES Figure 32 shows the AD7192 being used in a weigh scale application. The load cell is arranged in a bridge network and gives a differential output voltage between its OUT+ and OUT– terminals. Assuming a 5 V excitation voltage, the full-scale output range from the transducer is 10 mV when the sensitivity is 2 mV/V. The excitation voltage for the bridge can be used to directly provide the reference for the ADC because the reference input range includes the supply voltage. For simplicity, external filters are not included in Figure 32. However, an R-C antialias filter must be included on each analog input. This is required because the on-chip digital filter does not provide any rejection around the modulator sampling frequency or multiples of this frequency. Suitable values are a 100 Ω resistor in series with each analog input, a 0.1 μF capacitor between the analog input pins, and a 0.01 μF capacitor from each analog input pin to AGND. A second advantage of using the AD7192 in transducer-based applications is that the bridge power-down switch can be fully utilized to minimize the power consumption of the system. The bridge power-down switch is connected in series with the cold side of the bridge. In normal operation, the switch is closed and 5V OUT+ OUT– IN– AIN1 AIN2 AIN3 AIN4 AINCOM MUX BPDSW REFERENCE DETECT SERIAL INTERFACE AND CONTROL LOGIC Σ-Δ ADC PGA AGND REFIN1(–) DVDD DGND AVDD AVDD DOUT/RDY DIN SCLK CS SYNC TEMP SENSOR AD7192 P3 P2 CLOCK CIRCUITRY AGND MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+) Figure 32. Typical Application (Weigh Scale) Rev. A | Page 37 of 40 07822-024 REFIN1(+) AGND IN+ AD7192 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 33. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Model AD7192BRUZ 1 AD7192BRUZ-REEL1 1 Temperature Range –40°C to +105°C –40°C to +105°C Package Description 24-Lead TSSOP 24-Lead TSSOP Z = RoHS Compliant Part. Rev. A | Page 38 of 40 Package Option RU-24 RU-24 AD7192 NOTES Rev. A | Page 39 of 40 AD7192 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07822-0-5/09(A) Rev. A | Page 40 of 40