APA2030/2031 Stereo 2.6W Audio Amplifier (With Gain Control) Features • • • • • • • • • • • General Description Low Operating Current with 6mA Improved Depop Circuitry to Eliminate Turn-On APA2030/1 is a monolithic integrated circuit, which provides internal gain control, and a stereo bridged audio power amplifiers capable of producing 2.6W (1.9W) into Transients in Outputs High PSRR 3Ω with less than 10% (1.0%) THD+N. By controlling the two gain setting pins, Gain0 and Gain1, the amplifier can Internal Gain Control, Eliminate External Components provide 6dB, 10dB, 15.6dB, and 21.6dB gain settings. The advantage of internal gain setting can be less com- 2.6W Per Channel Output Power into 3Ω Load at 5V, BTL Mode ponents and PCB area. Both of the depop circuitry and the thermal shutdown protection circuitry are integrated Multiple Input Modes Allowable Selected by HP/LINE Pin (APA2030) in APA2030/1, that reduces pops and clicks noise during power up or shutdown mode operation. It also improves Two Output Modes Allowable with BTL and SE Modes Selected by SE/BTL Pin (for APA2030 only) the power off pop noise and protects the chip from being destroyed by over temperature and short current failure. Low Current Consumption in Shutdown Mode (50µA) To simplify the audio system design, APA2030 combines a stereo bridge-tied loads (BTL) mode for speaker drive Short Circuit Protection TSSOP-24P (APA2030), TSSOP-20P, and TQFN3x3- and a stereo single-end (SE) mode for headphone drive into a single chip, where both modes are easily switched 16 (APA2031) with Thermal Pad Packages. Lead Free and Green Devices Available by the SE/BTL input control pin signal. In addition, the multiple input selections are used for portable audio (RoHS Compliant) system. The APA2031 eliminates both input selection and single-end (SE) mode function to simplify the design and Applications save the PCB space. • • Pin Configuration Notebook PCs LCD Monitor APA2030 GND 1 GAIN0 2 24 23 22 21 GAIN1 3 LOUT+ 4 LLINEIN 5 LHPIN 6 PVDD 7 RIN+ 8 LOUT- 9 LIN+ 10 BYPASS 11 GND 12 TSSOP-24P (Top View) GND RLINEIN SHUTDOWN ROUT+ 20 RHPIN 19 VDD 18 PVDD 17 HP/LINE 16 ROUT15 SE/BTL 14 PCBEEP 13 GND = ThermalPad (connected the ThermalPad to GND plane for better heat dissipation) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 1 www.anpec.com.tw APA2030/2031 GND 1 19 SHUTDOWN GAIN1 3 18 ROUT+ LOUT+ 4 ROUT- 13 17 RIN- VDD 14 16 VDD TSSOP-20P (Top View) RIN- 15 15 PVDD 14 ROUT- RIN+ 7 LOUT- 8 8 RIN+ TQFN3X3-16 (Top View) ROUT+ 16 7 PVDD 6 LIN5 LOUT+ 13 GND LIN+ 9 = ThermalPad (connected the ThermalPad to GND plane for better heat dissipation) GAIN1 4 GAIN0 3 11 GND GND 2 12 NC BYPASS 10 SHUTDOWN 1 PVDD 6 9 LIN+ 20 GND GAIN0 2 LIN- 5 10 BYPASS 12 LOUT- APA2031 11 GND Pin Configuration (Cont.) Ordering and Marking Information Package Code R : TSSOP-24P (APA2030) / TSSOP-20P (APA2031) QB : TQFN3x3-16 (APA2031) Operating Ambient Temperature Range I : - 40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APA2030 APA2031 Assembly Material Handling Code Temperature Range Package Code APA2030 R : APA2030 XXXXX XXXXX - Date Code APA2031 R : APA2031 XXXXX XXXXX - Date Code APA2031 QB : APA 2031 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 2 www.anpec.com.tw APA2030/2031 Absolute Maximum Ratings (Note 1) (Over operating free-air temperature range unless otherwise noted.) Symbol Parameter Supply Voltage Range, VDD, PVDD Input Voltage Range at SE/BTL, HP/LINE, SHUTDOWN, Rating Unit -0.3V to 6V V -0.3V to VDD V TA Operating Ambient Temperature Range -40 oC to 85 oC TJ Maximum Junction Temperature Internal Limited Storage Temperature Range -65 oC to 150 oC TSTG TSDR PD o C o C o Maximum Lead Soldering Temperature, 10 Seconds o 260 C Power dissipation C Internal Limited Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Typical Value Thermal Resistance from Junction to Ambient in Free Air (Note 2) TSSOP-24P TSSOP-20P TQFN3x3-16 Unit 45 48 55 o C/W Note 2 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. * 5 in2 printed circuit board with 2oz trace and copper pad through 9 25mil diameter vias. The thermal pad on the TSSOP_P and TQFN3x3-16 packages with solder on the printed circuit board. Recommended Operating Conditions Symbol VDD Parameter Supply Voltage Range Unit 4.5V to 5.5V V Electrical Characteristics (VDD=5V, -20°C<TA<85°C, unless otherwise noted.) Symbol Parameter VDD Supply Voltage IDD Supply Current Typ. Max. 3.3 - 5.5 V SE/BTL = 0V - 6 12 mA SE/BTL = 5V - 4 8 mA - 50 300 µA SHUTDOWN, GAIN0, GAIN1 2 - - V SE/BTL, HP/LINE 4 - - V SHUTDOWN, GAIN0, GAIN1 - - 0.8 V SE/BTL, HP/LINE - - 3 V Supply Current in Shutdown Mode SHUTDOWN = 0V VIH High Level Threshold Voltage Low level Threshold Voltage Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 Unit Min. ISD VIL APA2030 / 2031 Test Conditions 3 www.anpec.com.tw APA2030/2031 Electrical Characteristics (Cont.) (VDD=5V, -20°C<TA<85°C, unless otherwise noted.) APA2030/2031 Symbol II Parameter Input Current Test Conditions Unit Min. Typ. Max. - 5 - nA VDD-1.0 - - V SHUTDOWN, SE/BTL, HP/LINE, GAIN0, GAIN1 VICM Common Mode Input Voltage VOS Output Differential Voltage - 5 - mV PC-BEEP Trigger Level - 1 - Vp.p BYPASS Equivalent Resistance - 250 - kΩ RBYPASS Operating Characteristics, BTL mode VDD=5V, TA=25°C, RL=4Ω, Gain=6dB, (Unless otherwise noted) APA2030 / 2031 Symbol PO THD+N PSRR Crosstalk S/N Parameter Maximum Output Power Total Harmonic Distortion Plus Noise Test Conditions Unit Min. Typ. Max. THD+N=10%, fin=1kHz, RL=3Ω - 2.6 - W THD+N =10%, fin=1kHz, RL=4Ω - 2.3 - W THD+N =10%, fin=1kHz, RL=8Ω - 1.5 - W THD+N =1%, fin=1kHz, RL=3Ω - 1.9 - W THD+N =1%, fin=1kHz, RL=4Ω - 1.7 - W THD+N =1%, fin=1kHz, RL=8Ω 1 1.1 - W PO=1.1W, RL=4Ω fin=1kHz - 0.05 - % PO=0.7W, RL=8Ω, fin=1kHz - 0.04 - % Power Ripple Rejection Ratio VIN=0.2Vrms, RL=8Ω, CB=0.47µF, fin =120Hz - 85 - dB Channel Separation fin =1kHz, CB=0.47µF, - 95 - dB HP/LINE Input Separation fin =1kHz, CB=0.47µF, - 80 - dB Signal to Noise Ratio PO=1.1W, RL=8Ω , A_weighting - 105 - dB Operating Characteristics, SE mode ( for APA2030 only) VDD=5V, TA=25°C, RL=32Ω, Gain=4, 1dB, (Unless otherwise noted) APA2030 Symbol PO Parameter Maximum Output Power Test Conditions Typ. Max. THD+N=10%, fin=1kHz, RL=32Ω - 110 - mW THD+N =1%, fin=1kHz, RL=32Ω - 90 - mW - 0.03 - % - 55 - dB - 80 - dB THD+N Total Harmonic Distortion Plus Noise PO=75mW, RL=32Ω, fin=1kHz PSRR Power Ripple Rejection Ratio VIN=0.2Vrms, RL=32Ω, CB=0.47µF, fin =120, SE/BTL Attenuation Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 Unit Min. 4 www.anpec.com.tw APA2030/2031 Electrical Characteristics (Cont.) Operating Characteristics, SE mode ( for APA2030 only) VDD=5V, TA=25°C, RL=32Ω, Gain=4, 1dB, (Unless otherwise noted) APA2030 Symbol Crosstalk S/N Parameter Test Conditions Unit Min. Typ. Max. Channel Separation fin =1kHz, CB=0.47µF, - 65 - dB HP/LINE Input Separation fin =1kHz, CB=0.47µF, BTL - 80 - dB Signal to Noise Ratio PO=75mW, RL=32Ω, A_weighting - 100 - dB Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 5 www.anpec.com.tw APA2030/2031 Typical Operating Characteristics THD+N vs. Output Power 10 THD+N vs. Output Power 10 VDD=5V AV=6dB fin=1kHz BTL 1 RL=8Ω THD+N (%) THD+N (%) RL=4Ω 1 RL=3Ω 0.1 0.01 0.5 0 1 2.5 2 1.5 VDD=5V AV=4.1dB fin=kHz COUT=330µF SE RL=16Ω 0.1 0.01 3 RL=32Ω 0 50 100 Output Power (W) 150 200 250 Output Power (mW) THD+N vs. Output Power Crosstalk vs. Output Power 10 10 1 V =5V DD AV=6dB RL=3Ω BTL Crosstalk (dB) THD+N (%) fin=15kHz fin=15kHz fin=1kHz 0.1 100m fin=1kHz 0.1 1 0.01 10m 5 100m Output Power (W) 2 5 THD+N vs. Output Power 10 VDD=5V AV=6dB RL=4Ω BTL fin=15kHz THD+N (%) THD+N (%) fin=15kHz 1 fin=1kHz 0.1 100m fin=1kHz fin=30Hz VDD=5V AV=15.6dB RL=4Ω BTL 1 2 0.01 10m 5 Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 1 0.1 fin=30Hz 0.01 10m 1 Output Power (W) THD+N vs. Output Power 10 fin=30Hz VDD=5V AV=15.6dB RL=3Ω BTL fin=30Hz 0.01 10m 1 100m 1 2 5 Output Power (W) 6 www.anpec.com.tw APA2030/2031 Typical Operating Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Power 10 10 VDD=5V AV=15.6dB RL=8Ω BTL VDD=5V AV=6dB RL=8Ω BTL 1 0.1 THD+N (%) THD+N (%) fin=15kHz fin=15kHz 1 fin=30Hz 0.1 fin=1kHz fin=1kHz fin=30Hz 0.01 10m 100m 1 2 0.01 10m 5 100m THD+N vs. Output Power 5 10 VDD=5V AV=4.1dB RL=16Ω COUT=1000µF BTL fin=30Hz 1 THD+N (%) THD+N (%) 2 THD+N vs. Output Power 10 1 1 Output Power (W) Output Power (W) fin=15kHz 0.1 VDD=5V AV=4.1dB RL=32Ω COUT=1000µf BTL fin=15kHz 0.1 fin=30Hz fin=1kHz 0.01 10m 50m 100m fin=1kHz 0.01 10m 200m 300m 50m Output Power (W) THD+N vs. Frequency 200m 300m THD+N vs. Frequency 10 10 VDD=5V AV=6dB RL=3Ω BTL VDD=5V PO=1.75W RL=3Ω BTL 1 THD+N (%) THD+N (%) 100m Output Power (W) PO=1.75W 0.1 1 AV=15.6dB 0.1 PO=1W AV=6dB 0.01 0.01 20 100 1k 10k 20k 20 1k 10k 20k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 100 7 www.anpec.com.tw APA2030/2031 Typical Operating Characteristics (Cont.) THD+N vs. Frequency THD+N vs. Frequency 10 10 VDD=5V AV=6dB RL=4Ω BTL VDD=5V PO=1.5W RL=4Ω BTL 1 THD+N (%) THD+N (%) 1 PO=1.5W 0.1 AV=15.6dB 0.1 AV=6dB PO=0.75W 0.01 20 0.01 100 1k 20 10k 20k 100 Frequency (Hz) THD+N vs. Frequency 10k 20k THD+N vs. Frequency 10 10 VDD=5V PO=1W RL=8Ω BTL VDD=5V AV=6dB RL=8Ω BTL 1 1 THD+N (%) THD+N (%) 1k Frequency (Hz) PO=1W 0.1 AV=6dB AV=15.6dB 0.1 PO=0.5W 0.01 20 0.01 100 1k 10k 20k 20 100 Frequency (Hz) THD+N vs. Frequency THD+N (%) THD+N (%) 10 VDD=5V AV=4.1dB RL=16Ω COUT=1000µF SE 0.1 1 VDD=5V AV=4.1dB RL=32Ω COUT=1000µF SE 0.1 PO=75mW PO=25mW PO=150mW 0.01 20 100 10k 20k THD+N vs. Frequency 10 1 1k Frequency (Hz) 1k PO=75mW 0.01 10k 20k 100 1k 10k 20k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 20 8 www.anpec.com.tw APA2030/2031 Typical Operating Characteristics (Cont.) Frequency Response +18 +220 +16 +210 +200 -0 +190 +180 -2 +170 Phase -4 -8 -10 10 +12 +10 1k 10k +8 +6 +150 100 Gain +14 +160 VDD=5V RL=4Ω AV=6dB PO=1W BTL -6 +140 +4 +130 +2 +120 100k 200k -0 10 100 1k Frequency Response Gain (dB) +7 +6 +5 +4 +2 +1 -0 Phase 10 100 1k 10k +300 +5 +280 +4 Gain +3 +240 +1 +220 +0 +200 +180 -1 Phase -2 -3 -4 -5 10 100 T T VDD=5V RL=4Ω AV=6dB PO=1.5W BTL -60 -80 Left to Right -100 -10 1k -20 -30 -40 -50 -60 Left to Right -70 -80 -100 20 10k 20k Right to Left 100 1k 10k 20k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 +100 100k 200k 10k -90 Right to Left 100 1k VDD=5V RL=32Ω AV=4.1dB VIN=1V COUT=330µF SE -120 -140 20 +120 Crosstalk vs. Frequency +0 Output Noise Voltage (Vrms) Crosstalk (dB) -40 +140 Frequency (Hz) Crosstalk vs. Frequency -20 +160 VDD=5V RL=32Ω AV=4.1dB VIN=1V SE Frequency (Hz) +0 +260 +2 Gain (dB) +8 Frequency Response +270 +260 +250 +240 +230 +220 +210 +200 +190 +180 +170 +160 +150 +140 +130 +120 100k200k Phase (deg) Gain VDD=5V RL=8Ω AV=10dB PO=0.5W BTL 10k Frequency (Hz) +10 +3 +170 +160 +150 +140 +130 +120 100k 200k Phase VDD=5V RL=4Ω AV=15.6dB PO=1W BTL Frequency (Hz) +9 +270 +260 +250 +240 +230 +220 +210 +200 +190 +180 Phase (deg) +230 Phase (deg) Gain (dB) +2 +20 Gain (dB) Gain +4 Frequency Response +240 Phase (deg) +6 9 www.anpec.com.tw APA2030/2031 Typical Operating Characteristics (Cont.) PSRR vs. Frequency PSRR vs. Frequency +0 +0 VDD=5V RL=4Ω CB=0.47µF BTL -10 -20 -20 -30 PSRR(dB) PSRR(dB) -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 VDD=5V RL=32Ω CB=0.47µF SE -10 100 1k -100 10k 20k 20 100 Output Noise Voltage vs. Frequency 100 100 50 50 Output Noise Voltage (µV) Output Noise Voltage (µV) Output Noise Voltage vs. Frequency Filter BW<22kHz 20 10 A-Weighting 5 VDD=5V RL=4Ω AV=6dB BTL 1 20 100 1k Filter BW<22kHz 20 10 A-Weighting 5 VDD=5V RL=32Ω AV=4.1dB SE 2 1 20 10k 20k 100 Frequency (Hz) Supply Current vs. Supply Voltage 10k 20k Power Dissipation vs. Output Power 2.0 No Load 1.8 BTL Power Dissipation (W) 6 Supply Current (mA) 1k Frequency (Hz) 7 5 4 SE 3 2 VDD=5V BTL RL=3Ω 1.6 1.4 1.2 RL=4Ω 1.0 0.8 0.6 RL=8Ω 0.4 1 0 10k 20k Frequency (Hz) Frequency (Hz) 2 1k 0.2 3.0 3.5 4.0 4.5 5.0 5.5 0.0 6.0 0.0 Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 10 0.5 1.0 1.5 Output Power (W) 2.0 2.5 www.anpec.com.tw APA2030/2031 Typical Operating Characteristics (Cont.) Power Dissipation vs. Output Power 200 VDD=5V SE 180 Power Dissipation (mW) 160 RL=8Ω 140 120 100 80 RL=16Ω 60 40 RL=32Ω 20 0 0 50 100 150 200 250 300 Output Power (mW) Pin Description APA2030 PIN TSSOP-24P CONFIG. FUNCTION NO. NAME 1,12,13,24 GND - 2 GAIN0 I/P Input signal for internal gain setting. 3 GAIN1 I/P Input signal for internal gain setting. 4 LOUT+ O/P Left channel positive output in BTL mode and SE mode. 5 LLINEIN I/P Left channel line input terminal, selected when HP/LINE is held low. 23 RLINEIN I/P Right channel line input terminal, selected when HP/LINE is held low. 6 LHPIN O/P Left channel headphone input terminal, selected when HP/LINE is held high. 7,18 PVDD - 8 RIN+ I/P Right channel positive signal input when differential signal is accepted. 9 LOUT- O/P Left channel negative output in BTL mode and high impedance in SE mode. 10 LIN+ I/P Left channel positive signal input when differential signal is accepted. Ground connection, connected to thermal pad. Supply voltage only for power amplifier. 11 BYPASS - 14 PCBEEP I/P Bypass voltage. PC-beep signal input. 15 SE/BTL I/P Output mode control input pin, high for SE output mode and low for BTL mode. 16 ROUT- O/P Right channel negative output in BTL mode and high impedance in SE mode. 17 HP/LINE I/P 19 VDD - 20 RHPIN I/P Right channel headphone input terminal, selected when HP/LINE is held high. 21 ROUT+ O/P Right channel positive output in BTL mode and SE mode. 22 SHUTDOWN I/P It will be into shutdown mode when pull low. 23 RLINEIN I/P Right channel line input terminal, selected when HP/LINE is held low. Multi-input selection input, headphone mode when held high, line-in mode when held low. Supply voltage for internal circuit excepting power amplifier. Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 11 www.anpec.com.tw APA2030/2031 Pin Description (Cont.) APA2031 PIN CONFIG. NO. FUNCTION NAME TSSOP-20P TQFN3x3-16 1,11,13,20 2,11 GND - Ground connection, connected to thermal pad. 2 3 GAIN0 I/P Input signal for internal gain setting. 3 4 GAIN1 I/P Input signal for internal gain setting. 4 5 LOUT+ O/P Left channel positive output. 5 6 LIN- I/P Left channel negative audio signal input. 6,15 7 PVDD - Supply voltage only for power amplifier. 7 8 RIN+ I/P Right channel positive audio signal input. 8 12 LOUT- O/P Left channel negative output. 9 9 LIN+ I/P Left channel positive audio signal input. 10 10 BYPASS - Bypass voltage. No connection. 12 - NC - 14 13 ROUT- O/P 16 14 VDD - 17 15 RIN- I/P Right channel negative audio signal input. 18 16 ROUT+ O/P Right channel positive output. 19 1 SHUTDOWN I/P It will be into shutdown mode when pull low. Right channel negative output. Supply voltage for internal circuit excepting power amplifier. Control Input Table ( for APA2030 only) HP/ LINE SE/BTL SHUTDOWN PCBEEP X L X L Disable Shutdown mode L H Disable Line input, BTL out H L H Disable HP input, BTL out Operating mode L H H Disable Line input, SE out H H H Disable HP input, SE out X X X Enable PC-BEEP input, BTL out Gain Setting Table (for both APA2030 and APA2031) GAIN0 GAIN1 Ri Rf AV 0 0 90kΩ 90kΩ 6dB 0 1 69kΩ 111kΩ 10dB 1 0 42kΩ 138kΩ 15.6dB 1 1 25.7kΩ 154.3kΩ 21.6dB Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 12 www.anpec.com.tw APA2030/2031 Block Diagram LLINEIN LHPIN LOUT+ MUX LIN+ BYPASS Vbias LOUTGAIN0 Gain selectable GIAN1 RLINEIN RHPIN ROUT+ MUX RIN+ HP/LINE SE/BTL SHUTDOWN PCBEEP HP/LINE Vbias SE/BTL ROUT- Shutdown ckt PC-BEEP ckt APA2030_Block Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 13 www.anpec.com.tw APA2030/2031 Typical Application Circuit (for APA2030 using SE input signal) VDD 0Ω 0.1µF VDD L-LINE 0.47µF L-HP 0.47µF LLINEIN LHPIN 0.47µF 0.47µF 100µF GND PVDD LOUT+ MUX 220µF LIN+ 1kΩ BYPASS Vbias Control Pin Ring 4Ω SE/BTL Signal GAIN0 GAIN1 0.47µF R-LINE R-HP 0.47µF 0.47µF RLINEIN RHPIN LOUT- Sleeve Tip Headphone Jack Gain selectable ROUT+ MUX 220µF RIN+ 1kΩ HP/LINE HP/LINE Control Signal HP/LINE VDD 100kΩ 100kΩ SE/BTL SE/BTL Signal Shutdown Signal SHUTDOWN PCBEEP BEEP Signal Vbias 4Ω SE/BTL ROUT - Shutdown ckt PC-BEEP ckt 0.47µF APA2030AppCk t APA2030 Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 14 www.anpec.com.tw APA2030/2031 Typical Application Circuit (Cont.) (for APA2031 using SE input signal) 0Ω VDD 0.1 µ F VDD L-INPUT 0.47 µ F 100 µF GND PVDD LIN- 0.47 µ F LOUT+ LIN+ BYPASS Vbias 0.47 µ F 4Ω LOUT- GAIN0 GAIN1 R-INPUT 0.47 µF Gain selectable RIN- ROUT+ 0.47 µF RIN+ Vbias 4Ω Shutdown Signal SHUTDOWN ROUT- Shutdown ckt APA2031 Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 15 www.anpec.com.tw APA2030/2031 Application Information BTL Operation so they tend to be expensive, occupy valuable PCB area, The APA2030/1 has two pairs of operational amplifiers internally, which allows for different amplifier configurations. and have the additional drawback of limiting low-frequency performance of the system (refer to the Output Coupling Capacitor). The rules described should be following the relationship: INPUT- - INPUT+ + OUT+ 1 1 1 ≤ ≤ ..........................(1) Cbypass× 250kΩ RiCi RLCC OP1 V bias Output SE/BTL Operation (for APA2030 only) The best cost saving feature of APA2030 is that it can be D I F F _AM P _CONF I G switched easily between BTL and SE modes. This feature eliminates the requirement for an additional head- + OUTOP2 Figure 1: APA2030 Internal Configuration (each channel) phone amplifier in applications where internal stereo speakers are driven in BTL mode but external headphone The OP1 and OP2 are all differential drive configurations. The differential driver configurates doubling voltage or speakers must be accommodated. The APA2030 has two separated amplifiers drive OUT+ and OUT- (See Figure 1). The SE/BTL input controls the swing on the load. Compare with the single-ending configuration, the differential gain for each channel is 2X operation of the amplifier that drives LOUT- and ROUT-. (Gain of SE mode). By driving the load differentially through outputs OUT+ and OUT-, an amplifier configuration which is commonly referred to bridged mode is established. BTL mode operation is different from the classical single-ended SE • When SE/BTL is held low, the OP2 is actived and • the APA2030 is in the BTL mode. When SE/BTL is held high, the OP2 is in a high output impedance state, which configures the APA2030 as SE driver from OUT+. IDD is reduced by amplifier configuration where one side of its load is connected to the ground. approximately one-half in SE mode. The SE/BTL input can be a logic-level TTL source, a re- A BTL amplifier design has a few distinct advantages over sistor divider network or the stereo headphone jack with switch pin as shown in the Application Circuit. the SE configuration, as it provides differential drive to the load, thus, doubling the output swing for a specified supply voltage. When placed under the same conditions, a BTL amplifier has four times the output power of a SE VDD 1kΩ amplifier. A BTL configuration, such as the one used in APA2030/1, also creates a second advantage over SE Control Pin Ring 100kΩ SE/BTL 100kΩ SE/BTL_Switch amplifiers. Since the differential outputs, ROUT+, ROUT-, LOUT+, and LOUT-, are biased at half-supply, it’s not necTip essary for DC voltage to be across the load. This eliminates the need for an output coupling capacitor which is Sleeve Headphone Jack required in a single supply, SE configuration. Figure 2: SE/BTL input selection by phonejack plug Single-Ended Operation (for APA2030 only) In Figure 2, input SE/BTL operates as below: Consider the single-supply SE configuration shown Application Circuit. A coupling capacitor is required to block When the phone jack plug is inserted, the 1kΩ resistor is disconnected and the SE/BTL input is pulled high and the DC offset voltage from reaching the load. These capacitors can be quite large (approximately 33µF to 1000µF) enables the SE mode. When the input goes high level, Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 16 www.anpec.com.tw APA2030/2031 Application Information (Cont.) Output SE/BTL Operation (for APA2030 only) (Cont.) Input Resistance, Ri the OUT- amplifier is shutdown and causes the speaker The APA2030/1 provides four gain setting decided by GAIN0 and GAIN1 input pins in differential mode and it to mute. And then, the OUT+ amplifier drives through the output capacitor (CO) into the headphone jack. becomes 4.1dB fixed gain when SE mode is selected (for APA2030). In Table 1, according to the BTL operation, When there is no headphone plugged into the system, the contact pin of the headphone jack is connected from internal resistors Ri and Rf set the gain for each audio input of the APA2030/1. the signal pin, the voltage divider is set up by resistors 100kΩ and 1kΩ. Resistor 1kΩ then pulls low the SE/BTL GAIN0 GAIN1 Ri Rf SE/BTL AV 0 0 90kΩ 90kΩ 0 6dB Input HP/LINE Operation (for APA2030 only) 0 1 69kΩ 111kΩ 0 10dB APA2030 amplifier has two separated inputs for each of the left and right stereo channels. An internal multiplexer 1 0 42kΩ 138kΩ 0 15.6dB 1 1 25.7kΩ 154.3kΩ 0 21.6dB X X 69kΩ 111kΩ 1 4.1dB pin, enabling the BTL function. selects which input will be connected to the amplifier based on the state of the HP/LINE pin on the IC. • • To select the line inputs, set HP/LINE pin tied to low Table 1: The close loop gain setting resistance Ri/Rf level BTL mode operation brings about the factor 2 in the gain To enable the headphone inputs, set HP/ LINE pin equation due to the inverting amplifier mirroring the voltage swing across the load. The input resistance has wide tied to high level variation (+/-10%) caused by manufacturing. Refer to the application circuit, the voltage divider of 100kΩ and 1kΩ sets the voltage at the HP/LINE pin to be approximately 50mV when there are no headphones Input Capacitor, Ci In the typical application, an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper plugged into the system. This logic low voltage at the HP/LINE pin enables the APA2030 and places it LINE DC level for optimum operation. In this case, Ci and the minimum input impedance Ri form a high-pass filter with input mode operation. When a set of headphones is plugged into the system, the corner frequency determined in the following equation: the contact pin of the headphone jack is disconnected from the signal pin, interrupting the voltage divider set up fc (highpass) = by resistors 100kΩ. Resistor 100kΩ then pulls-up the HP/LINE pin, enabling the headphone input function. 1 .....................................(2) 2πRi(min) × Ci The value of Ci must be considered carefully because it Differential Input Operation directly affects the low frequency performance of the circuit. Consider the example where Ri is 90kΩ when The APA2030/1 can accept the differential input signal and improve the CMRR (Common Mode Rejection Ratio). 6dB gain is set and the specification calls for a flat bass response down to 40Hz. The equation is reconfigured as For example, when applying differential input signals to APA2031, connect positive input signals to the IN+ (LIN+ below: Ci = 1 .................................................. ......(3 ) 2πRifc and RIN+) of APA2031 and negative input signals to the IN- (LIN- and RIN-) of APA2031. When the variation of input resistance (Ri) is considered, When input signals are single-end, just connect IN+ (LIN+ and RIN+) to ground via a capacitor. the value of Ci is 0.04µF. Therefore, a value in the range from 0.1µF to 1.0µF would be chosen. Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 17 www.anpec.com.tw APA2030/2031 Application Information (Cont.) Input Capacitor, Ci (Cont.) Output Coupling Capacitor, Cc (for APA2030 only) A further consideration for this capacitor is the leakage path from the input source through the input network In the typical single-supply SE configuration, an output coupling capacitor (Cc) is required to block the DC bias at (Ri+Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces the output of the amplifier thus preventing DC currents in the load. As with the input coupling capacitor, the output useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic ca- coupling capacitor and impedance of the load form a highpass filter governed by the following equation. pacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the fc (highpass ) = amplifiers’ input in most applications becasue the DC level of the amplifiers’inputs is held at VDD/2. Please note 1 ...........................................( 6) 2πRLCc For example, a 330µF capacitor with an 8Ω speaker would attenuate low frequencies below 60.6Hz. Large values of CC are required to pass low frequencies into that it is important to confirm the capacitor polarity in the application. the load. Effective Bypass Capacitor, Cbypass Power Supply Decoupling, CS As to any power amplifier, proper supply bypassing is critical for low noise performance and high power supply The APA2030/1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling rejection. The capacitor located on both the bypass and power supply pins should be as close to the device as possible. to ensure the output total harmonic distortion (THD+N) is as low as possible. Power supply decoupling also prevents the oscillations being caused by long lead length between the amplifier The effect of a larger half supply bypass capacitor improves PSRR due to increased half-supply stability. Typi- and the speaker. The optimum decoupling is achieved by using two differ- cal applications employ a 5V regulator with 1.0µF and a 0.1µF bypass capacitors which aid in supply filtering. This ent types of capacitors that targets on different types of noise on the power supply leads. For higher frequency does not eliminate the need for bypassing the supply nodes of the APA2030/1. The selection of bypass transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, capacitors, especially CB, is thus dependent upon desired PSRR requirements, click and pop performance. To avoid the start-up pop noise occurred, the bypass volt- typically 0.1µF placed as close as possible to the device VDD lead works best. For filtering lower-frequency noise age should rise slower than the input bias voltage and the relationship shown in equation should be maintained. signals, a large aluminum electrolytic capacitor of 10µF or greater placed near the audio power amplifier is 1 1 << ........................(4) Cbypass × 250kΩ Ci × 180kΩ recommended. Shutdown Function In order to reduce power consumption when not in use, The capacitor is fed from a 250kΩ source inside the amplifier. Bypass capacitor, CB, values of 3.3µF to 10µF the APA2030/1 contains a shutdown pin to externally turn off the amplifier bias circuitry. This shutdown feature ceramic or tantalum low-ESR capacitors are recommended for the best THD+N and noise performance. turns the amplifier off when a logic low is placed on the SHUTDOWN pin. The trigger point between a logic high The bypass capacitance also affects the start-up time. It and logic low level is typically 2.0V. It is better to switch between the ground and the supply VDD to provide maxi- is determined in the following equation: mum device performance. TStartup = 5 × (Cbypass × 250kΩ)................... ........( 5) Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 18 www.anpec.com.tw APA2030/2031 Application Information (Cont.) Shutdown Function (Cont.) using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relationship be- By switching the SHUTDOWN pin to low, the amplifier tween the size of CB and the turn-on time. enters a low-current state, IDD<50mA. The APA2030 is in shutdown mode, except PC-BEEP detect circuit. On nor- In a SE (for APA2030) configuration, the output coupling capacitor, CC, is of particular concern. This capacitor dis- mal operating, SHUTDOWN pin is pulled to high level to keep the IC out of the shutdown mode. The SHUTDOWN charges through the internal 10kΩ resistors. Depending on the size of CC, the time constant can be relatively large. pin should be tied to a definite voltage to avoid unwanted state changing. To reduce transients in SE mode, an external 1kΩ resistor can be placed in parallel with the internal 10kΩ resistor. PC-BEEP Detection ( for APA2030 only) The tradeoff for using this resistor is an increase in quiescent current. The APA2030 integrates a PC-BEEP detect circuit for NOTEBOOK PC using. Over 1Vpp amplitude PC-BEEP signal with the rising time/falling time under 1µs/V should be provided to trigger the APA2030 into PC-BEEP mode. In the cases, choosing a small value of Ci in the range of 0.33µF to 1µF, CB being equal to 0.47µF and an external 1kΩ resistor should be placed in parallel with the inter- The input impedance is 100kΩ and the bias voltage on PC-BEEP input pin is 2.5V. Therefore, the voltage level of nal 10kΩ resistor, and it should produce a virtually clickless and popless turn-on. PC-BEEP signal should be higher than 3V and lower than 2V to into PCBEEP mode correctly. A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. Hence, it is ad- When PC-BEEP signal drives to PC-BEEP input pin, the PC-BEEP mode will be active. When chip in the PC-BEEP vantageous to use low-gain configurations. mode, the APA2030 will be forced to be in BTL mode and the internal gain is fixed as -10dB. The PC-BEEP signal BTL Amplifier Efficiency An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power sup- turns to be the amplifier input signal and plays on the speaker without coupling capacitor. If the amplifier is in ply to the power delivered to the load. The following equations are the basis for calculating amplifier efficiency. the shutdown mode, it will be out of shutdown mode whenever PC-BEEP mode enabled. The APA2030 will Efficiency = return to previous setting when it is out of PC-BEEP mode. Optimizing Depop Circuitry PO ........................................ ......(7 ) PSUP Where Circuitry has been included in the APA2030/1 to minimize the amount of popping noise at power-up and when com- Vorms × Vorms VP × VP = RL 2RL VP Vorms = ...............................................................(8) 2 2VP PSUP = VDD × IDD( AVG ) = VDD × .............................(9) πRL PO = ing out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to eliminate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the de- Efficiency of a BTL configuration vice or the shutdown function will cause the click and pop circuitry. The value of Ci will also affect turn-on pops. (Refer VP × VP ( ) PO πVP 2RL = = ......................................(10) PSUP VDD × 2VP 4 VDD πRL to Effective Bypass Capacitance) The bypass voltage should rise slower than input bias voltage. Although the bypass pin current source cannot be modified, the size of CB can be changed to alter the device turn-on time and the amount of clicks and pops. By increasing the value of CB, turn-on pop can be reduced. However, the tradeoff for Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 19 www.anpec.com.tw APA2030/2031 Application Information (Cont.) BTL Amplifier Efficiency (Cont.) Table 2 calculates efficiencies for four different output Since the APA2030/1 is a dual channel power amplifier, the maximum internal power dissipation is 2 times that power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as both of equations depending on the mode of operation. Even with this substantial increase in power dissipation, power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating the APA2030/1 does not require extra heatsink. The power dissipation from equation12, assuming a 5V-power sup- range. Note that the internal dissipation at full output power is less than in the half power range. Calculating ply and an 8W load, must not be greater than the power dissipation that results from the equation 13: the efficiency for a specific system is the key to proper power supply design. For a stereo 1W audio system with PD.MAX = 8Ω loads and a 5V supply, the maximum draw on the power supply is almost 3W. Po (W) Efficiency (%) IDD(A) VPP(V) PD (W) 0.25 31.25 0.16 2.00 0.55 0.50 47.62 0.21 2.83 0.55 1.00 66.67 0.30 4.00 0.5 1.25 78.13 0.32 4.47 0.35 TJ.MAX − TA .........................................(13 ) θJA For TSSOP-24P (APA2030), TSSOP-20P and TQFN3x316 (APA2031) packages with and without thermal pad, the thermal resistance (θJA) is equal to 45oC/W, 48oC/W and 55oC/W respectively. Since the maximum junction temperature (TJ,MAX ) of APA2030/1 is 150oC and the ambient temperature (TA) is defined by the power system design, the maximum power **High peak voltages cause the THD+N to increase. dissipation which the IC package is able to handle can be obtained from equation12. Once the power dissipation Table 2: Efficiency vs. Output Power in 5V/8W BTL Systems is greater than the maximum limit (P D,MAX ), either the supply voltage (VDD) must be decreased, the load imped- A final point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency ance (RL) must be increased or the ambient temperature should be reduced. equation to the utmost advantage when possible. Note that in equation, VDD is in the dominator. This indicates Thermal Pad Consideration The thermal pad must be connected to the ground. The that as VDD goes down, efficiency goes up. In other words, use the efficiency analysis to choose the correct supply package with thermal pad of the APA2030/1 requires special attention on thermal design. If the thermal design voltage and speaker impedance for the application. issues are not properly addressed, the APA2030/1 4Ω will go into thermal shutdown when driving a 4Ω load. Power Dissipation The thermal pad on the bottom of the APA2030/1 should be soldered down to a copper pad on the circuit board. Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. In Heat can be conducted away from the thermal pad through the copper plane to ambient. If the copper plane is not on equation11, it states that the maximum power dissipation point for a SE mode operates at a given supply volt- the top surface of the circuit board, 8 to 10 vias of 13 mil or smaller in diameter should be used to thermally couple age and drives a specified load. SE mode : PD.MAX = VDD2 ..............................(11) 2π2RL the thermal pad to the bottom plane. For good thermal conduction, the vias must be plated through and solder In BTL mode operation, the output voltage swing is filled. The copper plane is used to conduct heat away from the thermal pad should be as large as practical. doubled as in SE mode. Thus, the maximum power dissipation point for a BTL mode operating at the same given If the ambient temperature is higher than 25°C, a larger copper plane or forced-air cooling will be required to keep conditions is 4 times as in SE mode. BLT mode : PD.MAX = 4 VDD2 ..............................(12) 2π2RL Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 the APA2030/1 junction temperature below the thermal shutdown temperature (150°C). 20 www.anpec.com.tw APA2030/2031 Application Information (Cont.) Thermal Pad Consideration (Cont.) Recommended Minimum Footprint In higher ambient temperature, higher airflow rate and/or larger copper area will be required to keep the IC out of thermal shutdown. Via diameter Via diameter =0.3mm X10 =0.3mm X8 3mm 1.7mm 4.7mm 1.7mm Thermal Consideration Linear power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. 0.35mm To calculate maximum ambient temperatures, first consideration is that the numbers from the Power Dissipation vs. Output Power graphs (Page 9 and 10) are per channel values, so the dissipation of the IC heat needs 4.5mm to be doubled for two-channel operation. Given θJA, the maximum allowable junction temperature (TJ,MAX), and the total internal dissipation (PD), the maximum ambient temperature can be calculated with the following equation. The maximum recommended junction temperature for the APA2030/1 is 150oC. The internal dissipation figures 0.65mm are taken from the Power Dissipation vs. Output Power graphs. (Page 9 and 10) TA.MAX = TJ.MAX - θJAPD......................................(14 ) Ground plane for ThermalPAD 150 - 45(0.8x2) = 78oC (TSSOP-24P) Exposed for thermal PAD connected TSSOP-24P o 150 - 48(0.8x2) = 73.2 C (TSSOP-20P) 150 - 55(0.8x2) = 62oC (TQFN3x3-16) Via diameter =0.3mm X6 The APA2030/1 is designed with a thermal shutdown pro- 1.7mm tection that turns the device off when the junction temperature surpasses 150 o C to prevent the IC from damages. Via diameter =0.3mm X8 3mm 4.7mm 1.7mm 4.0mm 0.35mm 0.65mm Ground plane for ThermalPAD Exposed for thermal PAD connected TSSOP-20P Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 21 www.anpec.com.tw APA2030/2031 Application Information (Cont.) Recommended Minimum Footprint 3mm Via diameter = 0.3mm X 5 0.5mm * 1.66 mm 0.24mm 3mm 0.5mm 0.508mm 1.66mm 0.162mm * Just Recommend Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 22 www.anpec.com.tw APA2030/2031 Package Information TSSOP-24P (APA2030) D SEE VIEW A b A VIEW A L 0 GAUGE PLANE SEATING PLANE A1 S Y M B O L 0.25 c A2 e E E2 EXPOSED PAD E1 D1 TSSOP-24P INCHES MILLIMETERS MIN. MAX. A MIN. MAX. 1.20 0.047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.031 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 D 7.70 7.90 0.303 0.311 D1 3.50 5.00 0.138 0.197 E 6.20 6.60 0.244 0.260 E1 4.30 4.50 0.169 0.177 E2 2.50 3.50 0.098 0.138 0.75 0.018 8o 0o e L 0 0.65 BSC 0.45 0o 0.026 BSC 0.030 8o Note : 1. Followed from JEDEC MO-153 ADT. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 23 www.anpec.com.tw APA2030/2031 Package Information TSSOP-20P (APA2031) D SEE VIEW A b A 0.25 c GAUGE PLANE SEATING PLANE A1 A2 e VIEW A S Y M B O L L 0 EXPOSE D PAD E E2 E1 D1 TSSOP-20P MILLIMETERS MIN. INCHES MIN. MAX. A MAX. 0.047 1.20 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.031 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 D 6.40 6.60 0.252 0.260 D1 3.00 4.50 0.118 0.177 E 6.20 6.40 0.244 0.260 E1 4.30 4.50 0.169 0.177 E2 2.50 3.50 0.098 0.138 0.75 0.018 8o 0o A1 e L 0 0.026 BSC 0.65 BSC 0.45 0o 0.030 8o Note : 1. Follow JEDEC MO-153 ACT. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 24 www.anpec.com.tw APA2030/2031 Package Information TQFN3x3-16 (APA2031) D b E A Pin 1 D2 A1 A3 k E2 Pin 1 Corner e S Y M B O L TQFN3x3-16 INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.012 D 2.90 3.10 0.114 0.122 D2 1.50 1.80 0.059 0.071 E 2.90 3.10 0.114 0.122 E2 1.50 1.80 0.059 0.071 e 0.50 BSC L 0.30 K 0.20 0.020 BSC 0.012 0.50 0.020 0.008 Note : Follow JEDEC MO-220 WEED-4. Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 25 www.anpec.com.tw APA2030/2031 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TSSOP-24P Application TSSOP-20P Application TQFN3x3-16 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 16.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.50±0.10 P0 P1 P2 D0 D1 T A0 B0 K0 2.00±0.10 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.9±0.20 8.30.±0.20 1.50±0.20 4.00±0.10 8.00±0.10 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 16.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.50±0.10 P0 P1 P2 D0 D1 T A0 B0 K0 2.00±0.10 1.5+0.10 -0.00 1.5 MIN. 0.30±0.05 6.9±0.20 6.90±0.20 1.60±0.20 4.00±0.10 8.00±0.10 A H T1 C d D W E1 F 330±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.30±0.20 4.0±0.10 8.0±0.10 (mm) Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 26 www.anpec.com.tw APA2030/2031 Devices Per Unit Package Type TSSOP-24P TSSOP-20P TQFN3x3-16 Unit Tape & Reel Tape & Reel Tape & Reel Quantity 2000 2000 3000 Taping Direction Information TSSOP-20P USER DIRECTION OF FEED TSSOP-24P USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 27 www.anpec.com.tw APA2030/2031 Taping Direction Information TQFN3x3-16 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 28 www.anpec.com.tw APA2030/2031 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 29 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APA2030/2031 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 30 www.anpec.com.tw